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bc5ad3f3 BH |
1 | /* |
2 | * Copyright 2012 Michael Ellerman, IBM Corporation. | |
3 | * Copyright 2012 Benjamin Herrenschmidt, IBM Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License, version 2, as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/kvm_host.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/gfp.h> | |
5975a2e0 | 14 | #include <linux/anon_inodes.h> |
433c5c20 | 15 | #include <linux/spinlock.h> |
bc5ad3f3 | 16 | |
7c0f6ba6 | 17 | #include <linux/uaccess.h> |
bc5ad3f3 BH |
18 | #include <asm/kvm_book3s.h> |
19 | #include <asm/kvm_ppc.h> | |
20 | #include <asm/hvcall.h> | |
21 | #include <asm/xics.h> | |
22 | #include <asm/debug.h> | |
7bfa9ad5 | 23 | #include <asm/time.h> |
bc5ad3f3 BH |
24 | |
25 | #include <linux/debugfs.h> | |
26 | #include <linux/seq_file.h> | |
27 | ||
28 | #include "book3s_xics.h" | |
29 | ||
30 | #if 1 | |
31 | #define XICS_DBG(fmt...) do { } while (0) | |
32 | #else | |
33 | #define XICS_DBG(fmt...) trace_printk(fmt) | |
34 | #endif | |
35 | ||
e7d26f28 BH |
36 | #define ENABLE_REALMODE true |
37 | #define DEBUG_REALMODE false | |
38 | ||
bc5ad3f3 BH |
39 | /* |
40 | * LOCKING | |
41 | * ======= | |
42 | * | |
34cb7954 | 43 | * Each ICS has a spin lock protecting the information about the IRQ |
4e33d1f0 | 44 | * sources and avoiding simultaneous deliveries of the same interrupt. |
bc5ad3f3 BH |
45 | * |
46 | * ICP operations are done via a single compare & swap transaction | |
47 | * (most ICP state fits in the union kvmppc_icp_state) | |
48 | */ | |
49 | ||
50 | /* | |
51 | * TODO | |
52 | * ==== | |
53 | * | |
54 | * - To speed up resends, keep a bitmap of "resend" set bits in the | |
55 | * ICS | |
56 | * | |
57 | * - Speed up server# -> ICP lookup (array ? hash table ?) | |
58 | * | |
59 | * - Make ICS lockless as well, or at least a per-interrupt lock or hashed | |
60 | * locks array to improve scalability | |
bc5ad3f3 BH |
61 | */ |
62 | ||
63 | /* -- ICS routines -- */ | |
64 | ||
65 | static void icp_deliver_irq(struct kvmppc_xics *xics, struct kvmppc_icp *icp, | |
66 | u32 new_irq); | |
67 | ||
25a2150b PM |
68 | /* |
69 | * Return value ideally indicates how the interrupt was handled, but no | |
70 | * callers look at it (given that we don't implement KVM_IRQ_LINE_STATUS), | |
71 | * so just return 0. | |
72 | */ | |
73 | static int ics_deliver_irq(struct kvmppc_xics *xics, u32 irq, u32 level) | |
bc5ad3f3 BH |
74 | { |
75 | struct ics_irq_state *state; | |
76 | struct kvmppc_ics *ics; | |
77 | u16 src; | |
17d48610 | 78 | u32 pq_old, pq_new; |
bc5ad3f3 BH |
79 | |
80 | XICS_DBG("ics deliver %#x (level: %d)\n", irq, level); | |
81 | ||
82 | ics = kvmppc_xics_find_ics(xics, irq, &src); | |
83 | if (!ics) { | |
84 | XICS_DBG("ics_deliver_irq: IRQ 0x%06x not found !\n", irq); | |
85 | return -EINVAL; | |
86 | } | |
87 | state = &ics->irq_state[src]; | |
88 | if (!state->exists) | |
89 | return -EINVAL; | |
90 | ||
17d48610 LZ |
91 | if (level == KVM_INTERRUPT_SET_LEVEL || level == KVM_INTERRUPT_SET) |
92 | level = 1; | |
93 | else if (level == KVM_INTERRUPT_UNSET) | |
94 | level = 0; | |
bc5ad3f3 | 95 | /* |
17d48610 LZ |
96 | * Take other values the same as 1, consistent with original code. |
97 | * maybe WARN here? | |
bc5ad3f3 | 98 | */ |
17d48610 LZ |
99 | |
100 | if (!state->lsi && level == 0) /* noop for MSI */ | |
bc5ad3f3 | 101 | return 0; |
17d48610 LZ |
102 | |
103 | do { | |
104 | pq_old = state->pq_state; | |
105 | if (state->lsi) { | |
106 | if (level) { | |
107 | if (pq_old & PQ_PRESENTED) | |
108 | /* Setting already set LSI ... */ | |
109 | return 0; | |
110 | ||
111 | pq_new = PQ_PRESENTED; | |
112 | } else | |
113 | pq_new = 0; | |
114 | } else | |
115 | pq_new = ((pq_old << 1) & 3) | PQ_PRESENTED; | |
116 | } while (cmpxchg(&state->pq_state, pq_old, pq_new) != pq_old); | |
117 | ||
118 | /* Test P=1, Q=0, this is the only case where we present */ | |
119 | if (pq_new == PQ_PRESENTED) | |
120 | icp_deliver_irq(xics, NULL, irq); | |
bc5ad3f3 | 121 | |
5d375199 PM |
122 | /* Record which CPU this arrived on for passed-through interrupts */ |
123 | if (state->host_irq) | |
124 | state->intr_cpu = raw_smp_processor_id(); | |
125 | ||
25a2150b | 126 | return 0; |
bc5ad3f3 BH |
127 | } |
128 | ||
129 | static void ics_check_resend(struct kvmppc_xics *xics, struct kvmppc_ics *ics, | |
130 | struct kvmppc_icp *icp) | |
131 | { | |
132 | int i; | |
133 | ||
34cb7954 SW |
134 | unsigned long flags; |
135 | ||
136 | local_irq_save(flags); | |
137 | arch_spin_lock(&ics->lock); | |
bc5ad3f3 BH |
138 | |
139 | for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) { | |
140 | struct ics_irq_state *state = &ics->irq_state[i]; | |
141 | ||
142 | if (!state->resend) | |
143 | continue; | |
144 | ||
bf5a71d5 LZ |
145 | state->resend = 0; |
146 | ||
bc5ad3f3 BH |
147 | XICS_DBG("resend %#x prio %#x\n", state->number, |
148 | state->priority); | |
149 | ||
34cb7954 SW |
150 | arch_spin_unlock(&ics->lock); |
151 | local_irq_restore(flags); | |
bc5ad3f3 | 152 | icp_deliver_irq(xics, icp, state->number); |
34cb7954 SW |
153 | local_irq_save(flags); |
154 | arch_spin_lock(&ics->lock); | |
bc5ad3f3 BH |
155 | } |
156 | ||
34cb7954 SW |
157 | arch_spin_unlock(&ics->lock); |
158 | local_irq_restore(flags); | |
bc5ad3f3 BH |
159 | } |
160 | ||
d19bd862 PM |
161 | static bool write_xive(struct kvmppc_xics *xics, struct kvmppc_ics *ics, |
162 | struct ics_irq_state *state, | |
163 | u32 server, u32 priority, u32 saved_priority) | |
164 | { | |
165 | bool deliver; | |
34cb7954 | 166 | unsigned long flags; |
d19bd862 | 167 | |
34cb7954 SW |
168 | local_irq_save(flags); |
169 | arch_spin_lock(&ics->lock); | |
d19bd862 PM |
170 | |
171 | state->server = server; | |
172 | state->priority = priority; | |
173 | state->saved_priority = saved_priority; | |
174 | deliver = false; | |
175 | if ((state->masked_pending || state->resend) && priority != MASKED) { | |
176 | state->masked_pending = 0; | |
bf5a71d5 | 177 | state->resend = 0; |
d19bd862 PM |
178 | deliver = true; |
179 | } | |
180 | ||
34cb7954 SW |
181 | arch_spin_unlock(&ics->lock); |
182 | local_irq_restore(flags); | |
d19bd862 PM |
183 | |
184 | return deliver; | |
185 | } | |
186 | ||
bc5ad3f3 BH |
187 | int kvmppc_xics_set_xive(struct kvm *kvm, u32 irq, u32 server, u32 priority) |
188 | { | |
189 | struct kvmppc_xics *xics = kvm->arch.xics; | |
190 | struct kvmppc_icp *icp; | |
191 | struct kvmppc_ics *ics; | |
192 | struct ics_irq_state *state; | |
193 | u16 src; | |
bc5ad3f3 BH |
194 | |
195 | if (!xics) | |
196 | return -ENODEV; | |
197 | ||
198 | ics = kvmppc_xics_find_ics(xics, irq, &src); | |
199 | if (!ics) | |
200 | return -EINVAL; | |
201 | state = &ics->irq_state[src]; | |
202 | ||
203 | icp = kvmppc_xics_find_server(kvm, server); | |
204 | if (!icp) | |
205 | return -EINVAL; | |
206 | ||
bc5ad3f3 BH |
207 | XICS_DBG("set_xive %#x server %#x prio %#x MP:%d RS:%d\n", |
208 | irq, server, priority, | |
209 | state->masked_pending, state->resend); | |
210 | ||
d19bd862 | 211 | if (write_xive(xics, ics, state, server, priority, priority)) |
bc5ad3f3 BH |
212 | icp_deliver_irq(xics, icp, irq); |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
217 | int kvmppc_xics_get_xive(struct kvm *kvm, u32 irq, u32 *server, u32 *priority) | |
218 | { | |
219 | struct kvmppc_xics *xics = kvm->arch.xics; | |
220 | struct kvmppc_ics *ics; | |
221 | struct ics_irq_state *state; | |
222 | u16 src; | |
34cb7954 | 223 | unsigned long flags; |
bc5ad3f3 BH |
224 | |
225 | if (!xics) | |
226 | return -ENODEV; | |
227 | ||
228 | ics = kvmppc_xics_find_ics(xics, irq, &src); | |
229 | if (!ics) | |
230 | return -EINVAL; | |
231 | state = &ics->irq_state[src]; | |
232 | ||
34cb7954 SW |
233 | local_irq_save(flags); |
234 | arch_spin_lock(&ics->lock); | |
bc5ad3f3 BH |
235 | *server = state->server; |
236 | *priority = state->priority; | |
34cb7954 SW |
237 | arch_spin_unlock(&ics->lock); |
238 | local_irq_restore(flags); | |
bc5ad3f3 BH |
239 | |
240 | return 0; | |
241 | } | |
242 | ||
d19bd862 PM |
243 | int kvmppc_xics_int_on(struct kvm *kvm, u32 irq) |
244 | { | |
245 | struct kvmppc_xics *xics = kvm->arch.xics; | |
246 | struct kvmppc_icp *icp; | |
247 | struct kvmppc_ics *ics; | |
248 | struct ics_irq_state *state; | |
249 | u16 src; | |
250 | ||
251 | if (!xics) | |
252 | return -ENODEV; | |
253 | ||
254 | ics = kvmppc_xics_find_ics(xics, irq, &src); | |
255 | if (!ics) | |
256 | return -EINVAL; | |
257 | state = &ics->irq_state[src]; | |
258 | ||
259 | icp = kvmppc_xics_find_server(kvm, state->server); | |
260 | if (!icp) | |
261 | return -EINVAL; | |
262 | ||
263 | if (write_xive(xics, ics, state, state->server, state->saved_priority, | |
264 | state->saved_priority)) | |
265 | icp_deliver_irq(xics, icp, irq); | |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
270 | int kvmppc_xics_int_off(struct kvm *kvm, u32 irq) | |
271 | { | |
272 | struct kvmppc_xics *xics = kvm->arch.xics; | |
273 | struct kvmppc_ics *ics; | |
274 | struct ics_irq_state *state; | |
275 | u16 src; | |
276 | ||
277 | if (!xics) | |
278 | return -ENODEV; | |
279 | ||
280 | ics = kvmppc_xics_find_ics(xics, irq, &src); | |
281 | if (!ics) | |
282 | return -EINVAL; | |
283 | state = &ics->irq_state[src]; | |
284 | ||
285 | write_xive(xics, ics, state, state->server, MASKED, state->priority); | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
bc5ad3f3 BH |
290 | /* -- ICP routines, including hcalls -- */ |
291 | ||
292 | static inline bool icp_try_update(struct kvmppc_icp *icp, | |
293 | union kvmppc_icp_state old, | |
294 | union kvmppc_icp_state new, | |
295 | bool change_self) | |
296 | { | |
297 | bool success; | |
298 | ||
299 | /* Calculate new output value */ | |
300 | new.out_ee = (new.xisr && (new.pending_pri < new.cppr)); | |
301 | ||
302 | /* Attempt atomic update */ | |
303 | success = cmpxchg64(&icp->state.raw, old.raw, new.raw) == old.raw; | |
304 | if (!success) | |
305 | goto bail; | |
306 | ||
ade3ac66 | 307 | XICS_DBG("UPD [%04lx] - C:%02x M:%02x PP: %02x PI:%06x R:%d O:%d\n", |
bc5ad3f3 BH |
308 | icp->server_num, |
309 | old.cppr, old.mfrr, old.pending_pri, old.xisr, | |
310 | old.need_resend, old.out_ee); | |
311 | XICS_DBG("UPD - C:%02x M:%02x PP: %02x PI:%06x R:%d O:%d\n", | |
312 | new.cppr, new.mfrr, new.pending_pri, new.xisr, | |
313 | new.need_resend, new.out_ee); | |
314 | /* | |
315 | * Check for output state update | |
316 | * | |
317 | * Note that this is racy since another processor could be updating | |
318 | * the state already. This is why we never clear the interrupt output | |
319 | * here, we only ever set it. The clear only happens prior to doing | |
320 | * an update and only by the processor itself. Currently we do it | |
321 | * in Accept (H_XIRR) and Up_Cppr (H_XPPR). | |
322 | * | |
323 | * We also do not try to figure out whether the EE state has changed, | |
e7d26f28 BH |
324 | * we unconditionally set it if the new state calls for it. The reason |
325 | * for that is that we opportunistically remove the pending interrupt | |
326 | * flag when raising CPPR, so we need to set it back here if an | |
327 | * interrupt is still pending. | |
bc5ad3f3 BH |
328 | */ |
329 | if (new.out_ee) { | |
330 | kvmppc_book3s_queue_irqprio(icp->vcpu, | |
331 | BOOK3S_INTERRUPT_EXTERNAL_LEVEL); | |
332 | if (!change_self) | |
54695c30 | 333 | kvmppc_fast_vcpu_kick(icp->vcpu); |
bc5ad3f3 BH |
334 | } |
335 | bail: | |
336 | return success; | |
337 | } | |
338 | ||
339 | static void icp_check_resend(struct kvmppc_xics *xics, | |
340 | struct kvmppc_icp *icp) | |
341 | { | |
342 | u32 icsid; | |
343 | ||
344 | /* Order this load with the test for need_resend in the caller */ | |
345 | smp_rmb(); | |
346 | for_each_set_bit(icsid, icp->resend_map, xics->max_icsid + 1) { | |
347 | struct kvmppc_ics *ics = xics->ics[icsid]; | |
348 | ||
349 | if (!test_and_clear_bit(icsid, icp->resend_map)) | |
350 | continue; | |
351 | if (!ics) | |
352 | continue; | |
353 | ics_check_resend(xics, ics, icp); | |
354 | } | |
355 | } | |
356 | ||
357 | static bool icp_try_to_deliver(struct kvmppc_icp *icp, u32 irq, u8 priority, | |
358 | u32 *reject) | |
359 | { | |
360 | union kvmppc_icp_state old_state, new_state; | |
361 | bool success; | |
362 | ||
ade3ac66 | 363 | XICS_DBG("try deliver %#x(P:%#x) to server %#lx\n", irq, priority, |
bc5ad3f3 BH |
364 | icp->server_num); |
365 | ||
366 | do { | |
5ee07612 | 367 | old_state = new_state = READ_ONCE(icp->state); |
bc5ad3f3 BH |
368 | |
369 | *reject = 0; | |
370 | ||
371 | /* See if we can deliver */ | |
372 | success = new_state.cppr > priority && | |
373 | new_state.mfrr > priority && | |
374 | new_state.pending_pri > priority; | |
375 | ||
376 | /* | |
377 | * If we can, check for a rejection and perform the | |
378 | * delivery | |
379 | */ | |
380 | if (success) { | |
381 | *reject = new_state.xisr; | |
382 | new_state.xisr = irq; | |
383 | new_state.pending_pri = priority; | |
384 | } else { | |
385 | /* | |
386 | * If we failed to deliver we set need_resend | |
387 | * so a subsequent CPPR state change causes us | |
388 | * to try a new delivery. | |
389 | */ | |
390 | new_state.need_resend = true; | |
391 | } | |
392 | ||
393 | } while (!icp_try_update(icp, old_state, new_state, false)); | |
394 | ||
395 | return success; | |
396 | } | |
397 | ||
398 | static void icp_deliver_irq(struct kvmppc_xics *xics, struct kvmppc_icp *icp, | |
399 | u32 new_irq) | |
400 | { | |
401 | struct ics_irq_state *state; | |
402 | struct kvmppc_ics *ics; | |
403 | u32 reject; | |
404 | u16 src; | |
34cb7954 | 405 | unsigned long flags; |
bc5ad3f3 BH |
406 | |
407 | /* | |
408 | * This is used both for initial delivery of an interrupt and | |
409 | * for subsequent rejection. | |
410 | * | |
411 | * Rejection can be racy vs. resends. We have evaluated the | |
412 | * rejection in an atomic ICP transaction which is now complete, | |
413 | * so potentially the ICP can already accept the interrupt again. | |
414 | * | |
415 | * So we need to retry the delivery. Essentially the reject path | |
416 | * boils down to a failed delivery. Always. | |
417 | * | |
418 | * Now the interrupt could also have moved to a different target, | |
419 | * thus we may need to re-do the ICP lookup as well | |
420 | */ | |
421 | ||
422 | again: | |
423 | /* Get the ICS state and lock it */ | |
424 | ics = kvmppc_xics_find_ics(xics, new_irq, &src); | |
425 | if (!ics) { | |
426 | XICS_DBG("icp_deliver_irq: IRQ 0x%06x not found !\n", new_irq); | |
427 | return; | |
428 | } | |
429 | state = &ics->irq_state[src]; | |
430 | ||
431 | /* Get a lock on the ICS */ | |
34cb7954 SW |
432 | local_irq_save(flags); |
433 | arch_spin_lock(&ics->lock); | |
bc5ad3f3 BH |
434 | |
435 | /* Get our server */ | |
436 | if (!icp || state->server != icp->server_num) { | |
437 | icp = kvmppc_xics_find_server(xics->kvm, state->server); | |
438 | if (!icp) { | |
439 | pr_warn("icp_deliver_irq: IRQ 0x%06x server 0x%x not found !\n", | |
440 | new_irq, state->server); | |
441 | goto out; | |
442 | } | |
443 | } | |
444 | ||
445 | /* Clear the resend bit of that interrupt */ | |
446 | state->resend = 0; | |
447 | ||
448 | /* | |
449 | * If masked, bail out | |
450 | * | |
451 | * Note: PAPR doesn't mention anything about masked pending | |
452 | * when doing a resend, only when doing a delivery. | |
453 | * | |
454 | * However that would have the effect of losing a masked | |
455 | * interrupt that was rejected and isn't consistent with | |
456 | * the whole masked_pending business which is about not | |
457 | * losing interrupts that occur while masked. | |
458 | * | |
446957ba | 459 | * I don't differentiate normal deliveries and resends, this |
bc5ad3f3 BH |
460 | * implementation will differ from PAPR and not lose such |
461 | * interrupts. | |
462 | */ | |
463 | if (state->priority == MASKED) { | |
464 | XICS_DBG("irq %#x masked pending\n", new_irq); | |
465 | state->masked_pending = 1; | |
466 | goto out; | |
467 | } | |
468 | ||
469 | /* | |
470 | * Try the delivery, this will set the need_resend flag | |
471 | * in the ICP as part of the atomic transaction if the | |
472 | * delivery is not possible. | |
473 | * | |
474 | * Note that if successful, the new delivery might have itself | |
475 | * rejected an interrupt that was "delivered" before we took the | |
34cb7954 | 476 | * ics spin lock. |
bc5ad3f3 BH |
477 | * |
478 | * In this case we do the whole sequence all over again for the | |
479 | * new guy. We cannot assume that the rejected interrupt is less | |
480 | * favored than the new one, and thus doesn't need to be delivered, | |
481 | * because by the time we exit icp_try_to_deliver() the target | |
482 | * processor may well have alrady consumed & completed it, and thus | |
483 | * the rejected interrupt might actually be already acceptable. | |
484 | */ | |
485 | if (icp_try_to_deliver(icp, new_irq, state->priority, &reject)) { | |
486 | /* | |
487 | * Delivery was successful, did we reject somebody else ? | |
488 | */ | |
489 | if (reject && reject != XICS_IPI) { | |
34cb7954 SW |
490 | arch_spin_unlock(&ics->lock); |
491 | local_irq_restore(flags); | |
bc5ad3f3 BH |
492 | new_irq = reject; |
493 | goto again; | |
494 | } | |
495 | } else { | |
496 | /* | |
497 | * We failed to deliver the interrupt we need to set the | |
498 | * resend map bit and mark the ICS state as needing a resend | |
499 | */ | |
500 | set_bit(ics->icsid, icp->resend_map); | |
501 | state->resend = 1; | |
502 | ||
503 | /* | |
504 | * If the need_resend flag got cleared in the ICP some time | |
505 | * between icp_try_to_deliver() atomic update and now, then | |
506 | * we know it might have missed the resend_map bit. So we | |
507 | * retry | |
508 | */ | |
509 | smp_mb(); | |
510 | if (!icp->state.need_resend) { | |
bf5a71d5 | 511 | state->resend = 0; |
34cb7954 SW |
512 | arch_spin_unlock(&ics->lock); |
513 | local_irq_restore(flags); | |
bc5ad3f3 BH |
514 | goto again; |
515 | } | |
516 | } | |
517 | out: | |
34cb7954 SW |
518 | arch_spin_unlock(&ics->lock); |
519 | local_irq_restore(flags); | |
bc5ad3f3 BH |
520 | } |
521 | ||
522 | static void icp_down_cppr(struct kvmppc_xics *xics, struct kvmppc_icp *icp, | |
523 | u8 new_cppr) | |
524 | { | |
525 | union kvmppc_icp_state old_state, new_state; | |
526 | bool resend; | |
527 | ||
528 | /* | |
529 | * This handles several related states in one operation: | |
530 | * | |
531 | * ICP State: Down_CPPR | |
532 | * | |
533 | * Load CPPR with new value and if the XISR is 0 | |
534 | * then check for resends: | |
535 | * | |
536 | * ICP State: Resend | |
537 | * | |
538 | * If MFRR is more favored than CPPR, check for IPIs | |
539 | * and notify ICS of a potential resend. This is done | |
540 | * asynchronously (when used in real mode, we will have | |
541 | * to exit here). | |
542 | * | |
543 | * We do not handle the complete Check_IPI as documented | |
544 | * here. In the PAPR, this state will be used for both | |
545 | * Set_MFRR and Down_CPPR. However, we know that we aren't | |
546 | * changing the MFRR state here so we don't need to handle | |
547 | * the case of an MFRR causing a reject of a pending irq, | |
548 | * this will have been handled when the MFRR was set in the | |
549 | * first place. | |
550 | * | |
551 | * Thus we don't have to handle rejects, only resends. | |
552 | * | |
553 | * When implementing real mode for HV KVM, resend will lead to | |
554 | * a H_TOO_HARD return and the whole transaction will be handled | |
555 | * in virtual mode. | |
556 | */ | |
557 | do { | |
5ee07612 | 558 | old_state = new_state = READ_ONCE(icp->state); |
bc5ad3f3 BH |
559 | |
560 | /* Down_CPPR */ | |
561 | new_state.cppr = new_cppr; | |
562 | ||
563 | /* | |
564 | * Cut down Resend / Check_IPI / IPI | |
565 | * | |
566 | * The logic is that we cannot have a pending interrupt | |
567 | * trumped by an IPI at this point (see above), so we | |
568 | * know that either the pending interrupt is already an | |
569 | * IPI (in which case we don't care to override it) or | |
570 | * it's either more favored than us or non existent | |
571 | */ | |
572 | if (new_state.mfrr < new_cppr && | |
573 | new_state.mfrr <= new_state.pending_pri) { | |
574 | WARN_ON(new_state.xisr != XICS_IPI && | |
575 | new_state.xisr != 0); | |
576 | new_state.pending_pri = new_state.mfrr; | |
577 | new_state.xisr = XICS_IPI; | |
578 | } | |
579 | ||
580 | /* Latch/clear resend bit */ | |
581 | resend = new_state.need_resend; | |
582 | new_state.need_resend = 0; | |
583 | ||
584 | } while (!icp_try_update(icp, old_state, new_state, true)); | |
585 | ||
586 | /* | |
587 | * Now handle resend checks. Those are asynchronous to the ICP | |
588 | * state update in HW (ie bus transactions) so we can handle them | |
589 | * separately here too | |
590 | */ | |
591 | if (resend) | |
592 | icp_check_resend(xics, icp); | |
593 | } | |
594 | ||
e7d26f28 | 595 | static noinline unsigned long kvmppc_h_xirr(struct kvm_vcpu *vcpu) |
bc5ad3f3 BH |
596 | { |
597 | union kvmppc_icp_state old_state, new_state; | |
598 | struct kvmppc_icp *icp = vcpu->arch.icp; | |
599 | u32 xirr; | |
600 | ||
601 | /* First, remove EE from the processor */ | |
602 | kvmppc_book3s_dequeue_irqprio(icp->vcpu, | |
603 | BOOK3S_INTERRUPT_EXTERNAL_LEVEL); | |
604 | ||
605 | /* | |
606 | * ICP State: Accept_Interrupt | |
607 | * | |
608 | * Return the pending interrupt (if any) along with the | |
609 | * current CPPR, then clear the XISR & set CPPR to the | |
610 | * pending priority | |
611 | */ | |
612 | do { | |
5ee07612 | 613 | old_state = new_state = READ_ONCE(icp->state); |
bc5ad3f3 BH |
614 | |
615 | xirr = old_state.xisr | (((u32)old_state.cppr) << 24); | |
616 | if (!old_state.xisr) | |
617 | break; | |
618 | new_state.cppr = new_state.pending_pri; | |
619 | new_state.pending_pri = 0xff; | |
620 | new_state.xisr = 0; | |
621 | ||
622 | } while (!icp_try_update(icp, old_state, new_state, true)); | |
623 | ||
624 | XICS_DBG("h_xirr vcpu %d xirr %#x\n", vcpu->vcpu_id, xirr); | |
625 | ||
626 | return xirr; | |
627 | } | |
628 | ||
e7d26f28 BH |
629 | static noinline int kvmppc_h_ipi(struct kvm_vcpu *vcpu, unsigned long server, |
630 | unsigned long mfrr) | |
bc5ad3f3 BH |
631 | { |
632 | union kvmppc_icp_state old_state, new_state; | |
633 | struct kvmppc_xics *xics = vcpu->kvm->arch.xics; | |
634 | struct kvmppc_icp *icp; | |
635 | u32 reject; | |
636 | bool resend; | |
637 | bool local; | |
638 | ||
639 | XICS_DBG("h_ipi vcpu %d to server %lu mfrr %#lx\n", | |
640 | vcpu->vcpu_id, server, mfrr); | |
641 | ||
642 | icp = vcpu->arch.icp; | |
643 | local = icp->server_num == server; | |
644 | if (!local) { | |
645 | icp = kvmppc_xics_find_server(vcpu->kvm, server); | |
646 | if (!icp) | |
647 | return H_PARAMETER; | |
648 | } | |
649 | ||
650 | /* | |
651 | * ICP state: Set_MFRR | |
652 | * | |
653 | * If the CPPR is more favored than the new MFRR, then | |
654 | * nothing needs to be rejected as there can be no XISR to | |
655 | * reject. If the MFRR is being made less favored then | |
656 | * there might be a previously-rejected interrupt needing | |
657 | * to be resent. | |
658 | * | |
5b88cda6 SW |
659 | * ICP state: Check_IPI |
660 | * | |
bc5ad3f3 | 661 | * If the CPPR is less favored, then we might be replacing |
5b88cda6 | 662 | * an interrupt, and thus need to possibly reject it. |
bc5ad3f3 | 663 | * |
5b88cda6 SW |
664 | * ICP State: IPI |
665 | * | |
666 | * Besides rejecting any pending interrupts, we also | |
667 | * update XISR and pending_pri to mark IPI as pending. | |
668 | * | |
669 | * PAPR does not describe this state, but if the MFRR is being | |
670 | * made less favored than its earlier value, there might be | |
671 | * a previously-rejected interrupt needing to be resent. | |
672 | * Ideally, we would want to resend only if | |
673 | * prio(pending_interrupt) < mfrr && | |
674 | * prio(pending_interrupt) < cppr | |
675 | * where pending interrupt is the one that was rejected. But | |
676 | * we don't have that state, so we simply trigger a resend | |
677 | * whenever the MFRR is made less favored. | |
bc5ad3f3 BH |
678 | */ |
679 | do { | |
5ee07612 | 680 | old_state = new_state = READ_ONCE(icp->state); |
bc5ad3f3 BH |
681 | |
682 | /* Set_MFRR */ | |
683 | new_state.mfrr = mfrr; | |
684 | ||
685 | /* Check_IPI */ | |
686 | reject = 0; | |
687 | resend = false; | |
688 | if (mfrr < new_state.cppr) { | |
689 | /* Reject a pending interrupt if not an IPI */ | |
5b88cda6 | 690 | if (mfrr <= new_state.pending_pri) { |
bc5ad3f3 | 691 | reject = new_state.xisr; |
5b88cda6 SW |
692 | new_state.pending_pri = mfrr; |
693 | new_state.xisr = XICS_IPI; | |
694 | } | |
bc5ad3f3 BH |
695 | } |
696 | ||
5b88cda6 | 697 | if (mfrr > old_state.mfrr) { |
bc5ad3f3 BH |
698 | resend = new_state.need_resend; |
699 | new_state.need_resend = 0; | |
700 | } | |
701 | } while (!icp_try_update(icp, old_state, new_state, local)); | |
702 | ||
703 | /* Handle reject */ | |
704 | if (reject && reject != XICS_IPI) | |
705 | icp_deliver_irq(xics, icp, reject); | |
706 | ||
707 | /* Handle resend */ | |
708 | if (resend) | |
709 | icp_check_resend(xics, icp); | |
710 | ||
711 | return H_SUCCESS; | |
712 | } | |
713 | ||
8e44ddc3 PM |
714 | static int kvmppc_h_ipoll(struct kvm_vcpu *vcpu, unsigned long server) |
715 | { | |
716 | union kvmppc_icp_state state; | |
717 | struct kvmppc_icp *icp; | |
718 | ||
719 | icp = vcpu->arch.icp; | |
720 | if (icp->server_num != server) { | |
721 | icp = kvmppc_xics_find_server(vcpu->kvm, server); | |
722 | if (!icp) | |
723 | return H_PARAMETER; | |
724 | } | |
5ee07612 | 725 | state = READ_ONCE(icp->state); |
8e44ddc3 PM |
726 | kvmppc_set_gpr(vcpu, 4, ((u32)state.cppr << 24) | state.xisr); |
727 | kvmppc_set_gpr(vcpu, 5, state.mfrr); | |
728 | return H_SUCCESS; | |
729 | } | |
730 | ||
e7d26f28 | 731 | static noinline void kvmppc_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr) |
bc5ad3f3 BH |
732 | { |
733 | union kvmppc_icp_state old_state, new_state; | |
734 | struct kvmppc_xics *xics = vcpu->kvm->arch.xics; | |
735 | struct kvmppc_icp *icp = vcpu->arch.icp; | |
736 | u32 reject; | |
737 | ||
738 | XICS_DBG("h_cppr vcpu %d cppr %#lx\n", vcpu->vcpu_id, cppr); | |
739 | ||
740 | /* | |
741 | * ICP State: Set_CPPR | |
742 | * | |
743 | * We can safely compare the new value with the current | |
744 | * value outside of the transaction as the CPPR is only | |
745 | * ever changed by the processor on itself | |
746 | */ | |
747 | if (cppr > icp->state.cppr) | |
748 | icp_down_cppr(xics, icp, cppr); | |
749 | else if (cppr == icp->state.cppr) | |
750 | return; | |
751 | ||
752 | /* | |
753 | * ICP State: Up_CPPR | |
754 | * | |
755 | * The processor is raising its priority, this can result | |
756 | * in a rejection of a pending interrupt: | |
757 | * | |
758 | * ICP State: Reject_Current | |
759 | * | |
760 | * We can remove EE from the current processor, the update | |
761 | * transaction will set it again if needed | |
762 | */ | |
763 | kvmppc_book3s_dequeue_irqprio(icp->vcpu, | |
764 | BOOK3S_INTERRUPT_EXTERNAL_LEVEL); | |
765 | ||
766 | do { | |
5ee07612 | 767 | old_state = new_state = READ_ONCE(icp->state); |
bc5ad3f3 BH |
768 | |
769 | reject = 0; | |
770 | new_state.cppr = cppr; | |
771 | ||
772 | if (cppr <= new_state.pending_pri) { | |
773 | reject = new_state.xisr; | |
774 | new_state.xisr = 0; | |
775 | new_state.pending_pri = 0xff; | |
776 | } | |
777 | ||
778 | } while (!icp_try_update(icp, old_state, new_state, true)); | |
779 | ||
780 | /* | |
781 | * Check for rejects. They are handled by doing a new delivery | |
782 | * attempt (see comments in icp_deliver_irq). | |
783 | */ | |
784 | if (reject && reject != XICS_IPI) | |
785 | icp_deliver_irq(xics, icp, reject); | |
786 | } | |
787 | ||
17d48610 | 788 | static int ics_eoi(struct kvm_vcpu *vcpu, u32 irq) |
bc5ad3f3 BH |
789 | { |
790 | struct kvmppc_xics *xics = vcpu->kvm->arch.xics; | |
791 | struct kvmppc_icp *icp = vcpu->arch.icp; | |
792 | struct kvmppc_ics *ics; | |
793 | struct ics_irq_state *state; | |
bc5ad3f3 | 794 | u16 src; |
17d48610 LZ |
795 | u32 pq_old, pq_new; |
796 | ||
797 | /* | |
798 | * ICS EOI handling: For LSI, if P bit is still set, we need to | |
799 | * resend it. | |
800 | * | |
801 | * For MSI, we move Q bit into P (and clear Q). If it is set, | |
802 | * resend it. | |
803 | */ | |
804 | ||
805 | ics = kvmppc_xics_find_ics(xics, irq, &src); | |
806 | if (!ics) { | |
807 | XICS_DBG("ios_eoi: IRQ 0x%06x not found !\n", irq); | |
808 | return H_PARAMETER; | |
809 | } | |
810 | state = &ics->irq_state[src]; | |
811 | ||
812 | if (state->lsi) | |
813 | pq_new = state->pq_state; | |
814 | else | |
815 | do { | |
816 | pq_old = state->pq_state; | |
817 | pq_new = pq_old >> 1; | |
818 | } while (cmpxchg(&state->pq_state, pq_old, pq_new) != pq_old); | |
819 | ||
820 | if (pq_new & PQ_PRESENTED) | |
821 | icp_deliver_irq(xics, icp, irq); | |
822 | ||
823 | kvm_notify_acked_irq(vcpu->kvm, 0, irq); | |
824 | ||
825 | return H_SUCCESS; | |
826 | } | |
827 | ||
828 | static noinline int kvmppc_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr) | |
829 | { | |
830 | struct kvmppc_xics *xics = vcpu->kvm->arch.xics; | |
831 | struct kvmppc_icp *icp = vcpu->arch.icp; | |
832 | u32 irq = xirr & 0x00ffffff; | |
bc5ad3f3 BH |
833 | |
834 | XICS_DBG("h_eoi vcpu %d eoi %#lx\n", vcpu->vcpu_id, xirr); | |
835 | ||
836 | /* | |
837 | * ICP State: EOI | |
838 | * | |
839 | * Note: If EOI is incorrectly used by SW to lower the CPPR | |
840 | * value (ie more favored), we do not check for rejection of | |
841 | * a pending interrupt, this is a SW error and PAPR sepcifies | |
842 | * that we don't have to deal with it. | |
843 | * | |
844 | * The sending of an EOI to the ICS is handled after the | |
845 | * CPPR update | |
846 | * | |
847 | * ICP State: Down_CPPR which we handle | |
848 | * in a separate function as it's shared with H_CPPR. | |
849 | */ | |
850 | icp_down_cppr(xics, icp, xirr >> 24); | |
851 | ||
852 | /* IPIs have no EOI */ | |
853 | if (irq == XICS_IPI) | |
854 | return H_SUCCESS; | |
25a2150b | 855 | |
17d48610 | 856 | return ics_eoi(vcpu, irq); |
bc5ad3f3 BH |
857 | } |
858 | ||
f7af5209 | 859 | int kvmppc_xics_rm_complete(struct kvm_vcpu *vcpu, u32 hcall) |
e7d26f28 BH |
860 | { |
861 | struct kvmppc_xics *xics = vcpu->kvm->arch.xics; | |
862 | struct kvmppc_icp *icp = vcpu->arch.icp; | |
863 | ||
864 | XICS_DBG("XICS_RM: H_%x completing, act: %x state: %lx tgt: %p\n", | |
865 | hcall, icp->rm_action, icp->rm_dbgstate.raw, icp->rm_dbgtgt); | |
866 | ||
878610fe SW |
867 | if (icp->rm_action & XICS_RM_KICK_VCPU) { |
868 | icp->n_rm_kick_vcpu++; | |
e7d26f28 | 869 | kvmppc_fast_vcpu_kick(icp->rm_kick_target); |
878610fe SW |
870 | } |
871 | if (icp->rm_action & XICS_RM_CHECK_RESEND) { | |
872 | icp->n_rm_check_resend++; | |
5b88cda6 | 873 | icp_check_resend(xics, icp->rm_resend_icp); |
878610fe | 874 | } |
878610fe SW |
875 | if (icp->rm_action & XICS_RM_NOTIFY_EOI) { |
876 | icp->n_rm_notify_eoi++; | |
25a2150b | 877 | kvm_notify_acked_irq(vcpu->kvm, 0, icp->rm_eoied_irq); |
878610fe | 878 | } |
e7d26f28 BH |
879 | |
880 | icp->rm_action = 0; | |
881 | ||
882 | return H_SUCCESS; | |
883 | } | |
f7af5209 | 884 | EXPORT_SYMBOL_GPL(kvmppc_xics_rm_complete); |
e7d26f28 | 885 | |
bc5ad3f3 BH |
886 | int kvmppc_xics_hcall(struct kvm_vcpu *vcpu, u32 req) |
887 | { | |
e7d26f28 | 888 | struct kvmppc_xics *xics = vcpu->kvm->arch.xics; |
bc5ad3f3 BH |
889 | unsigned long res; |
890 | int rc = H_SUCCESS; | |
891 | ||
892 | /* Check if we have an ICP */ | |
e7d26f28 | 893 | if (!xics || !vcpu->arch.icp) |
bc5ad3f3 BH |
894 | return H_HARDWARE; |
895 | ||
8e44ddc3 PM |
896 | /* These requests don't have real-mode implementations at present */ |
897 | switch (req) { | |
898 | case H_XIRR_X: | |
899 | res = kvmppc_h_xirr(vcpu); | |
900 | kvmppc_set_gpr(vcpu, 4, res); | |
901 | kvmppc_set_gpr(vcpu, 5, get_tb()); | |
902 | return rc; | |
903 | case H_IPOLL: | |
904 | rc = kvmppc_h_ipoll(vcpu, kvmppc_get_gpr(vcpu, 4)); | |
905 | return rc; | |
906 | } | |
907 | ||
e7d26f28 | 908 | /* Check for real mode returning too hard */ |
a78b55d1 | 909 | if (xics->real_mode && is_kvmppc_hv_enabled(vcpu->kvm)) |
e7d26f28 BH |
910 | return kvmppc_xics_rm_complete(vcpu, req); |
911 | ||
bc5ad3f3 BH |
912 | switch (req) { |
913 | case H_XIRR: | |
e7d26f28 | 914 | res = kvmppc_h_xirr(vcpu); |
bc5ad3f3 BH |
915 | kvmppc_set_gpr(vcpu, 4, res); |
916 | break; | |
917 | case H_CPPR: | |
e7d26f28 | 918 | kvmppc_h_cppr(vcpu, kvmppc_get_gpr(vcpu, 4)); |
bc5ad3f3 BH |
919 | break; |
920 | case H_EOI: | |
e7d26f28 | 921 | rc = kvmppc_h_eoi(vcpu, kvmppc_get_gpr(vcpu, 4)); |
bc5ad3f3 BH |
922 | break; |
923 | case H_IPI: | |
e7d26f28 BH |
924 | rc = kvmppc_h_ipi(vcpu, kvmppc_get_gpr(vcpu, 4), |
925 | kvmppc_get_gpr(vcpu, 5)); | |
bc5ad3f3 BH |
926 | break; |
927 | } | |
928 | ||
929 | return rc; | |
930 | } | |
2ba9f0d8 | 931 | EXPORT_SYMBOL_GPL(kvmppc_xics_hcall); |
bc5ad3f3 BH |
932 | |
933 | ||
934 | /* -- Initialisation code etc. -- */ | |
935 | ||
af893c7d SW |
936 | static void xics_debugfs_irqmap(struct seq_file *m, |
937 | struct kvmppc_passthru_irqmap *pimap) | |
938 | { | |
939 | int i; | |
940 | ||
941 | if (!pimap) | |
942 | return; | |
943 | seq_printf(m, "========\nPIRQ mappings: %d maps\n===========\n", | |
944 | pimap->n_mapped); | |
945 | for (i = 0; i < pimap->n_mapped; i++) { | |
946 | seq_printf(m, "r_hwirq=%x, v_hwirq=%x\n", | |
947 | pimap->mapped[i].r_hwirq, pimap->mapped[i].v_hwirq); | |
948 | } | |
949 | } | |
950 | ||
bc5ad3f3 BH |
951 | static int xics_debug_show(struct seq_file *m, void *private) |
952 | { | |
953 | struct kvmppc_xics *xics = m->private; | |
954 | struct kvm *kvm = xics->kvm; | |
955 | struct kvm_vcpu *vcpu; | |
956 | int icsid, i; | |
34cb7954 | 957 | unsigned long flags; |
878610fe | 958 | unsigned long t_rm_kick_vcpu, t_rm_check_resend; |
5efa6605 | 959 | unsigned long t_rm_notify_eoi; |
6e0365b7 | 960 | unsigned long t_reject, t_check_resend; |
bc5ad3f3 BH |
961 | |
962 | if (!kvm) | |
963 | return 0; | |
964 | ||
878610fe SW |
965 | t_rm_kick_vcpu = 0; |
966 | t_rm_notify_eoi = 0; | |
967 | t_rm_check_resend = 0; | |
6e0365b7 SW |
968 | t_check_resend = 0; |
969 | t_reject = 0; | |
878610fe | 970 | |
af893c7d SW |
971 | xics_debugfs_irqmap(m, kvm->arch.pimap); |
972 | ||
bc5ad3f3 BH |
973 | seq_printf(m, "=========\nICP state\n=========\n"); |
974 | ||
975 | kvm_for_each_vcpu(i, vcpu, kvm) { | |
976 | struct kvmppc_icp *icp = vcpu->arch.icp; | |
977 | union kvmppc_icp_state state; | |
978 | ||
979 | if (!icp) | |
980 | continue; | |
981 | ||
5ee07612 | 982 | state.raw = READ_ONCE(icp->state.raw); |
bc5ad3f3 BH |
983 | seq_printf(m, "cpu server %#lx XIRR:%#x PPRI:%#x CPPR:%#x MFRR:%#x OUT:%d NR:%d\n", |
984 | icp->server_num, state.xisr, | |
985 | state.pending_pri, state.cppr, state.mfrr, | |
986 | state.out_ee, state.need_resend); | |
878610fe SW |
987 | t_rm_kick_vcpu += icp->n_rm_kick_vcpu; |
988 | t_rm_notify_eoi += icp->n_rm_notify_eoi; | |
989 | t_rm_check_resend += icp->n_rm_check_resend; | |
6e0365b7 SW |
990 | t_check_resend += icp->n_check_resend; |
991 | t_reject += icp->n_reject; | |
bc5ad3f3 BH |
992 | } |
993 | ||
5efa6605 | 994 | seq_printf(m, "ICP Guest->Host totals: kick_vcpu=%lu check_resend=%lu notify_eoi=%lu\n", |
878610fe | 995 | t_rm_kick_vcpu, t_rm_check_resend, |
5efa6605 | 996 | t_rm_notify_eoi); |
6e0365b7 SW |
997 | seq_printf(m, "ICP Real Mode totals: check_resend=%lu resend=%lu\n", |
998 | t_check_resend, t_reject); | |
bc5ad3f3 BH |
999 | for (icsid = 0; icsid <= KVMPPC_XICS_MAX_ICS_ID; icsid++) { |
1000 | struct kvmppc_ics *ics = xics->ics[icsid]; | |
1001 | ||
1002 | if (!ics) | |
1003 | continue; | |
1004 | ||
1005 | seq_printf(m, "=========\nICS state for ICS 0x%x\n=========\n", | |
1006 | icsid); | |
1007 | ||
34cb7954 SW |
1008 | local_irq_save(flags); |
1009 | arch_spin_lock(&ics->lock); | |
bc5ad3f3 BH |
1010 | |
1011 | for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) { | |
1012 | struct ics_irq_state *irq = &ics->irq_state[i]; | |
1013 | ||
17d48610 | 1014 | seq_printf(m, "irq 0x%06x: server %#x prio %#x save prio %#x pq_state %d resend %d masked pending %d\n", |
bc5ad3f3 | 1015 | irq->number, irq->server, irq->priority, |
17d48610 | 1016 | irq->saved_priority, irq->pq_state, |
bc5ad3f3 BH |
1017 | irq->resend, irq->masked_pending); |
1018 | ||
1019 | } | |
34cb7954 SW |
1020 | arch_spin_unlock(&ics->lock); |
1021 | local_irq_restore(flags); | |
bc5ad3f3 BH |
1022 | } |
1023 | return 0; | |
1024 | } | |
1025 | ||
1026 | static int xics_debug_open(struct inode *inode, struct file *file) | |
1027 | { | |
1028 | return single_open(file, xics_debug_show, inode->i_private); | |
1029 | } | |
1030 | ||
1031 | static const struct file_operations xics_debug_fops = { | |
1032 | .open = xics_debug_open, | |
1033 | .read = seq_read, | |
1034 | .llseek = seq_lseek, | |
1035 | .release = single_release, | |
1036 | }; | |
1037 | ||
1038 | static void xics_debugfs_init(struct kvmppc_xics *xics) | |
1039 | { | |
1040 | char *name; | |
1041 | ||
1042 | name = kasprintf(GFP_KERNEL, "kvm-xics-%p", xics); | |
1043 | if (!name) { | |
1044 | pr_err("%s: no memory for name\n", __func__); | |
1045 | return; | |
1046 | } | |
1047 | ||
1048 | xics->dentry = debugfs_create_file(name, S_IRUGO, powerpc_debugfs_root, | |
1049 | xics, &xics_debug_fops); | |
1050 | ||
1051 | pr_debug("%s: created %s\n", __func__, name); | |
1052 | kfree(name); | |
1053 | } | |
1054 | ||
5975a2e0 PM |
1055 | static struct kvmppc_ics *kvmppc_xics_create_ics(struct kvm *kvm, |
1056 | struct kvmppc_xics *xics, int irq) | |
bc5ad3f3 BH |
1057 | { |
1058 | struct kvmppc_ics *ics; | |
1059 | int i, icsid; | |
1060 | ||
1061 | icsid = irq >> KVMPPC_XICS_ICS_SHIFT; | |
1062 | ||
1063 | mutex_lock(&kvm->lock); | |
1064 | ||
1065 | /* ICS already exists - somebody else got here first */ | |
1066 | if (xics->ics[icsid]) | |
1067 | goto out; | |
1068 | ||
1069 | /* Create the ICS */ | |
1070 | ics = kzalloc(sizeof(struct kvmppc_ics), GFP_KERNEL); | |
1071 | if (!ics) | |
1072 | goto out; | |
1073 | ||
bc5ad3f3 BH |
1074 | ics->icsid = icsid; |
1075 | ||
1076 | for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) { | |
1077 | ics->irq_state[i].number = (icsid << KVMPPC_XICS_ICS_SHIFT) | i; | |
1078 | ics->irq_state[i].priority = MASKED; | |
1079 | ics->irq_state[i].saved_priority = MASKED; | |
1080 | } | |
1081 | smp_wmb(); | |
1082 | xics->ics[icsid] = ics; | |
1083 | ||
1084 | if (icsid > xics->max_icsid) | |
1085 | xics->max_icsid = icsid; | |
1086 | ||
1087 | out: | |
1088 | mutex_unlock(&kvm->lock); | |
1089 | return xics->ics[icsid]; | |
1090 | } | |
1091 | ||
1092 | int kvmppc_xics_create_icp(struct kvm_vcpu *vcpu, unsigned long server_num) | |
1093 | { | |
1094 | struct kvmppc_icp *icp; | |
1095 | ||
1096 | if (!vcpu->kvm->arch.xics) | |
1097 | return -ENODEV; | |
1098 | ||
1099 | if (kvmppc_xics_find_server(vcpu->kvm, server_num)) | |
1100 | return -EEXIST; | |
1101 | ||
1102 | icp = kzalloc(sizeof(struct kvmppc_icp), GFP_KERNEL); | |
1103 | if (!icp) | |
1104 | return -ENOMEM; | |
1105 | ||
1106 | icp->vcpu = vcpu; | |
1107 | icp->server_num = server_num; | |
1108 | icp->state.mfrr = MASKED; | |
1109 | icp->state.pending_pri = MASKED; | |
1110 | vcpu->arch.icp = icp; | |
1111 | ||
1112 | XICS_DBG("created server for vcpu %d\n", vcpu->vcpu_id); | |
1113 | ||
1114 | return 0; | |
1115 | } | |
1116 | ||
8b78645c PM |
1117 | u64 kvmppc_xics_get_icp(struct kvm_vcpu *vcpu) |
1118 | { | |
1119 | struct kvmppc_icp *icp = vcpu->arch.icp; | |
1120 | union kvmppc_icp_state state; | |
1121 | ||
1122 | if (!icp) | |
1123 | return 0; | |
1124 | state = icp->state; | |
1125 | return ((u64)state.cppr << KVM_REG_PPC_ICP_CPPR_SHIFT) | | |
1126 | ((u64)state.xisr << KVM_REG_PPC_ICP_XISR_SHIFT) | | |
1127 | ((u64)state.mfrr << KVM_REG_PPC_ICP_MFRR_SHIFT) | | |
1128 | ((u64)state.pending_pri << KVM_REG_PPC_ICP_PPRI_SHIFT); | |
1129 | } | |
1130 | ||
1131 | int kvmppc_xics_set_icp(struct kvm_vcpu *vcpu, u64 icpval) | |
1132 | { | |
1133 | struct kvmppc_icp *icp = vcpu->arch.icp; | |
1134 | struct kvmppc_xics *xics = vcpu->kvm->arch.xics; | |
1135 | union kvmppc_icp_state old_state, new_state; | |
1136 | struct kvmppc_ics *ics; | |
1137 | u8 cppr, mfrr, pending_pri; | |
1138 | u32 xisr; | |
1139 | u16 src; | |
1140 | bool resend; | |
1141 | ||
1142 | if (!icp || !xics) | |
1143 | return -ENOENT; | |
1144 | ||
1145 | cppr = icpval >> KVM_REG_PPC_ICP_CPPR_SHIFT; | |
1146 | xisr = (icpval >> KVM_REG_PPC_ICP_XISR_SHIFT) & | |
1147 | KVM_REG_PPC_ICP_XISR_MASK; | |
1148 | mfrr = icpval >> KVM_REG_PPC_ICP_MFRR_SHIFT; | |
1149 | pending_pri = icpval >> KVM_REG_PPC_ICP_PPRI_SHIFT; | |
1150 | ||
1151 | /* Require the new state to be internally consistent */ | |
1152 | if (xisr == 0) { | |
1153 | if (pending_pri != 0xff) | |
1154 | return -EINVAL; | |
1155 | } else if (xisr == XICS_IPI) { | |
1156 | if (pending_pri != mfrr || pending_pri >= cppr) | |
1157 | return -EINVAL; | |
1158 | } else { | |
1159 | if (pending_pri >= mfrr || pending_pri >= cppr) | |
1160 | return -EINVAL; | |
1161 | ics = kvmppc_xics_find_ics(xics, xisr, &src); | |
1162 | if (!ics) | |
1163 | return -EINVAL; | |
1164 | } | |
1165 | ||
1166 | new_state.raw = 0; | |
1167 | new_state.cppr = cppr; | |
1168 | new_state.xisr = xisr; | |
1169 | new_state.mfrr = mfrr; | |
1170 | new_state.pending_pri = pending_pri; | |
1171 | ||
1172 | /* | |
1173 | * Deassert the CPU interrupt request. | |
1174 | * icp_try_update will reassert it if necessary. | |
1175 | */ | |
1176 | kvmppc_book3s_dequeue_irqprio(icp->vcpu, | |
1177 | BOOK3S_INTERRUPT_EXTERNAL_LEVEL); | |
1178 | ||
1179 | /* | |
1180 | * Note that if we displace an interrupt from old_state.xisr, | |
1181 | * we don't mark it as rejected. We expect userspace to set | |
1182 | * the state of the interrupt sources to be consistent with | |
1183 | * the ICP states (either before or afterwards, which doesn't | |
1184 | * matter). We do handle resends due to CPPR becoming less | |
1185 | * favoured because that is necessary to end up with a | |
1186 | * consistent state in the situation where userspace restores | |
1187 | * the ICS states before the ICP states. | |
1188 | */ | |
1189 | do { | |
5ee07612 | 1190 | old_state = READ_ONCE(icp->state); |
8b78645c PM |
1191 | |
1192 | if (new_state.mfrr <= old_state.mfrr) { | |
1193 | resend = false; | |
1194 | new_state.need_resend = old_state.need_resend; | |
1195 | } else { | |
1196 | resend = old_state.need_resend; | |
1197 | new_state.need_resend = 0; | |
1198 | } | |
1199 | } while (!icp_try_update(icp, old_state, new_state, false)); | |
1200 | ||
1201 | if (resend) | |
1202 | icp_check_resend(xics, icp); | |
1203 | ||
1204 | return 0; | |
1205 | } | |
1206 | ||
5975a2e0 PM |
1207 | static int xics_get_source(struct kvmppc_xics *xics, long irq, u64 addr) |
1208 | { | |
1209 | int ret; | |
1210 | struct kvmppc_ics *ics; | |
1211 | struct ics_irq_state *irqp; | |
1212 | u64 __user *ubufp = (u64 __user *) addr; | |
1213 | u16 idx; | |
1214 | u64 val, prio; | |
34cb7954 | 1215 | unsigned long flags; |
5975a2e0 PM |
1216 | |
1217 | ics = kvmppc_xics_find_ics(xics, irq, &idx); | |
1218 | if (!ics) | |
1219 | return -ENOENT; | |
bc5ad3f3 | 1220 | |
5975a2e0 | 1221 | irqp = &ics->irq_state[idx]; |
34cb7954 SW |
1222 | local_irq_save(flags); |
1223 | arch_spin_lock(&ics->lock); | |
5975a2e0 PM |
1224 | ret = -ENOENT; |
1225 | if (irqp->exists) { | |
1226 | val = irqp->server; | |
1227 | prio = irqp->priority; | |
1228 | if (prio == MASKED) { | |
1229 | val |= KVM_XICS_MASKED; | |
1230 | prio = irqp->saved_priority; | |
1231 | } | |
1232 | val |= prio << KVM_XICS_PRIORITY_SHIFT; | |
b1a4286b PM |
1233 | if (irqp->lsi) { |
1234 | val |= KVM_XICS_LEVEL_SENSITIVE; | |
17d48610 | 1235 | if (irqp->pq_state & PQ_PRESENTED) |
b1a4286b PM |
1236 | val |= KVM_XICS_PENDING; |
1237 | } else if (irqp->masked_pending || irqp->resend) | |
5975a2e0 | 1238 | val |= KVM_XICS_PENDING; |
17d48610 LZ |
1239 | |
1240 | if (irqp->pq_state & PQ_PRESENTED) | |
1241 | val |= KVM_XICS_PRESENTED; | |
1242 | ||
1243 | if (irqp->pq_state & PQ_QUEUED) | |
1244 | val |= KVM_XICS_QUEUED; | |
1245 | ||
5975a2e0 PM |
1246 | ret = 0; |
1247 | } | |
34cb7954 SW |
1248 | arch_spin_unlock(&ics->lock); |
1249 | local_irq_restore(flags); | |
5975a2e0 PM |
1250 | |
1251 | if (!ret && put_user(val, ubufp)) | |
1252 | ret = -EFAULT; | |
1253 | ||
1254 | return ret; | |
1255 | } | |
1256 | ||
1257 | static int xics_set_source(struct kvmppc_xics *xics, long irq, u64 addr) | |
bc5ad3f3 | 1258 | { |
5975a2e0 PM |
1259 | struct kvmppc_ics *ics; |
1260 | struct ics_irq_state *irqp; | |
1261 | u64 __user *ubufp = (u64 __user *) addr; | |
1262 | u16 idx; | |
1263 | u64 val; | |
1264 | u8 prio; | |
1265 | u32 server; | |
34cb7954 | 1266 | unsigned long flags; |
5975a2e0 PM |
1267 | |
1268 | if (irq < KVMPPC_XICS_FIRST_IRQ || irq >= KVMPPC_XICS_NR_IRQS) | |
1269 | return -ENOENT; | |
1270 | ||
1271 | ics = kvmppc_xics_find_ics(xics, irq, &idx); | |
1272 | if (!ics) { | |
1273 | ics = kvmppc_xics_create_ics(xics->kvm, xics, irq); | |
1274 | if (!ics) | |
1275 | return -ENOMEM; | |
1276 | } | |
1277 | irqp = &ics->irq_state[idx]; | |
1278 | if (get_user(val, ubufp)) | |
1279 | return -EFAULT; | |
1280 | ||
1281 | server = val & KVM_XICS_DESTINATION_MASK; | |
1282 | prio = val >> KVM_XICS_PRIORITY_SHIFT; | |
1283 | if (prio != MASKED && | |
1284 | kvmppc_xics_find_server(xics->kvm, server) == NULL) | |
1285 | return -EINVAL; | |
bc5ad3f3 | 1286 | |
34cb7954 SW |
1287 | local_irq_save(flags); |
1288 | arch_spin_lock(&ics->lock); | |
5975a2e0 PM |
1289 | irqp->server = server; |
1290 | irqp->saved_priority = prio; | |
1291 | if (val & KVM_XICS_MASKED) | |
1292 | prio = MASKED; | |
1293 | irqp->priority = prio; | |
1294 | irqp->resend = 0; | |
1295 | irqp->masked_pending = 0; | |
b1a4286b | 1296 | irqp->lsi = 0; |
17d48610 LZ |
1297 | irqp->pq_state = 0; |
1298 | if (val & KVM_XICS_LEVEL_SENSITIVE) | |
b1a4286b | 1299 | irqp->lsi = 1; |
17d48610 LZ |
1300 | /* If PENDING, set P in case P is not saved because of old code */ |
1301 | if (val & KVM_XICS_PRESENTED || val & KVM_XICS_PENDING) | |
1302 | irqp->pq_state |= PQ_PRESENTED; | |
1303 | if (val & KVM_XICS_QUEUED) | |
1304 | irqp->pq_state |= PQ_QUEUED; | |
5975a2e0 | 1305 | irqp->exists = 1; |
34cb7954 SW |
1306 | arch_spin_unlock(&ics->lock); |
1307 | local_irq_restore(flags); | |
bc5ad3f3 | 1308 | |
5975a2e0 PM |
1309 | if (val & KVM_XICS_PENDING) |
1310 | icp_deliver_irq(xics, NULL, irqp->number); | |
bc5ad3f3 | 1311 | |
5975a2e0 PM |
1312 | return 0; |
1313 | } | |
1314 | ||
1315 | int kvm_set_irq(struct kvm *kvm, int irq_source_id, u32 irq, int level, | |
1316 | bool line_status) | |
1317 | { | |
1318 | struct kvmppc_xics *xics = kvm->arch.xics; | |
1319 | ||
e48ba1cb PM |
1320 | if (!xics) |
1321 | return -ENODEV; | |
25a2150b PM |
1322 | return ics_deliver_irq(xics, irq, level); |
1323 | } | |
1324 | ||
b1a4286b PM |
1325 | int kvm_arch_set_irq_inatomic(struct kvm_kernel_irq_routing_entry *irq_entry, |
1326 | struct kvm *kvm, int irq_source_id, | |
1327 | int level, bool line_status) | |
25a2150b | 1328 | { |
25a2150b PM |
1329 | return kvm_set_irq(kvm, irq_source_id, irq_entry->gsi, |
1330 | level, line_status); | |
5975a2e0 PM |
1331 | } |
1332 | ||
1333 | static int xics_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr) | |
1334 | { | |
1335 | struct kvmppc_xics *xics = dev->private; | |
1336 | ||
1337 | switch (attr->group) { | |
1338 | case KVM_DEV_XICS_GRP_SOURCES: | |
1339 | return xics_set_source(xics, attr->attr, attr->addr); | |
bc5ad3f3 | 1340 | } |
5975a2e0 PM |
1341 | return -ENXIO; |
1342 | } | |
bc5ad3f3 | 1343 | |
5975a2e0 PM |
1344 | static int xics_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
1345 | { | |
1346 | struct kvmppc_xics *xics = dev->private; | |
1347 | ||
1348 | switch (attr->group) { | |
1349 | case KVM_DEV_XICS_GRP_SOURCES: | |
1350 | return xics_get_source(xics, attr->attr, attr->addr); | |
1351 | } | |
1352 | return -ENXIO; | |
bc5ad3f3 BH |
1353 | } |
1354 | ||
5975a2e0 | 1355 | static int xics_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr) |
bc5ad3f3 | 1356 | { |
5975a2e0 PM |
1357 | switch (attr->group) { |
1358 | case KVM_DEV_XICS_GRP_SOURCES: | |
1359 | if (attr->attr >= KVMPPC_XICS_FIRST_IRQ && | |
1360 | attr->attr < KVMPPC_XICS_NR_IRQS) | |
1361 | return 0; | |
1362 | break; | |
1363 | } | |
1364 | return -ENXIO; | |
1365 | } | |
1366 | ||
1367 | static void kvmppc_xics_free(struct kvm_device *dev) | |
1368 | { | |
1369 | struct kvmppc_xics *xics = dev->private; | |
bc5ad3f3 BH |
1370 | int i; |
1371 | struct kvm *kvm = xics->kvm; | |
1372 | ||
1373 | debugfs_remove(xics->dentry); | |
1374 | ||
1375 | if (kvm) | |
1376 | kvm->arch.xics = NULL; | |
1377 | ||
1378 | for (i = 0; i <= xics->max_icsid; i++) | |
1379 | kfree(xics->ics[i]); | |
1380 | kfree(xics); | |
5975a2e0 | 1381 | kfree(dev); |
bc5ad3f3 BH |
1382 | } |
1383 | ||
5975a2e0 | 1384 | static int kvmppc_xics_create(struct kvm_device *dev, u32 type) |
bc5ad3f3 BH |
1385 | { |
1386 | struct kvmppc_xics *xics; | |
5975a2e0 | 1387 | struct kvm *kvm = dev->kvm; |
bc5ad3f3 BH |
1388 | int ret = 0; |
1389 | ||
1390 | xics = kzalloc(sizeof(*xics), GFP_KERNEL); | |
1391 | if (!xics) | |
1392 | return -ENOMEM; | |
1393 | ||
5975a2e0 PM |
1394 | dev->private = xics; |
1395 | xics->dev = dev; | |
bc5ad3f3 BH |
1396 | xics->kvm = kvm; |
1397 | ||
1398 | /* Already there ? */ | |
bc5ad3f3 BH |
1399 | if (kvm->arch.xics) |
1400 | ret = -EEXIST; | |
1401 | else | |
1402 | kvm->arch.xics = xics; | |
bc5ad3f3 | 1403 | |
458ff3c0 GN |
1404 | if (ret) { |
1405 | kfree(xics); | |
bc5ad3f3 | 1406 | return ret; |
458ff3c0 | 1407 | } |
bc5ad3f3 | 1408 | |
3a167bea | 1409 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
e7d26f28 BH |
1410 | if (cpu_has_feature(CPU_FTR_ARCH_206)) { |
1411 | /* Enable real mode support */ | |
1412 | xics->real_mode = ENABLE_REALMODE; | |
1413 | xics->real_mode_dbg = DEBUG_REALMODE; | |
1414 | } | |
3a167bea | 1415 | #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */ |
e7d26f28 | 1416 | |
bc5ad3f3 BH |
1417 | return 0; |
1418 | } | |
1419 | ||
023e9fdd CD |
1420 | static void kvmppc_xics_init(struct kvm_device *dev) |
1421 | { | |
1422 | struct kvmppc_xics *xics = (struct kvmppc_xics *)dev->private; | |
1423 | ||
1424 | xics_debugfs_init(xics); | |
1425 | } | |
1426 | ||
5975a2e0 PM |
1427 | struct kvm_device_ops kvm_xics_ops = { |
1428 | .name = "kvm-xics", | |
1429 | .create = kvmppc_xics_create, | |
023e9fdd | 1430 | .init = kvmppc_xics_init, |
5975a2e0 PM |
1431 | .destroy = kvmppc_xics_free, |
1432 | .set_attr = xics_set_attr, | |
1433 | .get_attr = xics_get_attr, | |
1434 | .has_attr = xics_has_attr, | |
1435 | }; | |
1436 | ||
1437 | int kvmppc_xics_connect_vcpu(struct kvm_device *dev, struct kvm_vcpu *vcpu, | |
1438 | u32 xcpu) | |
1439 | { | |
1440 | struct kvmppc_xics *xics = dev->private; | |
1441 | int r = -EBUSY; | |
1442 | ||
1443 | if (dev->ops != &kvm_xics_ops) | |
1444 | return -EPERM; | |
1445 | if (xics->kvm != vcpu->kvm) | |
1446 | return -EPERM; | |
1447 | if (vcpu->arch.irq_type) | |
1448 | return -EBUSY; | |
1449 | ||
1450 | r = kvmppc_xics_create_icp(vcpu, xcpu); | |
1451 | if (!r) | |
1452 | vcpu->arch.irq_type = KVMPPC_IRQ_XICS; | |
1453 | ||
1454 | return r; | |
1455 | } | |
1456 | ||
bc5ad3f3 BH |
1457 | void kvmppc_xics_free_icp(struct kvm_vcpu *vcpu) |
1458 | { | |
1459 | if (!vcpu->arch.icp) | |
1460 | return; | |
1461 | kfree(vcpu->arch.icp); | |
1462 | vcpu->arch.icp = NULL; | |
1463 | vcpu->arch.irq_type = KVMPPC_IRQ_DEFAULT; | |
1464 | } | |
25a2150b PM |
1465 | |
1466 | static int xics_set_irq(struct kvm_kernel_irq_routing_entry *e, | |
1467 | struct kvm *kvm, int irq_source_id, int level, | |
1468 | bool line_status) | |
1469 | { | |
1470 | return kvm_set_irq(kvm, irq_source_id, e->gsi, level, line_status); | |
1471 | } | |
1472 | ||
1473 | int kvm_irq_map_gsi(struct kvm *kvm, | |
1474 | struct kvm_kernel_irq_routing_entry *entries, int gsi) | |
1475 | { | |
1476 | entries->gsi = gsi; | |
1477 | entries->type = KVM_IRQ_ROUTING_IRQCHIP; | |
1478 | entries->set = xics_set_irq; | |
1479 | entries->irqchip.irqchip = 0; | |
1480 | entries->irqchip.pin = gsi; | |
1481 | return 1; | |
1482 | } | |
1483 | ||
1484 | int kvm_irq_map_chip_pin(struct kvm *kvm, unsigned irqchip, unsigned pin) | |
1485 | { | |
1486 | return pin; | |
1487 | } | |
5d375199 PM |
1488 | |
1489 | void kvmppc_xics_set_mapped(struct kvm *kvm, unsigned long irq, | |
1490 | unsigned long host_irq) | |
1491 | { | |
1492 | struct kvmppc_xics *xics = kvm->arch.xics; | |
1493 | struct kvmppc_ics *ics; | |
1494 | u16 idx; | |
1495 | ||
1496 | ics = kvmppc_xics_find_ics(xics, irq, &idx); | |
1497 | if (!ics) | |
1498 | return; | |
1499 | ||
1500 | ics->irq_state[idx].host_irq = host_irq; | |
1501 | ics->irq_state[idx].intr_cpu = -1; | |
1502 | } | |
1503 | EXPORT_SYMBOL_GPL(kvmppc_xics_set_mapped); | |
1504 | ||
1505 | void kvmppc_xics_clr_mapped(struct kvm *kvm, unsigned long irq, | |
1506 | unsigned long host_irq) | |
1507 | { | |
1508 | struct kvmppc_xics *xics = kvm->arch.xics; | |
1509 | struct kvmppc_ics *ics; | |
1510 | u16 idx; | |
1511 | ||
1512 | ics = kvmppc_xics_find_ics(xics, irq, &idx); | |
1513 | if (!ics) | |
1514 | return; | |
1515 | ||
1516 | ics->irq_state[idx].host_irq = 0; | |
1517 | } | |
1518 | EXPORT_SYMBOL_GPL(kvmppc_xics_clr_mapped); |