Commit | Line | Data |
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de56a948 PM |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> | |
12 | * | |
13 | * Derived from book3s_rmhandlers.S and other files, which are: | |
14 | * | |
15 | * Copyright SUSE Linux Products GmbH 2009 | |
16 | * | |
17 | * Authors: Alexander Graf <agraf@suse.de> | |
18 | */ | |
19 | ||
20 | #include <asm/ppc_asm.h> | |
21 | #include <asm/kvm_asm.h> | |
22 | #include <asm/reg.h> | |
177339d7 | 23 | #include <asm/mmu.h> |
de56a948 | 24 | #include <asm/page.h> |
177339d7 PM |
25 | #include <asm/ptrace.h> |
26 | #include <asm/hvcall.h> | |
de56a948 PM |
27 | #include <asm/asm-offsets.h> |
28 | #include <asm/exception-64s.h> | |
f0888f70 | 29 | #include <asm/kvm_book3s_asm.h> |
f64e8084 | 30 | #include <asm/book3s/64/mmu-hash.h> |
e4e38121 | 31 | #include <asm/tm.h> |
fd7bacbc | 32 | #include <asm/opal.h> |
5af50993 | 33 | #include <asm/xive-regs.h> |
857b99e1 | 34 | #include <asm/thread_info.h> |
e4e38121 | 35 | |
2f272463 PM |
36 | /* Sign-extend HDEC if not on POWER9 */ |
37 | #define EXTEND_HDEC(reg) \ | |
38 | BEGIN_FTR_SECTION; \ | |
39 | extsw reg, reg; \ | |
40 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) | |
41 | ||
e4e38121 | 42 | #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM) |
de56a948 | 43 | |
e0b7ec05 PM |
44 | /* Values in HSTATE_NAPPING(r13) */ |
45 | #define NAPPING_CEDE 1 | |
46 | #define NAPPING_NOVCPU 2 | |
47 | ||
7ceaa6dc | 48 | /* Stack frame offsets for kvmppc_hv_entry */ |
769377f7 | 49 | #define SFS 160 |
7ceaa6dc PM |
50 | #define STACK_SLOT_TRAP (SFS-4) |
51 | #define STACK_SLOT_TID (SFS-16) | |
52 | #define STACK_SLOT_PSSCR (SFS-24) | |
53 | #define STACK_SLOT_PID (SFS-32) | |
54 | #define STACK_SLOT_IAMR (SFS-40) | |
55 | #define STACK_SLOT_CIABR (SFS-48) | |
56 | #define STACK_SLOT_DAWR (SFS-56) | |
57 | #define STACK_SLOT_DAWRX (SFS-64) | |
769377f7 | 58 | #define STACK_SLOT_HFSCR (SFS-72) |
7ceaa6dc | 59 | |
de56a948 | 60 | /* |
19ccb76a | 61 | * Call kvmppc_hv_entry in real mode. |
de56a948 PM |
62 | * Must be called with interrupts hard-disabled. |
63 | * | |
64 | * Input Registers: | |
65 | * | |
66 | * LR = return address to continue at after eventually re-enabling MMU | |
67 | */ | |
6ed179b6 | 68 | _GLOBAL_TOC(kvmppc_hv_entry_trampoline) |
218309b7 PM |
69 | mflr r0 |
70 | std r0, PPC_LR_STKOFF(r1) | |
71 | stdu r1, -112(r1) | |
de56a948 | 72 | mfmsr r10 |
8b24e69f | 73 | std r10, HSTATE_HOST_MSR(r13) |
218309b7 | 74 | LOAD_REG_ADDR(r5, kvmppc_call_hv_entry) |
de56a948 PM |
75 | li r0,MSR_RI |
76 | andc r0,r10,r0 | |
77 | li r6,MSR_IR | MSR_DR | |
78 | andc r6,r10,r6 | |
79 | mtmsrd r0,1 /* clear RI in MSR */ | |
80 | mtsrr0 r5 | |
81 | mtsrr1 r6 | |
222f20f1 | 82 | RFI_TO_KERNEL |
de56a948 | 83 | |
218309b7 | 84 | kvmppc_call_hv_entry: |
c0101509 PM |
85 | BEGIN_FTR_SECTION |
86 | /* On P9, do LPCR setting, if necessary */ | |
87 | ld r3, HSTATE_SPLIT_MODE(r13) | |
88 | cmpdi r3, 0 | |
89 | beq 46f | |
90 | lwz r4, KVM_SPLIT_DO_SET(r3) | |
91 | cmpwi r4, 0 | |
92 | beq 46f | |
93 | bl kvmhv_p9_set_lpcr | |
94 | nop | |
95 | 46: | |
96 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
97 | ||
e0b7ec05 | 98 | ld r4, HSTATE_KVM_VCPU(r13) |
218309b7 PM |
99 | bl kvmppc_hv_entry |
100 | ||
101 | /* Back from guest - restore host state and return to caller */ | |
102 | ||
eee7ff9d | 103 | BEGIN_FTR_SECTION |
218309b7 PM |
104 | /* Restore host DABR and DABRX */ |
105 | ld r5,HSTATE_DABR(r13) | |
106 | li r6,7 | |
107 | mtspr SPRN_DABR,r5 | |
108 | mtspr SPRN_DABRX,r6 | |
eee7ff9d | 109 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) |
218309b7 PM |
110 | |
111 | /* Restore SPRG3 */ | |
9d378dfa SW |
112 | ld r3,PACA_SPRG_VDSO(r13) |
113 | mtspr SPRN_SPRG_VDSO_WRITE,r3 | |
218309b7 | 114 | |
218309b7 PM |
115 | /* Reload the host's PMU registers */ |
116 | ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */ | |
117 | lbz r4, LPPACA_PMCINUSE(r3) | |
118 | cmpwi r4, 0 | |
119 | beq 23f /* skip if not */ | |
9bc01a9b | 120 | BEGIN_FTR_SECTION |
9a4fc4ea | 121 | ld r3, HSTATE_MMCR0(r13) |
9bc01a9b PM |
122 | andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO |
123 | cmpwi r4, MMCR0_PMAO | |
124 | beql kvmppc_fix_pmao | |
125 | END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG) | |
9a4fc4ea ME |
126 | lwz r3, HSTATE_PMC1(r13) |
127 | lwz r4, HSTATE_PMC2(r13) | |
128 | lwz r5, HSTATE_PMC3(r13) | |
129 | lwz r6, HSTATE_PMC4(r13) | |
130 | lwz r8, HSTATE_PMC5(r13) | |
131 | lwz r9, HSTATE_PMC6(r13) | |
218309b7 PM |
132 | mtspr SPRN_PMC1, r3 |
133 | mtspr SPRN_PMC2, r4 | |
134 | mtspr SPRN_PMC3, r5 | |
135 | mtspr SPRN_PMC4, r6 | |
136 | mtspr SPRN_PMC5, r8 | |
137 | mtspr SPRN_PMC6, r9 | |
9a4fc4ea ME |
138 | ld r3, HSTATE_MMCR0(r13) |
139 | ld r4, HSTATE_MMCR1(r13) | |
140 | ld r5, HSTATE_MMCRA(r13) | |
141 | ld r6, HSTATE_SIAR(r13) | |
142 | ld r7, HSTATE_SDAR(r13) | |
218309b7 PM |
143 | mtspr SPRN_MMCR1, r4 |
144 | mtspr SPRN_MMCRA, r5 | |
72cde5a8 PM |
145 | mtspr SPRN_SIAR, r6 |
146 | mtspr SPRN_SDAR, r7 | |
147 | BEGIN_FTR_SECTION | |
9a4fc4ea ME |
148 | ld r8, HSTATE_MMCR2(r13) |
149 | ld r9, HSTATE_SIER(r13) | |
72cde5a8 PM |
150 | mtspr SPRN_MMCR2, r8 |
151 | mtspr SPRN_SIER, r9 | |
152 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
218309b7 PM |
153 | mtspr SPRN_MMCR0, r3 |
154 | isync | |
155 | 23: | |
156 | ||
e0b7ec05 PM |
157 | /* |
158 | * Reload DEC. HDEC interrupts were disabled when | |
159 | * we reloaded the host's LPCR value. | |
160 | */ | |
161 | ld r3, HSTATE_DECEXP(r13) | |
162 | mftb r4 | |
163 | subf r4, r4, r3 | |
164 | mtspr SPRN_DEC, r4 | |
165 | ||
b4deba5c PM |
166 | /* hwthread_req may have got set by cede or no vcpu, so clear it */ |
167 | li r0, 0 | |
168 | stb r0, HSTATE_HWTHREAD_REQ(r13) | |
169 | ||
218309b7 | 170 | /* |
e20bbd3d AP |
171 | * For external interrupts we need to call the Linux |
172 | * handler to process the interrupt. We do that by jumping | |
173 | * to absolute address 0x500 for external interrupts. | |
174 | * The [h]rfid at the end of the handler will return to | |
175 | * the book3s_hv_interrupts.S code. For other interrupts | |
176 | * we do the rfid to get back to the book3s_hv_interrupts.S | |
177 | * code here. | |
218309b7 PM |
178 | */ |
179 | ld r8, 112+PPC_LR_STKOFF(r1) | |
180 | addi r1, r1, 112 | |
181 | ld r7, HSTATE_HOST_MSR(r13) | |
182 | ||
8b24e69f PM |
183 | /* Return the trap number on this thread as the return value */ |
184 | mr r3, r12 | |
185 | ||
53af3ba2 PM |
186 | /* |
187 | * If we came back from the guest via a relocation-on interrupt, | |
188 | * we will be in virtual mode at this point, which makes it a | |
189 | * little easier to get back to the caller. | |
190 | */ | |
191 | mfmsr r0 | |
192 | andi. r0, r0, MSR_IR /* in real mode? */ | |
193 | bne .Lvirt_return | |
194 | ||
8b24e69f | 195 | /* RFI into the highmem handler */ |
218309b7 PM |
196 | mfmsr r6 |
197 | li r0, MSR_RI | |
198 | andc r6, r6, r0 | |
199 | mtmsrd r6, 1 /* Clear RI in MSR */ | |
200 | mtsrr0 r8 | |
201 | mtsrr1 r7 | |
222f20f1 | 202 | RFI_TO_KERNEL |
218309b7 | 203 | |
8b24e69f | 204 | /* Virtual-mode return */ |
53af3ba2 | 205 | .Lvirt_return: |
8b24e69f | 206 | mtlr r8 |
53af3ba2 PM |
207 | blr |
208 | ||
e0b7ec05 PM |
209 | kvmppc_primary_no_guest: |
210 | /* We handle this much like a ceded vcpu */ | |
fd6d53b1 | 211 | /* put the HDEC into the DEC, since HDEC interrupts don't wake us */ |
2f272463 PM |
212 | /* HDEC may be larger than DEC for arch >= v3.00, but since the */ |
213 | /* HDEC value came from DEC in the first place, it will fit */ | |
fd6d53b1 PM |
214 | mfspr r3, SPRN_HDEC |
215 | mtspr SPRN_DEC, r3 | |
6af27c84 PM |
216 | /* |
217 | * Make sure the primary has finished the MMU switch. | |
218 | * We should never get here on a secondary thread, but | |
219 | * check it for robustness' sake. | |
220 | */ | |
221 | ld r5, HSTATE_KVM_VCORE(r13) | |
222 | 65: lbz r0, VCORE_IN_GUEST(r5) | |
223 | cmpwi r0, 0 | |
224 | beq 65b | |
225 | /* Set LPCR. */ | |
226 | ld r8,VCORE_LPCR(r5) | |
227 | mtspr SPRN_LPCR,r8 | |
228 | isync | |
e0b7ec05 PM |
229 | /* set our bit in napping_threads */ |
230 | ld r5, HSTATE_KVM_VCORE(r13) | |
231 | lbz r7, HSTATE_PTID(r13) | |
232 | li r0, 1 | |
233 | sld r0, r0, r7 | |
234 | addi r6, r5, VCORE_NAPPING_THREADS | |
235 | 1: lwarx r3, 0, r6 | |
236 | or r3, r3, r0 | |
237 | stwcx. r3, 0, r6 | |
238 | bne 1b | |
7d6c40da | 239 | /* order napping_threads update vs testing entry_exit_map */ |
e0b7ec05 PM |
240 | isync |
241 | li r12, 0 | |
242 | lwz r7, VCORE_ENTRY_EXIT(r5) | |
243 | cmpwi r7, 0x100 | |
244 | bge kvm_novcpu_exit /* another thread already exiting */ | |
245 | li r3, NAPPING_NOVCPU | |
246 | stb r3, HSTATE_NAPPING(r13) | |
e0b7ec05 | 247 | |
ccc07772 | 248 | li r3, 0 /* Don't wake on privileged (OS) doorbell */ |
e0b7ec05 PM |
249 | b kvm_do_nap |
250 | ||
37f55d30 SW |
251 | /* |
252 | * kvm_novcpu_wakeup | |
253 | * Entered from kvm_start_guest if kvm_hstate.napping is set | |
254 | * to NAPPING_NOVCPU | |
255 | * r2 = kernel TOC | |
256 | * r13 = paca | |
257 | */ | |
e0b7ec05 PM |
258 | kvm_novcpu_wakeup: |
259 | ld r1, HSTATE_HOST_R1(r13) | |
260 | ld r5, HSTATE_KVM_VCORE(r13) | |
261 | li r0, 0 | |
262 | stb r0, HSTATE_NAPPING(r13) | |
e0b7ec05 | 263 | |
e3bbbbfa PM |
264 | /* check the wake reason */ |
265 | bl kvmppc_check_wake_reason | |
6af27c84 | 266 | |
37f55d30 SW |
267 | /* |
268 | * Restore volatile registers since we could have called | |
269 | * a C routine in kvmppc_check_wake_reason. | |
270 | * r5 = VCORE | |
271 | */ | |
272 | ld r5, HSTATE_KVM_VCORE(r13) | |
273 | ||
e0b7ec05 | 274 | /* see if any other thread is already exiting */ |
e0b7ec05 PM |
275 | lwz r0, VCORE_ENTRY_EXIT(r5) |
276 | cmpwi r0, 0x100 | |
277 | bge kvm_novcpu_exit | |
278 | ||
279 | /* clear our bit in napping_threads */ | |
280 | lbz r7, HSTATE_PTID(r13) | |
281 | li r0, 1 | |
282 | sld r0, r0, r7 | |
283 | addi r6, r5, VCORE_NAPPING_THREADS | |
e3bbbbfa PM |
284 | 4: lwarx r7, 0, r6 |
285 | andc r7, r7, r0 | |
286 | stwcx. r7, 0, r6 | |
e0b7ec05 PM |
287 | bne 4b |
288 | ||
e3bbbbfa | 289 | /* See if the wake reason means we need to exit */ |
e0b7ec05 PM |
290 | cmpdi r3, 0 |
291 | bge kvm_novcpu_exit | |
e0b7ec05 | 292 | |
fd6d53b1 PM |
293 | /* See if our timeslice has expired (HDEC is negative) */ |
294 | mfspr r0, SPRN_HDEC | |
2f272463 | 295 | EXTEND_HDEC(r0) |
fd6d53b1 | 296 | li r12, BOOK3S_INTERRUPT_HV_DECREMENTER |
2f272463 | 297 | cmpdi r0, 0 |
fd6d53b1 PM |
298 | blt kvm_novcpu_exit |
299 | ||
e0b7ec05 PM |
300 | /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */ |
301 | ld r4, HSTATE_KVM_VCPU(r13) | |
302 | cmpdi r4, 0 | |
b6c295df PM |
303 | beq kvmppc_primary_no_guest |
304 | ||
305 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING | |
306 | addi r3, r4, VCPU_TB_RMENTRY | |
307 | bl kvmhv_start_timing | |
308 | #endif | |
309 | b kvmppc_got_guest | |
e0b7ec05 PM |
310 | |
311 | kvm_novcpu_exit: | |
6af27c84 PM |
312 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
313 | ld r4, HSTATE_KVM_VCPU(r13) | |
314 | cmpdi r4, 0 | |
315 | beq 13f | |
316 | addi r3, r4, VCPU_TB_RMEXIT | |
317 | bl kvmhv_accumulate_time | |
318 | #endif | |
eddb60fb | 319 | 13: mr r3, r12 |
7ceaa6dc | 320 | stw r12, STACK_SLOT_TRAP(r1) |
eddb60fb PM |
321 | bl kvmhv_commence_exit |
322 | nop | |
7ceaa6dc | 323 | lwz r12, STACK_SLOT_TRAP(r1) |
6af27c84 | 324 | b kvmhv_switch_to_host |
e0b7ec05 | 325 | |
371fefd6 | 326 | /* |
e0b7ec05 | 327 | * We come in here when wakened from nap mode. |
371fefd6 PM |
328 | * Relocation is off and most register values are lost. |
329 | * r13 points to the PACA. | |
9d292501 | 330 | * r3 contains the SRR1 wakeup value, SRR1 is trashed. |
371fefd6 PM |
331 | */ |
332 | .globl kvm_start_guest | |
333 | kvm_start_guest: | |
fd17dc7b | 334 | /* Set runlatch bit the minute you wake up from nap */ |
1f09c3ed PM |
335 | mfspr r0, SPRN_CTRLF |
336 | ori r0, r0, 1 | |
337 | mtspr SPRN_CTRLT, r0 | |
fd17dc7b | 338 | |
9d292501 NP |
339 | /* |
340 | * Could avoid this and pass it through in r3. For now, | |
341 | * code expects it to be in SRR1. | |
342 | */ | |
343 | mtspr SPRN_SRR1,r3 | |
344 | ||
19ccb76a PM |
345 | ld r2,PACATOC(r13) |
346 | ||
f0888f70 PM |
347 | li r0,KVM_HWTHREAD_IN_KVM |
348 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
371fefd6 | 349 | |
f0888f70 PM |
350 | /* NV GPR values from power7_idle() will no longer be valid */ |
351 | li r0,1 | |
352 | stb r0,PACA_NAPSTATELOST(r13) | |
371fefd6 | 353 | |
4619ac88 PM |
354 | /* were we napping due to cede? */ |
355 | lbz r0,HSTATE_NAPPING(r13) | |
e0b7ec05 PM |
356 | cmpwi r0,NAPPING_CEDE |
357 | beq kvm_end_cede | |
358 | cmpwi r0,NAPPING_NOVCPU | |
359 | beq kvm_novcpu_wakeup | |
360 | ||
361 | ld r1,PACAEMERGSP(r13) | |
362 | subi r1,r1,STACK_FRAME_OVERHEAD | |
4619ac88 PM |
363 | |
364 | /* | |
365 | * We weren't napping due to cede, so this must be a secondary | |
366 | * thread being woken up to run a guest, or being woken up due | |
367 | * to a stray IPI. (Or due to some machine check or hypervisor | |
368 | * maintenance interrupt while the core is in KVM.) | |
369 | */ | |
f0888f70 PM |
370 | |
371 | /* Check the wake reason in SRR1 to see why we got here */ | |
e3bbbbfa | 372 | bl kvmppc_check_wake_reason |
37f55d30 SW |
373 | /* |
374 | * kvmppc_check_wake_reason could invoke a C routine, but we | |
375 | * have no volatile registers to restore when we return. | |
376 | */ | |
377 | ||
e3bbbbfa PM |
378 | cmpdi r3, 0 |
379 | bge kvm_no_guest | |
371fefd6 | 380 | |
b4deba5c PM |
381 | /* get vcore pointer, NULL if we have nothing to run */ |
382 | ld r5,HSTATE_KVM_VCORE(r13) | |
383 | cmpdi r5,0 | |
384 | /* if we have no vcore to run, go back to sleep */ | |
7b444c67 | 385 | beq kvm_no_guest |
f0888f70 | 386 | |
56548fc0 PM |
387 | kvm_secondary_got_guest: |
388 | ||
e0b7ec05 | 389 | /* Set HSTATE_DSCR(r13) to something sensible */ |
1db36525 | 390 | ld r6, PACA_DSCR_DEFAULT(r13) |
e0b7ec05 | 391 | std r6, HSTATE_DSCR(r13) |
2fde6d20 | 392 | |
b4deba5c PM |
393 | /* On thread 0 of a subcore, set HDEC to max */ |
394 | lbz r4, HSTATE_PTID(r13) | |
395 | cmpwi r4, 0 | |
396 | bne 63f | |
2f272463 PM |
397 | LOAD_REG_ADDR(r6, decrementer_max) |
398 | ld r6, 0(r6) | |
b4deba5c PM |
399 | mtspr SPRN_HDEC, r6 |
400 | /* and set per-LPAR registers, if doing dynamic micro-threading */ | |
401 | ld r6, HSTATE_SPLIT_MODE(r13) | |
402 | cmpdi r6, 0 | |
403 | beq 63f | |
c0101509 | 404 | BEGIN_FTR_SECTION |
b4deba5c PM |
405 | ld r0, KVM_SPLIT_RPR(r6) |
406 | mtspr SPRN_RPR, r0 | |
407 | ld r0, KVM_SPLIT_PMMAR(r6) | |
408 | mtspr SPRN_PMMAR, r0 | |
409 | ld r0, KVM_SPLIT_LDBAR(r6) | |
410 | mtspr SPRN_LDBAR, r0 | |
411 | isync | |
c0101509 PM |
412 | FTR_SECTION_ELSE |
413 | /* On P9 we use the split_info for coordinating LPCR changes */ | |
414 | lwz r4, KVM_SPLIT_DO_SET(r6) | |
415 | cmpwi r4, 0 | |
d20fe50a | 416 | beq 1f |
c0101509 PM |
417 | mr r3, r6 |
418 | bl kvmhv_p9_set_lpcr | |
419 | nop | |
d20fe50a | 420 | 1: |
c0101509 | 421 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300) |
b4deba5c PM |
422 | 63: |
423 | /* Order load of vcpu after load of vcore */ | |
5d5b99cd | 424 | lwsync |
b4deba5c | 425 | ld r4, HSTATE_KVM_VCPU(r13) |
e0b7ec05 | 426 | bl kvmppc_hv_entry |
218309b7 PM |
427 | |
428 | /* Back from the guest, go back to nap */ | |
b4deba5c | 429 | /* Clear our vcpu and vcore pointers so we don't come back in early */ |
218309b7 | 430 | li r0, 0 |
b4deba5c | 431 | std r0, HSTATE_KVM_VCPU(r13) |
f019b7ad | 432 | /* |
b4deba5c | 433 | * Once we clear HSTATE_KVM_VCORE(r13), the code in |
5d5b99cd PM |
434 | * kvmppc_run_core() is going to assume that all our vcpu |
435 | * state is visible in memory. This lwsync makes sure | |
436 | * that that is true. | |
f019b7ad | 437 | */ |
218309b7 | 438 | lwsync |
b4deba5c | 439 | std r0, HSTATE_KVM_VCORE(r13) |
218309b7 | 440 | |
fd7bacbc MS |
441 | /* |
442 | * All secondaries exiting guest will fall through this path. | |
443 | * Before proceeding, just check for HMI interrupt and | |
444 | * invoke opal hmi handler. By now we are sure that the | |
445 | * primary thread on this core/subcore has already made partition | |
446 | * switch/TB resync and we are good to call opal hmi handler. | |
447 | */ | |
448 | cmpwi r12, BOOK3S_INTERRUPT_HMI | |
449 | bne kvm_no_guest | |
450 | ||
451 | li r3,0 /* NULL argument */ | |
452 | bl hmi_exception_realmode | |
56548fc0 PM |
453 | /* |
454 | * At this point we have finished executing in the guest. | |
455 | * We need to wait for hwthread_req to become zero, since | |
456 | * we may not turn on the MMU while hwthread_req is non-zero. | |
457 | * While waiting we also need to check if we get given a vcpu to run. | |
458 | */ | |
218309b7 | 459 | kvm_no_guest: |
56548fc0 PM |
460 | lbz r3, HSTATE_HWTHREAD_REQ(r13) |
461 | cmpwi r3, 0 | |
462 | bne 53f | |
463 | HMT_MEDIUM | |
464 | li r0, KVM_HWTHREAD_IN_KERNEL | |
218309b7 | 465 | stb r0, HSTATE_HWTHREAD_STATE(r13) |
56548fc0 PM |
466 | /* need to recheck hwthread_req after a barrier, to avoid race */ |
467 | sync | |
468 | lbz r3, HSTATE_HWTHREAD_REQ(r13) | |
469 | cmpwi r3, 0 | |
470 | bne 54f | |
471 | /* | |
5fa6b6bd | 472 | * We jump to pnv_wakeup_loss, which will return to the caller |
56548fc0 | 473 | * of power7_nap in the powernv cpu offline loop. The value we |
9d292501 NP |
474 | * put in r3 becomes the return value for power7_nap. pnv_wakeup_loss |
475 | * requires SRR1 in r12. | |
56548fc0 | 476 | */ |
218309b7 PM |
477 | li r3, LPCR_PECE0 |
478 | mfspr r4, SPRN_LPCR | |
479 | rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1 | |
480 | mtspr SPRN_LPCR, r4 | |
56548fc0 | 481 | li r3, 0 |
9d292501 | 482 | mfspr r12,SPRN_SRR1 |
5fa6b6bd | 483 | b pnv_wakeup_loss |
56548fc0 PM |
484 | |
485 | 53: HMT_LOW | |
b4deba5c PM |
486 | ld r5, HSTATE_KVM_VCORE(r13) |
487 | cmpdi r5, 0 | |
488 | bne 60f | |
489 | ld r3, HSTATE_SPLIT_MODE(r13) | |
490 | cmpdi r3, 0 | |
491 | beq kvm_no_guest | |
c0101509 PM |
492 | lwz r0, KVM_SPLIT_DO_SET(r3) |
493 | cmpwi r0, 0 | |
494 | bne kvmhv_do_set | |
495 | lwz r0, KVM_SPLIT_DO_RESTORE(r3) | |
496 | cmpwi r0, 0 | |
497 | bne kvmhv_do_restore | |
b4deba5c PM |
498 | lbz r0, KVM_SPLIT_DO_NAP(r3) |
499 | cmpwi r0, 0 | |
56548fc0 PM |
500 | beq kvm_no_guest |
501 | HMT_MEDIUM | |
b4deba5c PM |
502 | b kvm_unsplit_nap |
503 | 60: HMT_MEDIUM | |
56548fc0 PM |
504 | b kvm_secondary_got_guest |
505 | ||
506 | 54: li r0, KVM_HWTHREAD_IN_KVM | |
507 | stb r0, HSTATE_HWTHREAD_STATE(r13) | |
508 | b kvm_no_guest | |
218309b7 | 509 | |
c0101509 PM |
510 | kvmhv_do_set: |
511 | /* Set LPCR, LPIDR etc. on P9 */ | |
512 | HMT_MEDIUM | |
513 | bl kvmhv_p9_set_lpcr | |
514 | nop | |
515 | b kvm_no_guest | |
516 | ||
517 | kvmhv_do_restore: | |
518 | HMT_MEDIUM | |
519 | bl kvmhv_p9_restore_lpcr | |
520 | nop | |
521 | b kvm_no_guest | |
522 | ||
b4deba5c PM |
523 | /* |
524 | * Here the primary thread is trying to return the core to | |
525 | * whole-core mode, so we need to nap. | |
526 | */ | |
527 | kvm_unsplit_nap: | |
fd7bacbc MS |
528 | /* |
529 | * When secondaries are napping in kvm_unsplit_nap() with | |
530 | * hwthread_req = 1, HMI goes ignored even though subcores are | |
531 | * already exited the guest. Hence HMI keeps waking up secondaries | |
532 | * from nap in a loop and secondaries always go back to nap since | |
533 | * no vcore is assigned to them. This makes impossible for primary | |
534 | * thread to get hold of secondary threads resulting into a soft | |
535 | * lockup in KVM path. | |
536 | * | |
537 | * Let us check if HMI is pending and handle it before we go to nap. | |
538 | */ | |
539 | cmpwi r12, BOOK3S_INTERRUPT_HMI | |
540 | bne 55f | |
541 | li r3, 0 /* NULL argument */ | |
542 | bl hmi_exception_realmode | |
543 | 55: | |
7f235328 GS |
544 | /* |
545 | * Ensure that secondary doesn't nap when it has | |
546 | * its vcore pointer set. | |
547 | */ | |
548 | sync /* matches smp_mb() before setting split_info.do_nap */ | |
549 | ld r0, HSTATE_KVM_VCORE(r13) | |
550 | cmpdi r0, 0 | |
551 | bne kvm_no_guest | |
b4deba5c PM |
552 | /* clear any pending message */ |
553 | BEGIN_FTR_SECTION | |
554 | lis r6, (PPC_DBELL_SERVER << (63-36))@h | |
555 | PPC_MSGCLR(6) | |
556 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
557 | /* Set kvm_split_mode.napped[tid] = 1 */ | |
558 | ld r3, HSTATE_SPLIT_MODE(r13) | |
559 | li r0, 1 | |
c0101509 | 560 | lbz r4, HSTATE_TID(r13) |
b4deba5c PM |
561 | addi r4, r4, KVM_SPLIT_NAPPED |
562 | stbx r0, r3, r4 | |
563 | /* Check the do_nap flag again after setting napped[] */ | |
564 | sync | |
565 | lbz r0, KVM_SPLIT_DO_NAP(r3) | |
566 | cmpwi r0, 0 | |
567 | beq 57f | |
568 | li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4 | |
bf53c88e PM |
569 | mfspr r5, SPRN_LPCR |
570 | rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1) | |
571 | b kvm_nap_sequence | |
b4deba5c PM |
572 | |
573 | 57: li r0, 0 | |
574 | stbx r0, r3, r4 | |
575 | b kvm_no_guest | |
576 | ||
218309b7 PM |
577 | /****************************************************************************** |
578 | * * | |
579 | * Entry code * | |
580 | * * | |
581 | *****************************************************************************/ | |
582 | ||
de56a948 PM |
583 | .global kvmppc_hv_entry |
584 | kvmppc_hv_entry: | |
585 | ||
586 | /* Required state: | |
587 | * | |
e0b7ec05 | 588 | * R4 = vcpu pointer (or NULL) |
de56a948 PM |
589 | * MSR = ~IR|DR |
590 | * R13 = PACA | |
591 | * R1 = host R1 | |
06a29e42 | 592 | * R2 = TOC |
de56a948 | 593 | * all other volatile GPRS = free |
f4c51f84 | 594 | * Does not preserve non-volatile GPRs or CR fields |
de56a948 PM |
595 | */ |
596 | mflr r0 | |
218309b7 | 597 | std r0, PPC_LR_STKOFF(r1) |
7ceaa6dc | 598 | stdu r1, -SFS(r1) |
de56a948 | 599 | |
de56a948 PM |
600 | /* Save R1 in the PACA */ |
601 | std r1, HSTATE_HOST_R1(r13) | |
602 | ||
44a3add8 PM |
603 | li r6, KVM_GUEST_MODE_HOST_HV |
604 | stb r6, HSTATE_IN_GUEST(r13) | |
605 | ||
b6c295df PM |
606 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
607 | /* Store initial timestamp */ | |
608 | cmpdi r4, 0 | |
609 | beq 1f | |
610 | addi r3, r4, VCPU_TB_RMENTRY | |
611 | bl kvmhv_start_timing | |
612 | 1: | |
613 | #endif | |
f4c51f84 PM |
614 | |
615 | /* Use cr7 as an indication of radix mode */ | |
616 | ld r5, HSTATE_KVM_VCORE(r13) | |
617 | ld r9, VCORE_KVM(r5) /* pointer to struct kvm */ | |
618 | lbz r0, KVM_RADIX(r9) | |
619 | cmpwi cr7, r0, 0 | |
620 | ||
9e368f29 | 621 | /* |
c17b98cf | 622 | * POWER7/POWER8 host -> guest partition switch code. |
9e368f29 PM |
623 | * We don't have to lock against concurrent tlbies, |
624 | * but we do have to coordinate across hardware threads. | |
625 | */ | |
7d6c40da | 626 | /* Set bit in entry map iff exit map is zero. */ |
7d6c40da PM |
627 | li r7, 1 |
628 | lbz r6, HSTATE_PTID(r13) | |
629 | sld r7, r7, r6 | |
f4c51f84 PM |
630 | addi r8, r5, VCORE_ENTRY_EXIT |
631 | 21: lwarx r3, 0, r8 | |
7d6c40da | 632 | cmpwi r3, 0x100 /* any threads starting to exit? */ |
371fefd6 | 633 | bge secondary_too_late /* if so we're too late to the party */ |
7d6c40da | 634 | or r3, r3, r7 |
f4c51f84 | 635 | stwcx. r3, 0, r8 |
371fefd6 PM |
636 | bne 21b |
637 | ||
638 | /* Primary thread switches to guest partition. */ | |
371fefd6 | 639 | cmpwi r6,0 |
6af27c84 | 640 | bne 10f |
de56a948 | 641 | lwz r7,KVM_LPID(r9) |
7a84084c PM |
642 | BEGIN_FTR_SECTION |
643 | ld r6,KVM_SDR1(r9) | |
de56a948 PM |
644 | li r0,LPID_RSVD /* switch to reserved LPID */ |
645 | mtspr SPRN_LPID,r0 | |
646 | ptesync | |
647 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
7a84084c | 648 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) |
de56a948 PM |
649 | mtspr SPRN_LPID,r7 |
650 | isync | |
1b400ba0 PM |
651 | |
652 | /* See if we need to flush the TLB */ | |
653 | lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */ | |
a29ebeaf PM |
654 | BEGIN_FTR_SECTION |
655 | /* | |
656 | * On POWER9, individual threads can come in here, but the | |
657 | * TLB is shared between the 4 threads in a core, hence | |
658 | * invalidating on one thread invalidates for all. | |
659 | * Thus we make all 4 threads use the same bit here. | |
660 | */ | |
661 | clrrdi r6,r6,2 | |
662 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
1b400ba0 PM |
663 | clrldi r7,r6,64-6 /* extract bit number (6 bits) */ |
664 | srdi r6,r6,6 /* doubleword number */ | |
665 | sldi r6,r6,3 /* address offset */ | |
666 | add r6,r6,r9 | |
667 | addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */ | |
a29ebeaf PM |
668 | li r8,1 |
669 | sld r8,r8,r7 | |
1b400ba0 | 670 | ld r7,0(r6) |
a29ebeaf | 671 | and. r7,r7,r8 |
1b400ba0 | 672 | beq 22f |
ca252055 | 673 | /* Flush the TLB of any entries for this LPID */ |
a29ebeaf PM |
674 | lwz r0,KVM_TLB_SETS(r9) |
675 | mtctr r0 | |
1b400ba0 PM |
676 | li r7,0x800 /* IS field = 0b10 */ |
677 | ptesync | |
a29ebeaf PM |
678 | li r0,0 /* RS for P9 version of tlbiel */ |
679 | bne cr7, 29f | |
680 | 28: tlbiel r7 /* On P9, rs=0, RIC=0, PRS=0, R=0 */ | |
1b400ba0 PM |
681 | addi r7,r7,0x1000 |
682 | bdnz 28b | |
a29ebeaf PM |
683 | b 30f |
684 | 29: PPC_TLBIEL(7,0,2,1,1) /* for radix, RIC=2, PRS=1, R=1 */ | |
685 | addi r7,r7,0x1000 | |
686 | bdnz 29b | |
687 | 30: ptesync | |
688 | 23: ldarx r7,0,r6 /* clear the bit after TLB flushed */ | |
689 | andc r7,r7,r8 | |
690 | stdcx. r7,0,r6 | |
691 | bne 23b | |
1b400ba0 | 692 | |
93b0f4dc PM |
693 | /* Add timebase offset onto timebase */ |
694 | 22: ld r8,VCORE_TB_OFFSET(r5) | |
695 | cmpdi r8,0 | |
696 | beq 37f | |
697 | mftb r6 /* current host timebase */ | |
698 | add r8,r8,r6 | |
699 | mtspr SPRN_TBU40,r8 /* update upper 40 bits */ | |
700 | mftb r7 /* check if lower 24 bits overflowed */ | |
701 | clrldi r6,r6,40 | |
702 | clrldi r7,r7,40 | |
703 | cmpld r7,r6 | |
704 | bge 37f | |
705 | addis r8,r8,0x100 /* if so, increment upper 40 bits */ | |
706 | mtspr SPRN_TBU40,r8 | |
707 | ||
388cc6e1 PM |
708 | /* Load guest PCR value to select appropriate compat mode */ |
709 | 37: ld r7, VCORE_PCR(r5) | |
710 | cmpdi r7, 0 | |
711 | beq 38f | |
712 | mtspr SPRN_PCR, r7 | |
713 | 38: | |
b005255e MN |
714 | |
715 | BEGIN_FTR_SECTION | |
88b02cf9 | 716 | /* DPDES and VTB are shared between threads */ |
b005255e | 717 | ld r8, VCORE_DPDES(r5) |
88b02cf9 | 718 | ld r7, VCORE_VTB(r5) |
b005255e | 719 | mtspr SPRN_DPDES, r8 |
88b02cf9 | 720 | mtspr SPRN_VTB, r7 |
b005255e MN |
721 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
722 | ||
fd7bacbc MS |
723 | /* Mark the subcore state as inside guest */ |
724 | bl kvmppc_subcore_enter_guest | |
725 | nop | |
726 | ld r5, HSTATE_KVM_VCORE(r13) | |
727 | ld r4, HSTATE_KVM_VCPU(r13) | |
388cc6e1 | 728 | li r0,1 |
371fefd6 | 729 | stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */ |
9e368f29 | 730 | |
e0b7ec05 | 731 | /* Do we have a guest vcpu to run? */ |
6af27c84 | 732 | 10: cmpdi r4, 0 |
e0b7ec05 PM |
733 | beq kvmppc_primary_no_guest |
734 | kvmppc_got_guest: | |
e0b7ec05 PM |
735 | /* Increment yield count if they have a VPA */ |
736 | ld r3, VCPU_VPA(r4) | |
737 | cmpdi r3, 0 | |
738 | beq 25f | |
0865a583 AG |
739 | li r6, LPPACA_YIELDCOUNT |
740 | LWZX_BE r5, r3, r6 | |
e0b7ec05 | 741 | addi r5, r5, 1 |
0865a583 | 742 | STWX_BE r5, r3, r6 |
e0b7ec05 PM |
743 | li r6, 1 |
744 | stb r6, VCPU_VPA_DIRTY(r4) | |
745 | 25: | |
746 | ||
e0b7ec05 PM |
747 | /* Save purr/spurr */ |
748 | mfspr r5,SPRN_PURR | |
749 | mfspr r6,SPRN_SPURR | |
750 | std r5,HSTATE_PURR(r13) | |
751 | std r6,HSTATE_SPURR(r13) | |
752 | ld r7,VCPU_PURR(r4) | |
753 | ld r8,VCPU_SPURR(r4) | |
754 | mtspr SPRN_PURR,r7 | |
755 | mtspr SPRN_SPURR,r8 | |
e0b7ec05 | 756 | |
e9cf1e08 PM |
757 | /* Save host values of some registers */ |
758 | BEGIN_FTR_SECTION | |
759 | mfspr r5, SPRN_TIDR | |
760 | mfspr r6, SPRN_PSSCR | |
f4c51f84 | 761 | mfspr r7, SPRN_PID |
4c3bb4cc | 762 | mfspr r8, SPRN_IAMR |
e9cf1e08 PM |
763 | std r5, STACK_SLOT_TID(r1) |
764 | std r6, STACK_SLOT_PSSCR(r1) | |
f4c51f84 | 765 | std r7, STACK_SLOT_PID(r1) |
4c3bb4cc | 766 | std r8, STACK_SLOT_IAMR(r1) |
769377f7 PM |
767 | mfspr r5, SPRN_HFSCR |
768 | std r5, STACK_SLOT_HFSCR(r1) | |
e9cf1e08 | 769 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) |
7ceaa6dc PM |
770 | BEGIN_FTR_SECTION |
771 | mfspr r5, SPRN_CIABR | |
772 | mfspr r6, SPRN_DAWR | |
773 | mfspr r7, SPRN_DAWRX | |
774 | std r5, STACK_SLOT_CIABR(r1) | |
775 | std r6, STACK_SLOT_DAWR(r1) | |
776 | std r7, STACK_SLOT_DAWRX(r1) | |
777 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
e9cf1e08 | 778 | |
e0b7ec05 PM |
779 | BEGIN_FTR_SECTION |
780 | /* Set partition DABR */ | |
781 | /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */ | |
8563bf52 | 782 | lwz r5,VCPU_DABRX(r4) |
e0b7ec05 PM |
783 | ld r6,VCPU_DABR(r4) |
784 | mtspr SPRN_DABRX,r5 | |
785 | mtspr SPRN_DABR,r6 | |
e0b7ec05 | 786 | isync |
e0b7ec05 PM |
787 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) |
788 | ||
e4e38121 | 789 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
4bb3c7a0 PM |
790 | /* |
791 | * Branch around the call if both CPU_FTR_TM and | |
792 | * CPU_FTR_P9_TM_HV_ASSIST are off. | |
793 | */ | |
e4e38121 | 794 | BEGIN_FTR_SECTION |
4bb3c7a0 PM |
795 | b 91f |
796 | END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0) | |
67f8a8c1 PM |
797 | /* |
798 | * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR | |
799 | */ | |
f024ee09 | 800 | bl kvmppc_restore_tm |
4bb3c7a0 | 801 | 91: |
e4e38121 MN |
802 | #endif |
803 | ||
e0b7ec05 PM |
804 | /* Load guest PMU registers */ |
805 | /* R4 is live here (vcpu pointer) */ | |
806 | li r3, 1 | |
807 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
808 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ | |
809 | isync | |
9bc01a9b PM |
810 | BEGIN_FTR_SECTION |
811 | ld r3, VCPU_MMCR(r4) | |
812 | andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO | |
813 | cmpwi r5, MMCR0_PMAO | |
814 | beql kvmppc_fix_pmao | |
815 | END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG) | |
e0b7ec05 PM |
816 | lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */ |
817 | lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */ | |
818 | lwz r6, VCPU_PMC + 8(r4) | |
819 | lwz r7, VCPU_PMC + 12(r4) | |
820 | lwz r8, VCPU_PMC + 16(r4) | |
821 | lwz r9, VCPU_PMC + 20(r4) | |
e0b7ec05 PM |
822 | mtspr SPRN_PMC1, r3 |
823 | mtspr SPRN_PMC2, r5 | |
824 | mtspr SPRN_PMC3, r6 | |
825 | mtspr SPRN_PMC4, r7 | |
826 | mtspr SPRN_PMC5, r8 | |
827 | mtspr SPRN_PMC6, r9 | |
e0b7ec05 PM |
828 | ld r3, VCPU_MMCR(r4) |
829 | ld r5, VCPU_MMCR + 8(r4) | |
830 | ld r6, VCPU_MMCR + 16(r4) | |
831 | ld r7, VCPU_SIAR(r4) | |
832 | ld r8, VCPU_SDAR(r4) | |
833 | mtspr SPRN_MMCR1, r5 | |
834 | mtspr SPRN_MMCRA, r6 | |
835 | mtspr SPRN_SIAR, r7 | |
836 | mtspr SPRN_SDAR, r8 | |
b005255e MN |
837 | BEGIN_FTR_SECTION |
838 | ld r5, VCPU_MMCR + 24(r4) | |
839 | ld r6, VCPU_SIER(r4) | |
83677f55 PM |
840 | mtspr SPRN_MMCR2, r5 |
841 | mtspr SPRN_SIER, r6 | |
842 | BEGIN_FTR_SECTION_NESTED(96) | |
b005255e MN |
843 | lwz r7, VCPU_PMC + 24(r4) |
844 | lwz r8, VCPU_PMC + 28(r4) | |
845 | ld r9, VCPU_MMCR + 32(r4) | |
b005255e MN |
846 | mtspr SPRN_SPMC1, r7 |
847 | mtspr SPRN_SPMC2, r8 | |
848 | mtspr SPRN_MMCRS, r9 | |
83677f55 | 849 | END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96) |
b005255e | 850 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
e0b7ec05 PM |
851 | mtspr SPRN_MMCR0, r3 |
852 | isync | |
853 | ||
854 | /* Load up FP, VMX and VSX registers */ | |
855 | bl kvmppc_load_fp | |
856 | ||
857 | ld r14, VCPU_GPR(R14)(r4) | |
858 | ld r15, VCPU_GPR(R15)(r4) | |
859 | ld r16, VCPU_GPR(R16)(r4) | |
860 | ld r17, VCPU_GPR(R17)(r4) | |
861 | ld r18, VCPU_GPR(R18)(r4) | |
862 | ld r19, VCPU_GPR(R19)(r4) | |
863 | ld r20, VCPU_GPR(R20)(r4) | |
864 | ld r21, VCPU_GPR(R21)(r4) | |
865 | ld r22, VCPU_GPR(R22)(r4) | |
866 | ld r23, VCPU_GPR(R23)(r4) | |
867 | ld r24, VCPU_GPR(R24)(r4) | |
868 | ld r25, VCPU_GPR(R25)(r4) | |
869 | ld r26, VCPU_GPR(R26)(r4) | |
870 | ld r27, VCPU_GPR(R27)(r4) | |
871 | ld r28, VCPU_GPR(R28)(r4) | |
872 | ld r29, VCPU_GPR(R29)(r4) | |
873 | ld r30, VCPU_GPR(R30)(r4) | |
874 | ld r31, VCPU_GPR(R31)(r4) | |
875 | ||
e0b7ec05 PM |
876 | /* Switch DSCR to guest value */ |
877 | ld r5, VCPU_DSCR(r4) | |
878 | mtspr SPRN_DSCR, r5 | |
e0b7ec05 | 879 | |
b005255e | 880 | BEGIN_FTR_SECTION |
c17b98cf | 881 | /* Skip next section on POWER7 */ |
b005255e MN |
882 | b 8f |
883 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
b005255e MN |
884 | /* Load up POWER8-specific registers */ |
885 | ld r5, VCPU_IAMR(r4) | |
886 | lwz r6, VCPU_PSPB(r4) | |
887 | ld r7, VCPU_FSCR(r4) | |
888 | mtspr SPRN_IAMR, r5 | |
889 | mtspr SPRN_PSPB, r6 | |
890 | mtspr SPRN_FSCR, r7 | |
891 | ld r5, VCPU_DAWR(r4) | |
892 | ld r6, VCPU_DAWRX(r4) | |
893 | ld r7, VCPU_CIABR(r4) | |
894 | ld r8, VCPU_TAR(r4) | |
b53221e7 MN |
895 | /* |
896 | * Handle broken DAWR case by not writing it. This means we | |
897 | * can still store the DAWR register for migration. | |
898 | */ | |
899 | BEGIN_FTR_SECTION | |
b005255e MN |
900 | mtspr SPRN_DAWR, r5 |
901 | mtspr SPRN_DAWRX, r6 | |
b53221e7 | 902 | END_FTR_SECTION_IFSET(CPU_FTR_DAWR) |
b005255e MN |
903 | mtspr SPRN_CIABR, r7 |
904 | mtspr SPRN_TAR, r8 | |
905 | ld r5, VCPU_IC(r4) | |
7b490411 | 906 | ld r8, VCPU_EBBHR(r4) |
88b02cf9 | 907 | mtspr SPRN_IC, r5 |
b005255e MN |
908 | mtspr SPRN_EBBHR, r8 |
909 | ld r5, VCPU_EBBRR(r4) | |
910 | ld r6, VCPU_BESCR(r4) | |
83677f55 PM |
911 | lwz r7, VCPU_GUEST_PID(r4) |
912 | ld r8, VCPU_WORT(r4) | |
b005255e MN |
913 | mtspr SPRN_EBBRR, r5 |
914 | mtspr SPRN_BESCR, r6 | |
83677f55 PM |
915 | mtspr SPRN_PID, r7 |
916 | mtspr SPRN_WORT, r8 | |
f11f6f79 PM |
917 | BEGIN_FTR_SECTION |
918 | PPC_INVALIDATE_ERAT | |
919 | END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1) | |
83677f55 | 920 | BEGIN_FTR_SECTION |
e9cf1e08 | 921 | /* POWER8-only registers */ |
b005255e MN |
922 | ld r5, VCPU_TCSCR(r4) |
923 | ld r6, VCPU_ACOP(r4) | |
83677f55 PM |
924 | ld r7, VCPU_CSIGR(r4) |
925 | ld r8, VCPU_TACR(r4) | |
b005255e MN |
926 | mtspr SPRN_TCSCR, r5 |
927 | mtspr SPRN_ACOP, r6 | |
83677f55 PM |
928 | mtspr SPRN_CSIGR, r7 |
929 | mtspr SPRN_TACR, r8 | |
4bb3c7a0 | 930 | nop |
e9cf1e08 PM |
931 | FTR_SECTION_ELSE |
932 | /* POWER9-only registers */ | |
933 | ld r5, VCPU_TID(r4) | |
934 | ld r6, VCPU_PSSCR(r4) | |
4bb3c7a0 | 935 | lbz r8, HSTATE_FAKE_SUSPEND(r13) |
e9cf1e08 | 936 | oris r6, r6, PSSCR_EC@h /* This makes stop trap to HV */ |
4bb3c7a0 | 937 | rldimi r6, r8, PSSCR_FAKE_SUSPEND_LG, 63 - PSSCR_FAKE_SUSPEND_LG |
769377f7 | 938 | ld r7, VCPU_HFSCR(r4) |
e9cf1e08 PM |
939 | mtspr SPRN_TIDR, r5 |
940 | mtspr SPRN_PSSCR, r6 | |
769377f7 | 941 | mtspr SPRN_HFSCR, r7 |
e9cf1e08 | 942 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300) |
b005255e MN |
943 | 8: |
944 | ||
e0b7ec05 PM |
945 | /* |
946 | * Set the decrementer to the guest decrementer. | |
947 | */ | |
948 | ld r8,VCPU_DEC_EXPIRES(r4) | |
c5fb80d3 PM |
949 | /* r8 is a host timebase value here, convert to guest TB */ |
950 | ld r5,HSTATE_KVM_VCORE(r13) | |
951 | ld r6,VCORE_TB_OFFSET(r5) | |
952 | add r8,r8,r6 | |
e0b7ec05 PM |
953 | mftb r7 |
954 | subf r3,r7,r8 | |
955 | mtspr SPRN_DEC,r3 | |
e0b7ec05 PM |
956 | |
957 | ld r5, VCPU_SPRG0(r4) | |
958 | ld r6, VCPU_SPRG1(r4) | |
959 | ld r7, VCPU_SPRG2(r4) | |
960 | ld r8, VCPU_SPRG3(r4) | |
961 | mtspr SPRN_SPRG0, r5 | |
962 | mtspr SPRN_SPRG1, r6 | |
963 | mtspr SPRN_SPRG2, r7 | |
964 | mtspr SPRN_SPRG3, r8 | |
965 | ||
966 | /* Load up DAR and DSISR */ | |
967 | ld r5, VCPU_DAR(r4) | |
968 | lwz r6, VCPU_DSISR(r4) | |
969 | mtspr SPRN_DAR, r5 | |
970 | mtspr SPRN_DSISR, r6 | |
971 | ||
e0b7ec05 PM |
972 | /* Restore AMR and UAMOR, set AMOR to all 1s */ |
973 | ld r5,VCPU_AMR(r4) | |
974 | ld r6,VCPU_UAMOR(r4) | |
975 | li r7,-1 | |
976 | mtspr SPRN_AMR,r5 | |
977 | mtspr SPRN_UAMOR,r6 | |
978 | mtspr SPRN_AMOR,r7 | |
de56a948 PM |
979 | |
980 | /* Restore state of CTRL run bit; assume 1 on entry */ | |
981 | lwz r5,VCPU_CTRL(r4) | |
982 | andi. r5,r5,1 | |
983 | bne 4f | |
984 | mfspr r6,SPRN_CTRLF | |
985 | clrrdi r6,r6,1 | |
986 | mtspr SPRN_CTRLT,r6 | |
987 | 4: | |
6af27c84 PM |
988 | /* Secondary threads wait for primary to have done partition switch */ |
989 | ld r5, HSTATE_KVM_VCORE(r13) | |
990 | lbz r6, HSTATE_PTID(r13) | |
991 | cmpwi r6, 0 | |
992 | beq 21f | |
993 | lbz r0, VCORE_IN_GUEST(r5) | |
994 | cmpwi r0, 0 | |
995 | bne 21f | |
996 | HMT_LOW | |
b4deba5c PM |
997 | 20: lwz r3, VCORE_ENTRY_EXIT(r5) |
998 | cmpwi r3, 0x100 | |
999 | bge no_switch_exit | |
1000 | lbz r0, VCORE_IN_GUEST(r5) | |
6af27c84 PM |
1001 | cmpwi r0, 0 |
1002 | beq 20b | |
1003 | HMT_MEDIUM | |
1004 | 21: | |
1005 | /* Set LPCR. */ | |
1006 | ld r8,VCORE_LPCR(r5) | |
1007 | mtspr SPRN_LPCR,r8 | |
1008 | isync | |
1009 | ||
1010 | /* Check if HDEC expires soon */ | |
1011 | mfspr r3, SPRN_HDEC | |
2f272463 PM |
1012 | EXTEND_HDEC(r3) |
1013 | cmpdi r3, 512 /* 1 microsecond */ | |
6af27c84 PM |
1014 | blt hdec_soon |
1015 | ||
6964e6a4 PM |
1016 | /* For hash guest, clear out and reload the SLB */ |
1017 | ld r6, VCPU_KVM(r4) | |
1018 | lbz r0, KVM_RADIX(r6) | |
1019 | cmpwi r0, 0 | |
1020 | bne 9f | |
1021 | li r6, 0 | |
1022 | slbmte r6, r6 | |
1023 | slbia | |
1024 | ptesync | |
1025 | ||
1026 | /* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */ | |
1027 | lwz r5,VCPU_SLB_MAX(r4) | |
1028 | cmpwi r5,0 | |
1029 | beq 9f | |
1030 | mtctr r5 | |
1031 | addi r6,r4,VCPU_SLB | |
1032 | 1: ld r8,VCPU_SLB_E(r6) | |
1033 | ld r9,VCPU_SLB_V(r6) | |
1034 | slbmte r9,r8 | |
1035 | addi r6,r6,VCPU_SLB_SIZE | |
1036 | bdnz 1b | |
1037 | 9: | |
1038 | ||
5af50993 BH |
1039 | #ifdef CONFIG_KVM_XICS |
1040 | /* We are entering the guest on that thread, push VCPU to XIVE */ | |
1041 | ld r10, HSTATE_XIVE_TIMA_PHYS(r13) | |
0bfa33c7 | 1042 | cmpldi cr0, r10, 0 |
5af50993 BH |
1043 | beq no_xive |
1044 | ld r11, VCPU_XIVE_SAVED_STATE(r4) | |
1045 | li r9, TM_QW1_OS | |
5af50993 | 1046 | eieio |
ad98dd1a | 1047 | stdcix r11,r9,r10 |
5af50993 BH |
1048 | lwz r11, VCPU_XIVE_CAM_WORD(r4) |
1049 | li r9, TM_QW1_OS + TM_WORD2 | |
1050 | stwcix r11,r9,r10 | |
1051 | li r9, 1 | |
35c2405e | 1052 | stb r9, VCPU_XIVE_PUSHED(r4) |
ad98dd1a | 1053 | eieio |
2267ea76 BH |
1054 | |
1055 | /* | |
1056 | * We clear the irq_pending flag. There is a small chance of a | |
1057 | * race vs. the escalation interrupt happening on another | |
1058 | * processor setting it again, but the only consequence is to | |
1059 | * cause a spurrious wakeup on the next H_CEDE which is not an | |
1060 | * issue. | |
1061 | */ | |
1062 | li r0,0 | |
1063 | stb r0, VCPU_IRQ_PENDING(r4) | |
9b9b13a6 BH |
1064 | |
1065 | /* | |
1066 | * In single escalation mode, if the escalation interrupt is | |
1067 | * on, we mask it. | |
1068 | */ | |
1069 | lbz r0, VCPU_XIVE_ESC_ON(r4) | |
1070 | cmpwi r0,0 | |
1071 | beq 1f | |
1072 | ld r10, VCPU_XIVE_ESC_RADDR(r4) | |
1073 | li r9, XIVE_ESB_SET_PQ_01 | |
1074 | ldcix r0, r10, r9 | |
1075 | sync | |
1076 | ||
1077 | /* We have a possible subtle race here: The escalation interrupt might | |
1078 | * have fired and be on its way to the host queue while we mask it, | |
1079 | * and if we unmask it early enough (re-cede right away), there is | |
1080 | * a theorical possibility that it fires again, thus landing in the | |
1081 | * target queue more than once which is a big no-no. | |
1082 | * | |
1083 | * Fortunately, solving this is rather easy. If the above load setting | |
1084 | * PQ to 01 returns a previous value where P is set, then we know the | |
1085 | * escalation interrupt is somewhere on its way to the host. In that | |
1086 | * case we simply don't clear the xive_esc_on flag below. It will be | |
1087 | * eventually cleared by the handler for the escalation interrupt. | |
1088 | * | |
1089 | * Then, when doing a cede, we check that flag again before re-enabling | |
1090 | * the escalation interrupt, and if set, we abort the cede. | |
1091 | */ | |
1092 | andi. r0, r0, XIVE_ESB_VAL_P | |
1093 | bne- 1f | |
1094 | ||
1095 | /* Now P is 0, we can clear the flag */ | |
1096 | li r0, 0 | |
1097 | stb r0, VCPU_XIVE_ESC_ON(r4) | |
1098 | 1: | |
5af50993 BH |
1099 | no_xive: |
1100 | #endif /* CONFIG_KVM_XICS */ | |
1101 | ||
37f55d30 | 1102 | deliver_guest_interrupt: |
de56a948 | 1103 | ld r6, VCPU_CTR(r4) |
c63517c2 | 1104 | ld r7, VCPU_XER(r4) |
de56a948 PM |
1105 | |
1106 | mtctr r6 | |
1107 | mtxer r7 | |
1108 | ||
e3bbbbfa | 1109 | kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */ |
4619ac88 PM |
1110 | ld r10, VCPU_PC(r4) |
1111 | ld r11, VCPU_MSR(r4) | |
de56a948 PM |
1112 | ld r6, VCPU_SRR0(r4) |
1113 | ld r7, VCPU_SRR1(r4) | |
e3bbbbfa PM |
1114 | mtspr SPRN_SRR0, r6 |
1115 | mtspr SPRN_SRR1, r7 | |
de56a948 | 1116 | |
4619ac88 | 1117 | /* r11 = vcpu->arch.msr & ~MSR_HV */ |
de56a948 PM |
1118 | rldicl r11, r11, 63 - MSR_HV_LG, 1 |
1119 | rotldi r11, r11, 1 + MSR_HV_LG | |
1120 | ori r11, r11, MSR_ME | |
1121 | ||
19ccb76a | 1122 | /* Check if we can deliver an external or decrementer interrupt now */ |
e3bbbbfa PM |
1123 | ld r0, VCPU_PENDING_EXC(r4) |
1124 | rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63 | |
1125 | cmpdi cr1, r0, 0 | |
1126 | andi. r8, r11, MSR_EE | |
e3bbbbfa PM |
1127 | mfspr r8, SPRN_LPCR |
1128 | /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */ | |
1129 | rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH | |
1130 | mtspr SPRN_LPCR, r8 | |
19ccb76a | 1131 | isync |
19ccb76a | 1132 | beq 5f |
e3bbbbfa PM |
1133 | li r0, BOOK3S_INTERRUPT_EXTERNAL |
1134 | bne cr1, 12f | |
1135 | mfspr r0, SPRN_DEC | |
1bc3fe81 PM |
1136 | BEGIN_FTR_SECTION |
1137 | /* On POWER9 check whether the guest has large decrementer enabled */ | |
1138 | andis. r8, r8, LPCR_LD@h | |
1139 | bne 15f | |
1140 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
1141 | extsw r0, r0 | |
1142 | 15: cmpdi r0, 0 | |
e3bbbbfa PM |
1143 | li r0, BOOK3S_INTERRUPT_DECREMENTER |
1144 | bge 5f | |
19ccb76a | 1145 | |
e3bbbbfa | 1146 | 12: mtspr SPRN_SRR0, r10 |
19ccb76a | 1147 | mr r10,r0 |
e3bbbbfa | 1148 | mtspr SPRN_SRR1, r11 |
e4e38121 MN |
1149 | mr r9, r4 |
1150 | bl kvmppc_msr_interrupt | |
e3bbbbfa | 1151 | 5: |
57900694 PM |
1152 | BEGIN_FTR_SECTION |
1153 | b fast_guest_return | |
1154 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) | |
1155 | /* On POWER9, check for pending doorbell requests */ | |
1156 | lbz r0, VCPU_DBELL_REQ(r4) | |
1157 | cmpwi r0, 0 | |
1158 | beq fast_guest_return | |
1159 | ld r5, HSTATE_KVM_VCORE(r13) | |
1160 | /* Set DPDES register so the CPU will take a doorbell interrupt */ | |
1161 | li r0, 1 | |
1162 | mtspr SPRN_DPDES, r0 | |
1163 | std r0, VCORE_DPDES(r5) | |
1164 | /* Make sure other cpus see vcore->dpdes set before dbell req clear */ | |
1165 | lwsync | |
1166 | /* Clear the pending doorbell request */ | |
1167 | li r0, 0 | |
1168 | stb r0, VCPU_DBELL_REQ(r4) | |
19ccb76a | 1169 | |
27025a60 LPF |
1170 | /* |
1171 | * Required state: | |
1172 | * R4 = vcpu | |
1173 | * R10: value for HSRR0 | |
1174 | * R11: value for HSRR1 | |
1175 | * R13 = PACA | |
1176 | */ | |
de56a948 | 1177 | fast_guest_return: |
4619ac88 PM |
1178 | li r0,0 |
1179 | stb r0,VCPU_CEDED(r4) /* cancel cede */ | |
de56a948 PM |
1180 | mtspr SPRN_HSRR0,r10 |
1181 | mtspr SPRN_HSRR1,r11 | |
1182 | ||
1183 | /* Activate guest mode, so faults get handled by KVM */ | |
44a3add8 | 1184 | li r9, KVM_GUEST_MODE_GUEST_HV |
de56a948 PM |
1185 | stb r9, HSTATE_IN_GUEST(r13) |
1186 | ||
b6c295df PM |
1187 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
1188 | /* Accumulate timing */ | |
1189 | addi r3, r4, VCPU_TB_GUEST | |
1190 | bl kvmhv_accumulate_time | |
1191 | #endif | |
1192 | ||
de56a948 PM |
1193 | /* Enter guest */ |
1194 | ||
0acb9111 PM |
1195 | BEGIN_FTR_SECTION |
1196 | ld r5, VCPU_CFAR(r4) | |
1197 | mtspr SPRN_CFAR, r5 | |
1198 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
4b8473c9 PM |
1199 | BEGIN_FTR_SECTION |
1200 | ld r0, VCPU_PPR(r4) | |
1201 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
0acb9111 | 1202 | |
de56a948 PM |
1203 | ld r5, VCPU_LR(r4) |
1204 | lwz r6, VCPU_CR(r4) | |
1205 | mtlr r5 | |
1206 | mtcr r6 | |
1207 | ||
c75df6f9 MN |
1208 | ld r1, VCPU_GPR(R1)(r4) |
1209 | ld r2, VCPU_GPR(R2)(r4) | |
1210 | ld r3, VCPU_GPR(R3)(r4) | |
1211 | ld r5, VCPU_GPR(R5)(r4) | |
1212 | ld r6, VCPU_GPR(R6)(r4) | |
1213 | ld r7, VCPU_GPR(R7)(r4) | |
1214 | ld r8, VCPU_GPR(R8)(r4) | |
1215 | ld r9, VCPU_GPR(R9)(r4) | |
1216 | ld r10, VCPU_GPR(R10)(r4) | |
1217 | ld r11, VCPU_GPR(R11)(r4) | |
1218 | ld r12, VCPU_GPR(R12)(r4) | |
1219 | ld r13, VCPU_GPR(R13)(r4) | |
1220 | ||
4b8473c9 PM |
1221 | BEGIN_FTR_SECTION |
1222 | mtspr SPRN_PPR, r0 | |
1223 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
e001fa78 MN |
1224 | |
1225 | /* Move canary into DSISR to check for later */ | |
1226 | BEGIN_FTR_SECTION | |
1227 | li r0, 0x7fff | |
1228 | mtspr SPRN_HDSISR, r0 | |
1229 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
1230 | ||
4b8473c9 | 1231 | ld r0, VCPU_GPR(R0)(r4) |
c75df6f9 | 1232 | ld r4, VCPU_GPR(R4)(r4) |
222f20f1 | 1233 | HRFI_TO_GUEST |
de56a948 PM |
1234 | b . |
1235 | ||
b6c295df | 1236 | secondary_too_late: |
6af27c84 | 1237 | li r12, 0 |
b6c295df PM |
1238 | cmpdi r4, 0 |
1239 | beq 11f | |
6af27c84 PM |
1240 | stw r12, VCPU_TRAP(r4) |
1241 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING | |
b6c295df PM |
1242 | addi r3, r4, VCPU_TB_RMEXIT |
1243 | bl kvmhv_accumulate_time | |
6af27c84 | 1244 | #endif |
b6c295df PM |
1245 | 11: b kvmhv_switch_to_host |
1246 | ||
b4deba5c PM |
1247 | no_switch_exit: |
1248 | HMT_MEDIUM | |
1249 | li r12, 0 | |
1250 | b 12f | |
b6c295df | 1251 | hdec_soon: |
6af27c84 | 1252 | li r12, BOOK3S_INTERRUPT_HV_DECREMENTER |
b4deba5c | 1253 | 12: stw r12, VCPU_TRAP(r4) |
6af27c84 PM |
1254 | mr r9, r4 |
1255 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING | |
b6c295df PM |
1256 | addi r3, r4, VCPU_TB_RMEXIT |
1257 | bl kvmhv_accumulate_time | |
b6c295df | 1258 | #endif |
6964e6a4 | 1259 | b guest_bypass |
b6c295df | 1260 | |
de56a948 PM |
1261 | /****************************************************************************** |
1262 | * * | |
1263 | * Exit code * | |
1264 | * * | |
1265 | *****************************************************************************/ | |
1266 | ||
1267 | /* | |
1268 | * We come here from the first-level interrupt handlers. | |
1269 | */ | |
dd96b2c2 AK |
1270 | .globl kvmppc_interrupt_hv |
1271 | kvmppc_interrupt_hv: | |
de56a948 PM |
1272 | /* |
1273 | * Register contents: | |
d3918e7f | 1274 | * R12 = (guest CR << 32) | interrupt vector |
de56a948 | 1275 | * R13 = PACA |
d3918e7f | 1276 | * guest R12 saved in shadow VCPU SCRATCH0 |
a97a65d5 | 1277 | * guest CTR saved in shadow VCPU SCRATCH1 if RELOCATABLE |
de56a948 PM |
1278 | * guest R13 saved in SPRN_SCRATCH0 |
1279 | */ | |
a97a65d5 | 1280 | std r9, HSTATE_SCRATCH2(r13) |
44a3add8 PM |
1281 | lbz r9, HSTATE_IN_GUEST(r13) |
1282 | cmpwi r9, KVM_GUEST_MODE_HOST_HV | |
1283 | beq kvmppc_bad_host_intr | |
dd96b2c2 AK |
1284 | #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE |
1285 | cmpwi r9, KVM_GUEST_MODE_GUEST | |
a97a65d5 | 1286 | ld r9, HSTATE_SCRATCH2(r13) |
dd96b2c2 AK |
1287 | beq kvmppc_interrupt_pr |
1288 | #endif | |
44a3add8 PM |
1289 | /* We're now back in the host but in guest MMU context */ |
1290 | li r9, KVM_GUEST_MODE_HOST_HV | |
1291 | stb r9, HSTATE_IN_GUEST(r13) | |
1292 | ||
de56a948 PM |
1293 | ld r9, HSTATE_KVM_VCPU(r13) |
1294 | ||
1295 | /* Save registers */ | |
1296 | ||
c75df6f9 MN |
1297 | std r0, VCPU_GPR(R0)(r9) |
1298 | std r1, VCPU_GPR(R1)(r9) | |
1299 | std r2, VCPU_GPR(R2)(r9) | |
1300 | std r3, VCPU_GPR(R3)(r9) | |
1301 | std r4, VCPU_GPR(R4)(r9) | |
1302 | std r5, VCPU_GPR(R5)(r9) | |
1303 | std r6, VCPU_GPR(R6)(r9) | |
1304 | std r7, VCPU_GPR(R7)(r9) | |
1305 | std r8, VCPU_GPR(R8)(r9) | |
a97a65d5 | 1306 | ld r0, HSTATE_SCRATCH2(r13) |
c75df6f9 MN |
1307 | std r0, VCPU_GPR(R9)(r9) |
1308 | std r10, VCPU_GPR(R10)(r9) | |
1309 | std r11, VCPU_GPR(R11)(r9) | |
de56a948 | 1310 | ld r3, HSTATE_SCRATCH0(r13) |
c75df6f9 | 1311 | std r3, VCPU_GPR(R12)(r9) |
d3918e7f NP |
1312 | /* CR is in the high half of r12 */ |
1313 | srdi r4, r12, 32 | |
de56a948 | 1314 | stw r4, VCPU_CR(r9) |
0acb9111 PM |
1315 | BEGIN_FTR_SECTION |
1316 | ld r3, HSTATE_CFAR(r13) | |
1317 | std r3, VCPU_CFAR(r9) | |
1318 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
4b8473c9 PM |
1319 | BEGIN_FTR_SECTION |
1320 | ld r4, HSTATE_PPR(r13) | |
1321 | std r4, VCPU_PPR(r9) | |
1322 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
de56a948 PM |
1323 | |
1324 | /* Restore R1/R2 so we can handle faults */ | |
1325 | ld r1, HSTATE_HOST_R1(r13) | |
1326 | ld r2, PACATOC(r13) | |
1327 | ||
1328 | mfspr r10, SPRN_SRR0 | |
1329 | mfspr r11, SPRN_SRR1 | |
1330 | std r10, VCPU_SRR0(r9) | |
1331 | std r11, VCPU_SRR1(r9) | |
d3918e7f NP |
1332 | /* trap is in the low half of r12, clear CR from the high half */ |
1333 | clrldi r12, r12, 32 | |
de56a948 PM |
1334 | andi. r0, r12, 2 /* need to read HSRR0/1? */ |
1335 | beq 1f | |
1336 | mfspr r10, SPRN_HSRR0 | |
1337 | mfspr r11, SPRN_HSRR1 | |
1338 | clrrdi r12, r12, 2 | |
1339 | 1: std r10, VCPU_PC(r9) | |
1340 | std r11, VCPU_MSR(r9) | |
1341 | ||
1342 | GET_SCRATCH0(r3) | |
1343 | mflr r4 | |
c75df6f9 | 1344 | std r3, VCPU_GPR(R13)(r9) |
de56a948 PM |
1345 | std r4, VCPU_LR(r9) |
1346 | ||
de56a948 PM |
1347 | stw r12,VCPU_TRAP(r9) |
1348 | ||
8b24e69f PM |
1349 | /* |
1350 | * Now that we have saved away SRR0/1 and HSRR0/1, | |
1351 | * interrupts are recoverable in principle, so set MSR_RI. | |
1352 | * This becomes important for relocation-on interrupts from | |
1353 | * the guest, which we can get in radix mode on POWER9. | |
1354 | */ | |
1355 | li r0, MSR_RI | |
1356 | mtmsrd r0, 1 | |
1357 | ||
b6c295df PM |
1358 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
1359 | addi r3, r9, VCPU_TB_RMINTR | |
1360 | mr r4, r9 | |
1361 | bl kvmhv_accumulate_time | |
1362 | ld r5, VCPU_GPR(R5)(r9) | |
1363 | ld r6, VCPU_GPR(R6)(r9) | |
1364 | ld r7, VCPU_GPR(R7)(r9) | |
1365 | ld r8, VCPU_GPR(R8)(r9) | |
1366 | #endif | |
1367 | ||
4a157d61 | 1368 | /* Save HEIR (HV emulation assist reg) in emul_inst |
697d3899 PM |
1369 | if this is an HEI (HV emulation interrupt, e40) */ |
1370 | li r3,KVM_INST_FETCH_FAILED | |
2bf27601 | 1371 | stw r3,VCPU_LAST_INST(r9) |
697d3899 PM |
1372 | cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST |
1373 | bne 11f | |
1374 | mfspr r3,SPRN_HEIR | |
4a157d61 | 1375 | 11: stw r3,VCPU_HEIR(r9) |
697d3899 PM |
1376 | |
1377 | /* these are volatile across C function calls */ | |
a97a65d5 NP |
1378 | #ifdef CONFIG_RELOCATABLE |
1379 | ld r3, HSTATE_SCRATCH1(r13) | |
1380 | mtctr r3 | |
1381 | #else | |
697d3899 | 1382 | mfctr r3 |
a97a65d5 | 1383 | #endif |
697d3899 PM |
1384 | mfxer r4 |
1385 | std r3, VCPU_CTR(r9) | |
c63517c2 | 1386 | std r4, VCPU_XER(r9) |
697d3899 | 1387 | |
4bb3c7a0 PM |
1388 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1389 | /* For softpatch interrupt, go off and do TM instruction emulation */ | |
1390 | cmpwi r12, BOOK3S_INTERRUPT_HV_SOFTPATCH | |
1391 | beq kvmppc_tm_emul | |
1392 | #endif | |
1393 | ||
697d3899 PM |
1394 | /* If this is a page table miss then see if it's theirs or ours */ |
1395 | cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE | |
1396 | beq kvmppc_hdsi | |
342d3db7 PM |
1397 | cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE |
1398 | beq kvmppc_hisi | |
697d3899 | 1399 | |
de56a948 PM |
1400 | /* See if this is a leftover HDEC interrupt */ |
1401 | cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
1402 | bne 2f | |
1403 | mfspr r3,SPRN_HDEC | |
a4faf2e7 PM |
1404 | EXTEND_HDEC(r3) |
1405 | cmpdi r3,0 | |
1f09c3ed PM |
1406 | mr r4,r9 |
1407 | bge fast_guest_return | |
de56a948 | 1408 | 2: |
697d3899 | 1409 | /* See if this is an hcall we can handle in real mode */ |
a8606e20 PM |
1410 | cmpwi r12,BOOK3S_INTERRUPT_SYSCALL |
1411 | beq hcall_try_real_mode | |
de56a948 | 1412 | |
66feed61 PM |
1413 | /* Hypervisor doorbell - exit only if host IPI flag set */ |
1414 | cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL | |
1415 | bne 3f | |
bd0fdb19 NP |
1416 | BEGIN_FTR_SECTION |
1417 | PPC_MSGSYNC | |
2cde3716 | 1418 | lwsync |
bd0fdb19 | 1419 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) |
66feed61 | 1420 | lbz r0, HSTATE_HOST_IPI(r13) |
06554d9f | 1421 | cmpwi r0, 0 |
66feed61 PM |
1422 | beq 4f |
1423 | b guest_exit_cont | |
1424 | 3: | |
769377f7 PM |
1425 | /* If it's a hypervisor facility unavailable interrupt, save HFSCR */ |
1426 | cmpwi r12, BOOK3S_INTERRUPT_H_FAC_UNAVAIL | |
1427 | bne 14f | |
1428 | mfspr r3, SPRN_HFSCR | |
1429 | std r3, VCPU_HFSCR(r9) | |
1430 | b guest_exit_cont | |
1431 | 14: | |
54695c30 BH |
1432 | /* External interrupt ? */ |
1433 | cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL | |
1f09c3ed | 1434 | bne+ guest_exit_cont |
54695c30 BH |
1435 | |
1436 | /* External interrupt, first check for host_ipi. If this is | |
1437 | * set, we know the host wants us out so let's do it now | |
1438 | */ | |
c934243c | 1439 | bl kvmppc_read_intr |
37f55d30 SW |
1440 | |
1441 | /* | |
1442 | * Restore the active volatile registers after returning from | |
1443 | * a C function. | |
1444 | */ | |
1445 | ld r9, HSTATE_KVM_VCPU(r13) | |
1446 | li r12, BOOK3S_INTERRUPT_EXTERNAL | |
1447 | ||
1448 | /* | |
1449 | * kvmppc_read_intr return codes: | |
1450 | * | |
1451 | * Exit to host (r3 > 0) | |
1452 | * 1 An interrupt is pending that needs to be handled by the host | |
1453 | * Exit guest and return to host by branching to guest_exit_cont | |
1454 | * | |
f7af5209 SW |
1455 | * 2 Passthrough that needs completion in the host |
1456 | * Exit guest and return to host by branching to guest_exit_cont | |
1457 | * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD | |
1458 | * to indicate to the host to complete handling the interrupt | |
1459 | * | |
37f55d30 SW |
1460 | * Before returning to guest, we check if any CPU is heading out |
1461 | * to the host and if so, we head out also. If no CPUs are heading | |
1462 | * check return values <= 0. | |
1463 | * | |
1464 | * Return to guest (r3 <= 0) | |
1465 | * 0 No external interrupt is pending | |
1466 | * -1 A guest wakeup IPI (which has now been cleared) | |
1467 | * In either case, we return to guest to deliver any pending | |
1468 | * guest interrupts. | |
e3c13e56 SW |
1469 | * |
1470 | * -2 A PCI passthrough external interrupt was handled | |
1471 | * (interrupt was delivered directly to guest) | |
1472 | * Return to guest to deliver any pending guest interrupts. | |
37f55d30 SW |
1473 | */ |
1474 | ||
f7af5209 SW |
1475 | cmpdi r3, 1 |
1476 | ble 1f | |
1477 | ||
1478 | /* Return code = 2 */ | |
1479 | li r12, BOOK3S_INTERRUPT_HV_RM_HARD | |
1480 | stw r12, VCPU_TRAP(r9) | |
1481 | b guest_exit_cont | |
1482 | ||
1483 | 1: /* Return code <= 1 */ | |
c934243c | 1484 | cmpdi r3, 0 |
1f09c3ed | 1485 | bgt guest_exit_cont |
54695c30 | 1486 | |
37f55d30 | 1487 | /* Return code <= 0 */ |
66feed61 | 1488 | 4: ld r5, HSTATE_KVM_VCORE(r13) |
4619ac88 PM |
1489 | lwz r0, VCORE_ENTRY_EXIT(r5) |
1490 | cmpwi r0, 0x100 | |
e3bbbbfa | 1491 | mr r4, r9 |
1f09c3ed | 1492 | blt deliver_guest_interrupt |
de56a948 | 1493 | |
b4072df4 | 1494 | guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */ |
43ff3f65 PM |
1495 | /* Save more register state */ |
1496 | mfdar r6 | |
1497 | mfdsisr r7 | |
1498 | std r6, VCPU_DAR(r9) | |
1499 | stw r7, VCPU_DSISR(r9) | |
1500 | /* don't overwrite fault_dar/fault_dsisr if HDSI */ | |
1501 | cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE | |
1502 | beq mc_cont | |
1503 | std r6, VCPU_FAULT_DAR(r9) | |
1504 | stw r7, VCPU_FAULT_DSISR(r9) | |
1505 | ||
1506 | /* See if it is a machine check */ | |
1507 | cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
1508 | beq machine_check_realmode | |
1509 | mc_cont: | |
1510 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING | |
1511 | addi r3, r9, VCPU_TB_RMEXIT | |
1512 | mr r4, r9 | |
1513 | bl kvmhv_accumulate_time | |
1514 | #endif | |
5af50993 BH |
1515 | #ifdef CONFIG_KVM_XICS |
1516 | /* We are exiting, pull the VP from the XIVE */ | |
35c2405e | 1517 | lbz r0, VCPU_XIVE_PUSHED(r9) |
5af50993 BH |
1518 | cmpwi cr0, r0, 0 |
1519 | beq 1f | |
1520 | li r7, TM_SPC_PULL_OS_CTX | |
1521 | li r6, TM_QW1_OS | |
1522 | mfmsr r0 | |
2662efd0 | 1523 | andi. r0, r0, MSR_DR /* in real mode? */ |
5af50993 BH |
1524 | beq 2f |
1525 | ld r10, HSTATE_XIVE_TIMA_VIRT(r13) | |
1526 | cmpldi cr0, r10, 0 | |
1527 | beq 1f | |
1528 | /* First load to pull the context, we ignore the value */ | |
5af50993 | 1529 | eieio |
ad98dd1a | 1530 | lwzx r11, r7, r10 |
5af50993 BH |
1531 | /* Second load to recover the context state (Words 0 and 1) */ |
1532 | ldx r11, r6, r10 | |
1533 | b 3f | |
1534 | 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13) | |
1535 | cmpldi cr0, r10, 0 | |
1536 | beq 1f | |
1537 | /* First load to pull the context, we ignore the value */ | |
5af50993 | 1538 | eieio |
ad98dd1a | 1539 | lwzcix r11, r7, r10 |
5af50993 BH |
1540 | /* Second load to recover the context state (Words 0 and 1) */ |
1541 | ldcix r11, r6, r10 | |
1542 | 3: std r11, VCPU_XIVE_SAVED_STATE(r9) | |
1543 | /* Fixup some of the state for the next load */ | |
1544 | li r10, 0 | |
1545 | li r0, 0xff | |
35c2405e | 1546 | stb r10, VCPU_XIVE_PUSHED(r9) |
5af50993 BH |
1547 | stb r10, (VCPU_XIVE_SAVED_STATE+3)(r9) |
1548 | stb r0, (VCPU_XIVE_SAVED_STATE+4)(r9) | |
ad98dd1a | 1549 | eieio |
5af50993 BH |
1550 | 1: |
1551 | #endif /* CONFIG_KVM_XICS */ | |
de56a948 | 1552 | |
6964e6a4 | 1553 | /* For hash guest, read the guest SLB and save it away */ |
f4c51f84 PM |
1554 | ld r5, VCPU_KVM(r9) |
1555 | lbz r0, KVM_RADIX(r5) | |
f4c51f84 | 1556 | li r5, 0 |
6964e6a4 PM |
1557 | cmpwi r0, 0 |
1558 | bne 3f /* for radix, save 0 entries */ | |
de56a948 PM |
1559 | lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */ |
1560 | mtctr r0 | |
1561 | li r6,0 | |
1562 | addi r7,r9,VCPU_SLB | |
de56a948 PM |
1563 | 1: slbmfee r8,r6 |
1564 | andis. r0,r8,SLB_ESID_V@h | |
1565 | beq 2f | |
1566 | add r8,r8,r6 /* put index in */ | |
1567 | slbmfev r3,r6 | |
1568 | std r8,VCPU_SLB_E(r7) | |
1569 | std r3,VCPU_SLB_V(r7) | |
1570 | addi r7,r7,VCPU_SLB_SIZE | |
1571 | addi r5,r5,1 | |
1572 | 2: addi r6,r6,1 | |
1573 | bdnz 1b | |
6964e6a4 PM |
1574 | /* Finally clear out the SLB */ |
1575 | li r0,0 | |
1576 | slbmte r0,r0 | |
1577 | slbia | |
1578 | ptesync | |
f4c51f84 | 1579 | 3: stw r5,VCPU_SLB_MAX(r9) |
b4072df4 | 1580 | |
6964e6a4 | 1581 | guest_bypass: |
7e022e71 | 1582 | mr r3, r12 |
6af27c84 PM |
1583 | /* Increment exit count, poke other threads to exit */ |
1584 | bl kvmhv_commence_exit | |
eddb60fb PM |
1585 | nop |
1586 | ld r9, HSTATE_KVM_VCPU(r13) | |
1587 | lwz r12, VCPU_TRAP(r9) | |
6af27c84 | 1588 | |
ec257165 PM |
1589 | /* Stop others sending VCPU interrupts to this physical CPU */ |
1590 | li r0, -1 | |
1591 | stw r0, VCPU_CPU(r9) | |
1592 | stw r0, VCPU_THREAD_CPU(r9) | |
1593 | ||
de56a948 | 1594 | /* Save guest CTRL register, set runlatch to 1 */ |
6af27c84 | 1595 | mfspr r6,SPRN_CTRLF |
de56a948 PM |
1596 | stw r6,VCPU_CTRL(r9) |
1597 | andi. r0,r6,1 | |
1598 | bne 4f | |
1599 | ori r6,r6,1 | |
1600 | mtspr SPRN_CTRLT,r6 | |
1601 | 4: | |
de56a948 PM |
1602 | /* |
1603 | * Save the guest PURR/SPURR | |
1604 | */ | |
1605 | mfspr r5,SPRN_PURR | |
1606 | mfspr r6,SPRN_SPURR | |
1607 | ld r7,VCPU_PURR(r9) | |
1608 | ld r8,VCPU_SPURR(r9) | |
1609 | std r5,VCPU_PURR(r9) | |
1610 | std r6,VCPU_SPURR(r9) | |
1611 | subf r5,r7,r5 | |
1612 | subf r6,r8,r6 | |
1613 | ||
1614 | /* | |
1615 | * Restore host PURR/SPURR and add guest times | |
1616 | * so that the time in the guest gets accounted. | |
1617 | */ | |
1618 | ld r3,HSTATE_PURR(r13) | |
1619 | ld r4,HSTATE_SPURR(r13) | |
1620 | add r3,r3,r5 | |
1621 | add r4,r4,r6 | |
1622 | mtspr SPRN_PURR,r3 | |
1623 | mtspr SPRN_SPURR,r4 | |
1624 | ||
e0b7ec05 | 1625 | /* Save DEC */ |
1bc3fe81 | 1626 | ld r3, HSTATE_KVM_VCORE(r13) |
e0b7ec05 PM |
1627 | mfspr r5,SPRN_DEC |
1628 | mftb r6 | |
1bc3fe81 PM |
1629 | /* On P9, if the guest has large decr enabled, don't sign extend */ |
1630 | BEGIN_FTR_SECTION | |
1631 | ld r4, VCORE_LPCR(r3) | |
1632 | andis. r4, r4, LPCR_LD@h | |
1633 | bne 16f | |
1634 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
e0b7ec05 | 1635 | extsw r5,r5 |
1bc3fe81 | 1636 | 16: add r5,r5,r6 |
c5fb80d3 | 1637 | /* r5 is a guest timebase value here, convert to host TB */ |
c5fb80d3 PM |
1638 | ld r4,VCORE_TB_OFFSET(r3) |
1639 | subf r5,r4,r5 | |
e0b7ec05 PM |
1640 | std r5,VCPU_DEC_EXPIRES(r9) |
1641 | ||
b005255e MN |
1642 | BEGIN_FTR_SECTION |
1643 | b 8f | |
1644 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
b005255e MN |
1645 | /* Save POWER8-specific registers */ |
1646 | mfspr r5, SPRN_IAMR | |
1647 | mfspr r6, SPRN_PSPB | |
1648 | mfspr r7, SPRN_FSCR | |
1649 | std r5, VCPU_IAMR(r9) | |
1650 | stw r6, VCPU_PSPB(r9) | |
1651 | std r7, VCPU_FSCR(r9) | |
1652 | mfspr r5, SPRN_IC | |
b005255e MN |
1653 | mfspr r7, SPRN_TAR |
1654 | std r5, VCPU_IC(r9) | |
b005255e | 1655 | std r7, VCPU_TAR(r9) |
7b490411 | 1656 | mfspr r8, SPRN_EBBHR |
b005255e MN |
1657 | std r8, VCPU_EBBHR(r9) |
1658 | mfspr r5, SPRN_EBBRR | |
1659 | mfspr r6, SPRN_BESCR | |
83677f55 PM |
1660 | mfspr r7, SPRN_PID |
1661 | mfspr r8, SPRN_WORT | |
b005255e MN |
1662 | std r5, VCPU_EBBRR(r9) |
1663 | std r6, VCPU_BESCR(r9) | |
83677f55 PM |
1664 | stw r7, VCPU_GUEST_PID(r9) |
1665 | std r8, VCPU_WORT(r9) | |
1666 | BEGIN_FTR_SECTION | |
b005255e MN |
1667 | mfspr r5, SPRN_TCSCR |
1668 | mfspr r6, SPRN_ACOP | |
83677f55 PM |
1669 | mfspr r7, SPRN_CSIGR |
1670 | mfspr r8, SPRN_TACR | |
b005255e MN |
1671 | std r5, VCPU_TCSCR(r9) |
1672 | std r6, VCPU_ACOP(r9) | |
83677f55 PM |
1673 | std r7, VCPU_CSIGR(r9) |
1674 | std r8, VCPU_TACR(r9) | |
e9cf1e08 PM |
1675 | FTR_SECTION_ELSE |
1676 | mfspr r5, SPRN_TIDR | |
1677 | mfspr r6, SPRN_PSSCR | |
1678 | std r5, VCPU_TID(r9) | |
1679 | rldicl r6, r6, 4, 50 /* r6 &= PSSCR_GUEST_VIS */ | |
1680 | rotldi r6, r6, 60 | |
1681 | std r6, VCPU_PSSCR(r9) | |
769377f7 PM |
1682 | /* Restore host HFSCR value */ |
1683 | ld r7, STACK_SLOT_HFSCR(r1) | |
1684 | mtspr SPRN_HFSCR, r7 | |
e9cf1e08 | 1685 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300) |
ccec4456 PM |
1686 | /* |
1687 | * Restore various registers to 0, where non-zero values | |
1688 | * set by the guest could disrupt the host. | |
1689 | */ | |
1690 | li r0, 0 | |
4c3bb4cc | 1691 | mtspr SPRN_PSPB, r0 |
ccec4456 | 1692 | mtspr SPRN_WORT, r0 |
83677f55 | 1693 | BEGIN_FTR_SECTION |
4c3bb4cc | 1694 | mtspr SPRN_IAMR, r0 |
83677f55 | 1695 | mtspr SPRN_TCSCR, r0 |
ccec4456 PM |
1696 | /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */ |
1697 | li r0, 1 | |
1698 | sldi r0, r0, 31 | |
1699 | mtspr SPRN_MMCRS, r0 | |
83677f55 | 1700 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) |
b005255e MN |
1701 | 8: |
1702 | ||
e0b7ec05 | 1703 | /* Save and reset AMR and UAMOR before turning on the MMU */ |
e0b7ec05 PM |
1704 | mfspr r5,SPRN_AMR |
1705 | mfspr r6,SPRN_UAMOR | |
1706 | std r5,VCPU_AMR(r9) | |
1707 | std r6,VCPU_UAMOR(r9) | |
1708 | li r6,0 | |
1709 | mtspr SPRN_AMR,r6 | |
4c3bb4cc | 1710 | mtspr SPRN_UAMOR, r6 |
e0b7ec05 PM |
1711 | |
1712 | /* Switch DSCR back to host value */ | |
e0b7ec05 PM |
1713 | mfspr r8, SPRN_DSCR |
1714 | ld r7, HSTATE_DSCR(r13) | |
1715 | std r8, VCPU_DSCR(r9) | |
1716 | mtspr SPRN_DSCR, r7 | |
e0b7ec05 PM |
1717 | |
1718 | /* Save non-volatile GPRs */ | |
1719 | std r14, VCPU_GPR(R14)(r9) | |
1720 | std r15, VCPU_GPR(R15)(r9) | |
1721 | std r16, VCPU_GPR(R16)(r9) | |
1722 | std r17, VCPU_GPR(R17)(r9) | |
1723 | std r18, VCPU_GPR(R18)(r9) | |
1724 | std r19, VCPU_GPR(R19)(r9) | |
1725 | std r20, VCPU_GPR(R20)(r9) | |
1726 | std r21, VCPU_GPR(R21)(r9) | |
1727 | std r22, VCPU_GPR(R22)(r9) | |
1728 | std r23, VCPU_GPR(R23)(r9) | |
1729 | std r24, VCPU_GPR(R24)(r9) | |
1730 | std r25, VCPU_GPR(R25)(r9) | |
1731 | std r26, VCPU_GPR(R26)(r9) | |
1732 | std r27, VCPU_GPR(R27)(r9) | |
1733 | std r28, VCPU_GPR(R28)(r9) | |
1734 | std r29, VCPU_GPR(R29)(r9) | |
1735 | std r30, VCPU_GPR(R30)(r9) | |
1736 | std r31, VCPU_GPR(R31)(r9) | |
1737 | ||
1738 | /* Save SPRGs */ | |
1739 | mfspr r3, SPRN_SPRG0 | |
1740 | mfspr r4, SPRN_SPRG1 | |
1741 | mfspr r5, SPRN_SPRG2 | |
1742 | mfspr r6, SPRN_SPRG3 | |
1743 | std r3, VCPU_SPRG0(r9) | |
1744 | std r4, VCPU_SPRG1(r9) | |
1745 | std r5, VCPU_SPRG2(r9) | |
1746 | std r6, VCPU_SPRG3(r9) | |
1747 | ||
1748 | /* save FP state */ | |
1749 | mr r3, r9 | |
1750 | bl kvmppc_save_fp | |
de56a948 | 1751 | |
0a8eccef | 1752 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
4bb3c7a0 PM |
1753 | /* |
1754 | * Branch around the call if both CPU_FTR_TM and | |
1755 | * CPU_FTR_P9_TM_HV_ASSIST are off. | |
1756 | */ | |
0a8eccef | 1757 | BEGIN_FTR_SECTION |
4bb3c7a0 PM |
1758 | b 91f |
1759 | END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0) | |
67f8a8c1 PM |
1760 | /* |
1761 | * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR | |
1762 | */ | |
f024ee09 | 1763 | bl kvmppc_save_tm |
4bb3c7a0 | 1764 | 91: |
0a8eccef PM |
1765 | #endif |
1766 | ||
e0b7ec05 PM |
1767 | /* Increment yield count if they have a VPA */ |
1768 | ld r8, VCPU_VPA(r9) /* do they have a VPA? */ | |
1769 | cmpdi r8, 0 | |
1770 | beq 25f | |
0865a583 AG |
1771 | li r4, LPPACA_YIELDCOUNT |
1772 | LWZX_BE r3, r8, r4 | |
e0b7ec05 | 1773 | addi r3, r3, 1 |
0865a583 | 1774 | STWX_BE r3, r8, r4 |
e0b7ec05 PM |
1775 | li r3, 1 |
1776 | stb r3, VCPU_VPA_DIRTY(r9) | |
1777 | 25: | |
1778 | /* Save PMU registers if requested */ | |
1779 | /* r8 and cr0.eq are live here */ | |
9bc01a9b PM |
1780 | BEGIN_FTR_SECTION |
1781 | /* | |
1782 | * POWER8 seems to have a hardware bug where setting | |
1783 | * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE] | |
1784 | * when some counters are already negative doesn't seem | |
1785 | * to cause a performance monitor alert (and hence interrupt). | |
1786 | * The effect of this is that when saving the PMU state, | |
1787 | * if there is no PMU alert pending when we read MMCR0 | |
1788 | * before freezing the counters, but one becomes pending | |
1789 | * before we read the counters, we lose it. | |
1790 | * To work around this, we need a way to freeze the counters | |
1791 | * before reading MMCR0. Normally, freezing the counters | |
1792 | * is done by writing MMCR0 (to set MMCR0[FC]) which | |
1793 | * unavoidably writes MMCR0[PMA0] as well. On POWER8, | |
1794 | * we can also freeze the counters using MMCR2, by writing | |
1795 | * 1s to all the counter freeze condition bits (there are | |
1796 | * 9 bits each for 6 counters). | |
1797 | */ | |
1798 | li r3, -1 /* set all freeze bits */ | |
1799 | clrrdi r3, r3, 10 | |
1800 | mfspr r10, SPRN_MMCR2 | |
1801 | mtspr SPRN_MMCR2, r3 | |
1802 | isync | |
1803 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
e0b7ec05 PM |
1804 | li r3, 1 |
1805 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
1806 | mfspr r4, SPRN_MMCR0 /* save MMCR0 */ | |
1807 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ | |
1808 | mfspr r6, SPRN_MMCRA | |
c17b98cf | 1809 | /* Clear MMCRA in order to disable SDAR updates */ |
e0b7ec05 PM |
1810 | li r7, 0 |
1811 | mtspr SPRN_MMCRA, r7 | |
e0b7ec05 PM |
1812 | isync |
1813 | beq 21f /* if no VPA, save PMU stuff anyway */ | |
1814 | lbz r7, LPPACA_PMCINUSE(r8) | |
1815 | cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */ | |
1816 | bne 21f | |
1817 | std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */ | |
1818 | b 22f | |
1819 | 21: mfspr r5, SPRN_MMCR1 | |
1820 | mfspr r7, SPRN_SIAR | |
1821 | mfspr r8, SPRN_SDAR | |
1822 | std r4, VCPU_MMCR(r9) | |
1823 | std r5, VCPU_MMCR + 8(r9) | |
1824 | std r6, VCPU_MMCR + 16(r9) | |
9bc01a9b PM |
1825 | BEGIN_FTR_SECTION |
1826 | std r10, VCPU_MMCR + 24(r9) | |
1827 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
e0b7ec05 PM |
1828 | std r7, VCPU_SIAR(r9) |
1829 | std r8, VCPU_SDAR(r9) | |
1830 | mfspr r3, SPRN_PMC1 | |
1831 | mfspr r4, SPRN_PMC2 | |
1832 | mfspr r5, SPRN_PMC3 | |
1833 | mfspr r6, SPRN_PMC4 | |
1834 | mfspr r7, SPRN_PMC5 | |
1835 | mfspr r8, SPRN_PMC6 | |
e0b7ec05 PM |
1836 | stw r3, VCPU_PMC(r9) |
1837 | stw r4, VCPU_PMC + 4(r9) | |
1838 | stw r5, VCPU_PMC + 8(r9) | |
1839 | stw r6, VCPU_PMC + 12(r9) | |
1840 | stw r7, VCPU_PMC + 16(r9) | |
1841 | stw r8, VCPU_PMC + 20(r9) | |
b005255e | 1842 | BEGIN_FTR_SECTION |
b005255e | 1843 | mfspr r5, SPRN_SIER |
83677f55 PM |
1844 | std r5, VCPU_SIER(r9) |
1845 | BEGIN_FTR_SECTION_NESTED(96) | |
b005255e MN |
1846 | mfspr r6, SPRN_SPMC1 |
1847 | mfspr r7, SPRN_SPMC2 | |
1848 | mfspr r8, SPRN_MMCRS | |
b005255e MN |
1849 | stw r6, VCPU_PMC + 24(r9) |
1850 | stw r7, VCPU_PMC + 28(r9) | |
1851 | std r8, VCPU_MMCR + 32(r9) | |
1852 | lis r4, 0x8000 | |
1853 | mtspr SPRN_MMCRS, r4 | |
83677f55 | 1854 | END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96) |
b005255e | 1855 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
e0b7ec05 | 1856 | 22: |
de56a948 | 1857 | |
e9cf1e08 | 1858 | /* Restore host values of some registers */ |
7ceaa6dc PM |
1859 | BEGIN_FTR_SECTION |
1860 | ld r5, STACK_SLOT_CIABR(r1) | |
1861 | ld r6, STACK_SLOT_DAWR(r1) | |
1862 | ld r7, STACK_SLOT_DAWRX(r1) | |
1863 | mtspr SPRN_CIABR, r5 | |
b53221e7 MN |
1864 | /* |
1865 | * If the DAWR doesn't work, it's ok to write these here as | |
1866 | * this value should always be zero | |
1867 | */ | |
7ceaa6dc PM |
1868 | mtspr SPRN_DAWR, r6 |
1869 | mtspr SPRN_DAWRX, r7 | |
1870 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
e9cf1e08 PM |
1871 | BEGIN_FTR_SECTION |
1872 | ld r5, STACK_SLOT_TID(r1) | |
1873 | ld r6, STACK_SLOT_PSSCR(r1) | |
f4c51f84 | 1874 | ld r7, STACK_SLOT_PID(r1) |
4c3bb4cc | 1875 | ld r8, STACK_SLOT_IAMR(r1) |
e9cf1e08 PM |
1876 | mtspr SPRN_TIDR, r5 |
1877 | mtspr SPRN_PSSCR, r6 | |
f4c51f84 | 1878 | mtspr SPRN_PID, r7 |
4c3bb4cc | 1879 | mtspr SPRN_IAMR, r8 |
e9cf1e08 | 1880 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) |
a25bd72b BH |
1881 | |
1882 | #ifdef CONFIG_PPC_RADIX_MMU | |
1883 | /* | |
1884 | * Are we running hash or radix ? | |
1885 | */ | |
67f8a8c1 PM |
1886 | ld r5, VCPU_KVM(r9) |
1887 | lbz r0, KVM_RADIX(r5) | |
1888 | cmpwi cr2, r0, 0 | |
6964e6a4 | 1889 | beq cr2, 4f |
a25bd72b BH |
1890 | |
1891 | /* Radix: Handle the case where the guest used an illegal PID */ | |
1892 | LOAD_REG_ADDR(r4, mmu_base_pid) | |
1893 | lwz r3, VCPU_GUEST_PID(r9) | |
1894 | lwz r5, 0(r4) | |
1895 | cmpw cr0,r3,r5 | |
1896 | blt 2f | |
1897 | ||
1898 | /* | |
1899 | * Illegal PID, the HW might have prefetched and cached in the TLB | |
1900 | * some translations for the LPID 0 / guest PID combination which | |
1901 | * Linux doesn't know about, so we need to flush that PID out of | |
1902 | * the TLB. First we need to set LPIDR to 0 so tlbiel applies to | |
1903 | * the right context. | |
1904 | */ | |
1905 | li r0,0 | |
1906 | mtspr SPRN_LPID,r0 | |
1907 | isync | |
1908 | ||
1909 | /* Then do a congruence class local flush */ | |
1910 | ld r6,VCPU_KVM(r9) | |
1911 | lwz r0,KVM_TLB_SETS(r6) | |
1912 | mtctr r0 | |
1913 | li r7,0x400 /* IS field = 0b01 */ | |
1914 | ptesync | |
1915 | sldi r0,r3,32 /* RS has PID */ | |
1916 | 1: PPC_TLBIEL(7,0,2,1,1) /* RIC=2, PRS=1, R=1 */ | |
1917 | addi r7,r7,0x1000 | |
1918 | bdnz 1b | |
1919 | ptesync | |
1920 | ||
1921 | 2: /* Flush the ERAT on radix P9 DD1 guest exit */ | |
f11f6f79 PM |
1922 | BEGIN_FTR_SECTION |
1923 | PPC_INVALIDATE_ERAT | |
1924 | END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1) | |
6964e6a4 | 1925 | 4: |
a25bd72b | 1926 | #endif /* CONFIG_PPC_RADIX_MMU */ |
e9cf1e08 | 1927 | |
9e368f29 | 1928 | /* |
c17b98cf | 1929 | * POWER7/POWER8 guest -> host partition switch code. |
9e368f29 PM |
1930 | * We don't have to lock against tlbies but we do |
1931 | * have to coordinate the hardware threads. | |
1932 | */ | |
b6c295df | 1933 | kvmhv_switch_to_host: |
371fefd6 | 1934 | /* Secondary threads wait for primary to do partition switch */ |
6af27c84 | 1935 | ld r5,HSTATE_KVM_VCORE(r13) |
e0b7ec05 PM |
1936 | ld r4,VCORE_KVM(r5) /* pointer to struct kvm */ |
1937 | lbz r3,HSTATE_PTID(r13) | |
371fefd6 PM |
1938 | cmpwi r3,0 |
1939 | beq 15f | |
1940 | HMT_LOW | |
1941 | 13: lbz r3,VCORE_IN_GUEST(r5) | |
1942 | cmpwi r3,0 | |
1943 | bne 13b | |
1944 | HMT_MEDIUM | |
1945 | b 16f | |
1946 | ||
1947 | /* Primary thread waits for all the secondaries to exit guest */ | |
1948 | 15: lwz r3,VCORE_ENTRY_EXIT(r5) | |
b4deba5c | 1949 | rlwinm r0,r3,32-8,0xff |
371fefd6 PM |
1950 | clrldi r3,r3,56 |
1951 | cmpw r3,r0 | |
1952 | bne 15b | |
1953 | isync | |
1954 | ||
b4deba5c PM |
1955 | /* Did we actually switch to the guest at all? */ |
1956 | lbz r6, VCORE_IN_GUEST(r5) | |
1957 | cmpwi r6, 0 | |
1958 | beq 19f | |
1959 | ||
371fefd6 | 1960 | /* Primary thread switches back to host partition */ |
de56a948 | 1961 | lwz r7,KVM_HOST_LPID(r4) |
7a84084c PM |
1962 | BEGIN_FTR_SECTION |
1963 | ld r6,KVM_HOST_SDR1(r4) | |
de56a948 PM |
1964 | li r8,LPID_RSVD /* switch to reserved LPID */ |
1965 | mtspr SPRN_LPID,r8 | |
1966 | ptesync | |
7a84084c PM |
1967 | mtspr SPRN_SDR1,r6 /* switch to host page table */ |
1968 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) | |
de56a948 PM |
1969 | mtspr SPRN_LPID,r7 |
1970 | isync | |
93b0f4dc | 1971 | |
b005255e | 1972 | BEGIN_FTR_SECTION |
88b02cf9 | 1973 | /* DPDES and VTB are shared between threads */ |
b005255e | 1974 | mfspr r7, SPRN_DPDES |
88b02cf9 | 1975 | mfspr r8, SPRN_VTB |
b005255e | 1976 | std r7, VCORE_DPDES(r5) |
88b02cf9 | 1977 | std r8, VCORE_VTB(r5) |
b005255e MN |
1978 | /* clear DPDES so we don't get guest doorbells in the host */ |
1979 | li r8, 0 | |
1980 | mtspr SPRN_DPDES, r8 | |
1981 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
1982 | ||
fd7bacbc MS |
1983 | /* If HMI, call kvmppc_realmode_hmi_handler() */ |
1984 | cmpwi r12, BOOK3S_INTERRUPT_HMI | |
1985 | bne 27f | |
1986 | bl kvmppc_realmode_hmi_handler | |
1987 | nop | |
d075745d | 1988 | cmpdi r3, 0 |
fd7bacbc MS |
1989 | li r12, BOOK3S_INTERRUPT_HMI |
1990 | /* | |
d075745d PM |
1991 | * At this point kvmppc_realmode_hmi_handler may have resync-ed |
1992 | * the TB, and if it has, we must not subtract the guest timebase | |
1993 | * offset from the timebase. So, skip it. | |
fd7bacbc MS |
1994 | * |
1995 | * Also, do not call kvmppc_subcore_exit_guest() because it has | |
1996 | * been invoked as part of kvmppc_realmode_hmi_handler(). | |
1997 | */ | |
d075745d | 1998 | beq 30f |
fd7bacbc MS |
1999 | |
2000 | 27: | |
93b0f4dc PM |
2001 | /* Subtract timebase offset from timebase */ |
2002 | ld r8,VCORE_TB_OFFSET(r5) | |
2003 | cmpdi r8,0 | |
2004 | beq 17f | |
c5fb80d3 | 2005 | mftb r6 /* current guest timebase */ |
93b0f4dc PM |
2006 | subf r8,r8,r6 |
2007 | mtspr SPRN_TBU40,r8 /* update upper 40 bits */ | |
2008 | mftb r7 /* check if lower 24 bits overflowed */ | |
2009 | clrldi r6,r6,40 | |
2010 | clrldi r7,r7,40 | |
2011 | cmpld r7,r6 | |
2012 | bge 17f | |
2013 | addis r8,r8,0x100 /* if so, increment upper 40 bits */ | |
2014 | mtspr SPRN_TBU40,r8 | |
2015 | ||
fd7bacbc MS |
2016 | 17: bl kvmppc_subcore_exit_guest |
2017 | nop | |
2018 | 30: ld r5,HSTATE_KVM_VCORE(r13) | |
2019 | ld r4,VCORE_KVM(r5) /* pointer to struct kvm */ | |
2020 | ||
388cc6e1 | 2021 | /* Reset PCR */ |
fd7bacbc | 2022 | ld r0, VCORE_PCR(r5) |
388cc6e1 PM |
2023 | cmpdi r0, 0 |
2024 | beq 18f | |
2025 | li r0, 0 | |
2026 | mtspr SPRN_PCR, r0 | |
2027 | 18: | |
93b0f4dc | 2028 | /* Signal secondary CPUs to continue */ |
371fefd6 | 2029 | stb r0,VCORE_IN_GUEST(r5) |
b4deba5c | 2030 | 19: lis r8,0x7fff /* MAX_INT@h */ |
de56a948 PM |
2031 | mtspr SPRN_HDEC,r8 |
2032 | ||
c0101509 PM |
2033 | 16: |
2034 | BEGIN_FTR_SECTION | |
2035 | /* On POWER9 with HPT-on-radix we need to wait for all other threads */ | |
2036 | ld r3, HSTATE_SPLIT_MODE(r13) | |
2037 | cmpdi r3, 0 | |
2038 | beq 47f | |
2039 | lwz r8, KVM_SPLIT_DO_RESTORE(r3) | |
2040 | cmpwi r8, 0 | |
2041 | beq 47f | |
2042 | stw r12, STACK_SLOT_TRAP(r1) | |
2043 | bl kvmhv_p9_restore_lpcr | |
2044 | nop | |
2045 | lwz r12, STACK_SLOT_TRAP(r1) | |
2046 | b 48f | |
2047 | 47: | |
2048 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
2049 | ld r8,KVM_HOST_LPCR(r4) | |
de56a948 PM |
2050 | mtspr SPRN_LPCR,r8 |
2051 | isync | |
c0101509 | 2052 | 48: |
de56a948 | 2053 | /* load host SLB entries */ |
f4c51f84 PM |
2054 | BEGIN_MMU_FTR_SECTION |
2055 | b 0f | |
2056 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX) | |
c17b98cf | 2057 | ld r8,PACA_SLBSHADOWPTR(r13) |
de56a948 PM |
2058 | |
2059 | .rept SLB_NUM_BOLTED | |
0865a583 AG |
2060 | li r3, SLBSHADOW_SAVEAREA |
2061 | LDX_BE r5, r8, r3 | |
2062 | addi r3, r3, 8 | |
2063 | LDX_BE r6, r8, r3 | |
de56a948 PM |
2064 | andis. r7,r5,SLB_ESID_V@h |
2065 | beq 1f | |
2066 | slbmte r6,r5 | |
2067 | 1: addi r8,r8,16 | |
2068 | .endr | |
f4c51f84 | 2069 | 0: |
b6c295df PM |
2070 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
2071 | /* Finish timing, if we have a vcpu */ | |
2072 | ld r4, HSTATE_KVM_VCPU(r13) | |
2073 | cmpdi r4, 0 | |
2074 | li r3, 0 | |
2075 | beq 2f | |
2076 | bl kvmhv_accumulate_time | |
2077 | 2: | |
2078 | #endif | |
44a3add8 PM |
2079 | /* Unset guest mode */ |
2080 | li r0, KVM_GUEST_MODE_NONE | |
2081 | stb r0, HSTATE_IN_GUEST(r13) | |
2082 | ||
7ceaa6dc PM |
2083 | ld r0, SFS+PPC_LR_STKOFF(r1) |
2084 | addi r1, r1, SFS | |
218309b7 PM |
2085 | mtlr r0 |
2086 | blr | |
b4072df4 | 2087 | |
4bb3c7a0 PM |
2088 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
2089 | /* | |
2090 | * Softpatch interrupt for transactional memory emulation cases | |
2091 | * on POWER9 DD2.2. This is early in the guest exit path - we | |
2092 | * haven't saved registers or done a treclaim yet. | |
2093 | */ | |
2094 | kvmppc_tm_emul: | |
2095 | /* Save instruction image in HEIR */ | |
2096 | mfspr r3, SPRN_HEIR | |
2097 | stw r3, VCPU_HEIR(r9) | |
2098 | ||
2099 | /* | |
2100 | * The cases we want to handle here are those where the guest | |
2101 | * is in real suspend mode and is trying to transition to | |
2102 | * transactional mode. | |
2103 | */ | |
2104 | lbz r0, HSTATE_FAKE_SUSPEND(r13) | |
2105 | cmpwi r0, 0 /* keep exiting guest if in fake suspend */ | |
2106 | bne guest_exit_cont | |
2107 | rldicl r3, r11, 64 - MSR_TS_S_LG, 62 | |
2108 | cmpwi r3, 1 /* or if not in suspend state */ | |
2109 | bne guest_exit_cont | |
2110 | ||
2111 | /* Call C code to do the emulation */ | |
2112 | mr r3, r9 | |
2113 | bl kvmhv_p9_tm_emulation_early | |
2114 | nop | |
2115 | ld r9, HSTATE_KVM_VCPU(r13) | |
2116 | li r12, BOOK3S_INTERRUPT_HV_SOFTPATCH | |
2117 | cmpwi r3, 0 | |
2118 | beq guest_exit_cont /* continue exiting if not handled */ | |
2119 | ld r10, VCPU_PC(r9) | |
2120 | ld r11, VCPU_MSR(r9) | |
2121 | b fast_interrupt_c_return /* go back to guest if handled */ | |
2122 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ | |
2123 | ||
697d3899 PM |
2124 | /* |
2125 | * Check whether an HDSI is an HPTE not found fault or something else. | |
2126 | * If it is an HPTE not found fault that is due to the guest accessing | |
2127 | * a page that they have mapped but which we have paged out, then | |
2128 | * we continue on with the guest exit path. In all other cases, | |
2129 | * reflect the HDSI to the guest as a DSI. | |
2130 | */ | |
2131 | kvmppc_hdsi: | |
f4c51f84 PM |
2132 | ld r3, VCPU_KVM(r9) |
2133 | lbz r0, KVM_RADIX(r3) | |
697d3899 PM |
2134 | mfspr r4, SPRN_HDAR |
2135 | mfspr r6, SPRN_HDSISR | |
e001fa78 MN |
2136 | BEGIN_FTR_SECTION |
2137 | /* Look for DSISR canary. If we find it, retry instruction */ | |
2138 | cmpdi r6, 0x7fff | |
2139 | beq 6f | |
2140 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
2141 | cmpwi r0, 0 | |
f4c51f84 | 2142 | bne .Lradix_hdsi /* on radix, just save DAR/DSISR/ASDR */ |
4cf302bc PM |
2143 | /* HPTE not found fault or protection fault? */ |
2144 | andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h | |
697d3899 | 2145 | beq 1f /* if not, send it to the guest */ |
4e5acdc2 PM |
2146 | andi. r0, r11, MSR_DR /* data relocation enabled? */ |
2147 | beq 3f | |
ef8c640c PM |
2148 | BEGIN_FTR_SECTION |
2149 | mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */ | |
2150 | b 4f | |
2151 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
697d3899 | 2152 | clrrdi r0, r4, 28 |
c75df6f9 | 2153 | PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */ |
cf29b215 PM |
2154 | li r0, BOOK3S_INTERRUPT_DATA_SEGMENT |
2155 | bne 7f /* if no SLB entry found */ | |
697d3899 PM |
2156 | 4: std r4, VCPU_FAULT_DAR(r9) |
2157 | stw r6, VCPU_FAULT_DSISR(r9) | |
2158 | ||
2159 | /* Search the hash table. */ | |
2160 | mr r3, r9 /* vcpu pointer */ | |
342d3db7 | 2161 | li r7, 1 /* data fault */ |
b1576fec | 2162 | bl kvmppc_hpte_hv_fault |
697d3899 PM |
2163 | ld r9, HSTATE_KVM_VCPU(r13) |
2164 | ld r10, VCPU_PC(r9) | |
2165 | ld r11, VCPU_MSR(r9) | |
2166 | li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE | |
2167 | cmpdi r3, 0 /* retry the instruction */ | |
2168 | beq 6f | |
2169 | cmpdi r3, -1 /* handle in kernel mode */ | |
b4072df4 | 2170 | beq guest_exit_cont |
697d3899 PM |
2171 | cmpdi r3, -2 /* MMIO emulation; need instr word */ |
2172 | beq 2f | |
2173 | ||
cf29b215 | 2174 | /* Synthesize a DSI (or DSegI) for the guest */ |
697d3899 PM |
2175 | ld r4, VCPU_FAULT_DAR(r9) |
2176 | mr r6, r3 | |
cf29b215 | 2177 | 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE |
697d3899 | 2178 | mtspr SPRN_DSISR, r6 |
cf29b215 | 2179 | 7: mtspr SPRN_DAR, r4 |
697d3899 PM |
2180 | mtspr SPRN_SRR0, r10 |
2181 | mtspr SPRN_SRR1, r11 | |
cf29b215 | 2182 | mr r10, r0 |
e4e38121 | 2183 | bl kvmppc_msr_interrupt |
b4072df4 | 2184 | fast_interrupt_c_return: |
697d3899 | 2185 | 6: ld r7, VCPU_CTR(r9) |
c63517c2 | 2186 | ld r8, VCPU_XER(r9) |
697d3899 PM |
2187 | mtctr r7 |
2188 | mtxer r8 | |
2189 | mr r4, r9 | |
2190 | b fast_guest_return | |
2191 | ||
2192 | 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */ | |
2193 | ld r5, KVM_VRMA_SLB_V(r5) | |
2194 | b 4b | |
2195 | ||
2196 | /* If this is for emulated MMIO, load the instruction word */ | |
2197 | 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */ | |
2198 | ||
2199 | /* Set guest mode to 'jump over instruction' so if lwz faults | |
2200 | * we'll just continue at the next IP. */ | |
2201 | li r0, KVM_GUEST_MODE_SKIP | |
2202 | stb r0, HSTATE_IN_GUEST(r13) | |
2203 | ||
2204 | /* Do the access with MSR:DR enabled */ | |
2205 | mfmsr r3 | |
2206 | ori r4, r3, MSR_DR /* Enable paging for data */ | |
2207 | mtmsrd r4 | |
2208 | lwz r8, 0(r10) | |
2209 | mtmsrd r3 | |
2210 | ||
2211 | /* Store the result */ | |
2212 | stw r8, VCPU_LAST_INST(r9) | |
2213 | ||
2214 | /* Unset guest mode. */ | |
44a3add8 | 2215 | li r0, KVM_GUEST_MODE_HOST_HV |
697d3899 | 2216 | stb r0, HSTATE_IN_GUEST(r13) |
b4072df4 | 2217 | b guest_exit_cont |
de56a948 | 2218 | |
f4c51f84 PM |
2219 | .Lradix_hdsi: |
2220 | std r4, VCPU_FAULT_DAR(r9) | |
2221 | stw r6, VCPU_FAULT_DSISR(r9) | |
2222 | .Lradix_hisi: | |
2223 | mfspr r5, SPRN_ASDR | |
2224 | std r5, VCPU_FAULT_GPA(r9) | |
2225 | b guest_exit_cont | |
2226 | ||
342d3db7 PM |
2227 | /* |
2228 | * Similarly for an HISI, reflect it to the guest as an ISI unless | |
2229 | * it is an HPTE not found fault for a page that we have paged out. | |
2230 | */ | |
2231 | kvmppc_hisi: | |
f4c51f84 PM |
2232 | ld r3, VCPU_KVM(r9) |
2233 | lbz r0, KVM_RADIX(r3) | |
2234 | cmpwi r0, 0 | |
2235 | bne .Lradix_hisi /* for radix, just save ASDR */ | |
342d3db7 PM |
2236 | andis. r0, r11, SRR1_ISI_NOPT@h |
2237 | beq 1f | |
4e5acdc2 PM |
2238 | andi. r0, r11, MSR_IR /* instruction relocation enabled? */ |
2239 | beq 3f | |
ef8c640c PM |
2240 | BEGIN_FTR_SECTION |
2241 | mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */ | |
2242 | b 4f | |
2243 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
342d3db7 | 2244 | clrrdi r0, r10, 28 |
c75df6f9 | 2245 | PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */ |
cf29b215 PM |
2246 | li r0, BOOK3S_INTERRUPT_INST_SEGMENT |
2247 | bne 7f /* if no SLB entry found */ | |
342d3db7 PM |
2248 | 4: |
2249 | /* Search the hash table. */ | |
2250 | mr r3, r9 /* vcpu pointer */ | |
2251 | mr r4, r10 | |
2252 | mr r6, r11 | |
2253 | li r7, 0 /* instruction fault */ | |
b1576fec | 2254 | bl kvmppc_hpte_hv_fault |
342d3db7 PM |
2255 | ld r9, HSTATE_KVM_VCPU(r13) |
2256 | ld r10, VCPU_PC(r9) | |
2257 | ld r11, VCPU_MSR(r9) | |
2258 | li r12, BOOK3S_INTERRUPT_H_INST_STORAGE | |
2259 | cmpdi r3, 0 /* retry the instruction */ | |
b4072df4 | 2260 | beq fast_interrupt_c_return |
342d3db7 | 2261 | cmpdi r3, -1 /* handle in kernel mode */ |
b4072df4 | 2262 | beq guest_exit_cont |
342d3db7 | 2263 | |
cf29b215 | 2264 | /* Synthesize an ISI (or ISegI) for the guest */ |
342d3db7 | 2265 | mr r11, r3 |
cf29b215 PM |
2266 | 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE |
2267 | 7: mtspr SPRN_SRR0, r10 | |
342d3db7 | 2268 | mtspr SPRN_SRR1, r11 |
cf29b215 | 2269 | mr r10, r0 |
e4e38121 | 2270 | bl kvmppc_msr_interrupt |
b4072df4 | 2271 | b fast_interrupt_c_return |
342d3db7 PM |
2272 | |
2273 | 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */ | |
2274 | ld r5, KVM_VRMA_SLB_V(r6) | |
2275 | b 4b | |
2276 | ||
a8606e20 PM |
2277 | /* |
2278 | * Try to handle an hcall in real mode. | |
2279 | * Returns to the guest if we handle it, or continues on up to | |
2280 | * the kernel if we can't (i.e. if we don't have a handler for | |
2281 | * it, or if the handler returns H_TOO_HARD). | |
1f09c3ed PM |
2282 | * |
2283 | * r5 - r8 contain hcall args, | |
2284 | * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca | |
a8606e20 | 2285 | */ |
a8606e20 | 2286 | hcall_try_real_mode: |
c75df6f9 | 2287 | ld r3,VCPU_GPR(R3)(r9) |
a8606e20 | 2288 | andi. r0,r11,MSR_PR |
27025a60 LPF |
2289 | /* sc 1 from userspace - reflect to guest syscall */ |
2290 | bne sc_1_fast_return | |
a8606e20 PM |
2291 | clrrdi r3,r3,2 |
2292 | cmpldi r3,hcall_real_table_end - hcall_real_table | |
b4072df4 | 2293 | bge guest_exit_cont |
699a0ea0 PM |
2294 | /* See if this hcall is enabled for in-kernel handling */ |
2295 | ld r4, VCPU_KVM(r9) | |
2296 | srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */ | |
2297 | sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */ | |
2298 | add r4, r4, r0 | |
2299 | ld r0, KVM_ENABLED_HCALLS(r4) | |
2300 | rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */ | |
2301 | srd r0, r0, r4 | |
2302 | andi. r0, r0, 1 | |
2303 | beq guest_exit_cont | |
2304 | /* Get pointer to handler, if any, and call it */ | |
a8606e20 | 2305 | LOAD_REG_ADDR(r4, hcall_real_table) |
4baa1d87 | 2306 | lwax r3,r3,r4 |
a8606e20 | 2307 | cmpwi r3,0 |
b4072df4 | 2308 | beq guest_exit_cont |
05a308c7 AB |
2309 | add r12,r3,r4 |
2310 | mtctr r12 | |
a8606e20 | 2311 | mr r3,r9 /* get vcpu pointer */ |
c75df6f9 | 2312 | ld r4,VCPU_GPR(R4)(r9) |
a8606e20 PM |
2313 | bctrl |
2314 | cmpdi r3,H_TOO_HARD | |
2315 | beq hcall_real_fallback | |
2316 | ld r4,HSTATE_KVM_VCPU(r13) | |
c75df6f9 | 2317 | std r3,VCPU_GPR(R3)(r4) |
a8606e20 PM |
2318 | ld r10,VCPU_PC(r4) |
2319 | ld r11,VCPU_MSR(r4) | |
2320 | b fast_guest_return | |
2321 | ||
27025a60 LPF |
2322 | sc_1_fast_return: |
2323 | mtspr SPRN_SRR0,r10 | |
2324 | mtspr SPRN_SRR1,r11 | |
2325 | li r10, BOOK3S_INTERRUPT_SYSCALL | |
e4e38121 | 2326 | bl kvmppc_msr_interrupt |
27025a60 LPF |
2327 | mr r4,r9 |
2328 | b fast_guest_return | |
2329 | ||
a8606e20 PM |
2330 | /* We've attempted a real mode hcall, but it's punted it back |
2331 | * to userspace. We need to restore some clobbered volatiles | |
2332 | * before resuming the pass-it-to-qemu path */ | |
2333 | hcall_real_fallback: | |
2334 | li r12,BOOK3S_INTERRUPT_SYSCALL | |
2335 | ld r9, HSTATE_KVM_VCPU(r13) | |
a8606e20 | 2336 | |
b4072df4 | 2337 | b guest_exit_cont |
a8606e20 PM |
2338 | |
2339 | .globl hcall_real_table | |
2340 | hcall_real_table: | |
2341 | .long 0 /* 0 - unused */ | |
c1fb0194 AB |
2342 | .long DOTSYM(kvmppc_h_remove) - hcall_real_table |
2343 | .long DOTSYM(kvmppc_h_enter) - hcall_real_table | |
2344 | .long DOTSYM(kvmppc_h_read) - hcall_real_table | |
cdeee518 PM |
2345 | .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table |
2346 | .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table | |
c1fb0194 AB |
2347 | .long DOTSYM(kvmppc_h_protect) - hcall_real_table |
2348 | .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table | |
31217db7 | 2349 | .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table |
a8606e20 | 2350 | .long 0 /* 0x24 - H_SET_SPRG0 */ |
c1fb0194 | 2351 | .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table |
a8606e20 PM |
2352 | .long 0 /* 0x2c */ |
2353 | .long 0 /* 0x30 */ | |
2354 | .long 0 /* 0x34 */ | |
2355 | .long 0 /* 0x38 */ | |
2356 | .long 0 /* 0x3c */ | |
2357 | .long 0 /* 0x40 */ | |
2358 | .long 0 /* 0x44 */ | |
2359 | .long 0 /* 0x48 */ | |
2360 | .long 0 /* 0x4c */ | |
2361 | .long 0 /* 0x50 */ | |
2362 | .long 0 /* 0x54 */ | |
2363 | .long 0 /* 0x58 */ | |
2364 | .long 0 /* 0x5c */ | |
2365 | .long 0 /* 0x60 */ | |
e7d26f28 | 2366 | #ifdef CONFIG_KVM_XICS |
c1fb0194 AB |
2367 | .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table |
2368 | .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table | |
2369 | .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table | |
5af50993 | 2370 | .long DOTSYM(kvmppc_rm_h_ipoll) - hcall_real_table |
c1fb0194 | 2371 | .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table |
e7d26f28 BH |
2372 | #else |
2373 | .long 0 /* 0x64 - H_EOI */ | |
2374 | .long 0 /* 0x68 - H_CPPR */ | |
2375 | .long 0 /* 0x6c - H_IPI */ | |
2376 | .long 0 /* 0x70 - H_IPOLL */ | |
2377 | .long 0 /* 0x74 - H_XIRR */ | |
2378 | #endif | |
a8606e20 PM |
2379 | .long 0 /* 0x78 */ |
2380 | .long 0 /* 0x7c */ | |
2381 | .long 0 /* 0x80 */ | |
2382 | .long 0 /* 0x84 */ | |
2383 | .long 0 /* 0x88 */ | |
2384 | .long 0 /* 0x8c */ | |
2385 | .long 0 /* 0x90 */ | |
2386 | .long 0 /* 0x94 */ | |
2387 | .long 0 /* 0x98 */ | |
2388 | .long 0 /* 0x9c */ | |
2389 | .long 0 /* 0xa0 */ | |
2390 | .long 0 /* 0xa4 */ | |
2391 | .long 0 /* 0xa8 */ | |
2392 | .long 0 /* 0xac */ | |
2393 | .long 0 /* 0xb0 */ | |
2394 | .long 0 /* 0xb4 */ | |
2395 | .long 0 /* 0xb8 */ | |
2396 | .long 0 /* 0xbc */ | |
2397 | .long 0 /* 0xc0 */ | |
2398 | .long 0 /* 0xc4 */ | |
2399 | .long 0 /* 0xc8 */ | |
2400 | .long 0 /* 0xcc */ | |
2401 | .long 0 /* 0xd0 */ | |
2402 | .long 0 /* 0xd4 */ | |
2403 | .long 0 /* 0xd8 */ | |
2404 | .long 0 /* 0xdc */ | |
c1fb0194 | 2405 | .long DOTSYM(kvmppc_h_cede) - hcall_real_table |
90fd09f8 | 2406 | .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table |
a8606e20 PM |
2407 | .long 0 /* 0xe8 */ |
2408 | .long 0 /* 0xec */ | |
2409 | .long 0 /* 0xf0 */ | |
2410 | .long 0 /* 0xf4 */ | |
2411 | .long 0 /* 0xf8 */ | |
2412 | .long 0 /* 0xfc */ | |
2413 | .long 0 /* 0x100 */ | |
2414 | .long 0 /* 0x104 */ | |
2415 | .long 0 /* 0x108 */ | |
2416 | .long 0 /* 0x10c */ | |
2417 | .long 0 /* 0x110 */ | |
2418 | .long 0 /* 0x114 */ | |
2419 | .long 0 /* 0x118 */ | |
2420 | .long 0 /* 0x11c */ | |
2421 | .long 0 /* 0x120 */ | |
c1fb0194 | 2422 | .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table |
8563bf52 PM |
2423 | .long 0 /* 0x128 */ |
2424 | .long 0 /* 0x12c */ | |
2425 | .long 0 /* 0x130 */ | |
c1fb0194 | 2426 | .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table |
31217db7 | 2427 | .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table |
d3695aa4 | 2428 | .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table |
e928e9cb ME |
2429 | .long 0 /* 0x140 */ |
2430 | .long 0 /* 0x144 */ | |
2431 | .long 0 /* 0x148 */ | |
2432 | .long 0 /* 0x14c */ | |
2433 | .long 0 /* 0x150 */ | |
2434 | .long 0 /* 0x154 */ | |
2435 | .long 0 /* 0x158 */ | |
2436 | .long 0 /* 0x15c */ | |
2437 | .long 0 /* 0x160 */ | |
2438 | .long 0 /* 0x164 */ | |
2439 | .long 0 /* 0x168 */ | |
2440 | .long 0 /* 0x16c */ | |
2441 | .long 0 /* 0x170 */ | |
2442 | .long 0 /* 0x174 */ | |
2443 | .long 0 /* 0x178 */ | |
2444 | .long 0 /* 0x17c */ | |
2445 | .long 0 /* 0x180 */ | |
2446 | .long 0 /* 0x184 */ | |
2447 | .long 0 /* 0x188 */ | |
2448 | .long 0 /* 0x18c */ | |
2449 | .long 0 /* 0x190 */ | |
2450 | .long 0 /* 0x194 */ | |
2451 | .long 0 /* 0x198 */ | |
2452 | .long 0 /* 0x19c */ | |
2453 | .long 0 /* 0x1a0 */ | |
2454 | .long 0 /* 0x1a4 */ | |
2455 | .long 0 /* 0x1a8 */ | |
2456 | .long 0 /* 0x1ac */ | |
2457 | .long 0 /* 0x1b0 */ | |
2458 | .long 0 /* 0x1b4 */ | |
2459 | .long 0 /* 0x1b8 */ | |
2460 | .long 0 /* 0x1bc */ | |
2461 | .long 0 /* 0x1c0 */ | |
2462 | .long 0 /* 0x1c4 */ | |
2463 | .long 0 /* 0x1c8 */ | |
2464 | .long 0 /* 0x1cc */ | |
2465 | .long 0 /* 0x1d0 */ | |
2466 | .long 0 /* 0x1d4 */ | |
2467 | .long 0 /* 0x1d8 */ | |
2468 | .long 0 /* 0x1dc */ | |
2469 | .long 0 /* 0x1e0 */ | |
2470 | .long 0 /* 0x1e4 */ | |
2471 | .long 0 /* 0x1e8 */ | |
2472 | .long 0 /* 0x1ec */ | |
2473 | .long 0 /* 0x1f0 */ | |
2474 | .long 0 /* 0x1f4 */ | |
2475 | .long 0 /* 0x1f8 */ | |
2476 | .long 0 /* 0x1fc */ | |
2477 | .long 0 /* 0x200 */ | |
2478 | .long 0 /* 0x204 */ | |
2479 | .long 0 /* 0x208 */ | |
2480 | .long 0 /* 0x20c */ | |
2481 | .long 0 /* 0x210 */ | |
2482 | .long 0 /* 0x214 */ | |
2483 | .long 0 /* 0x218 */ | |
2484 | .long 0 /* 0x21c */ | |
2485 | .long 0 /* 0x220 */ | |
2486 | .long 0 /* 0x224 */ | |
2487 | .long 0 /* 0x228 */ | |
2488 | .long 0 /* 0x22c */ | |
2489 | .long 0 /* 0x230 */ | |
2490 | .long 0 /* 0x234 */ | |
2491 | .long 0 /* 0x238 */ | |
2492 | .long 0 /* 0x23c */ | |
2493 | .long 0 /* 0x240 */ | |
2494 | .long 0 /* 0x244 */ | |
2495 | .long 0 /* 0x248 */ | |
2496 | .long 0 /* 0x24c */ | |
2497 | .long 0 /* 0x250 */ | |
2498 | .long 0 /* 0x254 */ | |
2499 | .long 0 /* 0x258 */ | |
2500 | .long 0 /* 0x25c */ | |
2501 | .long 0 /* 0x260 */ | |
2502 | .long 0 /* 0x264 */ | |
2503 | .long 0 /* 0x268 */ | |
2504 | .long 0 /* 0x26c */ | |
2505 | .long 0 /* 0x270 */ | |
2506 | .long 0 /* 0x274 */ | |
2507 | .long 0 /* 0x278 */ | |
2508 | .long 0 /* 0x27c */ | |
2509 | .long 0 /* 0x280 */ | |
2510 | .long 0 /* 0x284 */ | |
2511 | .long 0 /* 0x288 */ | |
2512 | .long 0 /* 0x28c */ | |
2513 | .long 0 /* 0x290 */ | |
2514 | .long 0 /* 0x294 */ | |
2515 | .long 0 /* 0x298 */ | |
2516 | .long 0 /* 0x29c */ | |
2517 | .long 0 /* 0x2a0 */ | |
2518 | .long 0 /* 0x2a4 */ | |
2519 | .long 0 /* 0x2a8 */ | |
2520 | .long 0 /* 0x2ac */ | |
2521 | .long 0 /* 0x2b0 */ | |
2522 | .long 0 /* 0x2b4 */ | |
2523 | .long 0 /* 0x2b8 */ | |
2524 | .long 0 /* 0x2bc */ | |
2525 | .long 0 /* 0x2c0 */ | |
2526 | .long 0 /* 0x2c4 */ | |
2527 | .long 0 /* 0x2c8 */ | |
2528 | .long 0 /* 0x2cc */ | |
2529 | .long 0 /* 0x2d0 */ | |
2530 | .long 0 /* 0x2d4 */ | |
2531 | .long 0 /* 0x2d8 */ | |
2532 | .long 0 /* 0x2dc */ | |
2533 | .long 0 /* 0x2e0 */ | |
2534 | .long 0 /* 0x2e4 */ | |
2535 | .long 0 /* 0x2e8 */ | |
2536 | .long 0 /* 0x2ec */ | |
2537 | .long 0 /* 0x2f0 */ | |
2538 | .long 0 /* 0x2f4 */ | |
2539 | .long 0 /* 0x2f8 */ | |
5af50993 BH |
2540 | #ifdef CONFIG_KVM_XICS |
2541 | .long DOTSYM(kvmppc_rm_h_xirr_x) - hcall_real_table | |
2542 | #else | |
2543 | .long 0 /* 0x2fc - H_XIRR_X*/ | |
2544 | #endif | |
e928e9cb | 2545 | .long DOTSYM(kvmppc_h_random) - hcall_real_table |
ae2113a4 | 2546 | .globl hcall_real_table_end |
a8606e20 PM |
2547 | hcall_real_table_end: |
2548 | ||
8563bf52 PM |
2549 | _GLOBAL(kvmppc_h_set_xdabr) |
2550 | andi. r0, r5, DABRX_USER | DABRX_KERNEL | |
2551 | beq 6f | |
2552 | li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI | |
2553 | andc. r0, r5, r0 | |
2554 | beq 3f | |
2555 | 6: li r3, H_PARAMETER | |
2556 | blr | |
2557 | ||
a8606e20 | 2558 | _GLOBAL(kvmppc_h_set_dabr) |
8563bf52 PM |
2559 | li r5, DABRX_USER | DABRX_KERNEL |
2560 | 3: | |
eee7ff9d MN |
2561 | BEGIN_FTR_SECTION |
2562 | b 2f | |
2563 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
a8606e20 | 2564 | std r4,VCPU_DABR(r3) |
8563bf52 PM |
2565 | stw r5, VCPU_DABRX(r3) |
2566 | mtspr SPRN_DABRX, r5 | |
8943633c PM |
2567 | /* Work around P7 bug where DABR can get corrupted on mtspr */ |
2568 | 1: mtspr SPRN_DABR,r4 | |
2569 | mfspr r5, SPRN_DABR | |
2570 | cmpd r4, r5 | |
2571 | bne 1b | |
2572 | isync | |
a8606e20 PM |
2573 | li r3,0 |
2574 | blr | |
2575 | ||
e8ebedbf MN |
2576 | 2: |
2577 | BEGIN_FTR_SECTION | |
2578 | /* POWER9 with disabled DAWR */ | |
2579 | li r3, H_UNSUPPORTED | |
2580 | blr | |
2581 | END_FTR_SECTION_IFCLR(CPU_FTR_DAWR) | |
8563bf52 | 2582 | /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */ |
e8ebedbf | 2583 | rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW |
760a7364 | 2584 | rlwimi r5, r4, 2, DAWRX_WT |
8563bf52 PM |
2585 | clrrdi r4, r4, 3 |
2586 | std r4, VCPU_DAWR(r3) | |
2587 | std r5, VCPU_DAWRX(r3) | |
2588 | mtspr SPRN_DAWR, r4 | |
2589 | mtspr SPRN_DAWRX, r5 | |
2590 | li r3, 0 | |
a8606e20 PM |
2591 | blr |
2592 | ||
1f09c3ed | 2593 | _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */ |
19ccb76a PM |
2594 | ori r11,r11,MSR_EE |
2595 | std r11,VCPU_MSR(r3) | |
2596 | li r0,1 | |
2597 | stb r0,VCPU_CEDED(r3) | |
2598 | sync /* order setting ceded vs. testing prodded */ | |
2599 | lbz r5,VCPU_PRODDED(r3) | |
2600 | cmpwi r5,0 | |
04f995a5 | 2601 | bne kvm_cede_prodded |
6af27c84 PM |
2602 | li r12,0 /* set trap to 0 to say hcall is handled */ |
2603 | stw r12,VCPU_TRAP(r3) | |
19ccb76a | 2604 | li r0,H_SUCCESS |
c75df6f9 | 2605 | std r0,VCPU_GPR(R3)(r3) |
19ccb76a PM |
2606 | |
2607 | /* | |
2608 | * Set our bit in the bitmask of napping threads unless all the | |
2609 | * other threads are already napping, in which case we send this | |
2610 | * up to the host. | |
2611 | */ | |
2612 | ld r5,HSTATE_KVM_VCORE(r13) | |
e0b7ec05 | 2613 | lbz r6,HSTATE_PTID(r13) |
19ccb76a PM |
2614 | lwz r8,VCORE_ENTRY_EXIT(r5) |
2615 | clrldi r8,r8,56 | |
2616 | li r0,1 | |
2617 | sld r0,r0,r6 | |
2618 | addi r6,r5,VCORE_NAPPING_THREADS | |
2619 | 31: lwarx r4,0,r6 | |
2620 | or r4,r4,r0 | |
7d6c40da PM |
2621 | cmpw r4,r8 |
2622 | beq kvm_cede_exit | |
19ccb76a PM |
2623 | stwcx. r4,0,r6 |
2624 | bne 31b | |
7d6c40da | 2625 | /* order napping_threads update vs testing entry_exit_map */ |
f019b7ad | 2626 | isync |
e0b7ec05 | 2627 | li r0,NAPPING_CEDE |
19ccb76a | 2628 | stb r0,HSTATE_NAPPING(r13) |
19ccb76a PM |
2629 | lwz r7,VCORE_ENTRY_EXIT(r5) |
2630 | cmpwi r7,0x100 | |
2631 | bge 33f /* another thread already exiting */ | |
2632 | ||
2633 | /* | |
2634 | * Although not specifically required by the architecture, POWER7 | |
2635 | * preserves the following registers in nap mode, even if an SMT mode | |
2636 | * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3, | |
2637 | * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR. | |
2638 | */ | |
2639 | /* Save non-volatile GPRs */ | |
c75df6f9 MN |
2640 | std r14, VCPU_GPR(R14)(r3) |
2641 | std r15, VCPU_GPR(R15)(r3) | |
2642 | std r16, VCPU_GPR(R16)(r3) | |
2643 | std r17, VCPU_GPR(R17)(r3) | |
2644 | std r18, VCPU_GPR(R18)(r3) | |
2645 | std r19, VCPU_GPR(R19)(r3) | |
2646 | std r20, VCPU_GPR(R20)(r3) | |
2647 | std r21, VCPU_GPR(R21)(r3) | |
2648 | std r22, VCPU_GPR(R22)(r3) | |
2649 | std r23, VCPU_GPR(R23)(r3) | |
2650 | std r24, VCPU_GPR(R24)(r3) | |
2651 | std r25, VCPU_GPR(R25)(r3) | |
2652 | std r26, VCPU_GPR(R26)(r3) | |
2653 | std r27, VCPU_GPR(R27)(r3) | |
2654 | std r28, VCPU_GPR(R28)(r3) | |
2655 | std r29, VCPU_GPR(R29)(r3) | |
2656 | std r30, VCPU_GPR(R30)(r3) | |
2657 | std r31, VCPU_GPR(R31)(r3) | |
19ccb76a PM |
2658 | |
2659 | /* save FP state */ | |
595e4f7e | 2660 | bl kvmppc_save_fp |
19ccb76a | 2661 | |
93d17397 | 2662 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
4bb3c7a0 PM |
2663 | /* |
2664 | * Branch around the call if both CPU_FTR_TM and | |
2665 | * CPU_FTR_P9_TM_HV_ASSIST are off. | |
2666 | */ | |
93d17397 | 2667 | BEGIN_FTR_SECTION |
4bb3c7a0 PM |
2668 | b 91f |
2669 | END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0) | |
67f8a8c1 PM |
2670 | /* |
2671 | * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR | |
2672 | */ | |
93d17397 PM |
2673 | ld r9, HSTATE_KVM_VCPU(r13) |
2674 | bl kvmppc_save_tm | |
4bb3c7a0 | 2675 | 91: |
93d17397 PM |
2676 | #endif |
2677 | ||
fd6d53b1 PM |
2678 | /* |
2679 | * Set DEC to the smaller of DEC and HDEC, so that we wake | |
2680 | * no later than the end of our timeslice (HDEC interrupts | |
2681 | * don't wake us from nap). | |
2682 | */ | |
2683 | mfspr r3, SPRN_DEC | |
2684 | mfspr r4, SPRN_HDEC | |
2685 | mftb r5 | |
1bc3fe81 PM |
2686 | BEGIN_FTR_SECTION |
2687 | /* On P9 check whether the guest has large decrementer mode enabled */ | |
2688 | ld r6, HSTATE_KVM_VCORE(r13) | |
2689 | ld r6, VCORE_LPCR(r6) | |
2690 | andis. r6, r6, LPCR_LD@h | |
2691 | bne 68f | |
2692 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
2f272463 | 2693 | extsw r3, r3 |
1bc3fe81 | 2694 | 68: EXTEND_HDEC(r4) |
2f272463 | 2695 | cmpd r3, r4 |
fd6d53b1 PM |
2696 | ble 67f |
2697 | mtspr SPRN_DEC, r4 | |
2698 | 67: | |
2699 | /* save expiry time of guest decrementer */ | |
fd6d53b1 PM |
2700 | add r3, r3, r5 |
2701 | ld r4, HSTATE_KVM_VCPU(r13) | |
2702 | ld r5, HSTATE_KVM_VCORE(r13) | |
2703 | ld r6, VCORE_TB_OFFSET(r5) | |
2704 | subf r3, r6, r3 /* convert to host TB value */ | |
2705 | std r3, VCPU_DEC_EXPIRES(r4) | |
2706 | ||
b6c295df PM |
2707 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
2708 | ld r4, HSTATE_KVM_VCPU(r13) | |
2709 | addi r3, r4, VCPU_TB_CEDE | |
2710 | bl kvmhv_accumulate_time | |
2711 | #endif | |
2712 | ||
ccc07772 PM |
2713 | lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */ |
2714 | ||
19ccb76a | 2715 | /* |
aa31e843 | 2716 | * Take a nap until a decrementer or external or doobell interrupt |
ccc07772 | 2717 | * occurs, with PECE1 and PECE0 set in LPCR. |
66feed61 | 2718 | * On POWER8, set PECEDH, and if we are ceding, also set PECEDP. |
ccc07772 | 2719 | * Also clear the runlatch bit before napping. |
19ccb76a | 2720 | */ |
56548fc0 | 2721 | kvm_do_nap: |
1f09c3ed PM |
2722 | mfspr r0, SPRN_CTRLF |
2723 | clrrdi r0, r0, 1 | |
2724 | mtspr SPRN_CTRLT, r0 | |
582b910e | 2725 | |
f0888f70 PM |
2726 | li r0,1 |
2727 | stb r0,HSTATE_HWTHREAD_REQ(r13) | |
19ccb76a PM |
2728 | mfspr r5,SPRN_LPCR |
2729 | ori r5,r5,LPCR_PECE0 | LPCR_PECE1 | |
aa31e843 | 2730 | BEGIN_FTR_SECTION |
66feed61 | 2731 | ori r5, r5, LPCR_PECEDH |
ccc07772 | 2732 | rlwimi r5, r3, 0, LPCR_PECEDP |
aa31e843 | 2733 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
bf53c88e PM |
2734 | |
2735 | kvm_nap_sequence: /* desired LPCR value in r5 */ | |
2736 | BEGIN_FTR_SECTION | |
2737 | /* | |
2738 | * PSSCR bits: exit criterion = 1 (wakeup based on LPCR at sreset) | |
2739 | * enable state loss = 1 (allow SMT mode switch) | |
2740 | * requested level = 0 (just stop dispatching) | |
2741 | */ | |
2742 | lis r3, (PSSCR_EC | PSSCR_ESL)@h | |
2743 | mtspr SPRN_PSSCR, r3 | |
2744 | /* Set LPCR_PECE_HVEE bit to enable wakeup by HV interrupts */ | |
2745 | li r4, LPCR_PECE_HVEE@higher | |
2746 | sldi r4, r4, 32 | |
2747 | or r5, r5, r4 | |
2748 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
19ccb76a PM |
2749 | mtspr SPRN_LPCR,r5 |
2750 | isync | |
2751 | li r0, 0 | |
2752 | std r0, HSTATE_SCRATCH0(r13) | |
2753 | ptesync | |
2754 | ld r0, HSTATE_SCRATCH0(r13) | |
2755 | 1: cmpd r0, r0 | |
2756 | bne 1b | |
bf53c88e | 2757 | BEGIN_FTR_SECTION |
19ccb76a | 2758 | nap |
bf53c88e PM |
2759 | FTR_SECTION_ELSE |
2760 | PPC_STOP | |
2761 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300) | |
19ccb76a PM |
2762 | b . |
2763 | ||
e3bbbbfa PM |
2764 | 33: mr r4, r3 |
2765 | li r3, 0 | |
2766 | li r12, 0 | |
2767 | b 34f | |
2768 | ||
19ccb76a | 2769 | kvm_end_cede: |
4619ac88 PM |
2770 | /* get vcpu pointer */ |
2771 | ld r4, HSTATE_KVM_VCPU(r13) | |
2772 | ||
19ccb76a PM |
2773 | /* Woken by external or decrementer interrupt */ |
2774 | ld r1, HSTATE_HOST_R1(r13) | |
19ccb76a | 2775 | |
b6c295df PM |
2776 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
2777 | addi r3, r4, VCPU_TB_RMINTR | |
2778 | bl kvmhv_accumulate_time | |
2779 | #endif | |
2780 | ||
93d17397 | 2781 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
4bb3c7a0 PM |
2782 | /* |
2783 | * Branch around the call if both CPU_FTR_TM and | |
2784 | * CPU_FTR_P9_TM_HV_ASSIST are off. | |
2785 | */ | |
93d17397 | 2786 | BEGIN_FTR_SECTION |
4bb3c7a0 PM |
2787 | b 91f |
2788 | END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0) | |
67f8a8c1 PM |
2789 | /* |
2790 | * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS INCLUDING CR | |
2791 | */ | |
93d17397 | 2792 | bl kvmppc_restore_tm |
4bb3c7a0 | 2793 | 91: |
93d17397 PM |
2794 | #endif |
2795 | ||
19ccb76a PM |
2796 | /* load up FP state */ |
2797 | bl kvmppc_load_fp | |
2798 | ||
fd6d53b1 PM |
2799 | /* Restore guest decrementer */ |
2800 | ld r3, VCPU_DEC_EXPIRES(r4) | |
2801 | ld r5, HSTATE_KVM_VCORE(r13) | |
2802 | ld r6, VCORE_TB_OFFSET(r5) | |
2803 | add r3, r3, r6 /* convert host TB to guest TB value */ | |
2804 | mftb r7 | |
2805 | subf r3, r7, r3 | |
2806 | mtspr SPRN_DEC, r3 | |
2807 | ||
19ccb76a | 2808 | /* Load NV GPRS */ |
c75df6f9 MN |
2809 | ld r14, VCPU_GPR(R14)(r4) |
2810 | ld r15, VCPU_GPR(R15)(r4) | |
2811 | ld r16, VCPU_GPR(R16)(r4) | |
2812 | ld r17, VCPU_GPR(R17)(r4) | |
2813 | ld r18, VCPU_GPR(R18)(r4) | |
2814 | ld r19, VCPU_GPR(R19)(r4) | |
2815 | ld r20, VCPU_GPR(R20)(r4) | |
2816 | ld r21, VCPU_GPR(R21)(r4) | |
2817 | ld r22, VCPU_GPR(R22)(r4) | |
2818 | ld r23, VCPU_GPR(R23)(r4) | |
2819 | ld r24, VCPU_GPR(R24)(r4) | |
2820 | ld r25, VCPU_GPR(R25)(r4) | |
2821 | ld r26, VCPU_GPR(R26)(r4) | |
2822 | ld r27, VCPU_GPR(R27)(r4) | |
2823 | ld r28, VCPU_GPR(R28)(r4) | |
2824 | ld r29, VCPU_GPR(R29)(r4) | |
2825 | ld r30, VCPU_GPR(R30)(r4) | |
2826 | ld r31, VCPU_GPR(R31)(r4) | |
37f55d30 | 2827 | |
e3bbbbfa PM |
2828 | /* Check the wake reason in SRR1 to see why we got here */ |
2829 | bl kvmppc_check_wake_reason | |
19ccb76a | 2830 | |
37f55d30 SW |
2831 | /* |
2832 | * Restore volatile registers since we could have called a | |
2833 | * C routine in kvmppc_check_wake_reason | |
2834 | * r4 = VCPU | |
2835 | * r3 tells us whether we need to return to host or not | |
2836 | * WARNING: it gets checked further down: | |
2837 | * should not modify r3 until this check is done. | |
2838 | */ | |
2839 | ld r4, HSTATE_KVM_VCPU(r13) | |
2840 | ||
19ccb76a | 2841 | /* clear our bit in vcore->napping_threads */ |
e3bbbbfa PM |
2842 | 34: ld r5,HSTATE_KVM_VCORE(r13) |
2843 | lbz r7,HSTATE_PTID(r13) | |
19ccb76a | 2844 | li r0,1 |
e3bbbbfa | 2845 | sld r0,r0,r7 |
19ccb76a PM |
2846 | addi r6,r5,VCORE_NAPPING_THREADS |
2847 | 32: lwarx r7,0,r6 | |
2848 | andc r7,r7,r0 | |
2849 | stwcx. r7,0,r6 | |
2850 | bne 32b | |
2851 | li r0,0 | |
2852 | stb r0,HSTATE_NAPPING(r13) | |
2853 | ||
37f55d30 | 2854 | /* See if the wake reason saved in r3 means we need to exit */ |
e3bbbbfa | 2855 | stw r12, VCPU_TRAP(r4) |
4619ac88 | 2856 | mr r9, r4 |
e3bbbbfa PM |
2857 | cmpdi r3, 0 |
2858 | bgt guest_exit_cont | |
4619ac88 | 2859 | |
19ccb76a PM |
2860 | /* see if any other thread is already exiting */ |
2861 | lwz r0,VCORE_ENTRY_EXIT(r5) | |
2862 | cmpwi r0,0x100 | |
e3bbbbfa | 2863 | bge guest_exit_cont |
19ccb76a | 2864 | |
e3bbbbfa | 2865 | b kvmppc_cede_reentry /* if not go back to guest */ |
19ccb76a PM |
2866 | |
2867 | /* cede when already previously prodded case */ | |
04f995a5 PM |
2868 | kvm_cede_prodded: |
2869 | li r0,0 | |
19ccb76a PM |
2870 | stb r0,VCPU_PRODDED(r3) |
2871 | sync /* order testing prodded vs. clearing ceded */ | |
2872 | stb r0,VCPU_CEDED(r3) | |
2873 | li r3,H_SUCCESS | |
2874 | blr | |
2875 | ||
2876 | /* we've ceded but we want to give control to the host */ | |
04f995a5 | 2877 | kvm_cede_exit: |
6af27c84 | 2878 | ld r9, HSTATE_KVM_VCPU(r13) |
9b9b13a6 BH |
2879 | #ifdef CONFIG_KVM_XICS |
2880 | /* Abort if we still have a pending escalation */ | |
2881 | lbz r5, VCPU_XIVE_ESC_ON(r9) | |
2882 | cmpwi r5, 0 | |
2883 | beq 1f | |
2884 | li r0, 0 | |
2885 | stb r0, VCPU_CEDED(r9) | |
2886 | 1: /* Enable XIVE escalation */ | |
2887 | li r5, XIVE_ESB_SET_PQ_00 | |
2888 | mfmsr r0 | |
2889 | andi. r0, r0, MSR_DR /* in real mode? */ | |
2890 | beq 1f | |
2891 | ld r10, VCPU_XIVE_ESC_VADDR(r9) | |
2892 | cmpdi r10, 0 | |
2893 | beq 3f | |
2894 | ldx r0, r10, r5 | |
2895 | b 2f | |
2896 | 1: ld r10, VCPU_XIVE_ESC_RADDR(r9) | |
2897 | cmpdi r10, 0 | |
2898 | beq 3f | |
2899 | ldcix r0, r10, r5 | |
2900 | 2: sync | |
2901 | li r0, 1 | |
2902 | stb r0, VCPU_XIVE_ESC_ON(r9) | |
2903 | #endif /* CONFIG_KVM_XICS */ | |
2904 | 3: b guest_exit_cont | |
19ccb76a | 2905 | |
b4072df4 PM |
2906 | /* Try to handle a machine check in real mode */ |
2907 | machine_check_realmode: | |
2908 | mr r3, r9 /* get vcpu pointer */ | |
b1576fec | 2909 | bl kvmppc_realmode_machine_check |
b4072df4 | 2910 | nop |
b4072df4 PM |
2911 | ld r9, HSTATE_KVM_VCPU(r13) |
2912 | li r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
74845bc2 | 2913 | /* |
e20bbd3d AP |
2914 | * For the guest that is FWNMI capable, deliver all the MCE errors |
2915 | * (handled/unhandled) by exiting the guest with KVM_EXIT_NMI exit | |
2916 | * reason. This new approach injects machine check errors in guest | |
2917 | * address space to guest with additional information in the form | |
2918 | * of RTAS event, thus enabling guest kernel to suitably handle | |
2919 | * such errors. | |
966d713e | 2920 | * |
e20bbd3d AP |
2921 | * For the guest that is not FWNMI capable (old QEMU) fallback |
2922 | * to old behaviour for backward compatibility: | |
2923 | * Deliver unhandled/fatal (e.g. UE) MCE errors to guest either | |
2924 | * through machine check interrupt (set HSRR0 to 0x200). | |
2925 | * For handled errors (no-fatal), just go back to guest execution | |
2926 | * with current HSRR0. | |
966d713e MS |
2927 | * if we receive machine check with MSR(RI=0) then deliver it to |
2928 | * guest as machine check causing guest to crash. | |
74845bc2 | 2929 | */ |
74845bc2 | 2930 | ld r11, VCPU_MSR(r9) |
1c9e3d51 PM |
2931 | rldicl. r0, r11, 64-MSR_HV_LG, 63 /* check if it happened in HV mode */ |
2932 | bne mc_cont /* if so, exit to host */ | |
e20bbd3d AP |
2933 | /* Check if guest is capable of handling NMI exit */ |
2934 | ld r10, VCPU_KVM(r9) | |
2935 | lbz r10, KVM_FWNMI(r10) | |
2936 | cmpdi r10, 1 /* FWNMI capable? */ | |
2937 | beq mc_cont /* if so, exit with KVM_EXIT_NMI. */ | |
2938 | ||
2939 | /* if not, fall through for backward compatibility. */ | |
966d713e MS |
2940 | andi. r10, r11, MSR_RI /* check for unrecoverable exception */ |
2941 | beq 1f /* Deliver a machine check to guest */ | |
2942 | ld r10, VCPU_PC(r9) | |
2943 | cmpdi r3, 0 /* Did we handle MCE ? */ | |
74845bc2 | 2944 | bne 2f /* Continue guest execution. */ |
b4072df4 | 2945 | /* If not, deliver a machine check. SRR0/1 are already set */ |
966d713e | 2946 | 1: li r10, BOOK3S_INTERRUPT_MACHINE_CHECK |
e4e38121 | 2947 | bl kvmppc_msr_interrupt |
74845bc2 | 2948 | 2: b fast_interrupt_c_return |
b4072df4 | 2949 | |
e3bbbbfa PM |
2950 | /* |
2951 | * Check the reason we woke from nap, and take appropriate action. | |
1f09c3ed | 2952 | * Returns (in r3): |
e3bbbbfa PM |
2953 | * 0 if nothing needs to be done |
2954 | * 1 if something happened that needs to be handled by the host | |
66feed61 | 2955 | * -1 if there was a guest wakeup (IPI or msgsnd) |
e3c13e56 SW |
2956 | * -2 if we handled a PCI passthrough interrupt (returned by |
2957 | * kvmppc_read_intr only) | |
e3bbbbfa PM |
2958 | * |
2959 | * Also sets r12 to the interrupt vector for any interrupt that needs | |
2960 | * to be handled now by the host (0x500 for external interrupt), or zero. | |
37f55d30 SW |
2961 | * Modifies all volatile registers (since it may call a C function). |
2962 | * This routine calls kvmppc_read_intr, a C function, if an external | |
2963 | * interrupt is pending. | |
e3bbbbfa PM |
2964 | */ |
2965 | kvmppc_check_wake_reason: | |
2966 | mfspr r6, SPRN_SRR1 | |
aa31e843 PM |
2967 | BEGIN_FTR_SECTION |
2968 | rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */ | |
2969 | FTR_SECTION_ELSE | |
2970 | rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */ | |
2971 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S) | |
2972 | cmpwi r6, 8 /* was it an external interrupt? */ | |
37f55d30 | 2973 | beq 7f /* if so, see what it was */ |
e3bbbbfa PM |
2974 | li r3, 0 |
2975 | li r12, 0 | |
2976 | cmpwi r6, 6 /* was it the decrementer? */ | |
2977 | beq 0f | |
aa31e843 PM |
2978 | BEGIN_FTR_SECTION |
2979 | cmpwi r6, 5 /* privileged doorbell? */ | |
2980 | beq 0f | |
5d00f66b PM |
2981 | cmpwi r6, 3 /* hypervisor doorbell? */ |
2982 | beq 3f | |
aa31e843 | 2983 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
fd7bacbc MS |
2984 | cmpwi r6, 0xa /* Hypervisor maintenance ? */ |
2985 | beq 4f | |
e3bbbbfa PM |
2986 | li r3, 1 /* anything else, return 1 */ |
2987 | 0: blr | |
2988 | ||
5d00f66b PM |
2989 | /* hypervisor doorbell */ |
2990 | 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL | |
70aa3961 GS |
2991 | |
2992 | /* | |
2993 | * Clear the doorbell as we will invoke the handler | |
2994 | * explicitly in the guest exit path. | |
2995 | */ | |
2996 | lis r6, (PPC_DBELL_SERVER << (63-36))@h | |
2997 | PPC_MSGCLR(6) | |
66feed61 | 2998 | /* see if it's a host IPI */ |
5d00f66b | 2999 | li r3, 1 |
2cde3716 NP |
3000 | BEGIN_FTR_SECTION |
3001 | PPC_MSGSYNC | |
3002 | lwsync | |
3003 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
66feed61 PM |
3004 | lbz r0, HSTATE_HOST_IPI(r13) |
3005 | cmpwi r0, 0 | |
3006 | bnelr | |
70aa3961 | 3007 | /* if not, return -1 */ |
66feed61 | 3008 | li r3, -1 |
5d00f66b PM |
3009 | blr |
3010 | ||
fd7bacbc MS |
3011 | /* Woken up due to Hypervisor maintenance interrupt */ |
3012 | 4: li r12, BOOK3S_INTERRUPT_HMI | |
3013 | li r3, 1 | |
3014 | blr | |
3015 | ||
37f55d30 SW |
3016 | /* external interrupt - create a stack frame so we can call C */ |
3017 | 7: mflr r0 | |
3018 | std r0, PPC_LR_STKOFF(r1) | |
3019 | stdu r1, -PPC_MIN_STKFRM(r1) | |
3020 | bl kvmppc_read_intr | |
3021 | nop | |
3022 | li r12, BOOK3S_INTERRUPT_EXTERNAL | |
f7af5209 SW |
3023 | cmpdi r3, 1 |
3024 | ble 1f | |
3025 | ||
3026 | /* | |
3027 | * Return code of 2 means PCI passthrough interrupt, but | |
3028 | * we need to return back to host to complete handling the | |
3029 | * interrupt. Trap reason is expected in r12 by guest | |
3030 | * exit code. | |
3031 | */ | |
3032 | li r12, BOOK3S_INTERRUPT_HV_RM_HARD | |
3033 | 1: | |
37f55d30 SW |
3034 | ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1) |
3035 | addi r1, r1, PPC_MIN_STKFRM | |
3036 | mtlr r0 | |
3037 | blr | |
371fefd6 | 3038 | |
de56a948 PM |
3039 | /* |
3040 | * Save away FP, VMX and VSX registers. | |
3041 | * r3 = vcpu pointer | |
595e4f7e PM |
3042 | * N.B. r30 and r31 are volatile across this function, |
3043 | * thus it is not callable from C. | |
a8606e20 | 3044 | */ |
595e4f7e PM |
3045 | kvmppc_save_fp: |
3046 | mflr r30 | |
3047 | mr r31,r3 | |
8943633c PM |
3048 | mfmsr r5 |
3049 | ori r8,r5,MSR_FP | |
de56a948 PM |
3050 | #ifdef CONFIG_ALTIVEC |
3051 | BEGIN_FTR_SECTION | |
3052 | oris r8,r8,MSR_VEC@h | |
3053 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
3054 | #endif | |
3055 | #ifdef CONFIG_VSX | |
3056 | BEGIN_FTR_SECTION | |
3057 | oris r8,r8,MSR_VSX@h | |
3058 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
3059 | #endif | |
3060 | mtmsrd r8 | |
595e4f7e | 3061 | addi r3,r3,VCPU_FPRS |
9bf163f8 | 3062 | bl store_fp_state |
de56a948 PM |
3063 | #ifdef CONFIG_ALTIVEC |
3064 | BEGIN_FTR_SECTION | |
595e4f7e | 3065 | addi r3,r31,VCPU_VRS |
9bf163f8 | 3066 | bl store_vr_state |
de56a948 PM |
3067 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
3068 | #endif | |
3069 | mfspr r6,SPRN_VRSAVE | |
e724f080 | 3070 | stw r6,VCPU_VRSAVE(r31) |
595e4f7e | 3071 | mtlr r30 |
de56a948 PM |
3072 | blr |
3073 | ||
3074 | /* | |
3075 | * Load up FP, VMX and VSX registers | |
3076 | * r4 = vcpu pointer | |
595e4f7e PM |
3077 | * N.B. r30 and r31 are volatile across this function, |
3078 | * thus it is not callable from C. | |
de56a948 | 3079 | */ |
de56a948 | 3080 | kvmppc_load_fp: |
595e4f7e PM |
3081 | mflr r30 |
3082 | mr r31,r4 | |
de56a948 PM |
3083 | mfmsr r9 |
3084 | ori r8,r9,MSR_FP | |
3085 | #ifdef CONFIG_ALTIVEC | |
3086 | BEGIN_FTR_SECTION | |
3087 | oris r8,r8,MSR_VEC@h | |
3088 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
3089 | #endif | |
3090 | #ifdef CONFIG_VSX | |
3091 | BEGIN_FTR_SECTION | |
3092 | oris r8,r8,MSR_VSX@h | |
3093 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
3094 | #endif | |
3095 | mtmsrd r8 | |
595e4f7e | 3096 | addi r3,r4,VCPU_FPRS |
9bf163f8 | 3097 | bl load_fp_state |
de56a948 PM |
3098 | #ifdef CONFIG_ALTIVEC |
3099 | BEGIN_FTR_SECTION | |
595e4f7e | 3100 | addi r3,r31,VCPU_VRS |
9bf163f8 | 3101 | bl load_vr_state |
de56a948 PM |
3102 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
3103 | #endif | |
e724f080 | 3104 | lwz r7,VCPU_VRSAVE(r31) |
de56a948 | 3105 | mtspr SPRN_VRSAVE,r7 |
595e4f7e PM |
3106 | mtlr r30 |
3107 | mr r4,r31 | |
de56a948 | 3108 | blr |
44a3add8 | 3109 | |
f024ee09 PM |
3110 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
3111 | /* | |
3112 | * Save transactional state and TM-related registers. | |
3113 | * Called with r9 pointing to the vcpu struct. | |
3114 | * This can modify all checkpointed registers, but | |
3115 | * restores r1, r2 and r9 (vcpu pointer) before exit. | |
3116 | */ | |
3117 | kvmppc_save_tm: | |
3118 | mflr r0 | |
3119 | std r0, PPC_LR_STKOFF(r1) | |
87a11bb6 | 3120 | stdu r1, -PPC_MIN_STKFRM(r1) |
f024ee09 PM |
3121 | |
3122 | /* Turn on TM. */ | |
3123 | mfmsr r8 | |
3124 | li r0, 1 | |
3125 | rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG | |
3126 | mtmsrd r8 | |
3127 | ||
3128 | ld r5, VCPU_MSR(r9) | |
3129 | rldicl. r5, r5, 64 - MSR_TS_S_LG, 62 | |
3130 | beq 1f /* TM not active in guest. */ | |
3131 | ||
3132 | std r1, HSTATE_HOST_R1(r13) | |
3133 | li r3, TM_CAUSE_KVM_RESCHED | |
3134 | ||
4bb3c7a0 | 3135 | BEGIN_FTR_SECTION |
87a11bb6 SJS |
3136 | lbz r0, HSTATE_FAKE_SUSPEND(r13) /* Were we fake suspended? */ |
3137 | cmpwi r0, 0 | |
4bb3c7a0 | 3138 | beq 3f |
87a11bb6 SJS |
3139 | rldicl. r8, r8, 64 - MSR_TS_S_LG, 62 /* Did we actually hrfid? */ |
3140 | beq 4f | |
3141 | BEGIN_FTR_SECTION_NESTED(96) | |
3142 | bl pnv_power9_force_smt4_catch | |
3143 | END_FTR_SECTION_NESTED(CPU_FTR_P9_TM_XER_SO_BUG, CPU_FTR_P9_TM_XER_SO_BUG, 96) | |
3144 | nop | |
681c617b | 3145 | b 6f |
87a11bb6 | 3146 | 3: |
681c617b PM |
3147 | /* Emulation of the treclaim instruction needs TEXASR before treclaim */ |
3148 | mfspr r6, SPRN_TEXASR | |
3149 | std r6, VCPU_ORIG_TEXASR(r9) | |
3150 | 6: | |
4bb3c7a0 PM |
3151 | END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_HV_ASSIST) |
3152 | ||
f024ee09 PM |
3153 | /* Clear the MSR RI since r1, r13 are all going to be foobar. */ |
3154 | li r5, 0 | |
3155 | mtmsrd r5, 1 | |
3156 | ||
3157 | /* All GPRs are volatile at this point. */ | |
3158 | TRECLAIM(R3) | |
3159 | ||
3160 | /* Temporarily store r13 and r9 so we have some regs to play with */ | |
3161 | SET_SCRATCH0(r13) | |
3162 | GET_PACA(r13) | |
3163 | std r9, PACATMSCRATCH(r13) | |
4bb3c7a0 PM |
3164 | |
3165 | /* If doing TM emulation on POWER9 DD2.2, check for fake suspend mode */ | |
3166 | BEGIN_FTR_SECTION | |
4bb3c7a0 PM |
3167 | lbz r9, HSTATE_FAKE_SUSPEND(r13) |
3168 | cmpwi r9, 0 | |
3169 | beq 2f | |
3170 | /* | |
3171 | * We were in fake suspend, so we are not going to save the | |
3172 | * register state as the guest checkpointed state (since | |
3173 | * we already have it), therefore we can now use any volatile GPR. | |
3174 | */ | |
3175 | /* Reload stack pointer and TOC. */ | |
3176 | ld r1, HSTATE_HOST_R1(r13) | |
3177 | ld r2, PACATOC(r13) | |
87a11bb6 | 3178 | /* Set MSR RI now we have r1 and r13 back. */ |
4bb3c7a0 PM |
3179 | li r5, MSR_RI |
3180 | mtmsrd r5, 1 | |
3181 | HMT_MEDIUM | |
3182 | ld r6, HSTATE_DSCR(r13) | |
3183 | mtspr SPRN_DSCR, r6 | |
87a11bb6 SJS |
3184 | BEGIN_FTR_SECTION_NESTED(96) |
3185 | bl pnv_power9_force_smt4_release | |
3186 | END_FTR_SECTION_NESTED(CPU_FTR_P9_TM_XER_SO_BUG, CPU_FTR_P9_TM_XER_SO_BUG, 96) | |
3187 | nop | |
3188 | ||
3189 | 4: | |
4bb3c7a0 PM |
3190 | mfspr r3, SPRN_PSSCR |
3191 | /* PSSCR_FAKE_SUSPEND is a write-only bit, but clear it anyway */ | |
3192 | li r0, PSSCR_FAKE_SUSPEND | |
3193 | andc r3, r3, r0 | |
3194 | mtspr SPRN_PSSCR, r3 | |
3195 | ld r9, HSTATE_KVM_VCPU(r13) | |
681c617b PM |
3196 | /* Don't save TEXASR, use value from last exit in real suspend state */ |
3197 | b 11f | |
4bb3c7a0 PM |
3198 | 2: |
3199 | END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_HV_ASSIST) | |
3200 | ||
f024ee09 PM |
3201 | ld r9, HSTATE_KVM_VCPU(r13) |
3202 | ||
3203 | /* Get a few more GPRs free. */ | |
3204 | std r29, VCPU_GPRS_TM(29)(r9) | |
3205 | std r30, VCPU_GPRS_TM(30)(r9) | |
3206 | std r31, VCPU_GPRS_TM(31)(r9) | |
3207 | ||
3208 | /* Save away PPR and DSCR soon so don't run with user values. */ | |
3209 | mfspr r31, SPRN_PPR | |
3210 | HMT_MEDIUM | |
3211 | mfspr r30, SPRN_DSCR | |
3212 | ld r29, HSTATE_DSCR(r13) | |
3213 | mtspr SPRN_DSCR, r29 | |
3214 | ||
3215 | /* Save all but r9, r13 & r29-r31 */ | |
3216 | reg = 0 | |
3217 | .rept 29 | |
3218 | .if (reg != 9) && (reg != 13) | |
3219 | std reg, VCPU_GPRS_TM(reg)(r9) | |
3220 | .endif | |
3221 | reg = reg + 1 | |
3222 | .endr | |
3223 | /* ... now save r13 */ | |
3224 | GET_SCRATCH0(r4) | |
3225 | std r4, VCPU_GPRS_TM(13)(r9) | |
3226 | /* ... and save r9 */ | |
3227 | ld r4, PACATMSCRATCH(r13) | |
3228 | std r4, VCPU_GPRS_TM(9)(r9) | |
3229 | ||
3230 | /* Reload stack pointer and TOC. */ | |
3231 | ld r1, HSTATE_HOST_R1(r13) | |
3232 | ld r2, PACATOC(r13) | |
3233 | ||
3234 | /* Set MSR RI now we have r1 and r13 back. */ | |
3235 | li r5, MSR_RI | |
3236 | mtmsrd r5, 1 | |
3237 | ||
3238 | /* Save away checkpinted SPRs. */ | |
3239 | std r31, VCPU_PPR_TM(r9) | |
3240 | std r30, VCPU_DSCR_TM(r9) | |
3241 | mflr r5 | |
3242 | mfcr r6 | |
3243 | mfctr r7 | |
3244 | mfspr r8, SPRN_AMR | |
3245 | mfspr r10, SPRN_TAR | |
0d808df0 | 3246 | mfxer r11 |
f024ee09 PM |
3247 | std r5, VCPU_LR_TM(r9) |
3248 | stw r6, VCPU_CR_TM(r9) | |
3249 | std r7, VCPU_CTR_TM(r9) | |
3250 | std r8, VCPU_AMR_TM(r9) | |
3251 | std r10, VCPU_TAR_TM(r9) | |
0d808df0 | 3252 | std r11, VCPU_XER_TM(r9) |
f024ee09 PM |
3253 | |
3254 | /* Restore r12 as trap number. */ | |
3255 | lwz r12, VCPU_TRAP(r9) | |
3256 | ||
3257 | /* Save FP/VSX. */ | |
3258 | addi r3, r9, VCPU_FPRS_TM | |
3259 | bl store_fp_state | |
3260 | addi r3, r9, VCPU_VRS_TM | |
3261 | bl store_vr_state | |
3262 | mfspr r6, SPRN_VRSAVE | |
3263 | stw r6, VCPU_VRSAVE_TM(r9) | |
3264 | 1: | |
3265 | /* | |
3266 | * We need to save these SPRs after the treclaim so that the software | |
3267 | * error code is recorded correctly in the TEXASR. Also the user may | |
3268 | * change these outside of a transaction, so they must always be | |
3269 | * context switched. | |
3270 | */ | |
681c617b PM |
3271 | mfspr r7, SPRN_TEXASR |
3272 | std r7, VCPU_TEXASR(r9) | |
3273 | 11: | |
f024ee09 PM |
3274 | mfspr r5, SPRN_TFHAR |
3275 | mfspr r6, SPRN_TFIAR | |
f024ee09 PM |
3276 | std r5, VCPU_TFHAR(r9) |
3277 | std r6, VCPU_TFIAR(r9) | |
f024ee09 | 3278 | |
87a11bb6 | 3279 | addi r1, r1, PPC_MIN_STKFRM |
f024ee09 PM |
3280 | ld r0, PPC_LR_STKOFF(r1) |
3281 | mtlr r0 | |
3282 | blr | |
3283 | ||
3284 | /* | |
3285 | * Restore transactional state and TM-related registers. | |
3286 | * Called with r4 pointing to the vcpu struct. | |
3287 | * This potentially modifies all checkpointed registers. | |
3288 | * It restores r1, r2, r4 from the PACA. | |
3289 | */ | |
3290 | kvmppc_restore_tm: | |
3291 | mflr r0 | |
3292 | std r0, PPC_LR_STKOFF(r1) | |
3293 | ||
3294 | /* Turn on TM/FP/VSX/VMX so we can restore them. */ | |
3295 | mfmsr r5 | |
3296 | li r6, MSR_TM >> 32 | |
3297 | sldi r6, r6, 32 | |
3298 | or r5, r5, r6 | |
3299 | ori r5, r5, MSR_FP | |
3300 | oris r5, r5, (MSR_VEC | MSR_VSX)@h | |
3301 | mtmsrd r5 | |
3302 | ||
3303 | /* | |
3304 | * The user may change these outside of a transaction, so they must | |
3305 | * always be context switched. | |
3306 | */ | |
3307 | ld r5, VCPU_TFHAR(r4) | |
3308 | ld r6, VCPU_TFIAR(r4) | |
3309 | ld r7, VCPU_TEXASR(r4) | |
3310 | mtspr SPRN_TFHAR, r5 | |
3311 | mtspr SPRN_TFIAR, r6 | |
3312 | mtspr SPRN_TEXASR, r7 | |
3313 | ||
87a11bb6 SJS |
3314 | li r0, 0 |
3315 | stb r0, HSTATE_FAKE_SUSPEND(r13) | |
f024ee09 PM |
3316 | ld r5, VCPU_MSR(r4) |
3317 | rldicl. r5, r5, 64 - MSR_TS_S_LG, 62 | |
3318 | beqlr /* TM not active in guest */ | |
3319 | std r1, HSTATE_HOST_R1(r13) | |
3320 | ||
3321 | /* Make sure the failure summary is set, otherwise we'll program check | |
3322 | * when we trechkpt. It's possible that this might have been not set | |
3323 | * on a kvmppc_set_one_reg() call but we shouldn't let this crash the | |
3324 | * host. | |
3325 | */ | |
3326 | oris r7, r7, (TEXASR_FS)@h | |
3327 | mtspr SPRN_TEXASR, r7 | |
3328 | ||
4bb3c7a0 PM |
3329 | /* |
3330 | * If we are doing TM emulation for the guest on a POWER9 DD2, | |
3331 | * then we don't actually do a trechkpt -- we either set up | |
3332 | * fake-suspend mode, or emulate a TM rollback. | |
3333 | */ | |
3334 | BEGIN_FTR_SECTION | |
3335 | b .Ldo_tm_fake_load | |
3336 | END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_HV_ASSIST) | |
3337 | ||
f024ee09 PM |
3338 | /* |
3339 | * We need to load up the checkpointed state for the guest. | |
3340 | * We need to do this early as it will blow away any GPRs, VSRs and | |
3341 | * some SPRs. | |
3342 | */ | |
3343 | ||
3344 | mr r31, r4 | |
3345 | addi r3, r31, VCPU_FPRS_TM | |
3346 | bl load_fp_state | |
3347 | addi r3, r31, VCPU_VRS_TM | |
3348 | bl load_vr_state | |
3349 | mr r4, r31 | |
3350 | lwz r7, VCPU_VRSAVE_TM(r4) | |
3351 | mtspr SPRN_VRSAVE, r7 | |
3352 | ||
3353 | ld r5, VCPU_LR_TM(r4) | |
3354 | lwz r6, VCPU_CR_TM(r4) | |
3355 | ld r7, VCPU_CTR_TM(r4) | |
3356 | ld r8, VCPU_AMR_TM(r4) | |
3357 | ld r9, VCPU_TAR_TM(r4) | |
0d808df0 | 3358 | ld r10, VCPU_XER_TM(r4) |
f024ee09 PM |
3359 | mtlr r5 |
3360 | mtcr r6 | |
3361 | mtctr r7 | |
3362 | mtspr SPRN_AMR, r8 | |
3363 | mtspr SPRN_TAR, r9 | |
0d808df0 | 3364 | mtxer r10 |
f024ee09 PM |
3365 | |
3366 | /* | |
3367 | * Load up PPR and DSCR values but don't put them in the actual SPRs | |
3368 | * till the last moment to avoid running with userspace PPR and DSCR for | |
3369 | * too long. | |
3370 | */ | |
3371 | ld r29, VCPU_DSCR_TM(r4) | |
3372 | ld r30, VCPU_PPR_TM(r4) | |
3373 | ||
3374 | std r2, PACATMSCRATCH(r13) /* Save TOC */ | |
3375 | ||
3376 | /* Clear the MSR RI since r1, r13 are all going to be foobar. */ | |
3377 | li r5, 0 | |
3378 | mtmsrd r5, 1 | |
3379 | ||
3380 | /* Load GPRs r0-r28 */ | |
3381 | reg = 0 | |
3382 | .rept 29 | |
3383 | ld reg, VCPU_GPRS_TM(reg)(r31) | |
3384 | reg = reg + 1 | |
3385 | .endr | |
3386 | ||
3387 | mtspr SPRN_DSCR, r29 | |
3388 | mtspr SPRN_PPR, r30 | |
3389 | ||
3390 | /* Load final GPRs */ | |
3391 | ld 29, VCPU_GPRS_TM(29)(r31) | |
3392 | ld 30, VCPU_GPRS_TM(30)(r31) | |
3393 | ld 31, VCPU_GPRS_TM(31)(r31) | |
3394 | ||
3395 | /* TM checkpointed state is now setup. All GPRs are now volatile. */ | |
3396 | TRECHKPT | |
3397 | ||
3398 | /* Now let's get back the state we need. */ | |
3399 | HMT_MEDIUM | |
3400 | GET_PACA(r13) | |
3401 | ld r29, HSTATE_DSCR(r13) | |
3402 | mtspr SPRN_DSCR, r29 | |
3403 | ld r4, HSTATE_KVM_VCPU(r13) | |
3404 | ld r1, HSTATE_HOST_R1(r13) | |
3405 | ld r2, PACATMSCRATCH(r13) | |
3406 | ||
3407 | /* Set the MSR RI since we have our registers back. */ | |
3408 | li r5, MSR_RI | |
3409 | mtmsrd r5, 1 | |
4bb3c7a0 | 3410 | 9: |
f024ee09 PM |
3411 | ld r0, PPC_LR_STKOFF(r1) |
3412 | mtlr r0 | |
3413 | blr | |
4bb3c7a0 PM |
3414 | |
3415 | .Ldo_tm_fake_load: | |
3416 | cmpwi r5, 1 /* check for suspended state */ | |
3417 | bgt 10f | |
3418 | stb r5, HSTATE_FAKE_SUSPEND(r13) | |
3419 | b 9b /* and return */ | |
3420 | 10: stdu r1, -PPC_MIN_STKFRM(r1) | |
3421 | /* guest is in transactional state, so simulate rollback */ | |
3422 | mr r3, r4 | |
3423 | bl kvmhv_emulate_tm_rollback | |
3424 | nop | |
3425 | ld r4, HSTATE_KVM_VCPU(r13) /* our vcpu pointer has been trashed */ | |
3426 | addi r1, r1, PPC_MIN_STKFRM | |
3427 | b 9b | |
f024ee09 PM |
3428 | #endif |
3429 | ||
44a3add8 PM |
3430 | /* |
3431 | * We come here if we get any exception or interrupt while we are | |
3432 | * executing host real mode code while in guest MMU context. | |
857b99e1 PM |
3433 | * r12 is (CR << 32) | vector |
3434 | * r13 points to our PACA | |
3435 | * r12 is saved in HSTATE_SCRATCH0(r13) | |
3436 | * ctr is saved in HSTATE_SCRATCH1(r13) if RELOCATABLE | |
3437 | * r9 is saved in HSTATE_SCRATCH2(r13) | |
3438 | * r13 is saved in HSPRG1 | |
3439 | * cfar is saved in HSTATE_CFAR(r13) | |
3440 | * ppr is saved in HSTATE_PPR(r13) | |
44a3add8 PM |
3441 | */ |
3442 | kvmppc_bad_host_intr: | |
857b99e1 PM |
3443 | /* |
3444 | * Switch to the emergency stack, but start half-way down in | |
3445 | * case we were already on it. | |
3446 | */ | |
3447 | mr r9, r1 | |
3448 | std r1, PACAR1(r13) | |
3449 | ld r1, PACAEMERGSP(r13) | |
3450 | subi r1, r1, THREAD_SIZE/2 + INT_FRAME_SIZE | |
3451 | std r9, 0(r1) | |
3452 | std r0, GPR0(r1) | |
3453 | std r9, GPR1(r1) | |
3454 | std r2, GPR2(r1) | |
3455 | SAVE_4GPRS(3, r1) | |
3456 | SAVE_2GPRS(7, r1) | |
3457 | srdi r0, r12, 32 | |
3458 | clrldi r12, r12, 32 | |
3459 | std r0, _CCR(r1) | |
3460 | std r12, _TRAP(r1) | |
3461 | andi. r0, r12, 2 | |
3462 | beq 1f | |
3463 | mfspr r3, SPRN_HSRR0 | |
3464 | mfspr r4, SPRN_HSRR1 | |
3465 | mfspr r5, SPRN_HDAR | |
3466 | mfspr r6, SPRN_HDSISR | |
3467 | b 2f | |
3468 | 1: mfspr r3, SPRN_SRR0 | |
3469 | mfspr r4, SPRN_SRR1 | |
3470 | mfspr r5, SPRN_DAR | |
3471 | mfspr r6, SPRN_DSISR | |
3472 | 2: std r3, _NIP(r1) | |
3473 | std r4, _MSR(r1) | |
3474 | std r5, _DAR(r1) | |
3475 | std r6, _DSISR(r1) | |
3476 | ld r9, HSTATE_SCRATCH2(r13) | |
3477 | ld r12, HSTATE_SCRATCH0(r13) | |
3478 | GET_SCRATCH0(r0) | |
3479 | SAVE_4GPRS(9, r1) | |
3480 | std r0, GPR13(r1) | |
3481 | SAVE_NVGPRS(r1) | |
3482 | ld r5, HSTATE_CFAR(r13) | |
3483 | std r5, ORIG_GPR3(r1) | |
3484 | mflr r3 | |
3485 | #ifdef CONFIG_RELOCATABLE | |
3486 | ld r4, HSTATE_SCRATCH1(r13) | |
3487 | #else | |
3488 | mfctr r4 | |
3489 | #endif | |
3490 | mfxer r5 | |
4e26bc4a | 3491 | lbz r6, PACAIRQSOFTMASK(r13) |
857b99e1 PM |
3492 | std r3, _LINK(r1) |
3493 | std r4, _CTR(r1) | |
3494 | std r5, _XER(r1) | |
3495 | std r6, SOFTE(r1) | |
3496 | ld r2, PACATOC(r13) | |
3497 | LOAD_REG_IMMEDIATE(3, 0x7265677368657265) | |
3498 | std r3, STACK_FRAME_OVERHEAD-16(r1) | |
3499 | ||
3500 | /* | |
3501 | * On POWER9 do a minimal restore of the MMU and call C code, | |
3502 | * which will print a message and panic. | |
3503 | * XXX On POWER7 and POWER8, we just spin here since we don't | |
3504 | * know what the other threads are doing (and we don't want to | |
3505 | * coordinate with them) - but at least we now have register state | |
3506 | * in memory that we might be able to look at from another CPU. | |
3507 | */ | |
3508 | BEGIN_FTR_SECTION | |
44a3add8 | 3509 | b . |
857b99e1 PM |
3510 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) |
3511 | ld r9, HSTATE_KVM_VCPU(r13) | |
3512 | ld r10, VCPU_KVM(r9) | |
3513 | ||
3514 | li r0, 0 | |
3515 | mtspr SPRN_AMR, r0 | |
3516 | mtspr SPRN_IAMR, r0 | |
3517 | mtspr SPRN_CIABR, r0 | |
3518 | mtspr SPRN_DAWRX, r0 | |
3519 | ||
3520 | /* Flush the ERAT on radix P9 DD1 guest exit */ | |
3521 | BEGIN_FTR_SECTION | |
3522 | PPC_INVALIDATE_ERAT | |
3523 | END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1) | |
3524 | ||
3525 | BEGIN_MMU_FTR_SECTION | |
3526 | b 4f | |
3527 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX) | |
3528 | ||
3529 | slbmte r0, r0 | |
3530 | slbia | |
3531 | ptesync | |
3532 | ld r8, PACA_SLBSHADOWPTR(r13) | |
3533 | .rept SLB_NUM_BOLTED | |
3534 | li r3, SLBSHADOW_SAVEAREA | |
3535 | LDX_BE r5, r8, r3 | |
3536 | addi r3, r3, 8 | |
3537 | LDX_BE r6, r8, r3 | |
3538 | andis. r7, r5, SLB_ESID_V@h | |
3539 | beq 3f | |
3540 | slbmte r6, r5 | |
3541 | 3: addi r8, r8, 16 | |
3542 | .endr | |
3543 | ||
3544 | 4: lwz r7, KVM_HOST_LPID(r10) | |
3545 | mtspr SPRN_LPID, r7 | |
3546 | mtspr SPRN_PID, r0 | |
3547 | ld r8, KVM_HOST_LPCR(r10) | |
3548 | mtspr SPRN_LPCR, r8 | |
3549 | isync | |
3550 | li r0, KVM_GUEST_MODE_NONE | |
3551 | stb r0, HSTATE_IN_GUEST(r13) | |
3552 | ||
3553 | /* | |
3554 | * Turn on the MMU and jump to C code | |
3555 | */ | |
3556 | bcl 20, 31, .+4 | |
3557 | 5: mflr r3 | |
3558 | addi r3, r3, 9f - 5b | |
3559 | ld r4, PACAKMSR(r13) | |
3560 | mtspr SPRN_SRR0, r3 | |
3561 | mtspr SPRN_SRR1, r4 | |
222f20f1 | 3562 | RFI_TO_KERNEL |
857b99e1 PM |
3563 | 9: addi r3, r1, STACK_FRAME_OVERHEAD |
3564 | bl kvmppc_bad_interrupt | |
3565 | b 9b | |
e4e38121 MN |
3566 | |
3567 | /* | |
3568 | * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken | |
3569 | * from VCPU_INTR_MSR and is modified based on the required TM state changes. | |
3570 | * r11 has the guest MSR value (in/out) | |
3571 | * r9 has a vcpu pointer (in) | |
3572 | * r0 is used as a scratch register | |
3573 | */ | |
3574 | kvmppc_msr_interrupt: | |
3575 | rldicl r0, r11, 64 - MSR_TS_S_LG, 62 | |
3576 | cmpwi r0, 2 /* Check if we are in transactional state.. */ | |
3577 | ld r11, VCPU_INTR_MSR(r9) | |
3578 | bne 1f | |
3579 | /* ... if transactional, change to suspended */ | |
3580 | li r0, 1 | |
3581 | 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG | |
3582 | blr | |
9bc01a9b PM |
3583 | |
3584 | /* | |
3585 | * This works around a hardware bug on POWER8E processors, where | |
3586 | * writing a 1 to the MMCR0[PMAO] bit doesn't generate a | |
3587 | * performance monitor interrupt. Instead, when we need to have | |
3588 | * an interrupt pending, we have to arrange for a counter to overflow. | |
3589 | */ | |
3590 | kvmppc_fix_pmao: | |
3591 | li r3, 0 | |
3592 | mtspr SPRN_MMCR2, r3 | |
3593 | lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h | |
3594 | ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN | |
3595 | mtspr SPRN_MMCR0, r3 | |
3596 | lis r3, 0x7fff | |
3597 | ori r3, r3, 0xffff | |
3598 | mtspr SPRN_PMC6, r3 | |
3599 | isync | |
3600 | blr | |
b6c295df PM |
3601 | |
3602 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING | |
3603 | /* | |
3604 | * Start timing an activity | |
3605 | * r3 = pointer to time accumulation struct, r4 = vcpu | |
3606 | */ | |
3607 | kvmhv_start_timing: | |
3608 | ld r5, HSTATE_KVM_VCORE(r13) | |
3609 | lbz r6, VCORE_IN_GUEST(r5) | |
3610 | cmpwi r6, 0 | |
3611 | beq 5f /* if in guest, need to */ | |
3612 | ld r6, VCORE_TB_OFFSET(r5) /* subtract timebase offset */ | |
3613 | 5: mftb r5 | |
3614 | subf r5, r6, r5 | |
3615 | std r3, VCPU_CUR_ACTIVITY(r4) | |
3616 | std r5, VCPU_ACTIVITY_START(r4) | |
3617 | blr | |
3618 | ||
3619 | /* | |
3620 | * Accumulate time to one activity and start another. | |
3621 | * r3 = pointer to new time accumulation struct, r4 = vcpu | |
3622 | */ | |
3623 | kvmhv_accumulate_time: | |
3624 | ld r5, HSTATE_KVM_VCORE(r13) | |
3625 | lbz r8, VCORE_IN_GUEST(r5) | |
3626 | cmpwi r8, 0 | |
3627 | beq 4f /* if in guest, need to */ | |
3628 | ld r8, VCORE_TB_OFFSET(r5) /* subtract timebase offset */ | |
3629 | 4: ld r5, VCPU_CUR_ACTIVITY(r4) | |
3630 | ld r6, VCPU_ACTIVITY_START(r4) | |
3631 | std r3, VCPU_CUR_ACTIVITY(r4) | |
3632 | mftb r7 | |
3633 | subf r7, r8, r7 | |
3634 | std r7, VCPU_ACTIVITY_START(r4) | |
3635 | cmpdi r5, 0 | |
3636 | beqlr | |
3637 | subf r3, r6, r7 | |
3638 | ld r8, TAS_SEQCOUNT(r5) | |
3639 | cmpdi r8, 0 | |
3640 | addi r8, r8, 1 | |
3641 | std r8, TAS_SEQCOUNT(r5) | |
3642 | lwsync | |
3643 | ld r7, TAS_TOTAL(r5) | |
3644 | add r7, r7, r3 | |
3645 | std r7, TAS_TOTAL(r5) | |
3646 | ld r6, TAS_MIN(r5) | |
3647 | ld r7, TAS_MAX(r5) | |
3648 | beq 3f | |
3649 | cmpd r3, r6 | |
3650 | bge 1f | |
3651 | 3: std r3, TAS_MIN(r5) | |
3652 | 1: cmpd r3, r7 | |
3653 | ble 2f | |
3654 | std r3, TAS_MAX(r5) | |
3655 | 2: lwsync | |
3656 | addi r8, r8, 1 | |
3657 | std r8, TAS_SEQCOUNT(r5) | |
3658 | blr | |
3659 | #endif |