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de56a948 PM |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> | |
12 | * | |
13 | * Derived from book3s_rmhandlers.S and other files, which are: | |
14 | * | |
15 | * Copyright SUSE Linux Products GmbH 2009 | |
16 | * | |
17 | * Authors: Alexander Graf <agraf@suse.de> | |
18 | */ | |
19 | ||
20 | #include <asm/ppc_asm.h> | |
21 | #include <asm/kvm_asm.h> | |
22 | #include <asm/reg.h> | |
177339d7 | 23 | #include <asm/mmu.h> |
de56a948 | 24 | #include <asm/page.h> |
177339d7 PM |
25 | #include <asm/ptrace.h> |
26 | #include <asm/hvcall.h> | |
de56a948 PM |
27 | #include <asm/asm-offsets.h> |
28 | #include <asm/exception-64s.h> | |
f0888f70 | 29 | #include <asm/kvm_book3s_asm.h> |
b4072df4 | 30 | #include <asm/mmu-hash64.h> |
de56a948 | 31 | |
7ffcf8ec AB |
32 | #ifdef __LITTLE_ENDIAN__ |
33 | #error Need to fix lppaca and SLB shadow accesses in little endian mode | |
34 | #endif | |
35 | ||
de56a948 | 36 | /* |
19ccb76a | 37 | * Call kvmppc_hv_entry in real mode. |
de56a948 PM |
38 | * Must be called with interrupts hard-disabled. |
39 | * | |
40 | * Input Registers: | |
41 | * | |
42 | * LR = return address to continue at after eventually re-enabling MMU | |
43 | */ | |
44 | _GLOBAL(kvmppc_hv_entry_trampoline) | |
218309b7 PM |
45 | mflr r0 |
46 | std r0, PPC_LR_STKOFF(r1) | |
47 | stdu r1, -112(r1) | |
de56a948 | 48 | mfmsr r10 |
218309b7 | 49 | LOAD_REG_ADDR(r5, kvmppc_call_hv_entry) |
de56a948 PM |
50 | li r0,MSR_RI |
51 | andc r0,r10,r0 | |
52 | li r6,MSR_IR | MSR_DR | |
53 | andc r6,r10,r6 | |
54 | mtmsrd r0,1 /* clear RI in MSR */ | |
55 | mtsrr0 r5 | |
56 | mtsrr1 r6 | |
57 | RFI | |
58 | ||
218309b7 PM |
59 | kvmppc_call_hv_entry: |
60 | bl kvmppc_hv_entry | |
61 | ||
62 | /* Back from guest - restore host state and return to caller */ | |
63 | ||
64 | /* Restore host DABR and DABRX */ | |
65 | ld r5,HSTATE_DABR(r13) | |
66 | li r6,7 | |
67 | mtspr SPRN_DABR,r5 | |
68 | mtspr SPRN_DABRX,r6 | |
69 | ||
70 | /* Restore SPRG3 */ | |
71 | ld r3,PACA_SPRG3(r13) | |
72 | mtspr SPRN_SPRG3,r3 | |
73 | ||
74 | /* | |
75 | * Reload DEC. HDEC interrupts were disabled when | |
76 | * we reloaded the host's LPCR value. | |
77 | */ | |
78 | ld r3, HSTATE_DECEXP(r13) | |
79 | mftb r4 | |
80 | subf r4, r4, r3 | |
81 | mtspr SPRN_DEC, r4 | |
82 | ||
83 | /* Reload the host's PMU registers */ | |
84 | ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */ | |
85 | lbz r4, LPPACA_PMCINUSE(r3) | |
86 | cmpwi r4, 0 | |
87 | beq 23f /* skip if not */ | |
88 | lwz r3, HSTATE_PMC(r13) | |
89 | lwz r4, HSTATE_PMC + 4(r13) | |
90 | lwz r5, HSTATE_PMC + 8(r13) | |
91 | lwz r6, HSTATE_PMC + 12(r13) | |
92 | lwz r8, HSTATE_PMC + 16(r13) | |
93 | lwz r9, HSTATE_PMC + 20(r13) | |
94 | BEGIN_FTR_SECTION | |
95 | lwz r10, HSTATE_PMC + 24(r13) | |
96 | lwz r11, HSTATE_PMC + 28(r13) | |
97 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
98 | mtspr SPRN_PMC1, r3 | |
99 | mtspr SPRN_PMC2, r4 | |
100 | mtspr SPRN_PMC3, r5 | |
101 | mtspr SPRN_PMC4, r6 | |
102 | mtspr SPRN_PMC5, r8 | |
103 | mtspr SPRN_PMC6, r9 | |
104 | BEGIN_FTR_SECTION | |
105 | mtspr SPRN_PMC7, r10 | |
106 | mtspr SPRN_PMC8, r11 | |
107 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
108 | ld r3, HSTATE_MMCR(r13) | |
109 | ld r4, HSTATE_MMCR + 8(r13) | |
110 | ld r5, HSTATE_MMCR + 16(r13) | |
111 | mtspr SPRN_MMCR1, r4 | |
112 | mtspr SPRN_MMCRA, r5 | |
113 | mtspr SPRN_MMCR0, r3 | |
114 | isync | |
115 | 23: | |
116 | ||
117 | /* | |
118 | * For external and machine check interrupts, we need | |
119 | * to call the Linux handler to process the interrupt. | |
120 | * We do that by jumping to absolute address 0x500 for | |
121 | * external interrupts, or the machine_check_fwnmi label | |
122 | * for machine checks (since firmware might have patched | |
123 | * the vector area at 0x200). The [h]rfid at the end of the | |
124 | * handler will return to the book3s_hv_interrupts.S code. | |
125 | * For other interrupts we do the rfid to get back | |
126 | * to the book3s_hv_interrupts.S code here. | |
127 | */ | |
128 | ld r8, 112+PPC_LR_STKOFF(r1) | |
129 | addi r1, r1, 112 | |
130 | ld r7, HSTATE_HOST_MSR(r13) | |
131 | ||
132 | cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
133 | cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL | |
134 | BEGIN_FTR_SECTION | |
135 | beq 11f | |
136 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
137 | ||
138 | /* RFI into the highmem handler, or branch to interrupt handler */ | |
139 | mfmsr r6 | |
140 | li r0, MSR_RI | |
141 | andc r6, r6, r0 | |
142 | mtmsrd r6, 1 /* Clear RI in MSR */ | |
143 | mtsrr0 r8 | |
144 | mtsrr1 r7 | |
145 | beqa 0x500 /* external interrupt (PPC970) */ | |
146 | beq cr1, 13f /* machine check */ | |
147 | RFI | |
148 | ||
149 | /* On POWER7, we have external interrupts set to use HSRR0/1 */ | |
150 | 11: mtspr SPRN_HSRR0, r8 | |
151 | mtspr SPRN_HSRR1, r7 | |
152 | ba 0x500 | |
153 | ||
154 | 13: b machine_check_fwnmi | |
155 | ||
de56a948 | 156 | |
371fefd6 PM |
157 | /* |
158 | * We come in here when wakened from nap mode on a secondary hw thread. | |
159 | * Relocation is off and most register values are lost. | |
160 | * r13 points to the PACA. | |
161 | */ | |
162 | .globl kvm_start_guest | |
163 | kvm_start_guest: | |
164 | ld r1,PACAEMERGSP(r13) | |
165 | subi r1,r1,STACK_FRAME_OVERHEAD | |
19ccb76a PM |
166 | ld r2,PACATOC(r13) |
167 | ||
f0888f70 PM |
168 | li r0,KVM_HWTHREAD_IN_KVM |
169 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
371fefd6 | 170 | |
f0888f70 PM |
171 | /* NV GPR values from power7_idle() will no longer be valid */ |
172 | li r0,1 | |
173 | stb r0,PACA_NAPSTATELOST(r13) | |
371fefd6 | 174 | |
4619ac88 PM |
175 | /* were we napping due to cede? */ |
176 | lbz r0,HSTATE_NAPPING(r13) | |
177 | cmpwi r0,0 | |
178 | bne kvm_end_cede | |
179 | ||
180 | /* | |
181 | * We weren't napping due to cede, so this must be a secondary | |
182 | * thread being woken up to run a guest, or being woken up due | |
183 | * to a stray IPI. (Or due to some machine check or hypervisor | |
184 | * maintenance interrupt while the core is in KVM.) | |
185 | */ | |
f0888f70 PM |
186 | |
187 | /* Check the wake reason in SRR1 to see why we got here */ | |
188 | mfspr r3,SPRN_SRR1 | |
189 | rlwinm r3,r3,44-31,0x7 /* extract wake reason field */ | |
190 | cmpwi r3,4 /* was it an external interrupt? */ | |
4619ac88 PM |
191 | bne 27f /* if not */ |
192 | ld r5,HSTATE_XICS_PHYS(r13) | |
193 | li r7,XICS_XIRR /* if it was an external interrupt, */ | |
f0888f70 | 194 | lwzcix r8,r5,r7 /* get and ack the interrupt */ |
371fefd6 | 195 | sync |
f0888f70 | 196 | clrldi. r9,r8,40 /* get interrupt source ID. */ |
4619ac88 PM |
197 | beq 28f /* none there? */ |
198 | cmpwi r9,XICS_IPI /* was it an IPI? */ | |
199 | bne 29f | |
200 | li r0,0xff | |
201 | li r6,XICS_MFRR | |
f0888f70 | 202 | stbcix r0,r5,r6 /* clear IPI */ |
4619ac88 PM |
203 | stwcix r8,r5,r7 /* EOI the interrupt */ |
204 | sync /* order loading of vcpu after that */ | |
371fefd6 | 205 | |
4619ac88 | 206 | /* get vcpu pointer, NULL if we have no vcpu to run */ |
7b444c67 PM |
207 | ld r4,HSTATE_KVM_VCPU(r13) |
208 | cmpdi r4,0 | |
f0888f70 | 209 | /* if we have no vcpu to run, go back to sleep */ |
7b444c67 | 210 | beq kvm_no_guest |
218309b7 | 211 | b 30f |
f0888f70 | 212 | |
4619ac88 PM |
213 | 27: /* XXX should handle hypervisor maintenance interrupts etc. here */ |
214 | b kvm_no_guest | |
215 | 28: /* SRR1 said external but ICP said nope?? */ | |
216 | b kvm_no_guest | |
217 | 29: /* External non-IPI interrupt to offline secondary thread? help?? */ | |
218 | stw r8,HSTATE_SAVED_XIRR(r13) | |
219 | b kvm_no_guest | |
2fde6d20 | 220 | |
218309b7 PM |
221 | 30: bl kvmppc_hv_entry |
222 | ||
223 | /* Back from the guest, go back to nap */ | |
224 | /* Clear our vcpu pointer so we don't come back in early */ | |
225 | li r0, 0 | |
226 | std r0, HSTATE_KVM_VCPU(r13) | |
227 | lwsync | |
228 | /* Clear any pending IPI - we're an offline thread */ | |
229 | ld r5, HSTATE_XICS_PHYS(r13) | |
230 | li r7, XICS_XIRR | |
231 | lwzcix r3, r5, r7 /* ack any pending interrupt */ | |
232 | rlwinm. r0, r3, 0, 0xffffff /* any pending? */ | |
233 | beq 37f | |
234 | sync | |
235 | li r0, 0xff | |
236 | li r6, XICS_MFRR | |
237 | stbcix r0, r5, r6 /* clear the IPI */ | |
238 | stwcix r3, r5, r7 /* EOI it */ | |
239 | 37: sync | |
240 | ||
241 | /* increment the nap count and then go to nap mode */ | |
242 | ld r4, HSTATE_KVM_VCORE(r13) | |
243 | addi r4, r4, VCORE_NAP_COUNT | |
244 | lwsync /* make previous updates visible */ | |
245 | 51: lwarx r3, 0, r4 | |
246 | addi r3, r3, 1 | |
247 | stwcx. r3, 0, r4 | |
248 | bne 51b | |
249 | ||
250 | kvm_no_guest: | |
251 | li r0, KVM_HWTHREAD_IN_NAP | |
252 | stb r0, HSTATE_HWTHREAD_STATE(r13) | |
253 | li r3, LPCR_PECE0 | |
254 | mfspr r4, SPRN_LPCR | |
255 | rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1 | |
256 | mtspr SPRN_LPCR, r4 | |
257 | isync | |
258 | std r0, HSTATE_SCRATCH0(r13) | |
259 | ptesync | |
260 | ld r0, HSTATE_SCRATCH0(r13) | |
261 | 1: cmpd r0, r0 | |
262 | bne 1b | |
263 | nap | |
264 | b . | |
265 | ||
266 | /****************************************************************************** | |
267 | * * | |
268 | * Entry code * | |
269 | * * | |
270 | *****************************************************************************/ | |
271 | ||
de56a948 PM |
272 | .global kvmppc_hv_entry |
273 | kvmppc_hv_entry: | |
274 | ||
275 | /* Required state: | |
276 | * | |
277 | * R4 = vcpu pointer | |
278 | * MSR = ~IR|DR | |
279 | * R13 = PACA | |
280 | * R1 = host R1 | |
281 | * all other volatile GPRS = free | |
282 | */ | |
283 | mflr r0 | |
218309b7 PM |
284 | std r0, PPC_LR_STKOFF(r1) |
285 | stdu r1, -112(r1) | |
de56a948 | 286 | |
8943633c PM |
287 | /* Set partition DABR */ |
288 | /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */ | |
289 | li r5,3 | |
290 | ld r6,VCPU_DABR(r4) | |
291 | mtspr SPRN_DABRX,r5 | |
292 | mtspr SPRN_DABR,r6 | |
293 | BEGIN_FTR_SECTION | |
294 | isync | |
295 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
de56a948 PM |
296 | |
297 | /* Load guest PMU registers */ | |
298 | /* R4 is live here (vcpu pointer) */ | |
299 | li r3, 1 | |
300 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
301 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ | |
302 | isync | |
303 | lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */ | |
304 | lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */ | |
305 | lwz r6, VCPU_PMC + 8(r4) | |
306 | lwz r7, VCPU_PMC + 12(r4) | |
307 | lwz r8, VCPU_PMC + 16(r4) | |
308 | lwz r9, VCPU_PMC + 20(r4) | |
9e368f29 PM |
309 | BEGIN_FTR_SECTION |
310 | lwz r10, VCPU_PMC + 24(r4) | |
311 | lwz r11, VCPU_PMC + 28(r4) | |
312 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
313 | mtspr SPRN_PMC1, r3 |
314 | mtspr SPRN_PMC2, r5 | |
315 | mtspr SPRN_PMC3, r6 | |
316 | mtspr SPRN_PMC4, r7 | |
317 | mtspr SPRN_PMC5, r8 | |
318 | mtspr SPRN_PMC6, r9 | |
9e368f29 PM |
319 | BEGIN_FTR_SECTION |
320 | mtspr SPRN_PMC7, r10 | |
321 | mtspr SPRN_PMC8, r11 | |
322 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
323 | ld r3, VCPU_MMCR(r4) |
324 | ld r5, VCPU_MMCR + 8(r4) | |
325 | ld r6, VCPU_MMCR + 16(r4) | |
14941789 PM |
326 | ld r7, VCPU_SIAR(r4) |
327 | ld r8, VCPU_SDAR(r4) | |
de56a948 PM |
328 | mtspr SPRN_MMCR1, r5 |
329 | mtspr SPRN_MMCRA, r6 | |
14941789 PM |
330 | mtspr SPRN_SIAR, r7 |
331 | mtspr SPRN_SDAR, r8 | |
de56a948 PM |
332 | mtspr SPRN_MMCR0, r3 |
333 | isync | |
334 | ||
335 | /* Load up FP, VMX and VSX registers */ | |
336 | bl kvmppc_load_fp | |
337 | ||
c75df6f9 MN |
338 | ld r14, VCPU_GPR(R14)(r4) |
339 | ld r15, VCPU_GPR(R15)(r4) | |
340 | ld r16, VCPU_GPR(R16)(r4) | |
341 | ld r17, VCPU_GPR(R17)(r4) | |
342 | ld r18, VCPU_GPR(R18)(r4) | |
343 | ld r19, VCPU_GPR(R19)(r4) | |
344 | ld r20, VCPU_GPR(R20)(r4) | |
345 | ld r21, VCPU_GPR(R21)(r4) | |
346 | ld r22, VCPU_GPR(R22)(r4) | |
347 | ld r23, VCPU_GPR(R23)(r4) | |
348 | ld r24, VCPU_GPR(R24)(r4) | |
349 | ld r25, VCPU_GPR(R25)(r4) | |
350 | ld r26, VCPU_GPR(R26)(r4) | |
351 | ld r27, VCPU_GPR(R27)(r4) | |
352 | ld r28, VCPU_GPR(R28)(r4) | |
353 | ld r29, VCPU_GPR(R29)(r4) | |
354 | ld r30, VCPU_GPR(R30)(r4) | |
355 | ld r31, VCPU_GPR(R31)(r4) | |
8943633c | 356 | |
9e368f29 | 357 | BEGIN_FTR_SECTION |
de56a948 PM |
358 | /* Switch DSCR to guest value */ |
359 | ld r5, VCPU_DSCR(r4) | |
360 | mtspr SPRN_DSCR, r5 | |
9e368f29 | 361 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 PM |
362 | |
363 | /* | |
364 | * Set the decrementer to the guest decrementer. | |
365 | */ | |
366 | ld r8,VCPU_DEC_EXPIRES(r4) | |
367 | mftb r7 | |
368 | subf r3,r7,r8 | |
369 | mtspr SPRN_DEC,r3 | |
370 | stw r3,VCPU_DEC(r4) | |
371 | ||
372 | ld r5, VCPU_SPRG0(r4) | |
373 | ld r6, VCPU_SPRG1(r4) | |
374 | ld r7, VCPU_SPRG2(r4) | |
375 | ld r8, VCPU_SPRG3(r4) | |
376 | mtspr SPRN_SPRG0, r5 | |
377 | mtspr SPRN_SPRG1, r6 | |
378 | mtspr SPRN_SPRG2, r7 | |
379 | mtspr SPRN_SPRG3, r8 | |
380 | ||
381 | /* Save R1 in the PACA */ | |
382 | std r1, HSTATE_HOST_R1(r13) | |
383 | ||
384 | /* Load up DAR and DSISR */ | |
385 | ld r5, VCPU_DAR(r4) | |
386 | lwz r6, VCPU_DSISR(r4) | |
387 | mtspr SPRN_DAR, r5 | |
388 | mtspr SPRN_DSISR, r6 | |
389 | ||
44a3add8 PM |
390 | li r6, KVM_GUEST_MODE_HOST_HV |
391 | stb r6, HSTATE_IN_GUEST(r13) | |
392 | ||
9e368f29 | 393 | BEGIN_FTR_SECTION |
de56a948 PM |
394 | /* Restore AMR and UAMOR, set AMOR to all 1s */ |
395 | ld r5,VCPU_AMR(r4) | |
396 | ld r6,VCPU_UAMOR(r4) | |
397 | li r7,-1 | |
398 | mtspr SPRN_AMR,r5 | |
399 | mtspr SPRN_UAMOR,r6 | |
400 | mtspr SPRN_AMOR,r7 | |
9e368f29 | 401 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 PM |
402 | |
403 | /* Clear out SLB */ | |
404 | li r6,0 | |
405 | slbmte r6,r6 | |
406 | slbia | |
407 | ptesync | |
408 | ||
9e368f29 PM |
409 | BEGIN_FTR_SECTION |
410 | b 30f | |
411 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
412 | /* | |
413 | * POWER7 host -> guest partition switch code. | |
414 | * We don't have to lock against concurrent tlbies, | |
415 | * but we do have to coordinate across hardware threads. | |
416 | */ | |
371fefd6 PM |
417 | /* Increment entry count iff exit count is zero. */ |
418 | ld r5,HSTATE_KVM_VCORE(r13) | |
419 | addi r9,r5,VCORE_ENTRY_EXIT | |
420 | 21: lwarx r3,0,r9 | |
421 | cmpwi r3,0x100 /* any threads starting to exit? */ | |
422 | bge secondary_too_late /* if so we're too late to the party */ | |
423 | addi r3,r3,1 | |
424 | stwcx. r3,0,r9 | |
425 | bne 21b | |
426 | ||
427 | /* Primary thread switches to guest partition. */ | |
aa04b4cc | 428 | ld r9,VCPU_KVM(r4) /* pointer to struct kvm */ |
371fefd6 PM |
429 | lwz r6,VCPU_PTID(r4) |
430 | cmpwi r6,0 | |
431 | bne 20f | |
de56a948 PM |
432 | ld r6,KVM_SDR1(r9) |
433 | lwz r7,KVM_LPID(r9) | |
434 | li r0,LPID_RSVD /* switch to reserved LPID */ | |
435 | mtspr SPRN_LPID,r0 | |
436 | ptesync | |
437 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
438 | mtspr SPRN_LPID,r7 | |
439 | isync | |
1b400ba0 PM |
440 | |
441 | /* See if we need to flush the TLB */ | |
442 | lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */ | |
443 | clrldi r7,r6,64-6 /* extract bit number (6 bits) */ | |
444 | srdi r6,r6,6 /* doubleword number */ | |
445 | sldi r6,r6,3 /* address offset */ | |
446 | add r6,r6,r9 | |
447 | addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */ | |
371fefd6 | 448 | li r0,1 |
1b400ba0 PM |
449 | sld r0,r0,r7 |
450 | ld r7,0(r6) | |
451 | and. r7,r7,r0 | |
452 | beq 22f | |
453 | 23: ldarx r7,0,r6 /* if set, clear the bit */ | |
454 | andc r7,r7,r0 | |
455 | stdcx. r7,0,r6 | |
456 | bne 23b | |
457 | li r6,128 /* and flush the TLB */ | |
458 | mtctr r6 | |
459 | li r7,0x800 /* IS field = 0b10 */ | |
460 | ptesync | |
461 | 28: tlbiel r7 | |
462 | addi r7,r7,0x1000 | |
463 | bdnz 28b | |
464 | ptesync | |
465 | ||
93b0f4dc PM |
466 | /* Add timebase offset onto timebase */ |
467 | 22: ld r8,VCORE_TB_OFFSET(r5) | |
468 | cmpdi r8,0 | |
469 | beq 37f | |
470 | mftb r6 /* current host timebase */ | |
471 | add r8,r8,r6 | |
472 | mtspr SPRN_TBU40,r8 /* update upper 40 bits */ | |
473 | mftb r7 /* check if lower 24 bits overflowed */ | |
474 | clrldi r6,r6,40 | |
475 | clrldi r7,r7,40 | |
476 | cmpld r7,r6 | |
477 | bge 37f | |
478 | addis r8,r8,0x100 /* if so, increment upper 40 bits */ | |
479 | mtspr SPRN_TBU40,r8 | |
480 | ||
388cc6e1 PM |
481 | /* Load guest PCR value to select appropriate compat mode */ |
482 | 37: ld r7, VCORE_PCR(r5) | |
483 | cmpdi r7, 0 | |
484 | beq 38f | |
485 | mtspr SPRN_PCR, r7 | |
486 | 38: | |
487 | li r0,1 | |
371fefd6 PM |
488 | stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */ |
489 | b 10f | |
490 | ||
491 | /* Secondary threads wait for primary to have done partition switch */ | |
492 | 20: lbz r0,VCORE_IN_GUEST(r5) | |
493 | cmpwi r0,0 | |
494 | beq 20b | |
aa04b4cc | 495 | |
19ccb76a | 496 | /* Set LPCR and RMOR. */ |
a0144e2a | 497 | 10: ld r8,VCORE_LPCR(r5) |
19ccb76a | 498 | mtspr SPRN_LPCR,r8 |
aa04b4cc PM |
499 | ld r8,KVM_RMOR(r9) |
500 | mtspr SPRN_RMOR,r8 | |
de56a948 PM |
501 | isync |
502 | ||
8c2dbb79 PM |
503 | /* Increment yield count if they have a VPA */ |
504 | ld r3, VCPU_VPA(r4) | |
505 | cmpdi r3, 0 | |
506 | beq 25f | |
507 | lwz r5, LPPACA_YIELDCOUNT(r3) | |
508 | addi r5, r5, 1 | |
509 | stw r5, LPPACA_YIELDCOUNT(r3) | |
510 | li r6, 1 | |
511 | stb r6, VCPU_VPA_DIRTY(r4) | |
512 | 25: | |
de56a948 PM |
513 | /* Check if HDEC expires soon */ |
514 | mfspr r3,SPRN_HDEC | |
515 | cmpwi r3,10 | |
516 | li r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
517 | mr r9,r4 | |
518 | blt hdec_soon | |
519 | ||
de56a948 PM |
520 | /* Save purr/spurr */ |
521 | mfspr r5,SPRN_PURR | |
522 | mfspr r6,SPRN_SPURR | |
523 | std r5,HSTATE_PURR(r13) | |
524 | std r6,HSTATE_SPURR(r13) | |
525 | ld r7,VCPU_PURR(r4) | |
526 | ld r8,VCPU_SPURR(r4) | |
527 | mtspr SPRN_PURR,r7 | |
528 | mtspr SPRN_SPURR,r8 | |
9e368f29 PM |
529 | b 31f |
530 | ||
531 | /* | |
532 | * PPC970 host -> guest partition switch code. | |
533 | * We have to lock against concurrent tlbies, | |
534 | * using native_tlbie_lock to lock against host tlbies | |
535 | * and kvm->arch.tlbie_lock to lock against guest tlbies. | |
536 | * We also have to invalidate the TLB since its | |
537 | * entries aren't tagged with the LPID. | |
538 | */ | |
539 | 30: ld r9,VCPU_KVM(r4) /* pointer to struct kvm */ | |
540 | ||
541 | /* first take native_tlbie_lock */ | |
542 | .section ".toc","aw" | |
543 | toc_tlbie_lock: | |
544 | .tc native_tlbie_lock[TC],native_tlbie_lock | |
545 | .previous | |
546 | ld r3,toc_tlbie_lock@toc(2) | |
54bb7f4b | 547 | #ifdef __BIG_ENDIAN__ |
9e368f29 | 548 | lwz r8,PACA_LOCK_TOKEN(r13) |
54bb7f4b AB |
549 | #else |
550 | lwz r8,PACAPACAINDEX(r13) | |
551 | #endif | |
9e368f29 PM |
552 | 24: lwarx r0,0,r3 |
553 | cmpwi r0,0 | |
554 | bne 24b | |
555 | stwcx. r8,0,r3 | |
556 | bne 24b | |
557 | isync | |
558 | ||
a0144e2a PM |
559 | ld r5,HSTATE_KVM_VCORE(r13) |
560 | ld r7,VCORE_LPCR(r5) /* use vcore->lpcr to store HID4 */ | |
9e368f29 PM |
561 | li r0,0x18f |
562 | rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */ | |
563 | or r0,r7,r0 | |
564 | ptesync | |
565 | sync | |
566 | mtspr SPRN_HID4,r0 /* switch to reserved LPID */ | |
567 | isync | |
568 | li r0,0 | |
569 | stw r0,0(r3) /* drop native_tlbie_lock */ | |
570 | ||
571 | /* invalidate the whole TLB */ | |
572 | li r0,256 | |
573 | mtctr r0 | |
574 | li r6,0 | |
575 | 25: tlbiel r6 | |
576 | addi r6,r6,0x1000 | |
577 | bdnz 25b | |
578 | ptesync | |
579 | ||
580 | /* Take the guest's tlbie_lock */ | |
581 | addi r3,r9,KVM_TLBIE_LOCK | |
582 | 24: lwarx r0,0,r3 | |
583 | cmpwi r0,0 | |
584 | bne 24b | |
585 | stwcx. r8,0,r3 | |
586 | bne 24b | |
587 | isync | |
588 | ld r6,KVM_SDR1(r9) | |
589 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
590 | ||
591 | /* Set up HID4 with the guest's LPID etc. */ | |
592 | sync | |
593 | mtspr SPRN_HID4,r7 | |
594 | isync | |
595 | ||
596 | /* drop the guest's tlbie_lock */ | |
597 | li r0,0 | |
598 | stw r0,0(r3) | |
599 | ||
600 | /* Check if HDEC expires soon */ | |
601 | mfspr r3,SPRN_HDEC | |
602 | cmpwi r3,10 | |
603 | li r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
604 | mr r9,r4 | |
605 | blt hdec_soon | |
606 | ||
607 | /* Enable HDEC interrupts */ | |
608 | mfspr r0,SPRN_HID0 | |
609 | li r3,1 | |
610 | rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1 | |
611 | sync | |
612 | mtspr SPRN_HID0,r0 | |
613 | mfspr r0,SPRN_HID0 | |
614 | mfspr r0,SPRN_HID0 | |
615 | mfspr r0,SPRN_HID0 | |
616 | mfspr r0,SPRN_HID0 | |
617 | mfspr r0,SPRN_HID0 | |
618 | mfspr r0,SPRN_HID0 | |
de56a948 PM |
619 | |
620 | /* Load up guest SLB entries */ | |
9e368f29 | 621 | 31: lwz r5,VCPU_SLB_MAX(r4) |
de56a948 PM |
622 | cmpwi r5,0 |
623 | beq 9f | |
624 | mtctr r5 | |
625 | addi r6,r4,VCPU_SLB | |
626 | 1: ld r8,VCPU_SLB_E(r6) | |
627 | ld r9,VCPU_SLB_V(r6) | |
628 | slbmte r9,r8 | |
629 | addi r6,r6,VCPU_SLB_SIZE | |
630 | bdnz 1b | |
631 | 9: | |
632 | ||
633 | /* Restore state of CTRL run bit; assume 1 on entry */ | |
634 | lwz r5,VCPU_CTRL(r4) | |
635 | andi. r5,r5,1 | |
636 | bne 4f | |
637 | mfspr r6,SPRN_CTRLF | |
638 | clrrdi r6,r6,1 | |
639 | mtspr SPRN_CTRLT,r6 | |
640 | 4: | |
641 | ld r6, VCPU_CTR(r4) | |
642 | lwz r7, VCPU_XER(r4) | |
643 | ||
644 | mtctr r6 | |
645 | mtxer r7 | |
646 | ||
4619ac88 PM |
647 | ld r10, VCPU_PC(r4) |
648 | ld r11, VCPU_MSR(r4) | |
19ccb76a | 649 | kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */ |
de56a948 PM |
650 | ld r6, VCPU_SRR0(r4) |
651 | ld r7, VCPU_SRR1(r4) | |
de56a948 | 652 | |
4619ac88 | 653 | /* r11 = vcpu->arch.msr & ~MSR_HV */ |
de56a948 PM |
654 | rldicl r11, r11, 63 - MSR_HV_LG, 1 |
655 | rotldi r11, r11, 1 + MSR_HV_LG | |
656 | ori r11, r11, MSR_ME | |
657 | ||
19ccb76a PM |
658 | /* Check if we can deliver an external or decrementer interrupt now */ |
659 | ld r0,VCPU_PENDING_EXC(r4) | |
4619ac88 | 660 | lis r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h |
19ccb76a PM |
661 | and r0,r0,r8 |
662 | cmpdi cr1,r0,0 | |
663 | andi. r0,r11,MSR_EE | |
664 | beq cr1,11f | |
665 | BEGIN_FTR_SECTION | |
666 | mfspr r8,SPRN_LPCR | |
667 | ori r8,r8,LPCR_MER | |
668 | mtspr SPRN_LPCR,r8 | |
669 | isync | |
670 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
671 | beq 5f | |
672 | li r0,BOOK3S_INTERRUPT_EXTERNAL | |
673 | 12: mr r6,r10 | |
674 | mr r10,r0 | |
675 | mr r7,r11 | |
676 | li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
677 | rotldi r11,r11,63 | |
678 | b 5f | |
679 | 11: beq 5f | |
680 | mfspr r0,SPRN_DEC | |
681 | cmpwi r0,0 | |
682 | li r0,BOOK3S_INTERRUPT_DECREMENTER | |
683 | blt 12b | |
684 | ||
685 | /* Move SRR0 and SRR1 into the respective regs */ | |
686 | 5: mtspr SPRN_SRR0, r6 | |
687 | mtspr SPRN_SRR1, r7 | |
19ccb76a | 688 | |
27025a60 LPF |
689 | /* |
690 | * Required state: | |
691 | * R4 = vcpu | |
692 | * R10: value for HSRR0 | |
693 | * R11: value for HSRR1 | |
694 | * R13 = PACA | |
695 | */ | |
de56a948 | 696 | fast_guest_return: |
4619ac88 PM |
697 | li r0,0 |
698 | stb r0,VCPU_CEDED(r4) /* cancel cede */ | |
de56a948 PM |
699 | mtspr SPRN_HSRR0,r10 |
700 | mtspr SPRN_HSRR1,r11 | |
701 | ||
702 | /* Activate guest mode, so faults get handled by KVM */ | |
44a3add8 | 703 | li r9, KVM_GUEST_MODE_GUEST_HV |
de56a948 PM |
704 | stb r9, HSTATE_IN_GUEST(r13) |
705 | ||
706 | /* Enter guest */ | |
707 | ||
0acb9111 PM |
708 | BEGIN_FTR_SECTION |
709 | ld r5, VCPU_CFAR(r4) | |
710 | mtspr SPRN_CFAR, r5 | |
711 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
4b8473c9 PM |
712 | BEGIN_FTR_SECTION |
713 | ld r0, VCPU_PPR(r4) | |
714 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
0acb9111 | 715 | |
de56a948 PM |
716 | ld r5, VCPU_LR(r4) |
717 | lwz r6, VCPU_CR(r4) | |
718 | mtlr r5 | |
719 | mtcr r6 | |
720 | ||
c75df6f9 MN |
721 | ld r1, VCPU_GPR(R1)(r4) |
722 | ld r2, VCPU_GPR(R2)(r4) | |
723 | ld r3, VCPU_GPR(R3)(r4) | |
724 | ld r5, VCPU_GPR(R5)(r4) | |
725 | ld r6, VCPU_GPR(R6)(r4) | |
726 | ld r7, VCPU_GPR(R7)(r4) | |
727 | ld r8, VCPU_GPR(R8)(r4) | |
728 | ld r9, VCPU_GPR(R9)(r4) | |
729 | ld r10, VCPU_GPR(R10)(r4) | |
730 | ld r11, VCPU_GPR(R11)(r4) | |
731 | ld r12, VCPU_GPR(R12)(r4) | |
732 | ld r13, VCPU_GPR(R13)(r4) | |
733 | ||
4b8473c9 PM |
734 | BEGIN_FTR_SECTION |
735 | mtspr SPRN_PPR, r0 | |
736 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
737 | ld r0, VCPU_GPR(R0)(r4) | |
c75df6f9 | 738 | ld r4, VCPU_GPR(R4)(r4) |
de56a948 PM |
739 | |
740 | hrfid | |
741 | b . | |
742 | ||
743 | /****************************************************************************** | |
744 | * * | |
745 | * Exit code * | |
746 | * * | |
747 | *****************************************************************************/ | |
748 | ||
749 | /* | |
750 | * We come here from the first-level interrupt handlers. | |
751 | */ | |
dd96b2c2 AK |
752 | .globl kvmppc_interrupt_hv |
753 | kvmppc_interrupt_hv: | |
de56a948 PM |
754 | /* |
755 | * Register contents: | |
756 | * R12 = interrupt vector | |
757 | * R13 = PACA | |
758 | * guest CR, R12 saved in shadow VCPU SCRATCH1/0 | |
759 | * guest R13 saved in SPRN_SCRATCH0 | |
760 | */ | |
761 | /* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */ | |
762 | std r9, HSTATE_HOST_R2(r13) | |
44a3add8 PM |
763 | |
764 | lbz r9, HSTATE_IN_GUEST(r13) | |
765 | cmpwi r9, KVM_GUEST_MODE_HOST_HV | |
766 | beq kvmppc_bad_host_intr | |
dd96b2c2 AK |
767 | #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE |
768 | cmpwi r9, KVM_GUEST_MODE_GUEST | |
769 | ld r9, HSTATE_HOST_R2(r13) | |
770 | beq kvmppc_interrupt_pr | |
771 | #endif | |
44a3add8 PM |
772 | /* We're now back in the host but in guest MMU context */ |
773 | li r9, KVM_GUEST_MODE_HOST_HV | |
774 | stb r9, HSTATE_IN_GUEST(r13) | |
775 | ||
de56a948 PM |
776 | ld r9, HSTATE_KVM_VCPU(r13) |
777 | ||
778 | /* Save registers */ | |
779 | ||
c75df6f9 MN |
780 | std r0, VCPU_GPR(R0)(r9) |
781 | std r1, VCPU_GPR(R1)(r9) | |
782 | std r2, VCPU_GPR(R2)(r9) | |
783 | std r3, VCPU_GPR(R3)(r9) | |
784 | std r4, VCPU_GPR(R4)(r9) | |
785 | std r5, VCPU_GPR(R5)(r9) | |
786 | std r6, VCPU_GPR(R6)(r9) | |
787 | std r7, VCPU_GPR(R7)(r9) | |
788 | std r8, VCPU_GPR(R8)(r9) | |
de56a948 | 789 | ld r0, HSTATE_HOST_R2(r13) |
c75df6f9 MN |
790 | std r0, VCPU_GPR(R9)(r9) |
791 | std r10, VCPU_GPR(R10)(r9) | |
792 | std r11, VCPU_GPR(R11)(r9) | |
de56a948 PM |
793 | ld r3, HSTATE_SCRATCH0(r13) |
794 | lwz r4, HSTATE_SCRATCH1(r13) | |
c75df6f9 | 795 | std r3, VCPU_GPR(R12)(r9) |
de56a948 | 796 | stw r4, VCPU_CR(r9) |
0acb9111 PM |
797 | BEGIN_FTR_SECTION |
798 | ld r3, HSTATE_CFAR(r13) | |
799 | std r3, VCPU_CFAR(r9) | |
800 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
4b8473c9 PM |
801 | BEGIN_FTR_SECTION |
802 | ld r4, HSTATE_PPR(r13) | |
803 | std r4, VCPU_PPR(r9) | |
804 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
de56a948 PM |
805 | |
806 | /* Restore R1/R2 so we can handle faults */ | |
807 | ld r1, HSTATE_HOST_R1(r13) | |
808 | ld r2, PACATOC(r13) | |
809 | ||
810 | mfspr r10, SPRN_SRR0 | |
811 | mfspr r11, SPRN_SRR1 | |
812 | std r10, VCPU_SRR0(r9) | |
813 | std r11, VCPU_SRR1(r9) | |
814 | andi. r0, r12, 2 /* need to read HSRR0/1? */ | |
815 | beq 1f | |
816 | mfspr r10, SPRN_HSRR0 | |
817 | mfspr r11, SPRN_HSRR1 | |
818 | clrrdi r12, r12, 2 | |
819 | 1: std r10, VCPU_PC(r9) | |
820 | std r11, VCPU_MSR(r9) | |
821 | ||
822 | GET_SCRATCH0(r3) | |
823 | mflr r4 | |
c75df6f9 | 824 | std r3, VCPU_GPR(R13)(r9) |
de56a948 PM |
825 | std r4, VCPU_LR(r9) |
826 | ||
de56a948 PM |
827 | stw r12,VCPU_TRAP(r9) |
828 | ||
697d3899 PM |
829 | /* Save HEIR (HV emulation assist reg) in last_inst |
830 | if this is an HEI (HV emulation interrupt, e40) */ | |
831 | li r3,KVM_INST_FETCH_FAILED | |
832 | BEGIN_FTR_SECTION | |
833 | cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST | |
834 | bne 11f | |
835 | mfspr r3,SPRN_HEIR | |
836 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
837 | 11: stw r3,VCPU_LAST_INST(r9) | |
838 | ||
839 | /* these are volatile across C function calls */ | |
840 | mfctr r3 | |
841 | mfxer r4 | |
842 | std r3, VCPU_CTR(r9) | |
843 | stw r4, VCPU_XER(r9) | |
844 | ||
845 | BEGIN_FTR_SECTION | |
846 | /* If this is a page table miss then see if it's theirs or ours */ | |
847 | cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE | |
848 | beq kvmppc_hdsi | |
342d3db7 PM |
849 | cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE |
850 | beq kvmppc_hisi | |
697d3899 PM |
851 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
852 | ||
de56a948 PM |
853 | /* See if this is a leftover HDEC interrupt */ |
854 | cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
855 | bne 2f | |
856 | mfspr r3,SPRN_HDEC | |
857 | cmpwi r3,0 | |
858 | bge ignore_hdec | |
859 | 2: | |
697d3899 | 860 | /* See if this is an hcall we can handle in real mode */ |
a8606e20 PM |
861 | cmpwi r12,BOOK3S_INTERRUPT_SYSCALL |
862 | beq hcall_try_real_mode | |
de56a948 | 863 | |
54695c30 | 864 | /* Only handle external interrupts here on arch 206 and later */ |
9e368f29 | 865 | BEGIN_FTR_SECTION |
54695c30 BH |
866 | b ext_interrupt_to_host |
867 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206) | |
868 | ||
869 | /* External interrupt ? */ | |
870 | cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL | |
871 | bne+ ext_interrupt_to_host | |
872 | ||
873 | /* External interrupt, first check for host_ipi. If this is | |
874 | * set, we know the host wants us out so let's do it now | |
875 | */ | |
4619ac88 | 876 | do_ext_interrupt: |
c934243c PM |
877 | bl kvmppc_read_intr |
878 | cmpdi r3, 0 | |
879 | bgt ext_interrupt_to_host | |
54695c30 BH |
880 | |
881 | /* Allright, looks like an IPI for the guest, we need to set MER */ | |
4619ac88 PM |
882 | /* Check if any CPU is heading out to the host, if so head out too */ |
883 | ld r5, HSTATE_KVM_VCORE(r13) | |
884 | lwz r0, VCORE_ENTRY_EXIT(r5) | |
885 | cmpwi r0, 0x100 | |
886 | bge ext_interrupt_to_host | |
887 | ||
888 | /* See if there is a pending interrupt for the guest */ | |
889 | mfspr r8, SPRN_LPCR | |
890 | ld r0, VCPU_PENDING_EXC(r9) | |
891 | /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */ | |
892 | rldicl. r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63 | |
893 | rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH | |
894 | beq 2f | |
54695c30 BH |
895 | |
896 | /* And if the guest EE is set, we can deliver immediately, else | |
897 | * we return to the guest with MER set | |
898 | */ | |
899 | andi. r0, r11, MSR_EE | |
4619ac88 PM |
900 | beq 2f |
901 | mtspr SPRN_SRR0, r10 | |
902 | mtspr SPRN_SRR1, r11 | |
903 | li r10, BOOK3S_INTERRUPT_EXTERNAL | |
904 | li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
905 | rotldi r11, r11, 63 | |
906 | 2: mr r4, r9 | |
907 | mtspr SPRN_LPCR, r8 | |
54695c30 BH |
908 | b fast_guest_return |
909 | ||
54695c30 | 910 | ext_interrupt_to_host: |
de56a948 | 911 | |
b4072df4 | 912 | guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */ |
de56a948 | 913 | /* Save more register state */ |
de56a948 PM |
914 | mfdar r6 |
915 | mfdsisr r7 | |
de56a948 PM |
916 | std r6, VCPU_DAR(r9) |
917 | stw r7, VCPU_DSISR(r9) | |
9e368f29 | 918 | BEGIN_FTR_SECTION |
697d3899 | 919 | /* don't overwrite fault_dar/fault_dsisr if HDSI */ |
de56a948 PM |
920 | cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE |
921 | beq 6f | |
9e368f29 | 922 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
697d3899 | 923 | std r6, VCPU_FAULT_DAR(r9) |
de56a948 PM |
924 | stw r7, VCPU_FAULT_DSISR(r9) |
925 | ||
b4072df4 PM |
926 | /* See if it is a machine check */ |
927 | cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
928 | beq machine_check_realmode | |
929 | mc_cont: | |
930 | ||
de56a948 | 931 | /* Save guest CTRL register, set runlatch to 1 */ |
697d3899 | 932 | 6: mfspr r6,SPRN_CTRLF |
de56a948 PM |
933 | stw r6,VCPU_CTRL(r9) |
934 | andi. r0,r6,1 | |
935 | bne 4f | |
936 | ori r6,r6,1 | |
937 | mtspr SPRN_CTRLT,r6 | |
938 | 4: | |
939 | /* Read the guest SLB and save it away */ | |
940 | lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */ | |
941 | mtctr r0 | |
942 | li r6,0 | |
943 | addi r7,r9,VCPU_SLB | |
944 | li r5,0 | |
945 | 1: slbmfee r8,r6 | |
946 | andis. r0,r8,SLB_ESID_V@h | |
947 | beq 2f | |
948 | add r8,r8,r6 /* put index in */ | |
949 | slbmfev r3,r6 | |
950 | std r8,VCPU_SLB_E(r7) | |
951 | std r3,VCPU_SLB_V(r7) | |
952 | addi r7,r7,VCPU_SLB_SIZE | |
953 | addi r5,r5,1 | |
954 | 2: addi r6,r6,1 | |
955 | bdnz 1b | |
956 | stw r5,VCPU_SLB_MAX(r9) | |
957 | ||
958 | /* | |
959 | * Save the guest PURR/SPURR | |
960 | */ | |
9e368f29 | 961 | BEGIN_FTR_SECTION |
de56a948 PM |
962 | mfspr r5,SPRN_PURR |
963 | mfspr r6,SPRN_SPURR | |
964 | ld r7,VCPU_PURR(r9) | |
965 | ld r8,VCPU_SPURR(r9) | |
966 | std r5,VCPU_PURR(r9) | |
967 | std r6,VCPU_SPURR(r9) | |
968 | subf r5,r7,r5 | |
969 | subf r6,r8,r6 | |
970 | ||
971 | /* | |
972 | * Restore host PURR/SPURR and add guest times | |
973 | * so that the time in the guest gets accounted. | |
974 | */ | |
975 | ld r3,HSTATE_PURR(r13) | |
976 | ld r4,HSTATE_SPURR(r13) | |
977 | add r3,r3,r5 | |
978 | add r4,r4,r6 | |
979 | mtspr SPRN_PURR,r3 | |
980 | mtspr SPRN_SPURR,r4 | |
9e368f29 | 981 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201) |
de56a948 PM |
982 | |
983 | /* Clear out SLB */ | |
984 | li r5,0 | |
985 | slbmte r5,r5 | |
986 | slbia | |
987 | ptesync | |
988 | ||
19ccb76a | 989 | hdec_soon: /* r9 = vcpu, r12 = trap, r13 = paca */ |
9e368f29 PM |
990 | BEGIN_FTR_SECTION |
991 | b 32f | |
992 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
993 | /* | |
994 | * POWER7 guest -> host partition switch code. | |
995 | * We don't have to lock against tlbies but we do | |
996 | * have to coordinate the hardware threads. | |
997 | */ | |
371fefd6 PM |
998 | /* Increment the threads-exiting-guest count in the 0xff00 |
999 | bits of vcore->entry_exit_count */ | |
1000 | lwsync | |
1001 | ld r5,HSTATE_KVM_VCORE(r13) | |
1002 | addi r6,r5,VCORE_ENTRY_EXIT | |
1003 | 41: lwarx r3,0,r6 | |
1004 | addi r0,r3,0x100 | |
1005 | stwcx. r0,0,r6 | |
1006 | bne 41b | |
19ccb76a | 1007 | lwsync |
371fefd6 PM |
1008 | |
1009 | /* | |
1010 | * At this point we have an interrupt that we have to pass | |
1011 | * up to the kernel or qemu; we can't handle it in real mode. | |
1012 | * Thus we have to do a partition switch, so we have to | |
1013 | * collect the other threads, if we are the first thread | |
1014 | * to take an interrupt. To do this, we set the HDEC to 0, | |
1015 | * which causes an HDEC interrupt in all threads within 2ns | |
1016 | * because the HDEC register is shared between all 4 threads. | |
1017 | * However, we don't need to bother if this is an HDEC | |
1018 | * interrupt, since the other threads will already be on their | |
1019 | * way here in that case. | |
1020 | */ | |
19ccb76a PM |
1021 | cmpwi r3,0x100 /* Are we the first here? */ |
1022 | bge 43f | |
1023 | cmpwi r3,1 /* Are any other threads in the guest? */ | |
1024 | ble 43f | |
371fefd6 PM |
1025 | cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER |
1026 | beq 40f | |
371fefd6 PM |
1027 | li r0,0 |
1028 | mtspr SPRN_HDEC,r0 | |
1029 | 40: | |
19ccb76a PM |
1030 | /* |
1031 | * Send an IPI to any napping threads, since an HDEC interrupt | |
1032 | * doesn't wake CPUs up from nap. | |
1033 | */ | |
1034 | lwz r3,VCORE_NAPPING_THREADS(r5) | |
1035 | lwz r4,VCPU_PTID(r9) | |
1036 | li r0,1 | |
2f584a14 | 1037 | sld r0,r0,r4 |
19ccb76a PM |
1038 | andc. r3,r3,r0 /* no sense IPI'ing ourselves */ |
1039 | beq 43f | |
1040 | mulli r4,r4,PACA_SIZE /* get paca for thread 0 */ | |
1041 | subf r6,r4,r13 | |
1042 | 42: andi. r0,r3,1 | |
1043 | beq 44f | |
1044 | ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */ | |
1045 | li r0,IPI_PRIORITY | |
54695c30 | 1046 | li r7,XICS_MFRR |
19ccb76a PM |
1047 | stbcix r0,r7,r8 /* trigger the IPI */ |
1048 | 44: srdi. r3,r3,1 | |
1049 | addi r6,r6,PACA_SIZE | |
1050 | bne 42b | |
371fefd6 PM |
1051 | |
1052 | /* Secondary threads wait for primary to do partition switch */ | |
19ccb76a | 1053 | 43: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */ |
371fefd6 PM |
1054 | ld r5,HSTATE_KVM_VCORE(r13) |
1055 | lwz r3,VCPU_PTID(r9) | |
1056 | cmpwi r3,0 | |
1057 | beq 15f | |
1058 | HMT_LOW | |
1059 | 13: lbz r3,VCORE_IN_GUEST(r5) | |
1060 | cmpwi r3,0 | |
1061 | bne 13b | |
1062 | HMT_MEDIUM | |
1063 | b 16f | |
1064 | ||
1065 | /* Primary thread waits for all the secondaries to exit guest */ | |
1066 | 15: lwz r3,VCORE_ENTRY_EXIT(r5) | |
1067 | srwi r0,r3,8 | |
1068 | clrldi r3,r3,56 | |
1069 | cmpw r3,r0 | |
1070 | bne 15b | |
1071 | isync | |
1072 | ||
1073 | /* Primary thread switches back to host partition */ | |
de56a948 PM |
1074 | ld r6,KVM_HOST_SDR1(r4) |
1075 | lwz r7,KVM_HOST_LPID(r4) | |
1076 | li r8,LPID_RSVD /* switch to reserved LPID */ | |
1077 | mtspr SPRN_LPID,r8 | |
1078 | ptesync | |
1079 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
1080 | mtspr SPRN_LPID,r7 | |
1081 | isync | |
93b0f4dc PM |
1082 | |
1083 | /* Subtract timebase offset from timebase */ | |
1084 | ld r8,VCORE_TB_OFFSET(r5) | |
1085 | cmpdi r8,0 | |
1086 | beq 17f | |
1087 | mftb r6 /* current host timebase */ | |
1088 | subf r8,r8,r6 | |
1089 | mtspr SPRN_TBU40,r8 /* update upper 40 bits */ | |
1090 | mftb r7 /* check if lower 24 bits overflowed */ | |
1091 | clrldi r6,r6,40 | |
1092 | clrldi r7,r7,40 | |
1093 | cmpld r7,r6 | |
1094 | bge 17f | |
1095 | addis r8,r8,0x100 /* if so, increment upper 40 bits */ | |
1096 | mtspr SPRN_TBU40,r8 | |
1097 | ||
388cc6e1 PM |
1098 | /* Reset PCR */ |
1099 | 17: ld r0, VCORE_PCR(r5) | |
1100 | cmpdi r0, 0 | |
1101 | beq 18f | |
1102 | li r0, 0 | |
1103 | mtspr SPRN_PCR, r0 | |
1104 | 18: | |
93b0f4dc | 1105 | /* Signal secondary CPUs to continue */ |
371fefd6 | 1106 | stb r0,VCORE_IN_GUEST(r5) |
de56a948 PM |
1107 | lis r8,0x7fff /* MAX_INT@h */ |
1108 | mtspr SPRN_HDEC,r8 | |
1109 | ||
371fefd6 | 1110 | 16: ld r8,KVM_HOST_LPCR(r4) |
de56a948 PM |
1111 | mtspr SPRN_LPCR,r8 |
1112 | isync | |
9e368f29 PM |
1113 | b 33f |
1114 | ||
1115 | /* | |
1116 | * PPC970 guest -> host partition switch code. | |
1117 | * We have to lock against concurrent tlbies, and | |
1118 | * we have to flush the whole TLB. | |
1119 | */ | |
1120 | 32: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */ | |
1121 | ||
1122 | /* Take the guest's tlbie_lock */ | |
54bb7f4b | 1123 | #ifdef __BIG_ENDIAN__ |
9e368f29 | 1124 | lwz r8,PACA_LOCK_TOKEN(r13) |
54bb7f4b AB |
1125 | #else |
1126 | lwz r8,PACAPACAINDEX(r13) | |
1127 | #endif | |
9e368f29 PM |
1128 | addi r3,r4,KVM_TLBIE_LOCK |
1129 | 24: lwarx r0,0,r3 | |
1130 | cmpwi r0,0 | |
1131 | bne 24b | |
1132 | stwcx. r8,0,r3 | |
1133 | bne 24b | |
1134 | isync | |
1135 | ||
1136 | ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */ | |
1137 | li r0,0x18f | |
1138 | rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */ | |
1139 | or r0,r7,r0 | |
1140 | ptesync | |
1141 | sync | |
1142 | mtspr SPRN_HID4,r0 /* switch to reserved LPID */ | |
1143 | isync | |
1144 | li r0,0 | |
1145 | stw r0,0(r3) /* drop guest tlbie_lock */ | |
1146 | ||
1147 | /* invalidate the whole TLB */ | |
1148 | li r0,256 | |
1149 | mtctr r0 | |
1150 | li r6,0 | |
1151 | 25: tlbiel r6 | |
1152 | addi r6,r6,0x1000 | |
1153 | bdnz 25b | |
1154 | ptesync | |
1155 | ||
1156 | /* take native_tlbie_lock */ | |
1157 | ld r3,toc_tlbie_lock@toc(2) | |
1158 | 24: lwarx r0,0,r3 | |
1159 | cmpwi r0,0 | |
1160 | bne 24b | |
1161 | stwcx. r8,0,r3 | |
1162 | bne 24b | |
1163 | isync | |
1164 | ||
1165 | ld r6,KVM_HOST_SDR1(r4) | |
1166 | mtspr SPRN_SDR1,r6 /* switch to host page table */ | |
1167 | ||
1168 | /* Set up host HID4 value */ | |
1169 | sync | |
1170 | mtspr SPRN_HID4,r7 | |
1171 | isync | |
1172 | li r0,0 | |
1173 | stw r0,0(r3) /* drop native_tlbie_lock */ | |
1174 | ||
1175 | lis r8,0x7fff /* MAX_INT@h */ | |
1176 | mtspr SPRN_HDEC,r8 | |
1177 | ||
1178 | /* Disable HDEC interrupts */ | |
1179 | mfspr r0,SPRN_HID0 | |
1180 | li r3,0 | |
1181 | rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1 | |
1182 | sync | |
1183 | mtspr SPRN_HID0,r0 | |
1184 | mfspr r0,SPRN_HID0 | |
1185 | mfspr r0,SPRN_HID0 | |
1186 | mfspr r0,SPRN_HID0 | |
1187 | mfspr r0,SPRN_HID0 | |
1188 | mfspr r0,SPRN_HID0 | |
1189 | mfspr r0,SPRN_HID0 | |
de56a948 PM |
1190 | |
1191 | /* load host SLB entries */ | |
9e368f29 | 1192 | 33: ld r8,PACA_SLBSHADOWPTR(r13) |
de56a948 PM |
1193 | |
1194 | .rept SLB_NUM_BOLTED | |
1195 | ld r5,SLBSHADOW_SAVEAREA(r8) | |
1196 | ld r6,SLBSHADOW_SAVEAREA+8(r8) | |
1197 | andis. r7,r5,SLB_ESID_V@h | |
1198 | beq 1f | |
1199 | slbmte r6,r5 | |
1200 | 1: addi r8,r8,16 | |
1201 | .endr | |
1202 | ||
93b0f4dc PM |
1203 | /* Save DEC */ |
1204 | mfspr r5,SPRN_DEC | |
1205 | mftb r6 | |
1206 | extsw r5,r5 | |
1207 | add r5,r5,r6 | |
1208 | std r5,VCPU_DEC_EXPIRES(r9) | |
1209 | ||
de56a948 | 1210 | /* Save and reset AMR and UAMOR before turning on the MMU */ |
9e368f29 | 1211 | BEGIN_FTR_SECTION |
de56a948 PM |
1212 | mfspr r5,SPRN_AMR |
1213 | mfspr r6,SPRN_UAMOR | |
1214 | std r5,VCPU_AMR(r9) | |
1215 | std r6,VCPU_UAMOR(r9) | |
1216 | li r6,0 | |
1217 | mtspr SPRN_AMR,r6 | |
9e368f29 | 1218 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 | 1219 | |
44a3add8 PM |
1220 | /* Unset guest mode */ |
1221 | li r0, KVM_GUEST_MODE_NONE | |
1222 | stb r0, HSTATE_IN_GUEST(r13) | |
1223 | ||
de56a948 | 1224 | /* Switch DSCR back to host value */ |
9e368f29 | 1225 | BEGIN_FTR_SECTION |
de56a948 PM |
1226 | mfspr r8, SPRN_DSCR |
1227 | ld r7, HSTATE_DSCR(r13) | |
cfc86025 | 1228 | std r8, VCPU_DSCR(r9) |
de56a948 | 1229 | mtspr SPRN_DSCR, r7 |
9e368f29 | 1230 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 PM |
1231 | |
1232 | /* Save non-volatile GPRs */ | |
c75df6f9 MN |
1233 | std r14, VCPU_GPR(R14)(r9) |
1234 | std r15, VCPU_GPR(R15)(r9) | |
1235 | std r16, VCPU_GPR(R16)(r9) | |
1236 | std r17, VCPU_GPR(R17)(r9) | |
1237 | std r18, VCPU_GPR(R18)(r9) | |
1238 | std r19, VCPU_GPR(R19)(r9) | |
1239 | std r20, VCPU_GPR(R20)(r9) | |
1240 | std r21, VCPU_GPR(R21)(r9) | |
1241 | std r22, VCPU_GPR(R22)(r9) | |
1242 | std r23, VCPU_GPR(R23)(r9) | |
1243 | std r24, VCPU_GPR(R24)(r9) | |
1244 | std r25, VCPU_GPR(R25)(r9) | |
1245 | std r26, VCPU_GPR(R26)(r9) | |
1246 | std r27, VCPU_GPR(R27)(r9) | |
1247 | std r28, VCPU_GPR(R28)(r9) | |
1248 | std r29, VCPU_GPR(R29)(r9) | |
1249 | std r30, VCPU_GPR(R30)(r9) | |
1250 | std r31, VCPU_GPR(R31)(r9) | |
de56a948 PM |
1251 | |
1252 | /* Save SPRGs */ | |
1253 | mfspr r3, SPRN_SPRG0 | |
1254 | mfspr r4, SPRN_SPRG1 | |
1255 | mfspr r5, SPRN_SPRG2 | |
1256 | mfspr r6, SPRN_SPRG3 | |
1257 | std r3, VCPU_SPRG0(r9) | |
1258 | std r4, VCPU_SPRG1(r9) | |
1259 | std r5, VCPU_SPRG2(r9) | |
1260 | std r6, VCPU_SPRG3(r9) | |
1261 | ||
8943633c PM |
1262 | /* save FP state */ |
1263 | mr r3, r9 | |
1264 | bl .kvmppc_save_fp | |
1265 | ||
a8606e20 PM |
1266 | /* Increment yield count if they have a VPA */ |
1267 | ld r8, VCPU_VPA(r9) /* do they have a VPA? */ | |
1268 | cmpdi r8, 0 | |
1269 | beq 25f | |
1270 | lwz r3, LPPACA_YIELDCOUNT(r8) | |
1271 | addi r3, r3, 1 | |
1272 | stw r3, LPPACA_YIELDCOUNT(r8) | |
c35635ef PM |
1273 | li r3, 1 |
1274 | stb r3, VCPU_VPA_DIRTY(r9) | |
a8606e20 PM |
1275 | 25: |
1276 | /* Save PMU registers if requested */ | |
1277 | /* r8 and cr0.eq are live here */ | |
de56a948 PM |
1278 | li r3, 1 |
1279 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
1280 | mfspr r4, SPRN_MMCR0 /* save MMCR0 */ | |
1281 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ | |
8943633c PM |
1282 | mfspr r6, SPRN_MMCRA |
1283 | BEGIN_FTR_SECTION | |
1284 | /* On P7, clear MMCRA in order to disable SDAR updates */ | |
1285 | li r7, 0 | |
1286 | mtspr SPRN_MMCRA, r7 | |
1287 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
de56a948 | 1288 | isync |
a8606e20 PM |
1289 | beq 21f /* if no VPA, save PMU stuff anyway */ |
1290 | lbz r7, LPPACA_PMCINUSE(r8) | |
1291 | cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */ | |
1292 | bne 21f | |
1293 | std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */ | |
1294 | b 22f | |
1295 | 21: mfspr r5, SPRN_MMCR1 | |
14941789 PM |
1296 | mfspr r7, SPRN_SIAR |
1297 | mfspr r8, SPRN_SDAR | |
de56a948 PM |
1298 | std r4, VCPU_MMCR(r9) |
1299 | std r5, VCPU_MMCR + 8(r9) | |
1300 | std r6, VCPU_MMCR + 16(r9) | |
14941789 PM |
1301 | std r7, VCPU_SIAR(r9) |
1302 | std r8, VCPU_SDAR(r9) | |
de56a948 PM |
1303 | mfspr r3, SPRN_PMC1 |
1304 | mfspr r4, SPRN_PMC2 | |
1305 | mfspr r5, SPRN_PMC3 | |
1306 | mfspr r6, SPRN_PMC4 | |
1307 | mfspr r7, SPRN_PMC5 | |
1308 | mfspr r8, SPRN_PMC6 | |
9e368f29 PM |
1309 | BEGIN_FTR_SECTION |
1310 | mfspr r10, SPRN_PMC7 | |
1311 | mfspr r11, SPRN_PMC8 | |
1312 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
1313 | stw r3, VCPU_PMC(r9) |
1314 | stw r4, VCPU_PMC + 4(r9) | |
1315 | stw r5, VCPU_PMC + 8(r9) | |
1316 | stw r6, VCPU_PMC + 12(r9) | |
1317 | stw r7, VCPU_PMC + 16(r9) | |
1318 | stw r8, VCPU_PMC + 20(r9) | |
9e368f29 PM |
1319 | BEGIN_FTR_SECTION |
1320 | stw r10, VCPU_PMC + 24(r9) | |
1321 | stw r11, VCPU_PMC + 28(r9) | |
1322 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 | 1323 | 22: |
218309b7 PM |
1324 | ld r0, 112+PPC_LR_STKOFF(r1) |
1325 | addi r1, r1, 112 | |
1326 | mtlr r0 | |
1327 | blr | |
1328 | secondary_too_late: | |
1329 | ld r5,HSTATE_KVM_VCORE(r13) | |
1330 | HMT_LOW | |
1331 | 13: lbz r3,VCORE_IN_GUEST(r5) | |
1332 | cmpwi r3,0 | |
1333 | bne 13b | |
1334 | HMT_MEDIUM | |
1335 | li r0, KVM_GUEST_MODE_NONE | |
1336 | stb r0, HSTATE_IN_GUEST(r13) | |
1337 | ld r11,PACA_SLBSHADOWPTR(r13) | |
de56a948 | 1338 | |
218309b7 PM |
1339 | .rept SLB_NUM_BOLTED |
1340 | ld r5,SLBSHADOW_SAVEAREA(r11) | |
1341 | ld r6,SLBSHADOW_SAVEAREA+8(r11) | |
1342 | andis. r7,r5,SLB_ESID_V@h | |
1343 | beq 1f | |
1344 | slbmte r6,r5 | |
1345 | 1: addi r11,r11,16 | |
1346 | .endr | |
1347 | b 22b | |
b4072df4 | 1348 | |
697d3899 PM |
1349 | /* |
1350 | * Check whether an HDSI is an HPTE not found fault or something else. | |
1351 | * If it is an HPTE not found fault that is due to the guest accessing | |
1352 | * a page that they have mapped but which we have paged out, then | |
1353 | * we continue on with the guest exit path. In all other cases, | |
1354 | * reflect the HDSI to the guest as a DSI. | |
1355 | */ | |
1356 | kvmppc_hdsi: | |
1357 | mfspr r4, SPRN_HDAR | |
1358 | mfspr r6, SPRN_HDSISR | |
4cf302bc PM |
1359 | /* HPTE not found fault or protection fault? */ |
1360 | andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h | |
697d3899 PM |
1361 | beq 1f /* if not, send it to the guest */ |
1362 | andi. r0, r11, MSR_DR /* data relocation enabled? */ | |
1363 | beq 3f | |
1364 | clrrdi r0, r4, 28 | |
c75df6f9 | 1365 | PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */ |
697d3899 PM |
1366 | bne 1f /* if no SLB entry found */ |
1367 | 4: std r4, VCPU_FAULT_DAR(r9) | |
1368 | stw r6, VCPU_FAULT_DSISR(r9) | |
1369 | ||
1370 | /* Search the hash table. */ | |
1371 | mr r3, r9 /* vcpu pointer */ | |
342d3db7 | 1372 | li r7, 1 /* data fault */ |
697d3899 PM |
1373 | bl .kvmppc_hpte_hv_fault |
1374 | ld r9, HSTATE_KVM_VCPU(r13) | |
1375 | ld r10, VCPU_PC(r9) | |
1376 | ld r11, VCPU_MSR(r9) | |
1377 | li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE | |
1378 | cmpdi r3, 0 /* retry the instruction */ | |
1379 | beq 6f | |
1380 | cmpdi r3, -1 /* handle in kernel mode */ | |
b4072df4 | 1381 | beq guest_exit_cont |
697d3899 PM |
1382 | cmpdi r3, -2 /* MMIO emulation; need instr word */ |
1383 | beq 2f | |
1384 | ||
1385 | /* Synthesize a DSI for the guest */ | |
1386 | ld r4, VCPU_FAULT_DAR(r9) | |
1387 | mr r6, r3 | |
1388 | 1: mtspr SPRN_DAR, r4 | |
1389 | mtspr SPRN_DSISR, r6 | |
1390 | mtspr SPRN_SRR0, r10 | |
1391 | mtspr SPRN_SRR1, r11 | |
1392 | li r10, BOOK3S_INTERRUPT_DATA_STORAGE | |
1393 | li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
1394 | rotldi r11, r11, 63 | |
b4072df4 | 1395 | fast_interrupt_c_return: |
697d3899 PM |
1396 | 6: ld r7, VCPU_CTR(r9) |
1397 | lwz r8, VCPU_XER(r9) | |
1398 | mtctr r7 | |
1399 | mtxer r8 | |
1400 | mr r4, r9 | |
1401 | b fast_guest_return | |
1402 | ||
1403 | 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */ | |
1404 | ld r5, KVM_VRMA_SLB_V(r5) | |
1405 | b 4b | |
1406 | ||
1407 | /* If this is for emulated MMIO, load the instruction word */ | |
1408 | 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */ | |
1409 | ||
1410 | /* Set guest mode to 'jump over instruction' so if lwz faults | |
1411 | * we'll just continue at the next IP. */ | |
1412 | li r0, KVM_GUEST_MODE_SKIP | |
1413 | stb r0, HSTATE_IN_GUEST(r13) | |
1414 | ||
1415 | /* Do the access with MSR:DR enabled */ | |
1416 | mfmsr r3 | |
1417 | ori r4, r3, MSR_DR /* Enable paging for data */ | |
1418 | mtmsrd r4 | |
1419 | lwz r8, 0(r10) | |
1420 | mtmsrd r3 | |
1421 | ||
1422 | /* Store the result */ | |
1423 | stw r8, VCPU_LAST_INST(r9) | |
1424 | ||
1425 | /* Unset guest mode. */ | |
44a3add8 | 1426 | li r0, KVM_GUEST_MODE_HOST_HV |
697d3899 | 1427 | stb r0, HSTATE_IN_GUEST(r13) |
b4072df4 | 1428 | b guest_exit_cont |
de56a948 | 1429 | |
342d3db7 PM |
1430 | /* |
1431 | * Similarly for an HISI, reflect it to the guest as an ISI unless | |
1432 | * it is an HPTE not found fault for a page that we have paged out. | |
1433 | */ | |
1434 | kvmppc_hisi: | |
1435 | andis. r0, r11, SRR1_ISI_NOPT@h | |
1436 | beq 1f | |
1437 | andi. r0, r11, MSR_IR /* instruction relocation enabled? */ | |
1438 | beq 3f | |
1439 | clrrdi r0, r10, 28 | |
c75df6f9 | 1440 | PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */ |
342d3db7 PM |
1441 | bne 1f /* if no SLB entry found */ |
1442 | 4: | |
1443 | /* Search the hash table. */ | |
1444 | mr r3, r9 /* vcpu pointer */ | |
1445 | mr r4, r10 | |
1446 | mr r6, r11 | |
1447 | li r7, 0 /* instruction fault */ | |
1448 | bl .kvmppc_hpte_hv_fault | |
1449 | ld r9, HSTATE_KVM_VCPU(r13) | |
1450 | ld r10, VCPU_PC(r9) | |
1451 | ld r11, VCPU_MSR(r9) | |
1452 | li r12, BOOK3S_INTERRUPT_H_INST_STORAGE | |
1453 | cmpdi r3, 0 /* retry the instruction */ | |
b4072df4 | 1454 | beq fast_interrupt_c_return |
342d3db7 | 1455 | cmpdi r3, -1 /* handle in kernel mode */ |
b4072df4 | 1456 | beq guest_exit_cont |
342d3db7 PM |
1457 | |
1458 | /* Synthesize an ISI for the guest */ | |
1459 | mr r11, r3 | |
1460 | 1: mtspr SPRN_SRR0, r10 | |
1461 | mtspr SPRN_SRR1, r11 | |
1462 | li r10, BOOK3S_INTERRUPT_INST_STORAGE | |
1463 | li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
1464 | rotldi r11, r11, 63 | |
b4072df4 | 1465 | b fast_interrupt_c_return |
342d3db7 PM |
1466 | |
1467 | 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */ | |
1468 | ld r5, KVM_VRMA_SLB_V(r6) | |
1469 | b 4b | |
1470 | ||
a8606e20 PM |
1471 | /* |
1472 | * Try to handle an hcall in real mode. | |
1473 | * Returns to the guest if we handle it, or continues on up to | |
1474 | * the kernel if we can't (i.e. if we don't have a handler for | |
1475 | * it, or if the handler returns H_TOO_HARD). | |
1476 | */ | |
1477 | .globl hcall_try_real_mode | |
1478 | hcall_try_real_mode: | |
c75df6f9 | 1479 | ld r3,VCPU_GPR(R3)(r9) |
a8606e20 | 1480 | andi. r0,r11,MSR_PR |
27025a60 LPF |
1481 | /* sc 1 from userspace - reflect to guest syscall */ |
1482 | bne sc_1_fast_return | |
a8606e20 PM |
1483 | clrrdi r3,r3,2 |
1484 | cmpldi r3,hcall_real_table_end - hcall_real_table | |
b4072df4 | 1485 | bge guest_exit_cont |
a8606e20 | 1486 | LOAD_REG_ADDR(r4, hcall_real_table) |
4baa1d87 | 1487 | lwax r3,r3,r4 |
a8606e20 | 1488 | cmpwi r3,0 |
b4072df4 | 1489 | beq guest_exit_cont |
a8606e20 PM |
1490 | add r3,r3,r4 |
1491 | mtctr r3 | |
1492 | mr r3,r9 /* get vcpu pointer */ | |
c75df6f9 | 1493 | ld r4,VCPU_GPR(R4)(r9) |
a8606e20 PM |
1494 | bctrl |
1495 | cmpdi r3,H_TOO_HARD | |
1496 | beq hcall_real_fallback | |
1497 | ld r4,HSTATE_KVM_VCPU(r13) | |
c75df6f9 | 1498 | std r3,VCPU_GPR(R3)(r4) |
a8606e20 PM |
1499 | ld r10,VCPU_PC(r4) |
1500 | ld r11,VCPU_MSR(r4) | |
1501 | b fast_guest_return | |
1502 | ||
27025a60 LPF |
1503 | sc_1_fast_return: |
1504 | mtspr SPRN_SRR0,r10 | |
1505 | mtspr SPRN_SRR1,r11 | |
1506 | li r10, BOOK3S_INTERRUPT_SYSCALL | |
1507 | li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
1508 | rotldi r11, r11, 63 | |
1509 | mr r4,r9 | |
1510 | b fast_guest_return | |
1511 | ||
a8606e20 PM |
1512 | /* We've attempted a real mode hcall, but it's punted it back |
1513 | * to userspace. We need to restore some clobbered volatiles | |
1514 | * before resuming the pass-it-to-qemu path */ | |
1515 | hcall_real_fallback: | |
1516 | li r12,BOOK3S_INTERRUPT_SYSCALL | |
1517 | ld r9, HSTATE_KVM_VCPU(r13) | |
a8606e20 | 1518 | |
b4072df4 | 1519 | b guest_exit_cont |
a8606e20 PM |
1520 | |
1521 | .globl hcall_real_table | |
1522 | hcall_real_table: | |
1523 | .long 0 /* 0 - unused */ | |
1524 | .long .kvmppc_h_remove - hcall_real_table | |
1525 | .long .kvmppc_h_enter - hcall_real_table | |
1526 | .long .kvmppc_h_read - hcall_real_table | |
1527 | .long 0 /* 0x10 - H_CLEAR_MOD */ | |
1528 | .long 0 /* 0x14 - H_CLEAR_REF */ | |
1529 | .long .kvmppc_h_protect - hcall_real_table | |
1530 | .long 0 /* 0x1c - H_GET_TCE */ | |
54738c09 | 1531 | .long .kvmppc_h_put_tce - hcall_real_table |
a8606e20 PM |
1532 | .long 0 /* 0x24 - H_SET_SPRG0 */ |
1533 | .long .kvmppc_h_set_dabr - hcall_real_table | |
1534 | .long 0 /* 0x2c */ | |
1535 | .long 0 /* 0x30 */ | |
1536 | .long 0 /* 0x34 */ | |
1537 | .long 0 /* 0x38 */ | |
1538 | .long 0 /* 0x3c */ | |
1539 | .long 0 /* 0x40 */ | |
1540 | .long 0 /* 0x44 */ | |
1541 | .long 0 /* 0x48 */ | |
1542 | .long 0 /* 0x4c */ | |
1543 | .long 0 /* 0x50 */ | |
1544 | .long 0 /* 0x54 */ | |
1545 | .long 0 /* 0x58 */ | |
1546 | .long 0 /* 0x5c */ | |
1547 | .long 0 /* 0x60 */ | |
e7d26f28 BH |
1548 | #ifdef CONFIG_KVM_XICS |
1549 | .long .kvmppc_rm_h_eoi - hcall_real_table | |
1550 | .long .kvmppc_rm_h_cppr - hcall_real_table | |
1551 | .long .kvmppc_rm_h_ipi - hcall_real_table | |
1552 | .long 0 /* 0x70 - H_IPOLL */ | |
1553 | .long .kvmppc_rm_h_xirr - hcall_real_table | |
1554 | #else | |
1555 | .long 0 /* 0x64 - H_EOI */ | |
1556 | .long 0 /* 0x68 - H_CPPR */ | |
1557 | .long 0 /* 0x6c - H_IPI */ | |
1558 | .long 0 /* 0x70 - H_IPOLL */ | |
1559 | .long 0 /* 0x74 - H_XIRR */ | |
1560 | #endif | |
a8606e20 PM |
1561 | .long 0 /* 0x78 */ |
1562 | .long 0 /* 0x7c */ | |
1563 | .long 0 /* 0x80 */ | |
1564 | .long 0 /* 0x84 */ | |
1565 | .long 0 /* 0x88 */ | |
1566 | .long 0 /* 0x8c */ | |
1567 | .long 0 /* 0x90 */ | |
1568 | .long 0 /* 0x94 */ | |
1569 | .long 0 /* 0x98 */ | |
1570 | .long 0 /* 0x9c */ | |
1571 | .long 0 /* 0xa0 */ | |
1572 | .long 0 /* 0xa4 */ | |
1573 | .long 0 /* 0xa8 */ | |
1574 | .long 0 /* 0xac */ | |
1575 | .long 0 /* 0xb0 */ | |
1576 | .long 0 /* 0xb4 */ | |
1577 | .long 0 /* 0xb8 */ | |
1578 | .long 0 /* 0xbc */ | |
1579 | .long 0 /* 0xc0 */ | |
1580 | .long 0 /* 0xc4 */ | |
1581 | .long 0 /* 0xc8 */ | |
1582 | .long 0 /* 0xcc */ | |
1583 | .long 0 /* 0xd0 */ | |
1584 | .long 0 /* 0xd4 */ | |
1585 | .long 0 /* 0xd8 */ | |
1586 | .long 0 /* 0xdc */ | |
19ccb76a | 1587 | .long .kvmppc_h_cede - hcall_real_table |
a8606e20 PM |
1588 | .long 0 /* 0xe4 */ |
1589 | .long 0 /* 0xe8 */ | |
1590 | .long 0 /* 0xec */ | |
1591 | .long 0 /* 0xf0 */ | |
1592 | .long 0 /* 0xf4 */ | |
1593 | .long 0 /* 0xf8 */ | |
1594 | .long 0 /* 0xfc */ | |
1595 | .long 0 /* 0x100 */ | |
1596 | .long 0 /* 0x104 */ | |
1597 | .long 0 /* 0x108 */ | |
1598 | .long 0 /* 0x10c */ | |
1599 | .long 0 /* 0x110 */ | |
1600 | .long 0 /* 0x114 */ | |
1601 | .long 0 /* 0x118 */ | |
1602 | .long 0 /* 0x11c */ | |
1603 | .long 0 /* 0x120 */ | |
1604 | .long .kvmppc_h_bulk_remove - hcall_real_table | |
1605 | hcall_real_table_end: | |
1606 | ||
de56a948 PM |
1607 | ignore_hdec: |
1608 | mr r4,r9 | |
1609 | b fast_guest_return | |
1610 | ||
a8606e20 PM |
1611 | _GLOBAL(kvmppc_h_set_dabr) |
1612 | std r4,VCPU_DABR(r3) | |
8943633c PM |
1613 | /* Work around P7 bug where DABR can get corrupted on mtspr */ |
1614 | 1: mtspr SPRN_DABR,r4 | |
1615 | mfspr r5, SPRN_DABR | |
1616 | cmpd r4, r5 | |
1617 | bne 1b | |
1618 | isync | |
a8606e20 PM |
1619 | li r3,0 |
1620 | blr | |
1621 | ||
19ccb76a PM |
1622 | _GLOBAL(kvmppc_h_cede) |
1623 | ori r11,r11,MSR_EE | |
1624 | std r11,VCPU_MSR(r3) | |
1625 | li r0,1 | |
1626 | stb r0,VCPU_CEDED(r3) | |
1627 | sync /* order setting ceded vs. testing prodded */ | |
1628 | lbz r5,VCPU_PRODDED(r3) | |
1629 | cmpwi r5,0 | |
04f995a5 | 1630 | bne kvm_cede_prodded |
19ccb76a PM |
1631 | li r0,0 /* set trap to 0 to say hcall is handled */ |
1632 | stw r0,VCPU_TRAP(r3) | |
1633 | li r0,H_SUCCESS | |
c75df6f9 | 1634 | std r0,VCPU_GPR(R3)(r3) |
19ccb76a | 1635 | BEGIN_FTR_SECTION |
04f995a5 | 1636 | b kvm_cede_exit /* just send it up to host on 970 */ |
19ccb76a PM |
1637 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206) |
1638 | ||
1639 | /* | |
1640 | * Set our bit in the bitmask of napping threads unless all the | |
1641 | * other threads are already napping, in which case we send this | |
1642 | * up to the host. | |
1643 | */ | |
1644 | ld r5,HSTATE_KVM_VCORE(r13) | |
1645 | lwz r6,VCPU_PTID(r3) | |
1646 | lwz r8,VCORE_ENTRY_EXIT(r5) | |
1647 | clrldi r8,r8,56 | |
1648 | li r0,1 | |
1649 | sld r0,r0,r6 | |
1650 | addi r6,r5,VCORE_NAPPING_THREADS | |
1651 | 31: lwarx r4,0,r6 | |
1652 | or r4,r4,r0 | |
c75df6f9 | 1653 | PPC_POPCNTW(R7,R4) |
19ccb76a | 1654 | cmpw r7,r8 |
04f995a5 | 1655 | bge kvm_cede_exit |
19ccb76a PM |
1656 | stwcx. r4,0,r6 |
1657 | bne 31b | |
1658 | li r0,1 | |
1659 | stb r0,HSTATE_NAPPING(r13) | |
1660 | /* order napping_threads update vs testing entry_exit_count */ | |
1661 | lwsync | |
1662 | mr r4,r3 | |
1663 | lwz r7,VCORE_ENTRY_EXIT(r5) | |
1664 | cmpwi r7,0x100 | |
1665 | bge 33f /* another thread already exiting */ | |
1666 | ||
1667 | /* | |
1668 | * Although not specifically required by the architecture, POWER7 | |
1669 | * preserves the following registers in nap mode, even if an SMT mode | |
1670 | * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3, | |
1671 | * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR. | |
1672 | */ | |
1673 | /* Save non-volatile GPRs */ | |
c75df6f9 MN |
1674 | std r14, VCPU_GPR(R14)(r3) |
1675 | std r15, VCPU_GPR(R15)(r3) | |
1676 | std r16, VCPU_GPR(R16)(r3) | |
1677 | std r17, VCPU_GPR(R17)(r3) | |
1678 | std r18, VCPU_GPR(R18)(r3) | |
1679 | std r19, VCPU_GPR(R19)(r3) | |
1680 | std r20, VCPU_GPR(R20)(r3) | |
1681 | std r21, VCPU_GPR(R21)(r3) | |
1682 | std r22, VCPU_GPR(R22)(r3) | |
1683 | std r23, VCPU_GPR(R23)(r3) | |
1684 | std r24, VCPU_GPR(R24)(r3) | |
1685 | std r25, VCPU_GPR(R25)(r3) | |
1686 | std r26, VCPU_GPR(R26)(r3) | |
1687 | std r27, VCPU_GPR(R27)(r3) | |
1688 | std r28, VCPU_GPR(R28)(r3) | |
1689 | std r29, VCPU_GPR(R29)(r3) | |
1690 | std r30, VCPU_GPR(R30)(r3) | |
1691 | std r31, VCPU_GPR(R31)(r3) | |
19ccb76a PM |
1692 | |
1693 | /* save FP state */ | |
1694 | bl .kvmppc_save_fp | |
1695 | ||
1696 | /* | |
1697 | * Take a nap until a decrementer or external interrupt occurs, | |
1698 | * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR | |
1699 | */ | |
f0888f70 PM |
1700 | li r0,1 |
1701 | stb r0,HSTATE_HWTHREAD_REQ(r13) | |
19ccb76a PM |
1702 | mfspr r5,SPRN_LPCR |
1703 | ori r5,r5,LPCR_PECE0 | LPCR_PECE1 | |
1704 | mtspr SPRN_LPCR,r5 | |
1705 | isync | |
1706 | li r0, 0 | |
1707 | std r0, HSTATE_SCRATCH0(r13) | |
1708 | ptesync | |
1709 | ld r0, HSTATE_SCRATCH0(r13) | |
1710 | 1: cmpd r0, r0 | |
1711 | bne 1b | |
1712 | nap | |
1713 | b . | |
1714 | ||
1715 | kvm_end_cede: | |
4619ac88 PM |
1716 | /* get vcpu pointer */ |
1717 | ld r4, HSTATE_KVM_VCPU(r13) | |
1718 | ||
19ccb76a PM |
1719 | /* Woken by external or decrementer interrupt */ |
1720 | ld r1, HSTATE_HOST_R1(r13) | |
19ccb76a | 1721 | |
19ccb76a PM |
1722 | /* load up FP state */ |
1723 | bl kvmppc_load_fp | |
1724 | ||
1725 | /* Load NV GPRS */ | |
c75df6f9 MN |
1726 | ld r14, VCPU_GPR(R14)(r4) |
1727 | ld r15, VCPU_GPR(R15)(r4) | |
1728 | ld r16, VCPU_GPR(R16)(r4) | |
1729 | ld r17, VCPU_GPR(R17)(r4) | |
1730 | ld r18, VCPU_GPR(R18)(r4) | |
1731 | ld r19, VCPU_GPR(R19)(r4) | |
1732 | ld r20, VCPU_GPR(R20)(r4) | |
1733 | ld r21, VCPU_GPR(R21)(r4) | |
1734 | ld r22, VCPU_GPR(R22)(r4) | |
1735 | ld r23, VCPU_GPR(R23)(r4) | |
1736 | ld r24, VCPU_GPR(R24)(r4) | |
1737 | ld r25, VCPU_GPR(R25)(r4) | |
1738 | ld r26, VCPU_GPR(R26)(r4) | |
1739 | ld r27, VCPU_GPR(R27)(r4) | |
1740 | ld r28, VCPU_GPR(R28)(r4) | |
1741 | ld r29, VCPU_GPR(R29)(r4) | |
1742 | ld r30, VCPU_GPR(R30)(r4) | |
1743 | ld r31, VCPU_GPR(R31)(r4) | |
19ccb76a PM |
1744 | |
1745 | /* clear our bit in vcore->napping_threads */ | |
1746 | 33: ld r5,HSTATE_KVM_VCORE(r13) | |
1747 | lwz r3,VCPU_PTID(r4) | |
1748 | li r0,1 | |
1749 | sld r0,r0,r3 | |
1750 | addi r6,r5,VCORE_NAPPING_THREADS | |
1751 | 32: lwarx r7,0,r6 | |
1752 | andc r7,r7,r0 | |
1753 | stwcx. r7,0,r6 | |
1754 | bne 32b | |
1755 | li r0,0 | |
1756 | stb r0,HSTATE_NAPPING(r13) | |
1757 | ||
4619ac88 PM |
1758 | /* Check the wake reason in SRR1 to see why we got here */ |
1759 | mfspr r3, SPRN_SRR1 | |
1760 | rlwinm r3, r3, 44-31, 0x7 /* extract wake reason field */ | |
1761 | cmpwi r3, 4 /* was it an external interrupt? */ | |
1762 | li r12, BOOK3S_INTERRUPT_EXTERNAL | |
1763 | mr r9, r4 | |
1764 | ld r10, VCPU_PC(r9) | |
1765 | ld r11, VCPU_MSR(r9) | |
1766 | beq do_ext_interrupt /* if so */ | |
1767 | ||
19ccb76a PM |
1768 | /* see if any other thread is already exiting */ |
1769 | lwz r0,VCORE_ENTRY_EXIT(r5) | |
1770 | cmpwi r0,0x100 | |
1771 | blt kvmppc_cede_reentry /* if not go back to guest */ | |
1772 | ||
1773 | /* some threads are exiting, so go to the guest exit path */ | |
1774 | b hcall_real_fallback | |
1775 | ||
1776 | /* cede when already previously prodded case */ | |
04f995a5 PM |
1777 | kvm_cede_prodded: |
1778 | li r0,0 | |
19ccb76a PM |
1779 | stb r0,VCPU_PRODDED(r3) |
1780 | sync /* order testing prodded vs. clearing ceded */ | |
1781 | stb r0,VCPU_CEDED(r3) | |
1782 | li r3,H_SUCCESS | |
1783 | blr | |
1784 | ||
1785 | /* we've ceded but we want to give control to the host */ | |
04f995a5 | 1786 | kvm_cede_exit: |
4619ac88 | 1787 | b hcall_real_fallback |
19ccb76a | 1788 | |
b4072df4 PM |
1789 | /* Try to handle a machine check in real mode */ |
1790 | machine_check_realmode: | |
1791 | mr r3, r9 /* get vcpu pointer */ | |
1792 | bl .kvmppc_realmode_machine_check | |
1793 | nop | |
1794 | cmpdi r3, 0 /* continue exiting from guest? */ | |
1795 | ld r9, HSTATE_KVM_VCPU(r13) | |
1796 | li r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
1797 | beq mc_cont | |
1798 | /* If not, deliver a machine check. SRR0/1 are already set */ | |
1799 | li r10, BOOK3S_INTERRUPT_MACHINE_CHECK | |
1800 | li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
1801 | rotldi r11, r11, 63 | |
1802 | b fast_interrupt_c_return | |
1803 | ||
c934243c PM |
1804 | /* |
1805 | * Determine what sort of external interrupt is pending (if any). | |
1806 | * Returns: | |
1807 | * 0 if no interrupt is pending | |
1808 | * 1 if an interrupt is pending that needs to be handled by the host | |
1809 | * -1 if there was a guest wakeup IPI (which has now been cleared) | |
1810 | */ | |
1811 | kvmppc_read_intr: | |
1812 | /* see if a host IPI is pending */ | |
1813 | li r3, 1 | |
1814 | lbz r0, HSTATE_HOST_IPI(r13) | |
1815 | cmpwi r0, 0 | |
1816 | bne 1f | |
371fefd6 | 1817 | |
c934243c PM |
1818 | /* Now read the interrupt from the ICP */ |
1819 | ld r6, HSTATE_XICS_PHYS(r13) | |
19ccb76a | 1820 | li r7, XICS_XIRR |
c934243c PM |
1821 | cmpdi r6, 0 |
1822 | beq- 1f | |
1823 | lwzcix r0, r6, r7 | |
1824 | rlwinm. r3, r0, 0, 0xffffff | |
19ccb76a | 1825 | sync |
c934243c | 1826 | beq 1f /* if nothing pending in the ICP */ |
371fefd6 | 1827 | |
c934243c PM |
1828 | /* We found something in the ICP... |
1829 | * | |
1830 | * If it's not an IPI, stash it in the PACA and return to | |
1831 | * the host, we don't (yet) handle directing real external | |
1832 | * interrupts directly to the guest | |
1833 | */ | |
1834 | cmpwi r3, XICS_IPI /* if there is, is it an IPI? */ | |
1835 | li r3, 1 | |
1836 | bne 42f | |
371fefd6 | 1837 | |
c934243c PM |
1838 | /* It's an IPI, clear the MFRR and EOI it */ |
1839 | li r3, 0xff | |
1840 | li r8, XICS_MFRR | |
1841 | stbcix r3, r6, r8 /* clear the IPI */ | |
1842 | stwcix r0, r6, r7 /* EOI it */ | |
1843 | sync | |
f0888f70 | 1844 | |
c934243c PM |
1845 | /* We need to re-check host IPI now in case it got set in the |
1846 | * meantime. If it's clear, we bounce the interrupt to the | |
1847 | * guest | |
1848 | */ | |
1849 | lbz r0, HSTATE_HOST_IPI(r13) | |
1850 | cmpwi r0, 0 | |
1851 | bne- 43f | |
1852 | ||
1853 | /* OK, it's an IPI for us */ | |
1854 | li r3, -1 | |
1855 | 1: blr | |
1856 | ||
1857 | 42: /* It's not an IPI and it's for the host, stash it in the PACA | |
1858 | * before exit, it will be picked up by the host ICP driver | |
1859 | */ | |
1860 | stw r0, HSTATE_SAVED_XIRR(r13) | |
1861 | b 1b | |
1862 | ||
1863 | 43: /* We raced with the host, we need to resend that IPI, bummer */ | |
1864 | li r0, IPI_PRIORITY | |
1865 | stbcix r0, r6, r8 /* set the IPI */ | |
1866 | sync | |
1867 | b 1b | |
371fefd6 | 1868 | |
de56a948 PM |
1869 | /* |
1870 | * Save away FP, VMX and VSX registers. | |
1871 | * r3 = vcpu pointer | |
a8606e20 | 1872 | */ |
de56a948 | 1873 | _GLOBAL(kvmppc_save_fp) |
8943633c PM |
1874 | mfmsr r5 |
1875 | ori r8,r5,MSR_FP | |
de56a948 PM |
1876 | #ifdef CONFIG_ALTIVEC |
1877 | BEGIN_FTR_SECTION | |
1878 | oris r8,r8,MSR_VEC@h | |
1879 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1880 | #endif | |
1881 | #ifdef CONFIG_VSX | |
1882 | BEGIN_FTR_SECTION | |
1883 | oris r8,r8,MSR_VSX@h | |
1884 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1885 | #endif | |
1886 | mtmsrd r8 | |
1887 | isync | |
1888 | #ifdef CONFIG_VSX | |
1889 | BEGIN_FTR_SECTION | |
1890 | reg = 0 | |
1891 | .rept 32 | |
efff1912 | 1892 | li r6,reg*16+VCPU_FPRS |
c75df6f9 | 1893 | STXVD2X(reg,R6,R3) |
de56a948 PM |
1894 | reg = reg + 1 |
1895 | .endr | |
1896 | FTR_SECTION_ELSE | |
1897 | #endif | |
1898 | reg = 0 | |
1899 | .rept 32 | |
1900 | stfd reg,reg*8+VCPU_FPRS(r3) | |
1901 | reg = reg + 1 | |
1902 | .endr | |
1903 | #ifdef CONFIG_VSX | |
1904 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX) | |
1905 | #endif | |
1906 | mffs fr0 | |
1907 | stfd fr0,VCPU_FPSCR(r3) | |
1908 | ||
1909 | #ifdef CONFIG_ALTIVEC | |
1910 | BEGIN_FTR_SECTION | |
1911 | reg = 0 | |
1912 | .rept 32 | |
1913 | li r6,reg*16+VCPU_VRS | |
1914 | stvx reg,r6,r3 | |
1915 | reg = reg + 1 | |
1916 | .endr | |
1917 | mfvscr vr0 | |
1918 | li r6,VCPU_VSCR | |
1919 | stvx vr0,r6,r3 | |
1920 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1921 | #endif | |
1922 | mfspr r6,SPRN_VRSAVE | |
1923 | stw r6,VCPU_VRSAVE(r3) | |
8943633c | 1924 | mtmsrd r5 |
de56a948 PM |
1925 | isync |
1926 | blr | |
1927 | ||
1928 | /* | |
1929 | * Load up FP, VMX and VSX registers | |
1930 | * r4 = vcpu pointer | |
1931 | */ | |
1932 | .globl kvmppc_load_fp | |
1933 | kvmppc_load_fp: | |
1934 | mfmsr r9 | |
1935 | ori r8,r9,MSR_FP | |
1936 | #ifdef CONFIG_ALTIVEC | |
1937 | BEGIN_FTR_SECTION | |
1938 | oris r8,r8,MSR_VEC@h | |
1939 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1940 | #endif | |
1941 | #ifdef CONFIG_VSX | |
1942 | BEGIN_FTR_SECTION | |
1943 | oris r8,r8,MSR_VSX@h | |
1944 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1945 | #endif | |
1946 | mtmsrd r8 | |
1947 | isync | |
1948 | lfd fr0,VCPU_FPSCR(r4) | |
1949 | MTFSF_L(fr0) | |
1950 | #ifdef CONFIG_VSX | |
1951 | BEGIN_FTR_SECTION | |
1952 | reg = 0 | |
1953 | .rept 32 | |
efff1912 | 1954 | li r7,reg*16+VCPU_FPRS |
c75df6f9 | 1955 | LXVD2X(reg,R7,R4) |
de56a948 PM |
1956 | reg = reg + 1 |
1957 | .endr | |
1958 | FTR_SECTION_ELSE | |
1959 | #endif | |
1960 | reg = 0 | |
1961 | .rept 32 | |
1962 | lfd reg,reg*8+VCPU_FPRS(r4) | |
1963 | reg = reg + 1 | |
1964 | .endr | |
1965 | #ifdef CONFIG_VSX | |
1966 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX) | |
1967 | #endif | |
1968 | ||
1969 | #ifdef CONFIG_ALTIVEC | |
1970 | BEGIN_FTR_SECTION | |
1971 | li r7,VCPU_VSCR | |
1972 | lvx vr0,r7,r4 | |
1973 | mtvscr vr0 | |
1974 | reg = 0 | |
1975 | .rept 32 | |
1976 | li r7,reg*16+VCPU_VRS | |
1977 | lvx reg,r7,r4 | |
1978 | reg = reg + 1 | |
1979 | .endr | |
1980 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1981 | #endif | |
1982 | lwz r7,VCPU_VRSAVE(r4) | |
1983 | mtspr SPRN_VRSAVE,r7 | |
1984 | blr | |
44a3add8 PM |
1985 | |
1986 | /* | |
1987 | * We come here if we get any exception or interrupt while we are | |
1988 | * executing host real mode code while in guest MMU context. | |
1989 | * For now just spin, but we should do something better. | |
1990 | */ | |
1991 | kvmppc_bad_host_intr: | |
1992 | b . |