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de56a948 PM |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> | |
12 | * | |
13 | * Derived from book3s_rmhandlers.S and other files, which are: | |
14 | * | |
15 | * Copyright SUSE Linux Products GmbH 2009 | |
16 | * | |
17 | * Authors: Alexander Graf <agraf@suse.de> | |
18 | */ | |
19 | ||
20 | #include <asm/ppc_asm.h> | |
21 | #include <asm/kvm_asm.h> | |
22 | #include <asm/reg.h> | |
177339d7 | 23 | #include <asm/mmu.h> |
de56a948 | 24 | #include <asm/page.h> |
177339d7 PM |
25 | #include <asm/ptrace.h> |
26 | #include <asm/hvcall.h> | |
de56a948 PM |
27 | #include <asm/asm-offsets.h> |
28 | #include <asm/exception-64s.h> | |
f0888f70 | 29 | #include <asm/kvm_book3s_asm.h> |
b4072df4 | 30 | #include <asm/mmu-hash64.h> |
e4e38121 MN |
31 | #include <asm/tm.h> |
32 | ||
33 | #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM) | |
de56a948 | 34 | |
e0b7ec05 PM |
35 | /* Values in HSTATE_NAPPING(r13) */ |
36 | #define NAPPING_CEDE 1 | |
37 | #define NAPPING_NOVCPU 2 | |
38 | ||
de56a948 | 39 | /* |
19ccb76a | 40 | * Call kvmppc_hv_entry in real mode. |
de56a948 PM |
41 | * Must be called with interrupts hard-disabled. |
42 | * | |
43 | * Input Registers: | |
44 | * | |
45 | * LR = return address to continue at after eventually re-enabling MMU | |
46 | */ | |
6ed179b6 | 47 | _GLOBAL_TOC(kvmppc_hv_entry_trampoline) |
218309b7 PM |
48 | mflr r0 |
49 | std r0, PPC_LR_STKOFF(r1) | |
50 | stdu r1, -112(r1) | |
de56a948 | 51 | mfmsr r10 |
218309b7 | 52 | LOAD_REG_ADDR(r5, kvmppc_call_hv_entry) |
de56a948 PM |
53 | li r0,MSR_RI |
54 | andc r0,r10,r0 | |
55 | li r6,MSR_IR | MSR_DR | |
56 | andc r6,r10,r6 | |
57 | mtmsrd r0,1 /* clear RI in MSR */ | |
58 | mtsrr0 r5 | |
59 | mtsrr1 r6 | |
60 | RFI | |
61 | ||
218309b7 | 62 | kvmppc_call_hv_entry: |
e0b7ec05 | 63 | ld r4, HSTATE_KVM_VCPU(r13) |
218309b7 PM |
64 | bl kvmppc_hv_entry |
65 | ||
66 | /* Back from guest - restore host state and return to caller */ | |
67 | ||
eee7ff9d | 68 | BEGIN_FTR_SECTION |
218309b7 PM |
69 | /* Restore host DABR and DABRX */ |
70 | ld r5,HSTATE_DABR(r13) | |
71 | li r6,7 | |
72 | mtspr SPRN_DABR,r5 | |
73 | mtspr SPRN_DABRX,r6 | |
eee7ff9d | 74 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) |
218309b7 PM |
75 | |
76 | /* Restore SPRG3 */ | |
9d378dfa SW |
77 | ld r3,PACA_SPRG_VDSO(r13) |
78 | mtspr SPRN_SPRG_VDSO_WRITE,r3 | |
218309b7 | 79 | |
218309b7 PM |
80 | /* Reload the host's PMU registers */ |
81 | ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */ | |
82 | lbz r4, LPPACA_PMCINUSE(r3) | |
83 | cmpwi r4, 0 | |
84 | beq 23f /* skip if not */ | |
9bc01a9b | 85 | BEGIN_FTR_SECTION |
9a4fc4ea | 86 | ld r3, HSTATE_MMCR0(r13) |
9bc01a9b PM |
87 | andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO |
88 | cmpwi r4, MMCR0_PMAO | |
89 | beql kvmppc_fix_pmao | |
90 | END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG) | |
9a4fc4ea ME |
91 | lwz r3, HSTATE_PMC1(r13) |
92 | lwz r4, HSTATE_PMC2(r13) | |
93 | lwz r5, HSTATE_PMC3(r13) | |
94 | lwz r6, HSTATE_PMC4(r13) | |
95 | lwz r8, HSTATE_PMC5(r13) | |
96 | lwz r9, HSTATE_PMC6(r13) | |
218309b7 PM |
97 | mtspr SPRN_PMC1, r3 |
98 | mtspr SPRN_PMC2, r4 | |
99 | mtspr SPRN_PMC3, r5 | |
100 | mtspr SPRN_PMC4, r6 | |
101 | mtspr SPRN_PMC5, r8 | |
102 | mtspr SPRN_PMC6, r9 | |
9a4fc4ea ME |
103 | ld r3, HSTATE_MMCR0(r13) |
104 | ld r4, HSTATE_MMCR1(r13) | |
105 | ld r5, HSTATE_MMCRA(r13) | |
106 | ld r6, HSTATE_SIAR(r13) | |
107 | ld r7, HSTATE_SDAR(r13) | |
218309b7 PM |
108 | mtspr SPRN_MMCR1, r4 |
109 | mtspr SPRN_MMCRA, r5 | |
72cde5a8 PM |
110 | mtspr SPRN_SIAR, r6 |
111 | mtspr SPRN_SDAR, r7 | |
112 | BEGIN_FTR_SECTION | |
9a4fc4ea ME |
113 | ld r8, HSTATE_MMCR2(r13) |
114 | ld r9, HSTATE_SIER(r13) | |
72cde5a8 PM |
115 | mtspr SPRN_MMCR2, r8 |
116 | mtspr SPRN_SIER, r9 | |
117 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
218309b7 PM |
118 | mtspr SPRN_MMCR0, r3 |
119 | isync | |
120 | 23: | |
121 | ||
e0b7ec05 PM |
122 | /* |
123 | * Reload DEC. HDEC interrupts were disabled when | |
124 | * we reloaded the host's LPCR value. | |
125 | */ | |
126 | ld r3, HSTATE_DECEXP(r13) | |
127 | mftb r4 | |
128 | subf r4, r4, r3 | |
129 | mtspr SPRN_DEC, r4 | |
130 | ||
218309b7 PM |
131 | /* |
132 | * For external and machine check interrupts, we need | |
133 | * to call the Linux handler to process the interrupt. | |
134 | * We do that by jumping to absolute address 0x500 for | |
135 | * external interrupts, or the machine_check_fwnmi label | |
136 | * for machine checks (since firmware might have patched | |
137 | * the vector area at 0x200). The [h]rfid at the end of the | |
138 | * handler will return to the book3s_hv_interrupts.S code. | |
139 | * For other interrupts we do the rfid to get back | |
140 | * to the book3s_hv_interrupts.S code here. | |
141 | */ | |
142 | ld r8, 112+PPC_LR_STKOFF(r1) | |
143 | addi r1, r1, 112 | |
144 | ld r7, HSTATE_HOST_MSR(r13) | |
145 | ||
146 | cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
147 | cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL | |
218309b7 | 148 | beq 11f |
0869b6fd MS |
149 | cmpwi cr2, r12, BOOK3S_INTERRUPT_HMI |
150 | beq cr2, 14f /* HMI check */ | |
218309b7 PM |
151 | |
152 | /* RFI into the highmem handler, or branch to interrupt handler */ | |
153 | mfmsr r6 | |
154 | li r0, MSR_RI | |
155 | andc r6, r6, r0 | |
156 | mtmsrd r6, 1 /* Clear RI in MSR */ | |
157 | mtsrr0 r8 | |
158 | mtsrr1 r7 | |
218309b7 PM |
159 | beq cr1, 13f /* machine check */ |
160 | RFI | |
161 | ||
162 | /* On POWER7, we have external interrupts set to use HSRR0/1 */ | |
163 | 11: mtspr SPRN_HSRR0, r8 | |
164 | mtspr SPRN_HSRR1, r7 | |
165 | ba 0x500 | |
166 | ||
167 | 13: b machine_check_fwnmi | |
168 | ||
0869b6fd MS |
169 | 14: mtspr SPRN_HSRR0, r8 |
170 | mtspr SPRN_HSRR1, r7 | |
171 | b hmi_exception_after_realmode | |
172 | ||
e0b7ec05 PM |
173 | kvmppc_primary_no_guest: |
174 | /* We handle this much like a ceded vcpu */ | |
fd6d53b1 PM |
175 | /* put the HDEC into the DEC, since HDEC interrupts don't wake us */ |
176 | mfspr r3, SPRN_HDEC | |
177 | mtspr SPRN_DEC, r3 | |
6af27c84 PM |
178 | /* |
179 | * Make sure the primary has finished the MMU switch. | |
180 | * We should never get here on a secondary thread, but | |
181 | * check it for robustness' sake. | |
182 | */ | |
183 | ld r5, HSTATE_KVM_VCORE(r13) | |
184 | 65: lbz r0, VCORE_IN_GUEST(r5) | |
185 | cmpwi r0, 0 | |
186 | beq 65b | |
187 | /* Set LPCR. */ | |
188 | ld r8,VCORE_LPCR(r5) | |
189 | mtspr SPRN_LPCR,r8 | |
190 | isync | |
e0b7ec05 PM |
191 | /* set our bit in napping_threads */ |
192 | ld r5, HSTATE_KVM_VCORE(r13) | |
193 | lbz r7, HSTATE_PTID(r13) | |
194 | li r0, 1 | |
195 | sld r0, r0, r7 | |
196 | addi r6, r5, VCORE_NAPPING_THREADS | |
197 | 1: lwarx r3, 0, r6 | |
198 | or r3, r3, r0 | |
199 | stwcx. r3, 0, r6 | |
200 | bne 1b | |
7d6c40da | 201 | /* order napping_threads update vs testing entry_exit_map */ |
e0b7ec05 PM |
202 | isync |
203 | li r12, 0 | |
204 | lwz r7, VCORE_ENTRY_EXIT(r5) | |
205 | cmpwi r7, 0x100 | |
206 | bge kvm_novcpu_exit /* another thread already exiting */ | |
207 | li r3, NAPPING_NOVCPU | |
208 | stb r3, HSTATE_NAPPING(r13) | |
e0b7ec05 | 209 | |
ccc07772 | 210 | li r3, 0 /* Don't wake on privileged (OS) doorbell */ |
e0b7ec05 PM |
211 | b kvm_do_nap |
212 | ||
213 | kvm_novcpu_wakeup: | |
214 | ld r1, HSTATE_HOST_R1(r13) | |
215 | ld r5, HSTATE_KVM_VCORE(r13) | |
216 | li r0, 0 | |
217 | stb r0, HSTATE_NAPPING(r13) | |
218 | stb r0, HSTATE_HWTHREAD_REQ(r13) | |
219 | ||
e3bbbbfa PM |
220 | /* check the wake reason */ |
221 | bl kvmppc_check_wake_reason | |
6af27c84 | 222 | |
e0b7ec05 | 223 | /* see if any other thread is already exiting */ |
e0b7ec05 PM |
224 | lwz r0, VCORE_ENTRY_EXIT(r5) |
225 | cmpwi r0, 0x100 | |
226 | bge kvm_novcpu_exit | |
227 | ||
228 | /* clear our bit in napping_threads */ | |
229 | lbz r7, HSTATE_PTID(r13) | |
230 | li r0, 1 | |
231 | sld r0, r0, r7 | |
232 | addi r6, r5, VCORE_NAPPING_THREADS | |
e3bbbbfa PM |
233 | 4: lwarx r7, 0, r6 |
234 | andc r7, r7, r0 | |
235 | stwcx. r7, 0, r6 | |
e0b7ec05 PM |
236 | bne 4b |
237 | ||
e3bbbbfa | 238 | /* See if the wake reason means we need to exit */ |
e0b7ec05 PM |
239 | cmpdi r3, 0 |
240 | bge kvm_novcpu_exit | |
e0b7ec05 | 241 | |
fd6d53b1 PM |
242 | /* See if our timeslice has expired (HDEC is negative) */ |
243 | mfspr r0, SPRN_HDEC | |
244 | li r12, BOOK3S_INTERRUPT_HV_DECREMENTER | |
245 | cmpwi r0, 0 | |
246 | blt kvm_novcpu_exit | |
247 | ||
e0b7ec05 PM |
248 | /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */ |
249 | ld r4, HSTATE_KVM_VCPU(r13) | |
250 | cmpdi r4, 0 | |
b6c295df PM |
251 | beq kvmppc_primary_no_guest |
252 | ||
253 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING | |
254 | addi r3, r4, VCPU_TB_RMENTRY | |
255 | bl kvmhv_start_timing | |
256 | #endif | |
257 | b kvmppc_got_guest | |
e0b7ec05 PM |
258 | |
259 | kvm_novcpu_exit: | |
6af27c84 PM |
260 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
261 | ld r4, HSTATE_KVM_VCPU(r13) | |
262 | cmpdi r4, 0 | |
263 | beq 13f | |
264 | addi r3, r4, VCPU_TB_RMEXIT | |
265 | bl kvmhv_accumulate_time | |
266 | #endif | |
267 | 13: bl kvmhv_commence_exit | |
268 | b kvmhv_switch_to_host | |
e0b7ec05 | 269 | |
371fefd6 | 270 | /* |
e0b7ec05 | 271 | * We come in here when wakened from nap mode. |
371fefd6 PM |
272 | * Relocation is off and most register values are lost. |
273 | * r13 points to the PACA. | |
274 | */ | |
275 | .globl kvm_start_guest | |
276 | kvm_start_guest: | |
fd17dc7b PM |
277 | |
278 | /* Set runlatch bit the minute you wake up from nap */ | |
1f09c3ed PM |
279 | mfspr r0, SPRN_CTRLF |
280 | ori r0, r0, 1 | |
281 | mtspr SPRN_CTRLT, r0 | |
fd17dc7b | 282 | |
19ccb76a PM |
283 | ld r2,PACATOC(r13) |
284 | ||
f0888f70 PM |
285 | li r0,KVM_HWTHREAD_IN_KVM |
286 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
371fefd6 | 287 | |
f0888f70 PM |
288 | /* NV GPR values from power7_idle() will no longer be valid */ |
289 | li r0,1 | |
290 | stb r0,PACA_NAPSTATELOST(r13) | |
371fefd6 | 291 | |
4619ac88 PM |
292 | /* were we napping due to cede? */ |
293 | lbz r0,HSTATE_NAPPING(r13) | |
e0b7ec05 PM |
294 | cmpwi r0,NAPPING_CEDE |
295 | beq kvm_end_cede | |
296 | cmpwi r0,NAPPING_NOVCPU | |
297 | beq kvm_novcpu_wakeup | |
298 | ||
299 | ld r1,PACAEMERGSP(r13) | |
300 | subi r1,r1,STACK_FRAME_OVERHEAD | |
4619ac88 PM |
301 | |
302 | /* | |
303 | * We weren't napping due to cede, so this must be a secondary | |
304 | * thread being woken up to run a guest, or being woken up due | |
305 | * to a stray IPI. (Or due to some machine check or hypervisor | |
306 | * maintenance interrupt while the core is in KVM.) | |
307 | */ | |
f0888f70 PM |
308 | |
309 | /* Check the wake reason in SRR1 to see why we got here */ | |
e3bbbbfa PM |
310 | bl kvmppc_check_wake_reason |
311 | cmpdi r3, 0 | |
312 | bge kvm_no_guest | |
371fefd6 | 313 | |
4619ac88 | 314 | /* get vcpu pointer, NULL if we have no vcpu to run */ |
7b444c67 PM |
315 | ld r4,HSTATE_KVM_VCPU(r13) |
316 | cmpdi r4,0 | |
f0888f70 | 317 | /* if we have no vcpu to run, go back to sleep */ |
7b444c67 | 318 | beq kvm_no_guest |
f0888f70 | 319 | |
56548fc0 PM |
320 | kvm_secondary_got_guest: |
321 | ||
e0b7ec05 | 322 | /* Set HSTATE_DSCR(r13) to something sensible */ |
1739ea9e | 323 | ld r6, PACA_DSCR(r13) |
e0b7ec05 | 324 | std r6, HSTATE_DSCR(r13) |
2fde6d20 | 325 | |
5d5b99cd PM |
326 | /* Order load of vcore, ptid etc. after load of vcpu */ |
327 | lwsync | |
e0b7ec05 | 328 | bl kvmppc_hv_entry |
218309b7 PM |
329 | |
330 | /* Back from the guest, go back to nap */ | |
331 | /* Clear our vcpu pointer so we don't come back in early */ | |
332 | li r0, 0 | |
f019b7ad | 333 | /* |
5d5b99cd PM |
334 | * Once we clear HSTATE_KVM_VCPU(r13), the code in |
335 | * kvmppc_run_core() is going to assume that all our vcpu | |
336 | * state is visible in memory. This lwsync makes sure | |
337 | * that that is true. | |
f019b7ad | 338 | */ |
218309b7 | 339 | lwsync |
5d5b99cd | 340 | std r0, HSTATE_KVM_VCPU(r13) |
218309b7 | 341 | |
56548fc0 PM |
342 | /* |
343 | * At this point we have finished executing in the guest. | |
344 | * We need to wait for hwthread_req to become zero, since | |
345 | * we may not turn on the MMU while hwthread_req is non-zero. | |
346 | * While waiting we also need to check if we get given a vcpu to run. | |
347 | */ | |
218309b7 | 348 | kvm_no_guest: |
56548fc0 PM |
349 | lbz r3, HSTATE_HWTHREAD_REQ(r13) |
350 | cmpwi r3, 0 | |
351 | bne 53f | |
352 | HMT_MEDIUM | |
353 | li r0, KVM_HWTHREAD_IN_KERNEL | |
218309b7 | 354 | stb r0, HSTATE_HWTHREAD_STATE(r13) |
56548fc0 PM |
355 | /* need to recheck hwthread_req after a barrier, to avoid race */ |
356 | sync | |
357 | lbz r3, HSTATE_HWTHREAD_REQ(r13) | |
358 | cmpwi r3, 0 | |
359 | bne 54f | |
360 | /* | |
361 | * We jump to power7_wakeup_loss, which will return to the caller | |
362 | * of power7_nap in the powernv cpu offline loop. The value we | |
363 | * put in r3 becomes the return value for power7_nap. | |
364 | */ | |
218309b7 PM |
365 | li r3, LPCR_PECE0 |
366 | mfspr r4, SPRN_LPCR | |
367 | rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1 | |
368 | mtspr SPRN_LPCR, r4 | |
56548fc0 PM |
369 | li r3, 0 |
370 | b power7_wakeup_loss | |
371 | ||
372 | 53: HMT_LOW | |
373 | ld r4, HSTATE_KVM_VCPU(r13) | |
374 | cmpdi r4, 0 | |
375 | beq kvm_no_guest | |
376 | HMT_MEDIUM | |
377 | b kvm_secondary_got_guest | |
378 | ||
379 | 54: li r0, KVM_HWTHREAD_IN_KVM | |
380 | stb r0, HSTATE_HWTHREAD_STATE(r13) | |
381 | b kvm_no_guest | |
218309b7 PM |
382 | |
383 | /****************************************************************************** | |
384 | * * | |
385 | * Entry code * | |
386 | * * | |
387 | *****************************************************************************/ | |
388 | ||
de56a948 PM |
389 | .global kvmppc_hv_entry |
390 | kvmppc_hv_entry: | |
391 | ||
392 | /* Required state: | |
393 | * | |
e0b7ec05 | 394 | * R4 = vcpu pointer (or NULL) |
de56a948 PM |
395 | * MSR = ~IR|DR |
396 | * R13 = PACA | |
397 | * R1 = host R1 | |
06a29e42 | 398 | * R2 = TOC |
de56a948 PM |
399 | * all other volatile GPRS = free |
400 | */ | |
401 | mflr r0 | |
218309b7 PM |
402 | std r0, PPC_LR_STKOFF(r1) |
403 | stdu r1, -112(r1) | |
de56a948 | 404 | |
de56a948 PM |
405 | /* Save R1 in the PACA */ |
406 | std r1, HSTATE_HOST_R1(r13) | |
407 | ||
44a3add8 PM |
408 | li r6, KVM_GUEST_MODE_HOST_HV |
409 | stb r6, HSTATE_IN_GUEST(r13) | |
410 | ||
b6c295df PM |
411 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
412 | /* Store initial timestamp */ | |
413 | cmpdi r4, 0 | |
414 | beq 1f | |
415 | addi r3, r4, VCPU_TB_RMENTRY | |
416 | bl kvmhv_start_timing | |
417 | 1: | |
418 | #endif | |
de56a948 PM |
419 | /* Clear out SLB */ |
420 | li r6,0 | |
421 | slbmte r6,r6 | |
422 | slbia | |
423 | ptesync | |
424 | ||
9e368f29 | 425 | /* |
c17b98cf | 426 | * POWER7/POWER8 host -> guest partition switch code. |
9e368f29 PM |
427 | * We don't have to lock against concurrent tlbies, |
428 | * but we do have to coordinate across hardware threads. | |
429 | */ | |
7d6c40da PM |
430 | /* Set bit in entry map iff exit map is zero. */ |
431 | ld r5, HSTATE_KVM_VCORE(r13) | |
432 | li r7, 1 | |
433 | lbz r6, HSTATE_PTID(r13) | |
434 | sld r7, r7, r6 | |
435 | addi r9, r5, VCORE_ENTRY_EXIT | |
436 | 21: lwarx r3, 0, r9 | |
437 | cmpwi r3, 0x100 /* any threads starting to exit? */ | |
371fefd6 | 438 | bge secondary_too_late /* if so we're too late to the party */ |
7d6c40da PM |
439 | or r3, r3, r7 |
440 | stwcx. r3, 0, r9 | |
371fefd6 PM |
441 | bne 21b |
442 | ||
443 | /* Primary thread switches to guest partition. */ | |
e0b7ec05 | 444 | ld r9,VCORE_KVM(r5) /* pointer to struct kvm */ |
371fefd6 | 445 | cmpwi r6,0 |
6af27c84 | 446 | bne 10f |
de56a948 PM |
447 | ld r6,KVM_SDR1(r9) |
448 | lwz r7,KVM_LPID(r9) | |
449 | li r0,LPID_RSVD /* switch to reserved LPID */ | |
450 | mtspr SPRN_LPID,r0 | |
451 | ptesync | |
452 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
453 | mtspr SPRN_LPID,r7 | |
454 | isync | |
1b400ba0 PM |
455 | |
456 | /* See if we need to flush the TLB */ | |
457 | lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */ | |
458 | clrldi r7,r6,64-6 /* extract bit number (6 bits) */ | |
459 | srdi r6,r6,6 /* doubleword number */ | |
460 | sldi r6,r6,3 /* address offset */ | |
461 | add r6,r6,r9 | |
462 | addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */ | |
371fefd6 | 463 | li r0,1 |
1b400ba0 PM |
464 | sld r0,r0,r7 |
465 | ld r7,0(r6) | |
466 | and. r7,r7,r0 | |
467 | beq 22f | |
468 | 23: ldarx r7,0,r6 /* if set, clear the bit */ | |
469 | andc r7,r7,r0 | |
470 | stdcx. r7,0,r6 | |
471 | bne 23b | |
ca252055 PM |
472 | /* Flush the TLB of any entries for this LPID */ |
473 | /* use arch 2.07S as a proxy for POWER8 */ | |
474 | BEGIN_FTR_SECTION | |
475 | li r6,512 /* POWER8 has 512 sets */ | |
476 | FTR_SECTION_ELSE | |
477 | li r6,128 /* POWER7 has 128 sets */ | |
478 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S) | |
1b400ba0 PM |
479 | mtctr r6 |
480 | li r7,0x800 /* IS field = 0b10 */ | |
481 | ptesync | |
482 | 28: tlbiel r7 | |
483 | addi r7,r7,0x1000 | |
484 | bdnz 28b | |
485 | ptesync | |
486 | ||
93b0f4dc PM |
487 | /* Add timebase offset onto timebase */ |
488 | 22: ld r8,VCORE_TB_OFFSET(r5) | |
489 | cmpdi r8,0 | |
490 | beq 37f | |
491 | mftb r6 /* current host timebase */ | |
492 | add r8,r8,r6 | |
493 | mtspr SPRN_TBU40,r8 /* update upper 40 bits */ | |
494 | mftb r7 /* check if lower 24 bits overflowed */ | |
495 | clrldi r6,r6,40 | |
496 | clrldi r7,r7,40 | |
497 | cmpld r7,r6 | |
498 | bge 37f | |
499 | addis r8,r8,0x100 /* if so, increment upper 40 bits */ | |
500 | mtspr SPRN_TBU40,r8 | |
501 | ||
388cc6e1 PM |
502 | /* Load guest PCR value to select appropriate compat mode */ |
503 | 37: ld r7, VCORE_PCR(r5) | |
504 | cmpdi r7, 0 | |
505 | beq 38f | |
506 | mtspr SPRN_PCR, r7 | |
507 | 38: | |
b005255e MN |
508 | |
509 | BEGIN_FTR_SECTION | |
510 | /* DPDES is shared between threads */ | |
511 | ld r8, VCORE_DPDES(r5) | |
512 | mtspr SPRN_DPDES, r8 | |
513 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
514 | ||
388cc6e1 | 515 | li r0,1 |
371fefd6 | 516 | stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */ |
9e368f29 | 517 | |
e0b7ec05 | 518 | /* Do we have a guest vcpu to run? */ |
6af27c84 | 519 | 10: cmpdi r4, 0 |
e0b7ec05 PM |
520 | beq kvmppc_primary_no_guest |
521 | kvmppc_got_guest: | |
de56a948 PM |
522 | |
523 | /* Load up guest SLB entries */ | |
e0b7ec05 | 524 | lwz r5,VCPU_SLB_MAX(r4) |
de56a948 PM |
525 | cmpwi r5,0 |
526 | beq 9f | |
527 | mtctr r5 | |
528 | addi r6,r4,VCPU_SLB | |
529 | 1: ld r8,VCPU_SLB_E(r6) | |
530 | ld r9,VCPU_SLB_V(r6) | |
531 | slbmte r9,r8 | |
532 | addi r6,r6,VCPU_SLB_SIZE | |
533 | bdnz 1b | |
534 | 9: | |
e0b7ec05 PM |
535 | /* Increment yield count if they have a VPA */ |
536 | ld r3, VCPU_VPA(r4) | |
537 | cmpdi r3, 0 | |
538 | beq 25f | |
0865a583 AG |
539 | li r6, LPPACA_YIELDCOUNT |
540 | LWZX_BE r5, r3, r6 | |
e0b7ec05 | 541 | addi r5, r5, 1 |
0865a583 | 542 | STWX_BE r5, r3, r6 |
e0b7ec05 PM |
543 | li r6, 1 |
544 | stb r6, VCPU_VPA_DIRTY(r4) | |
545 | 25: | |
546 | ||
e0b7ec05 PM |
547 | /* Save purr/spurr */ |
548 | mfspr r5,SPRN_PURR | |
549 | mfspr r6,SPRN_SPURR | |
550 | std r5,HSTATE_PURR(r13) | |
551 | std r6,HSTATE_SPURR(r13) | |
552 | ld r7,VCPU_PURR(r4) | |
553 | ld r8,VCPU_SPURR(r4) | |
554 | mtspr SPRN_PURR,r7 | |
555 | mtspr SPRN_SPURR,r8 | |
e0b7ec05 PM |
556 | |
557 | BEGIN_FTR_SECTION | |
558 | /* Set partition DABR */ | |
559 | /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */ | |
8563bf52 | 560 | lwz r5,VCPU_DABRX(r4) |
e0b7ec05 PM |
561 | ld r6,VCPU_DABR(r4) |
562 | mtspr SPRN_DABRX,r5 | |
563 | mtspr SPRN_DABR,r6 | |
e0b7ec05 | 564 | isync |
e0b7ec05 PM |
565 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) |
566 | ||
e4e38121 MN |
567 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
568 | BEGIN_FTR_SECTION | |
569 | b skip_tm | |
570 | END_FTR_SECTION_IFCLR(CPU_FTR_TM) | |
571 | ||
572 | /* Turn on TM/FP/VSX/VMX so we can restore them. */ | |
573 | mfmsr r5 | |
574 | li r6, MSR_TM >> 32 | |
575 | sldi r6, r6, 32 | |
576 | or r5, r5, r6 | |
577 | ori r5, r5, MSR_FP | |
578 | oris r5, r5, (MSR_VEC | MSR_VSX)@h | |
579 | mtmsrd r5 | |
580 | ||
581 | /* | |
582 | * The user may change these outside of a transaction, so they must | |
583 | * always be context switched. | |
584 | */ | |
585 | ld r5, VCPU_TFHAR(r4) | |
586 | ld r6, VCPU_TFIAR(r4) | |
587 | ld r7, VCPU_TEXASR(r4) | |
588 | mtspr SPRN_TFHAR, r5 | |
589 | mtspr SPRN_TFIAR, r6 | |
590 | mtspr SPRN_TEXASR, r7 | |
591 | ||
592 | ld r5, VCPU_MSR(r4) | |
593 | rldicl. r5, r5, 64 - MSR_TS_S_LG, 62 | |
594 | beq skip_tm /* TM not active in guest */ | |
595 | ||
596 | /* Make sure the failure summary is set, otherwise we'll program check | |
597 | * when we trechkpt. It's possible that this might have been not set | |
598 | * on a kvmppc_set_one_reg() call but we shouldn't let this crash the | |
599 | * host. | |
600 | */ | |
601 | oris r7, r7, (TEXASR_FS)@h | |
602 | mtspr SPRN_TEXASR, r7 | |
603 | ||
604 | /* | |
605 | * We need to load up the checkpointed state for the guest. | |
606 | * We need to do this early as it will blow away any GPRs, VSRs and | |
607 | * some SPRs. | |
608 | */ | |
609 | ||
610 | mr r31, r4 | |
611 | addi r3, r31, VCPU_FPRS_TM | |
9bf163f8 | 612 | bl load_fp_state |
e4e38121 | 613 | addi r3, r31, VCPU_VRS_TM |
9bf163f8 | 614 | bl load_vr_state |
e4e38121 MN |
615 | mr r4, r31 |
616 | lwz r7, VCPU_VRSAVE_TM(r4) | |
617 | mtspr SPRN_VRSAVE, r7 | |
618 | ||
619 | ld r5, VCPU_LR_TM(r4) | |
620 | lwz r6, VCPU_CR_TM(r4) | |
621 | ld r7, VCPU_CTR_TM(r4) | |
622 | ld r8, VCPU_AMR_TM(r4) | |
623 | ld r9, VCPU_TAR_TM(r4) | |
624 | mtlr r5 | |
625 | mtcr r6 | |
626 | mtctr r7 | |
627 | mtspr SPRN_AMR, r8 | |
628 | mtspr SPRN_TAR, r9 | |
629 | ||
630 | /* | |
631 | * Load up PPR and DSCR values but don't put them in the actual SPRs | |
632 | * till the last moment to avoid running with userspace PPR and DSCR for | |
633 | * too long. | |
634 | */ | |
635 | ld r29, VCPU_DSCR_TM(r4) | |
636 | ld r30, VCPU_PPR_TM(r4) | |
637 | ||
638 | std r2, PACATMSCRATCH(r13) /* Save TOC */ | |
639 | ||
640 | /* Clear the MSR RI since r1, r13 are all going to be foobar. */ | |
641 | li r5, 0 | |
642 | mtmsrd r5, 1 | |
643 | ||
644 | /* Load GPRs r0-r28 */ | |
645 | reg = 0 | |
646 | .rept 29 | |
647 | ld reg, VCPU_GPRS_TM(reg)(r31) | |
648 | reg = reg + 1 | |
649 | .endr | |
650 | ||
651 | mtspr SPRN_DSCR, r29 | |
652 | mtspr SPRN_PPR, r30 | |
653 | ||
654 | /* Load final GPRs */ | |
655 | ld 29, VCPU_GPRS_TM(29)(r31) | |
656 | ld 30, VCPU_GPRS_TM(30)(r31) | |
657 | ld 31, VCPU_GPRS_TM(31)(r31) | |
658 | ||
659 | /* TM checkpointed state is now setup. All GPRs are now volatile. */ | |
660 | TRECHKPT | |
661 | ||
662 | /* Now let's get back the state we need. */ | |
663 | HMT_MEDIUM | |
664 | GET_PACA(r13) | |
665 | ld r29, HSTATE_DSCR(r13) | |
666 | mtspr SPRN_DSCR, r29 | |
667 | ld r4, HSTATE_KVM_VCPU(r13) | |
668 | ld r1, HSTATE_HOST_R1(r13) | |
669 | ld r2, PACATMSCRATCH(r13) | |
670 | ||
671 | /* Set the MSR RI since we have our registers back. */ | |
672 | li r5, MSR_RI | |
673 | mtmsrd r5, 1 | |
674 | skip_tm: | |
675 | #endif | |
676 | ||
e0b7ec05 PM |
677 | /* Load guest PMU registers */ |
678 | /* R4 is live here (vcpu pointer) */ | |
679 | li r3, 1 | |
680 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
681 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ | |
682 | isync | |
9bc01a9b PM |
683 | BEGIN_FTR_SECTION |
684 | ld r3, VCPU_MMCR(r4) | |
685 | andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO | |
686 | cmpwi r5, MMCR0_PMAO | |
687 | beql kvmppc_fix_pmao | |
688 | END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG) | |
e0b7ec05 PM |
689 | lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */ |
690 | lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */ | |
691 | lwz r6, VCPU_PMC + 8(r4) | |
692 | lwz r7, VCPU_PMC + 12(r4) | |
693 | lwz r8, VCPU_PMC + 16(r4) | |
694 | lwz r9, VCPU_PMC + 20(r4) | |
e0b7ec05 PM |
695 | mtspr SPRN_PMC1, r3 |
696 | mtspr SPRN_PMC2, r5 | |
697 | mtspr SPRN_PMC3, r6 | |
698 | mtspr SPRN_PMC4, r7 | |
699 | mtspr SPRN_PMC5, r8 | |
700 | mtspr SPRN_PMC6, r9 | |
e0b7ec05 PM |
701 | ld r3, VCPU_MMCR(r4) |
702 | ld r5, VCPU_MMCR + 8(r4) | |
703 | ld r6, VCPU_MMCR + 16(r4) | |
704 | ld r7, VCPU_SIAR(r4) | |
705 | ld r8, VCPU_SDAR(r4) | |
706 | mtspr SPRN_MMCR1, r5 | |
707 | mtspr SPRN_MMCRA, r6 | |
708 | mtspr SPRN_SIAR, r7 | |
709 | mtspr SPRN_SDAR, r8 | |
b005255e MN |
710 | BEGIN_FTR_SECTION |
711 | ld r5, VCPU_MMCR + 24(r4) | |
712 | ld r6, VCPU_SIER(r4) | |
713 | lwz r7, VCPU_PMC + 24(r4) | |
714 | lwz r8, VCPU_PMC + 28(r4) | |
715 | ld r9, VCPU_MMCR + 32(r4) | |
716 | mtspr SPRN_MMCR2, r5 | |
717 | mtspr SPRN_SIER, r6 | |
718 | mtspr SPRN_SPMC1, r7 | |
719 | mtspr SPRN_SPMC2, r8 | |
720 | mtspr SPRN_MMCRS, r9 | |
721 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
e0b7ec05 PM |
722 | mtspr SPRN_MMCR0, r3 |
723 | isync | |
724 | ||
725 | /* Load up FP, VMX and VSX registers */ | |
726 | bl kvmppc_load_fp | |
727 | ||
728 | ld r14, VCPU_GPR(R14)(r4) | |
729 | ld r15, VCPU_GPR(R15)(r4) | |
730 | ld r16, VCPU_GPR(R16)(r4) | |
731 | ld r17, VCPU_GPR(R17)(r4) | |
732 | ld r18, VCPU_GPR(R18)(r4) | |
733 | ld r19, VCPU_GPR(R19)(r4) | |
734 | ld r20, VCPU_GPR(R20)(r4) | |
735 | ld r21, VCPU_GPR(R21)(r4) | |
736 | ld r22, VCPU_GPR(R22)(r4) | |
737 | ld r23, VCPU_GPR(R23)(r4) | |
738 | ld r24, VCPU_GPR(R24)(r4) | |
739 | ld r25, VCPU_GPR(R25)(r4) | |
740 | ld r26, VCPU_GPR(R26)(r4) | |
741 | ld r27, VCPU_GPR(R27)(r4) | |
742 | ld r28, VCPU_GPR(R28)(r4) | |
743 | ld r29, VCPU_GPR(R29)(r4) | |
744 | ld r30, VCPU_GPR(R30)(r4) | |
745 | ld r31, VCPU_GPR(R31)(r4) | |
746 | ||
e0b7ec05 PM |
747 | /* Switch DSCR to guest value */ |
748 | ld r5, VCPU_DSCR(r4) | |
749 | mtspr SPRN_DSCR, r5 | |
e0b7ec05 | 750 | |
b005255e | 751 | BEGIN_FTR_SECTION |
c17b98cf | 752 | /* Skip next section on POWER7 */ |
b005255e MN |
753 | b 8f |
754 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
755 | /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */ | |
756 | mfmsr r8 | |
757 | li r0, 1 | |
758 | rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG | |
759 | mtmsrd r8 | |
760 | ||
761 | /* Load up POWER8-specific registers */ | |
762 | ld r5, VCPU_IAMR(r4) | |
763 | lwz r6, VCPU_PSPB(r4) | |
764 | ld r7, VCPU_FSCR(r4) | |
765 | mtspr SPRN_IAMR, r5 | |
766 | mtspr SPRN_PSPB, r6 | |
767 | mtspr SPRN_FSCR, r7 | |
768 | ld r5, VCPU_DAWR(r4) | |
769 | ld r6, VCPU_DAWRX(r4) | |
770 | ld r7, VCPU_CIABR(r4) | |
771 | ld r8, VCPU_TAR(r4) | |
772 | mtspr SPRN_DAWR, r5 | |
773 | mtspr SPRN_DAWRX, r6 | |
774 | mtspr SPRN_CIABR, r7 | |
775 | mtspr SPRN_TAR, r8 | |
776 | ld r5, VCPU_IC(r4) | |
777 | ld r6, VCPU_VTB(r4) | |
778 | mtspr SPRN_IC, r5 | |
779 | mtspr SPRN_VTB, r6 | |
7b490411 | 780 | ld r8, VCPU_EBBHR(r4) |
b005255e MN |
781 | mtspr SPRN_EBBHR, r8 |
782 | ld r5, VCPU_EBBRR(r4) | |
783 | ld r6, VCPU_BESCR(r4) | |
784 | ld r7, VCPU_CSIGR(r4) | |
785 | ld r8, VCPU_TACR(r4) | |
786 | mtspr SPRN_EBBRR, r5 | |
787 | mtspr SPRN_BESCR, r6 | |
788 | mtspr SPRN_CSIGR, r7 | |
789 | mtspr SPRN_TACR, r8 | |
790 | ld r5, VCPU_TCSCR(r4) | |
791 | ld r6, VCPU_ACOP(r4) | |
792 | lwz r7, VCPU_GUEST_PID(r4) | |
793 | ld r8, VCPU_WORT(r4) | |
794 | mtspr SPRN_TCSCR, r5 | |
795 | mtspr SPRN_ACOP, r6 | |
796 | mtspr SPRN_PID, r7 | |
797 | mtspr SPRN_WORT, r8 | |
798 | 8: | |
799 | ||
e0b7ec05 PM |
800 | /* |
801 | * Set the decrementer to the guest decrementer. | |
802 | */ | |
803 | ld r8,VCPU_DEC_EXPIRES(r4) | |
c5fb80d3 PM |
804 | /* r8 is a host timebase value here, convert to guest TB */ |
805 | ld r5,HSTATE_KVM_VCORE(r13) | |
806 | ld r6,VCORE_TB_OFFSET(r5) | |
807 | add r8,r8,r6 | |
e0b7ec05 PM |
808 | mftb r7 |
809 | subf r3,r7,r8 | |
810 | mtspr SPRN_DEC,r3 | |
811 | stw r3,VCPU_DEC(r4) | |
812 | ||
813 | ld r5, VCPU_SPRG0(r4) | |
814 | ld r6, VCPU_SPRG1(r4) | |
815 | ld r7, VCPU_SPRG2(r4) | |
816 | ld r8, VCPU_SPRG3(r4) | |
817 | mtspr SPRN_SPRG0, r5 | |
818 | mtspr SPRN_SPRG1, r6 | |
819 | mtspr SPRN_SPRG2, r7 | |
820 | mtspr SPRN_SPRG3, r8 | |
821 | ||
822 | /* Load up DAR and DSISR */ | |
823 | ld r5, VCPU_DAR(r4) | |
824 | lwz r6, VCPU_DSISR(r4) | |
825 | mtspr SPRN_DAR, r5 | |
826 | mtspr SPRN_DSISR, r6 | |
827 | ||
e0b7ec05 PM |
828 | /* Restore AMR and UAMOR, set AMOR to all 1s */ |
829 | ld r5,VCPU_AMR(r4) | |
830 | ld r6,VCPU_UAMOR(r4) | |
831 | li r7,-1 | |
832 | mtspr SPRN_AMR,r5 | |
833 | mtspr SPRN_UAMOR,r6 | |
834 | mtspr SPRN_AMOR,r7 | |
de56a948 PM |
835 | |
836 | /* Restore state of CTRL run bit; assume 1 on entry */ | |
837 | lwz r5,VCPU_CTRL(r4) | |
838 | andi. r5,r5,1 | |
839 | bne 4f | |
840 | mfspr r6,SPRN_CTRLF | |
841 | clrrdi r6,r6,1 | |
842 | mtspr SPRN_CTRLT,r6 | |
843 | 4: | |
6af27c84 PM |
844 | /* Secondary threads wait for primary to have done partition switch */ |
845 | ld r5, HSTATE_KVM_VCORE(r13) | |
846 | lbz r6, HSTATE_PTID(r13) | |
847 | cmpwi r6, 0 | |
848 | beq 21f | |
849 | lbz r0, VCORE_IN_GUEST(r5) | |
850 | cmpwi r0, 0 | |
851 | bne 21f | |
852 | HMT_LOW | |
853 | 20: lbz r0, VCORE_IN_GUEST(r5) | |
854 | cmpwi r0, 0 | |
855 | beq 20b | |
856 | HMT_MEDIUM | |
857 | 21: | |
858 | /* Set LPCR. */ | |
859 | ld r8,VCORE_LPCR(r5) | |
860 | mtspr SPRN_LPCR,r8 | |
861 | isync | |
862 | ||
863 | /* Check if HDEC expires soon */ | |
864 | mfspr r3, SPRN_HDEC | |
865 | cmpwi r3, 512 /* 1 microsecond */ | |
866 | blt hdec_soon | |
867 | ||
de56a948 PM |
868 | ld r6, VCPU_CTR(r4) |
869 | lwz r7, VCPU_XER(r4) | |
870 | ||
871 | mtctr r6 | |
872 | mtxer r7 | |
873 | ||
e3bbbbfa | 874 | kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */ |
4619ac88 PM |
875 | ld r10, VCPU_PC(r4) |
876 | ld r11, VCPU_MSR(r4) | |
de56a948 PM |
877 | ld r6, VCPU_SRR0(r4) |
878 | ld r7, VCPU_SRR1(r4) | |
e3bbbbfa PM |
879 | mtspr SPRN_SRR0, r6 |
880 | mtspr SPRN_SRR1, r7 | |
de56a948 | 881 | |
e3bbbbfa | 882 | deliver_guest_interrupt: |
4619ac88 | 883 | /* r11 = vcpu->arch.msr & ~MSR_HV */ |
de56a948 PM |
884 | rldicl r11, r11, 63 - MSR_HV_LG, 1 |
885 | rotldi r11, r11, 1 + MSR_HV_LG | |
886 | ori r11, r11, MSR_ME | |
887 | ||
19ccb76a | 888 | /* Check if we can deliver an external or decrementer interrupt now */ |
e3bbbbfa PM |
889 | ld r0, VCPU_PENDING_EXC(r4) |
890 | rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63 | |
891 | cmpdi cr1, r0, 0 | |
892 | andi. r8, r11, MSR_EE | |
e3bbbbfa PM |
893 | mfspr r8, SPRN_LPCR |
894 | /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */ | |
895 | rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH | |
896 | mtspr SPRN_LPCR, r8 | |
19ccb76a | 897 | isync |
19ccb76a | 898 | beq 5f |
e3bbbbfa PM |
899 | li r0, BOOK3S_INTERRUPT_EXTERNAL |
900 | bne cr1, 12f | |
901 | mfspr r0, SPRN_DEC | |
902 | cmpwi r0, 0 | |
903 | li r0, BOOK3S_INTERRUPT_DECREMENTER | |
904 | bge 5f | |
19ccb76a | 905 | |
e3bbbbfa | 906 | 12: mtspr SPRN_SRR0, r10 |
19ccb76a | 907 | mr r10,r0 |
e3bbbbfa | 908 | mtspr SPRN_SRR1, r11 |
e4e38121 MN |
909 | mr r9, r4 |
910 | bl kvmppc_msr_interrupt | |
e3bbbbfa | 911 | 5: |
19ccb76a | 912 | |
27025a60 LPF |
913 | /* |
914 | * Required state: | |
915 | * R4 = vcpu | |
916 | * R10: value for HSRR0 | |
917 | * R11: value for HSRR1 | |
918 | * R13 = PACA | |
919 | */ | |
de56a948 | 920 | fast_guest_return: |
4619ac88 PM |
921 | li r0,0 |
922 | stb r0,VCPU_CEDED(r4) /* cancel cede */ | |
de56a948 PM |
923 | mtspr SPRN_HSRR0,r10 |
924 | mtspr SPRN_HSRR1,r11 | |
925 | ||
926 | /* Activate guest mode, so faults get handled by KVM */ | |
44a3add8 | 927 | li r9, KVM_GUEST_MODE_GUEST_HV |
de56a948 PM |
928 | stb r9, HSTATE_IN_GUEST(r13) |
929 | ||
b6c295df PM |
930 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
931 | /* Accumulate timing */ | |
932 | addi r3, r4, VCPU_TB_GUEST | |
933 | bl kvmhv_accumulate_time | |
934 | #endif | |
935 | ||
de56a948 PM |
936 | /* Enter guest */ |
937 | ||
0acb9111 PM |
938 | BEGIN_FTR_SECTION |
939 | ld r5, VCPU_CFAR(r4) | |
940 | mtspr SPRN_CFAR, r5 | |
941 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
4b8473c9 PM |
942 | BEGIN_FTR_SECTION |
943 | ld r0, VCPU_PPR(r4) | |
944 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
0acb9111 | 945 | |
de56a948 PM |
946 | ld r5, VCPU_LR(r4) |
947 | lwz r6, VCPU_CR(r4) | |
948 | mtlr r5 | |
949 | mtcr r6 | |
950 | ||
c75df6f9 MN |
951 | ld r1, VCPU_GPR(R1)(r4) |
952 | ld r2, VCPU_GPR(R2)(r4) | |
953 | ld r3, VCPU_GPR(R3)(r4) | |
954 | ld r5, VCPU_GPR(R5)(r4) | |
955 | ld r6, VCPU_GPR(R6)(r4) | |
956 | ld r7, VCPU_GPR(R7)(r4) | |
957 | ld r8, VCPU_GPR(R8)(r4) | |
958 | ld r9, VCPU_GPR(R9)(r4) | |
959 | ld r10, VCPU_GPR(R10)(r4) | |
960 | ld r11, VCPU_GPR(R11)(r4) | |
961 | ld r12, VCPU_GPR(R12)(r4) | |
962 | ld r13, VCPU_GPR(R13)(r4) | |
963 | ||
4b8473c9 PM |
964 | BEGIN_FTR_SECTION |
965 | mtspr SPRN_PPR, r0 | |
966 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
967 | ld r0, VCPU_GPR(R0)(r4) | |
c75df6f9 | 968 | ld r4, VCPU_GPR(R4)(r4) |
de56a948 PM |
969 | |
970 | hrfid | |
971 | b . | |
972 | ||
b6c295df | 973 | secondary_too_late: |
6af27c84 | 974 | li r12, 0 |
b6c295df PM |
975 | cmpdi r4, 0 |
976 | beq 11f | |
6af27c84 PM |
977 | stw r12, VCPU_TRAP(r4) |
978 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING | |
b6c295df PM |
979 | addi r3, r4, VCPU_TB_RMEXIT |
980 | bl kvmhv_accumulate_time | |
6af27c84 | 981 | #endif |
b6c295df PM |
982 | 11: b kvmhv_switch_to_host |
983 | ||
984 | hdec_soon: | |
6af27c84 PM |
985 | li r12, BOOK3S_INTERRUPT_HV_DECREMENTER |
986 | stw r12, VCPU_TRAP(r4) | |
987 | mr r9, r4 | |
988 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING | |
b6c295df PM |
989 | addi r3, r4, VCPU_TB_RMEXIT |
990 | bl kvmhv_accumulate_time | |
b6c295df | 991 | #endif |
6af27c84 | 992 | b guest_exit_cont |
b6c295df | 993 | |
de56a948 PM |
994 | /****************************************************************************** |
995 | * * | |
996 | * Exit code * | |
997 | * * | |
998 | *****************************************************************************/ | |
999 | ||
1000 | /* | |
1001 | * We come here from the first-level interrupt handlers. | |
1002 | */ | |
dd96b2c2 AK |
1003 | .globl kvmppc_interrupt_hv |
1004 | kvmppc_interrupt_hv: | |
de56a948 PM |
1005 | /* |
1006 | * Register contents: | |
1007 | * R12 = interrupt vector | |
1008 | * R13 = PACA | |
1009 | * guest CR, R12 saved in shadow VCPU SCRATCH1/0 | |
1010 | * guest R13 saved in SPRN_SCRATCH0 | |
1011 | */ | |
36e7bb38 | 1012 | std r9, HSTATE_SCRATCH2(r13) |
44a3add8 PM |
1013 | |
1014 | lbz r9, HSTATE_IN_GUEST(r13) | |
1015 | cmpwi r9, KVM_GUEST_MODE_HOST_HV | |
1016 | beq kvmppc_bad_host_intr | |
dd96b2c2 AK |
1017 | #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE |
1018 | cmpwi r9, KVM_GUEST_MODE_GUEST | |
36e7bb38 | 1019 | ld r9, HSTATE_SCRATCH2(r13) |
dd96b2c2 AK |
1020 | beq kvmppc_interrupt_pr |
1021 | #endif | |
44a3add8 PM |
1022 | /* We're now back in the host but in guest MMU context */ |
1023 | li r9, KVM_GUEST_MODE_HOST_HV | |
1024 | stb r9, HSTATE_IN_GUEST(r13) | |
1025 | ||
de56a948 PM |
1026 | ld r9, HSTATE_KVM_VCPU(r13) |
1027 | ||
1028 | /* Save registers */ | |
1029 | ||
c75df6f9 MN |
1030 | std r0, VCPU_GPR(R0)(r9) |
1031 | std r1, VCPU_GPR(R1)(r9) | |
1032 | std r2, VCPU_GPR(R2)(r9) | |
1033 | std r3, VCPU_GPR(R3)(r9) | |
1034 | std r4, VCPU_GPR(R4)(r9) | |
1035 | std r5, VCPU_GPR(R5)(r9) | |
1036 | std r6, VCPU_GPR(R6)(r9) | |
1037 | std r7, VCPU_GPR(R7)(r9) | |
1038 | std r8, VCPU_GPR(R8)(r9) | |
36e7bb38 | 1039 | ld r0, HSTATE_SCRATCH2(r13) |
c75df6f9 MN |
1040 | std r0, VCPU_GPR(R9)(r9) |
1041 | std r10, VCPU_GPR(R10)(r9) | |
1042 | std r11, VCPU_GPR(R11)(r9) | |
de56a948 PM |
1043 | ld r3, HSTATE_SCRATCH0(r13) |
1044 | lwz r4, HSTATE_SCRATCH1(r13) | |
c75df6f9 | 1045 | std r3, VCPU_GPR(R12)(r9) |
de56a948 | 1046 | stw r4, VCPU_CR(r9) |
0acb9111 PM |
1047 | BEGIN_FTR_SECTION |
1048 | ld r3, HSTATE_CFAR(r13) | |
1049 | std r3, VCPU_CFAR(r9) | |
1050 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
4b8473c9 PM |
1051 | BEGIN_FTR_SECTION |
1052 | ld r4, HSTATE_PPR(r13) | |
1053 | std r4, VCPU_PPR(r9) | |
1054 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
de56a948 PM |
1055 | |
1056 | /* Restore R1/R2 so we can handle faults */ | |
1057 | ld r1, HSTATE_HOST_R1(r13) | |
1058 | ld r2, PACATOC(r13) | |
1059 | ||
1060 | mfspr r10, SPRN_SRR0 | |
1061 | mfspr r11, SPRN_SRR1 | |
1062 | std r10, VCPU_SRR0(r9) | |
1063 | std r11, VCPU_SRR1(r9) | |
1064 | andi. r0, r12, 2 /* need to read HSRR0/1? */ | |
1065 | beq 1f | |
1066 | mfspr r10, SPRN_HSRR0 | |
1067 | mfspr r11, SPRN_HSRR1 | |
1068 | clrrdi r12, r12, 2 | |
1069 | 1: std r10, VCPU_PC(r9) | |
1070 | std r11, VCPU_MSR(r9) | |
1071 | ||
1072 | GET_SCRATCH0(r3) | |
1073 | mflr r4 | |
c75df6f9 | 1074 | std r3, VCPU_GPR(R13)(r9) |
de56a948 PM |
1075 | std r4, VCPU_LR(r9) |
1076 | ||
de56a948 PM |
1077 | stw r12,VCPU_TRAP(r9) |
1078 | ||
b6c295df PM |
1079 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
1080 | addi r3, r9, VCPU_TB_RMINTR | |
1081 | mr r4, r9 | |
1082 | bl kvmhv_accumulate_time | |
1083 | ld r5, VCPU_GPR(R5)(r9) | |
1084 | ld r6, VCPU_GPR(R6)(r9) | |
1085 | ld r7, VCPU_GPR(R7)(r9) | |
1086 | ld r8, VCPU_GPR(R8)(r9) | |
1087 | #endif | |
1088 | ||
4a157d61 | 1089 | /* Save HEIR (HV emulation assist reg) in emul_inst |
697d3899 PM |
1090 | if this is an HEI (HV emulation interrupt, e40) */ |
1091 | li r3,KVM_INST_FETCH_FAILED | |
2bf27601 | 1092 | stw r3,VCPU_LAST_INST(r9) |
697d3899 PM |
1093 | cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST |
1094 | bne 11f | |
1095 | mfspr r3,SPRN_HEIR | |
4a157d61 | 1096 | 11: stw r3,VCPU_HEIR(r9) |
697d3899 PM |
1097 | |
1098 | /* these are volatile across C function calls */ | |
1099 | mfctr r3 | |
1100 | mfxer r4 | |
1101 | std r3, VCPU_CTR(r9) | |
1102 | stw r4, VCPU_XER(r9) | |
1103 | ||
697d3899 PM |
1104 | /* If this is a page table miss then see if it's theirs or ours */ |
1105 | cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE | |
1106 | beq kvmppc_hdsi | |
342d3db7 PM |
1107 | cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE |
1108 | beq kvmppc_hisi | |
697d3899 | 1109 | |
de56a948 PM |
1110 | /* See if this is a leftover HDEC interrupt */ |
1111 | cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
1112 | bne 2f | |
1113 | mfspr r3,SPRN_HDEC | |
1114 | cmpwi r3,0 | |
1f09c3ed PM |
1115 | mr r4,r9 |
1116 | bge fast_guest_return | |
de56a948 | 1117 | 2: |
697d3899 | 1118 | /* See if this is an hcall we can handle in real mode */ |
a8606e20 PM |
1119 | cmpwi r12,BOOK3S_INTERRUPT_SYSCALL |
1120 | beq hcall_try_real_mode | |
de56a948 | 1121 | |
54695c30 BH |
1122 | /* External interrupt ? */ |
1123 | cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL | |
1f09c3ed | 1124 | bne+ guest_exit_cont |
54695c30 BH |
1125 | |
1126 | /* External interrupt, first check for host_ipi. If this is | |
1127 | * set, we know the host wants us out so let's do it now | |
1128 | */ | |
c934243c PM |
1129 | bl kvmppc_read_intr |
1130 | cmpdi r3, 0 | |
1f09c3ed | 1131 | bgt guest_exit_cont |
54695c30 | 1132 | |
4619ac88 PM |
1133 | /* Check if any CPU is heading out to the host, if so head out too */ |
1134 | ld r5, HSTATE_KVM_VCORE(r13) | |
1135 | lwz r0, VCORE_ENTRY_EXIT(r5) | |
1136 | cmpwi r0, 0x100 | |
e3bbbbfa | 1137 | mr r4, r9 |
1f09c3ed | 1138 | blt deliver_guest_interrupt |
de56a948 | 1139 | |
b4072df4 | 1140 | guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */ |
de56a948 | 1141 | /* Save more register state */ |
de56a948 PM |
1142 | mfdar r6 |
1143 | mfdsisr r7 | |
de56a948 PM |
1144 | std r6, VCPU_DAR(r9) |
1145 | stw r7, VCPU_DSISR(r9) | |
697d3899 | 1146 | /* don't overwrite fault_dar/fault_dsisr if HDSI */ |
de56a948 | 1147 | cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE |
6af27c84 | 1148 | beq mc_cont |
697d3899 | 1149 | std r6, VCPU_FAULT_DAR(r9) |
de56a948 PM |
1150 | stw r7, VCPU_FAULT_DSISR(r9) |
1151 | ||
b4072df4 PM |
1152 | /* See if it is a machine check */ |
1153 | cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
1154 | beq machine_check_realmode | |
1155 | mc_cont: | |
b6c295df PM |
1156 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
1157 | addi r3, r9, VCPU_TB_RMEXIT | |
1158 | mr r4, r9 | |
1159 | bl kvmhv_accumulate_time | |
1160 | #endif | |
b4072df4 | 1161 | |
6af27c84 PM |
1162 | /* Increment exit count, poke other threads to exit */ |
1163 | bl kvmhv_commence_exit | |
1164 | ||
de56a948 | 1165 | /* Save guest CTRL register, set runlatch to 1 */ |
6af27c84 | 1166 | mfspr r6,SPRN_CTRLF |
de56a948 PM |
1167 | stw r6,VCPU_CTRL(r9) |
1168 | andi. r0,r6,1 | |
1169 | bne 4f | |
1170 | ori r6,r6,1 | |
1171 | mtspr SPRN_CTRLT,r6 | |
1172 | 4: | |
1173 | /* Read the guest SLB and save it away */ | |
1174 | lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */ | |
1175 | mtctr r0 | |
1176 | li r6,0 | |
1177 | addi r7,r9,VCPU_SLB | |
1178 | li r5,0 | |
1179 | 1: slbmfee r8,r6 | |
1180 | andis. r0,r8,SLB_ESID_V@h | |
1181 | beq 2f | |
1182 | add r8,r8,r6 /* put index in */ | |
1183 | slbmfev r3,r6 | |
1184 | std r8,VCPU_SLB_E(r7) | |
1185 | std r3,VCPU_SLB_V(r7) | |
1186 | addi r7,r7,VCPU_SLB_SIZE | |
1187 | addi r5,r5,1 | |
1188 | 2: addi r6,r6,1 | |
1189 | bdnz 1b | |
1190 | stw r5,VCPU_SLB_MAX(r9) | |
1191 | ||
1192 | /* | |
1193 | * Save the guest PURR/SPURR | |
1194 | */ | |
1195 | mfspr r5,SPRN_PURR | |
1196 | mfspr r6,SPRN_SPURR | |
1197 | ld r7,VCPU_PURR(r9) | |
1198 | ld r8,VCPU_SPURR(r9) | |
1199 | std r5,VCPU_PURR(r9) | |
1200 | std r6,VCPU_SPURR(r9) | |
1201 | subf r5,r7,r5 | |
1202 | subf r6,r8,r6 | |
1203 | ||
1204 | /* | |
1205 | * Restore host PURR/SPURR and add guest times | |
1206 | * so that the time in the guest gets accounted. | |
1207 | */ | |
1208 | ld r3,HSTATE_PURR(r13) | |
1209 | ld r4,HSTATE_SPURR(r13) | |
1210 | add r3,r3,r5 | |
1211 | add r4,r4,r6 | |
1212 | mtspr SPRN_PURR,r3 | |
1213 | mtspr SPRN_SPURR,r4 | |
1214 | ||
e0b7ec05 PM |
1215 | /* Save DEC */ |
1216 | mfspr r5,SPRN_DEC | |
1217 | mftb r6 | |
1218 | extsw r5,r5 | |
1219 | add r5,r5,r6 | |
c5fb80d3 PM |
1220 | /* r5 is a guest timebase value here, convert to host TB */ |
1221 | ld r3,HSTATE_KVM_VCORE(r13) | |
1222 | ld r4,VCORE_TB_OFFSET(r3) | |
1223 | subf r5,r4,r5 | |
e0b7ec05 PM |
1224 | std r5,VCPU_DEC_EXPIRES(r9) |
1225 | ||
b005255e MN |
1226 | BEGIN_FTR_SECTION |
1227 | b 8f | |
1228 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
b005255e MN |
1229 | /* Save POWER8-specific registers */ |
1230 | mfspr r5, SPRN_IAMR | |
1231 | mfspr r6, SPRN_PSPB | |
1232 | mfspr r7, SPRN_FSCR | |
1233 | std r5, VCPU_IAMR(r9) | |
1234 | stw r6, VCPU_PSPB(r9) | |
1235 | std r7, VCPU_FSCR(r9) | |
1236 | mfspr r5, SPRN_IC | |
1237 | mfspr r6, SPRN_VTB | |
1238 | mfspr r7, SPRN_TAR | |
1239 | std r5, VCPU_IC(r9) | |
1240 | std r6, VCPU_VTB(r9) | |
1241 | std r7, VCPU_TAR(r9) | |
7b490411 | 1242 | mfspr r8, SPRN_EBBHR |
b005255e MN |
1243 | std r8, VCPU_EBBHR(r9) |
1244 | mfspr r5, SPRN_EBBRR | |
1245 | mfspr r6, SPRN_BESCR | |
1246 | mfspr r7, SPRN_CSIGR | |
1247 | mfspr r8, SPRN_TACR | |
1248 | std r5, VCPU_EBBRR(r9) | |
1249 | std r6, VCPU_BESCR(r9) | |
1250 | std r7, VCPU_CSIGR(r9) | |
1251 | std r8, VCPU_TACR(r9) | |
1252 | mfspr r5, SPRN_TCSCR | |
1253 | mfspr r6, SPRN_ACOP | |
1254 | mfspr r7, SPRN_PID | |
1255 | mfspr r8, SPRN_WORT | |
1256 | std r5, VCPU_TCSCR(r9) | |
1257 | std r6, VCPU_ACOP(r9) | |
1258 | stw r7, VCPU_GUEST_PID(r9) | |
1259 | std r8, VCPU_WORT(r9) | |
1260 | 8: | |
1261 | ||
e0b7ec05 | 1262 | /* Save and reset AMR and UAMOR before turning on the MMU */ |
e0b7ec05 PM |
1263 | mfspr r5,SPRN_AMR |
1264 | mfspr r6,SPRN_UAMOR | |
1265 | std r5,VCPU_AMR(r9) | |
1266 | std r6,VCPU_UAMOR(r9) | |
1267 | li r6,0 | |
1268 | mtspr SPRN_AMR,r6 | |
e0b7ec05 PM |
1269 | |
1270 | /* Switch DSCR back to host value */ | |
e0b7ec05 PM |
1271 | mfspr r8, SPRN_DSCR |
1272 | ld r7, HSTATE_DSCR(r13) | |
1273 | std r8, VCPU_DSCR(r9) | |
1274 | mtspr SPRN_DSCR, r7 | |
e0b7ec05 PM |
1275 | |
1276 | /* Save non-volatile GPRs */ | |
1277 | std r14, VCPU_GPR(R14)(r9) | |
1278 | std r15, VCPU_GPR(R15)(r9) | |
1279 | std r16, VCPU_GPR(R16)(r9) | |
1280 | std r17, VCPU_GPR(R17)(r9) | |
1281 | std r18, VCPU_GPR(R18)(r9) | |
1282 | std r19, VCPU_GPR(R19)(r9) | |
1283 | std r20, VCPU_GPR(R20)(r9) | |
1284 | std r21, VCPU_GPR(R21)(r9) | |
1285 | std r22, VCPU_GPR(R22)(r9) | |
1286 | std r23, VCPU_GPR(R23)(r9) | |
1287 | std r24, VCPU_GPR(R24)(r9) | |
1288 | std r25, VCPU_GPR(R25)(r9) | |
1289 | std r26, VCPU_GPR(R26)(r9) | |
1290 | std r27, VCPU_GPR(R27)(r9) | |
1291 | std r28, VCPU_GPR(R28)(r9) | |
1292 | std r29, VCPU_GPR(R29)(r9) | |
1293 | std r30, VCPU_GPR(R30)(r9) | |
1294 | std r31, VCPU_GPR(R31)(r9) | |
1295 | ||
1296 | /* Save SPRGs */ | |
1297 | mfspr r3, SPRN_SPRG0 | |
1298 | mfspr r4, SPRN_SPRG1 | |
1299 | mfspr r5, SPRN_SPRG2 | |
1300 | mfspr r6, SPRN_SPRG3 | |
1301 | std r3, VCPU_SPRG0(r9) | |
1302 | std r4, VCPU_SPRG1(r9) | |
1303 | std r5, VCPU_SPRG2(r9) | |
1304 | std r6, VCPU_SPRG3(r9) | |
1305 | ||
1306 | /* save FP state */ | |
1307 | mr r3, r9 | |
1308 | bl kvmppc_save_fp | |
de56a948 | 1309 | |
0a8eccef PM |
1310 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1311 | BEGIN_FTR_SECTION | |
1312 | b 2f | |
1313 | END_FTR_SECTION_IFCLR(CPU_FTR_TM) | |
1314 | /* Turn on TM. */ | |
1315 | mfmsr r8 | |
1316 | li r0, 1 | |
1317 | rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG | |
1318 | mtmsrd r8 | |
1319 | ||
1320 | ld r5, VCPU_MSR(r9) | |
1321 | rldicl. r5, r5, 64 - MSR_TS_S_LG, 62 | |
1322 | beq 1f /* TM not active in guest. */ | |
1323 | ||
1324 | li r3, TM_CAUSE_KVM_RESCHED | |
1325 | ||
1326 | /* Clear the MSR RI since r1, r13 are all going to be foobar. */ | |
1327 | li r5, 0 | |
1328 | mtmsrd r5, 1 | |
1329 | ||
1330 | /* All GPRs are volatile at this point. */ | |
1331 | TRECLAIM(R3) | |
1332 | ||
1333 | /* Temporarily store r13 and r9 so we have some regs to play with */ | |
1334 | SET_SCRATCH0(r13) | |
1335 | GET_PACA(r13) | |
1336 | std r9, PACATMSCRATCH(r13) | |
1337 | ld r9, HSTATE_KVM_VCPU(r13) | |
1338 | ||
1339 | /* Get a few more GPRs free. */ | |
1340 | std r29, VCPU_GPRS_TM(29)(r9) | |
1341 | std r30, VCPU_GPRS_TM(30)(r9) | |
1342 | std r31, VCPU_GPRS_TM(31)(r9) | |
1343 | ||
1344 | /* Save away PPR and DSCR soon so don't run with user values. */ | |
1345 | mfspr r31, SPRN_PPR | |
1346 | HMT_MEDIUM | |
1347 | mfspr r30, SPRN_DSCR | |
1348 | ld r29, HSTATE_DSCR(r13) | |
1349 | mtspr SPRN_DSCR, r29 | |
1350 | ||
1351 | /* Save all but r9, r13 & r29-r31 */ | |
1352 | reg = 0 | |
1353 | .rept 29 | |
1354 | .if (reg != 9) && (reg != 13) | |
1355 | std reg, VCPU_GPRS_TM(reg)(r9) | |
1356 | .endif | |
1357 | reg = reg + 1 | |
1358 | .endr | |
1359 | /* ... now save r13 */ | |
1360 | GET_SCRATCH0(r4) | |
1361 | std r4, VCPU_GPRS_TM(13)(r9) | |
1362 | /* ... and save r9 */ | |
1363 | ld r4, PACATMSCRATCH(r13) | |
1364 | std r4, VCPU_GPRS_TM(9)(r9) | |
1365 | ||
1366 | /* Reload stack pointer and TOC. */ | |
1367 | ld r1, HSTATE_HOST_R1(r13) | |
1368 | ld r2, PACATOC(r13) | |
1369 | ||
1370 | /* Set MSR RI now we have r1 and r13 back. */ | |
1371 | li r5, MSR_RI | |
1372 | mtmsrd r5, 1 | |
1373 | ||
1374 | /* Save away checkpinted SPRs. */ | |
1375 | std r31, VCPU_PPR_TM(r9) | |
1376 | std r30, VCPU_DSCR_TM(r9) | |
1377 | mflr r5 | |
1378 | mfcr r6 | |
1379 | mfctr r7 | |
1380 | mfspr r8, SPRN_AMR | |
1381 | mfspr r10, SPRN_TAR | |
1382 | std r5, VCPU_LR_TM(r9) | |
1383 | stw r6, VCPU_CR_TM(r9) | |
1384 | std r7, VCPU_CTR_TM(r9) | |
1385 | std r8, VCPU_AMR_TM(r9) | |
1386 | std r10, VCPU_TAR_TM(r9) | |
1387 | ||
1388 | /* Restore r12 as trap number. */ | |
1389 | lwz r12, VCPU_TRAP(r9) | |
1390 | ||
1391 | /* Save FP/VSX. */ | |
1392 | addi r3, r9, VCPU_FPRS_TM | |
9bf163f8 | 1393 | bl store_fp_state |
0a8eccef | 1394 | addi r3, r9, VCPU_VRS_TM |
9bf163f8 | 1395 | bl store_vr_state |
0a8eccef PM |
1396 | mfspr r6, SPRN_VRSAVE |
1397 | stw r6, VCPU_VRSAVE_TM(r9) | |
1398 | 1: | |
1399 | /* | |
1400 | * We need to save these SPRs after the treclaim so that the software | |
1401 | * error code is recorded correctly in the TEXASR. Also the user may | |
1402 | * change these outside of a transaction, so they must always be | |
1403 | * context switched. | |
1404 | */ | |
1405 | mfspr r5, SPRN_TFHAR | |
1406 | mfspr r6, SPRN_TFIAR | |
1407 | mfspr r7, SPRN_TEXASR | |
1408 | std r5, VCPU_TFHAR(r9) | |
1409 | std r6, VCPU_TFIAR(r9) | |
1410 | std r7, VCPU_TEXASR(r9) | |
1411 | 2: | |
1412 | #endif | |
1413 | ||
e0b7ec05 PM |
1414 | /* Increment yield count if they have a VPA */ |
1415 | ld r8, VCPU_VPA(r9) /* do they have a VPA? */ | |
1416 | cmpdi r8, 0 | |
1417 | beq 25f | |
0865a583 AG |
1418 | li r4, LPPACA_YIELDCOUNT |
1419 | LWZX_BE r3, r8, r4 | |
e0b7ec05 | 1420 | addi r3, r3, 1 |
0865a583 | 1421 | STWX_BE r3, r8, r4 |
e0b7ec05 PM |
1422 | li r3, 1 |
1423 | stb r3, VCPU_VPA_DIRTY(r9) | |
1424 | 25: | |
1425 | /* Save PMU registers if requested */ | |
1426 | /* r8 and cr0.eq are live here */ | |
9bc01a9b PM |
1427 | BEGIN_FTR_SECTION |
1428 | /* | |
1429 | * POWER8 seems to have a hardware bug where setting | |
1430 | * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE] | |
1431 | * when some counters are already negative doesn't seem | |
1432 | * to cause a performance monitor alert (and hence interrupt). | |
1433 | * The effect of this is that when saving the PMU state, | |
1434 | * if there is no PMU alert pending when we read MMCR0 | |
1435 | * before freezing the counters, but one becomes pending | |
1436 | * before we read the counters, we lose it. | |
1437 | * To work around this, we need a way to freeze the counters | |
1438 | * before reading MMCR0. Normally, freezing the counters | |
1439 | * is done by writing MMCR0 (to set MMCR0[FC]) which | |
1440 | * unavoidably writes MMCR0[PMA0] as well. On POWER8, | |
1441 | * we can also freeze the counters using MMCR2, by writing | |
1442 | * 1s to all the counter freeze condition bits (there are | |
1443 | * 9 bits each for 6 counters). | |
1444 | */ | |
1445 | li r3, -1 /* set all freeze bits */ | |
1446 | clrrdi r3, r3, 10 | |
1447 | mfspr r10, SPRN_MMCR2 | |
1448 | mtspr SPRN_MMCR2, r3 | |
1449 | isync | |
1450 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
e0b7ec05 PM |
1451 | li r3, 1 |
1452 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
1453 | mfspr r4, SPRN_MMCR0 /* save MMCR0 */ | |
1454 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ | |
1455 | mfspr r6, SPRN_MMCRA | |
c17b98cf | 1456 | /* Clear MMCRA in order to disable SDAR updates */ |
e0b7ec05 PM |
1457 | li r7, 0 |
1458 | mtspr SPRN_MMCRA, r7 | |
e0b7ec05 PM |
1459 | isync |
1460 | beq 21f /* if no VPA, save PMU stuff anyway */ | |
1461 | lbz r7, LPPACA_PMCINUSE(r8) | |
1462 | cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */ | |
1463 | bne 21f | |
1464 | std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */ | |
1465 | b 22f | |
1466 | 21: mfspr r5, SPRN_MMCR1 | |
1467 | mfspr r7, SPRN_SIAR | |
1468 | mfspr r8, SPRN_SDAR | |
1469 | std r4, VCPU_MMCR(r9) | |
1470 | std r5, VCPU_MMCR + 8(r9) | |
1471 | std r6, VCPU_MMCR + 16(r9) | |
9bc01a9b PM |
1472 | BEGIN_FTR_SECTION |
1473 | std r10, VCPU_MMCR + 24(r9) | |
1474 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
e0b7ec05 PM |
1475 | std r7, VCPU_SIAR(r9) |
1476 | std r8, VCPU_SDAR(r9) | |
1477 | mfspr r3, SPRN_PMC1 | |
1478 | mfspr r4, SPRN_PMC2 | |
1479 | mfspr r5, SPRN_PMC3 | |
1480 | mfspr r6, SPRN_PMC4 | |
1481 | mfspr r7, SPRN_PMC5 | |
1482 | mfspr r8, SPRN_PMC6 | |
e0b7ec05 PM |
1483 | stw r3, VCPU_PMC(r9) |
1484 | stw r4, VCPU_PMC + 4(r9) | |
1485 | stw r5, VCPU_PMC + 8(r9) | |
1486 | stw r6, VCPU_PMC + 12(r9) | |
1487 | stw r7, VCPU_PMC + 16(r9) | |
1488 | stw r8, VCPU_PMC + 20(r9) | |
b005255e | 1489 | BEGIN_FTR_SECTION |
b005255e MN |
1490 | mfspr r5, SPRN_SIER |
1491 | mfspr r6, SPRN_SPMC1 | |
1492 | mfspr r7, SPRN_SPMC2 | |
1493 | mfspr r8, SPRN_MMCRS | |
b005255e MN |
1494 | std r5, VCPU_SIER(r9) |
1495 | stw r6, VCPU_PMC + 24(r9) | |
1496 | stw r7, VCPU_PMC + 28(r9) | |
1497 | std r8, VCPU_MMCR + 32(r9) | |
1498 | lis r4, 0x8000 | |
1499 | mtspr SPRN_MMCRS, r4 | |
1500 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
e0b7ec05 | 1501 | 22: |
de56a948 PM |
1502 | /* Clear out SLB */ |
1503 | li r5,0 | |
1504 | slbmte r5,r5 | |
1505 | slbia | |
1506 | ptesync | |
1507 | ||
9e368f29 | 1508 | /* |
c17b98cf | 1509 | * POWER7/POWER8 guest -> host partition switch code. |
9e368f29 PM |
1510 | * We don't have to lock against tlbies but we do |
1511 | * have to coordinate the hardware threads. | |
1512 | */ | |
b6c295df | 1513 | kvmhv_switch_to_host: |
371fefd6 | 1514 | /* Secondary threads wait for primary to do partition switch */ |
6af27c84 | 1515 | ld r5,HSTATE_KVM_VCORE(r13) |
e0b7ec05 PM |
1516 | ld r4,VCORE_KVM(r5) /* pointer to struct kvm */ |
1517 | lbz r3,HSTATE_PTID(r13) | |
371fefd6 PM |
1518 | cmpwi r3,0 |
1519 | beq 15f | |
1520 | HMT_LOW | |
1521 | 13: lbz r3,VCORE_IN_GUEST(r5) | |
1522 | cmpwi r3,0 | |
1523 | bne 13b | |
1524 | HMT_MEDIUM | |
1525 | b 16f | |
1526 | ||
1527 | /* Primary thread waits for all the secondaries to exit guest */ | |
1528 | 15: lwz r3,VCORE_ENTRY_EXIT(r5) | |
1529 | srwi r0,r3,8 | |
1530 | clrldi r3,r3,56 | |
1531 | cmpw r3,r0 | |
1532 | bne 15b | |
1533 | isync | |
1534 | ||
1535 | /* Primary thread switches back to host partition */ | |
de56a948 PM |
1536 | ld r6,KVM_HOST_SDR1(r4) |
1537 | lwz r7,KVM_HOST_LPID(r4) | |
1538 | li r8,LPID_RSVD /* switch to reserved LPID */ | |
1539 | mtspr SPRN_LPID,r8 | |
1540 | ptesync | |
1541 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
1542 | mtspr SPRN_LPID,r7 | |
1543 | isync | |
93b0f4dc | 1544 | |
b005255e MN |
1545 | BEGIN_FTR_SECTION |
1546 | /* DPDES is shared between threads */ | |
1547 | mfspr r7, SPRN_DPDES | |
1548 | std r7, VCORE_DPDES(r5) | |
1549 | /* clear DPDES so we don't get guest doorbells in the host */ | |
1550 | li r8, 0 | |
1551 | mtspr SPRN_DPDES, r8 | |
1552 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
1553 | ||
93b0f4dc PM |
1554 | /* Subtract timebase offset from timebase */ |
1555 | ld r8,VCORE_TB_OFFSET(r5) | |
1556 | cmpdi r8,0 | |
1557 | beq 17f | |
c5fb80d3 | 1558 | mftb r6 /* current guest timebase */ |
93b0f4dc PM |
1559 | subf r8,r8,r6 |
1560 | mtspr SPRN_TBU40,r8 /* update upper 40 bits */ | |
1561 | mftb r7 /* check if lower 24 bits overflowed */ | |
1562 | clrldi r6,r6,40 | |
1563 | clrldi r7,r7,40 | |
1564 | cmpld r7,r6 | |
1565 | bge 17f | |
1566 | addis r8,r8,0x100 /* if so, increment upper 40 bits */ | |
1567 | mtspr SPRN_TBU40,r8 | |
1568 | ||
388cc6e1 PM |
1569 | /* Reset PCR */ |
1570 | 17: ld r0, VCORE_PCR(r5) | |
1571 | cmpdi r0, 0 | |
1572 | beq 18f | |
1573 | li r0, 0 | |
1574 | mtspr SPRN_PCR, r0 | |
1575 | 18: | |
93b0f4dc | 1576 | /* Signal secondary CPUs to continue */ |
371fefd6 | 1577 | stb r0,VCORE_IN_GUEST(r5) |
de56a948 PM |
1578 | lis r8,0x7fff /* MAX_INT@h */ |
1579 | mtspr SPRN_HDEC,r8 | |
1580 | ||
371fefd6 | 1581 | 16: ld r8,KVM_HOST_LPCR(r4) |
de56a948 PM |
1582 | mtspr SPRN_LPCR,r8 |
1583 | isync | |
1584 | ||
1585 | /* load host SLB entries */ | |
c17b98cf | 1586 | ld r8,PACA_SLBSHADOWPTR(r13) |
de56a948 PM |
1587 | |
1588 | .rept SLB_NUM_BOLTED | |
0865a583 AG |
1589 | li r3, SLBSHADOW_SAVEAREA |
1590 | LDX_BE r5, r8, r3 | |
1591 | addi r3, r3, 8 | |
1592 | LDX_BE r6, r8, r3 | |
de56a948 PM |
1593 | andis. r7,r5,SLB_ESID_V@h |
1594 | beq 1f | |
1595 | slbmte r6,r5 | |
1596 | 1: addi r8,r8,16 | |
1597 | .endr | |
1598 | ||
b6c295df PM |
1599 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
1600 | /* Finish timing, if we have a vcpu */ | |
1601 | ld r4, HSTATE_KVM_VCPU(r13) | |
1602 | cmpdi r4, 0 | |
1603 | li r3, 0 | |
1604 | beq 2f | |
1605 | bl kvmhv_accumulate_time | |
1606 | 2: | |
1607 | #endif | |
44a3add8 PM |
1608 | /* Unset guest mode */ |
1609 | li r0, KVM_GUEST_MODE_NONE | |
1610 | stb r0, HSTATE_IN_GUEST(r13) | |
1611 | ||
218309b7 PM |
1612 | ld r0, 112+PPC_LR_STKOFF(r1) |
1613 | addi r1, r1, 112 | |
1614 | mtlr r0 | |
1615 | blr | |
b4072df4 | 1616 | |
6af27c84 PM |
1617 | kvmhv_commence_exit: /* r12 = trap, r13 = paca, doesn't trash r9 */ |
1618 | mflr r0 | |
1619 | std r0, PPC_LR_STKOFF(r1) | |
1620 | stdu r1, -PPC_MIN_STKFRM(r1) | |
1621 | ||
1622 | /* Set our bit in the threads-exiting-guest map in the 0xff00 | |
1623 | bits of vcore->entry_exit_map */ | |
1624 | ld r5, HSTATE_KVM_VCORE(r13) | |
1625 | lbz r4, HSTATE_PTID(r13) | |
1626 | li r7, 0x100 | |
1627 | sld r7, r7, r4 | |
1628 | addi r6, r5, VCORE_ENTRY_EXIT | |
1629 | 41: lwarx r3, 0, r6 | |
1630 | or r0, r3, r7 | |
1631 | stwcx. r0, 0, r6 | |
1632 | bne 41b | |
1633 | isync /* order stwcx. vs. reading napping_threads */ | |
1634 | ||
1635 | /* | |
1636 | * At this point we have an interrupt that we have to pass | |
1637 | * up to the kernel or qemu; we can't handle it in real mode. | |
1638 | * Thus we have to do a partition switch, so we have to | |
1639 | * collect the other threads, if we are the first thread | |
1640 | * to take an interrupt. To do this, we send a message or | |
1641 | * IPI to all the threads that have their bit set in the entry | |
1642 | * map in vcore->entry_exit_map (other than ourselves). | |
1643 | * However, we don't need to bother if this is an HDEC | |
1644 | * interrupt, since the other threads will already be on their | |
1645 | * way here in that case. | |
1646 | */ | |
1647 | cmpwi r3,0x100 /* Are we the first here? */ | |
1648 | bge 43f | |
1649 | cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
1650 | beq 43f | |
1651 | ||
1652 | srwi r0,r7,8 | |
1653 | andc. r3,r3,r0 /* no sense IPI'ing ourselves */ | |
1654 | beq 43f | |
1655 | /* Order entry/exit update vs. IPIs */ | |
1656 | sync | |
1657 | mulli r4,r4,PACA_SIZE /* get paca for thread 0 */ | |
1658 | subf r6,r4,r13 | |
1659 | 42: andi. r0,r3,1 | |
1660 | beq 44f | |
1661 | ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */ | |
1662 | li r0,IPI_PRIORITY | |
1663 | li r7,XICS_MFRR | |
1664 | stbcix r0,r7,r8 /* trigger the IPI */ | |
1665 | 44: srdi. r3,r3,1 | |
1666 | addi r6,r6,PACA_SIZE | |
1667 | bne 42b | |
1668 | ||
1669 | 43: ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1) | |
1670 | addi r1, r1, PPC_MIN_STKFRM | |
1671 | mtlr r0 | |
1672 | blr | |
1673 | ||
697d3899 PM |
1674 | /* |
1675 | * Check whether an HDSI is an HPTE not found fault or something else. | |
1676 | * If it is an HPTE not found fault that is due to the guest accessing | |
1677 | * a page that they have mapped but which we have paged out, then | |
1678 | * we continue on with the guest exit path. In all other cases, | |
1679 | * reflect the HDSI to the guest as a DSI. | |
1680 | */ | |
1681 | kvmppc_hdsi: | |
1682 | mfspr r4, SPRN_HDAR | |
1683 | mfspr r6, SPRN_HDSISR | |
4cf302bc PM |
1684 | /* HPTE not found fault or protection fault? */ |
1685 | andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h | |
697d3899 PM |
1686 | beq 1f /* if not, send it to the guest */ |
1687 | andi. r0, r11, MSR_DR /* data relocation enabled? */ | |
1688 | beq 3f | |
1689 | clrrdi r0, r4, 28 | |
c75df6f9 | 1690 | PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */ |
697d3899 PM |
1691 | bne 1f /* if no SLB entry found */ |
1692 | 4: std r4, VCPU_FAULT_DAR(r9) | |
1693 | stw r6, VCPU_FAULT_DSISR(r9) | |
1694 | ||
1695 | /* Search the hash table. */ | |
1696 | mr r3, r9 /* vcpu pointer */ | |
342d3db7 | 1697 | li r7, 1 /* data fault */ |
b1576fec | 1698 | bl kvmppc_hpte_hv_fault |
697d3899 PM |
1699 | ld r9, HSTATE_KVM_VCPU(r13) |
1700 | ld r10, VCPU_PC(r9) | |
1701 | ld r11, VCPU_MSR(r9) | |
1702 | li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE | |
1703 | cmpdi r3, 0 /* retry the instruction */ | |
1704 | beq 6f | |
1705 | cmpdi r3, -1 /* handle in kernel mode */ | |
b4072df4 | 1706 | beq guest_exit_cont |
697d3899 PM |
1707 | cmpdi r3, -2 /* MMIO emulation; need instr word */ |
1708 | beq 2f | |
1709 | ||
1710 | /* Synthesize a DSI for the guest */ | |
1711 | ld r4, VCPU_FAULT_DAR(r9) | |
1712 | mr r6, r3 | |
1713 | 1: mtspr SPRN_DAR, r4 | |
1714 | mtspr SPRN_DSISR, r6 | |
1715 | mtspr SPRN_SRR0, r10 | |
1716 | mtspr SPRN_SRR1, r11 | |
1717 | li r10, BOOK3S_INTERRUPT_DATA_STORAGE | |
e4e38121 | 1718 | bl kvmppc_msr_interrupt |
b4072df4 | 1719 | fast_interrupt_c_return: |
697d3899 PM |
1720 | 6: ld r7, VCPU_CTR(r9) |
1721 | lwz r8, VCPU_XER(r9) | |
1722 | mtctr r7 | |
1723 | mtxer r8 | |
1724 | mr r4, r9 | |
1725 | b fast_guest_return | |
1726 | ||
1727 | 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */ | |
1728 | ld r5, KVM_VRMA_SLB_V(r5) | |
1729 | b 4b | |
1730 | ||
1731 | /* If this is for emulated MMIO, load the instruction word */ | |
1732 | 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */ | |
1733 | ||
1734 | /* Set guest mode to 'jump over instruction' so if lwz faults | |
1735 | * we'll just continue at the next IP. */ | |
1736 | li r0, KVM_GUEST_MODE_SKIP | |
1737 | stb r0, HSTATE_IN_GUEST(r13) | |
1738 | ||
1739 | /* Do the access with MSR:DR enabled */ | |
1740 | mfmsr r3 | |
1741 | ori r4, r3, MSR_DR /* Enable paging for data */ | |
1742 | mtmsrd r4 | |
1743 | lwz r8, 0(r10) | |
1744 | mtmsrd r3 | |
1745 | ||
1746 | /* Store the result */ | |
1747 | stw r8, VCPU_LAST_INST(r9) | |
1748 | ||
1749 | /* Unset guest mode. */ | |
44a3add8 | 1750 | li r0, KVM_GUEST_MODE_HOST_HV |
697d3899 | 1751 | stb r0, HSTATE_IN_GUEST(r13) |
b4072df4 | 1752 | b guest_exit_cont |
de56a948 | 1753 | |
342d3db7 PM |
1754 | /* |
1755 | * Similarly for an HISI, reflect it to the guest as an ISI unless | |
1756 | * it is an HPTE not found fault for a page that we have paged out. | |
1757 | */ | |
1758 | kvmppc_hisi: | |
1759 | andis. r0, r11, SRR1_ISI_NOPT@h | |
1760 | beq 1f | |
1761 | andi. r0, r11, MSR_IR /* instruction relocation enabled? */ | |
1762 | beq 3f | |
1763 | clrrdi r0, r10, 28 | |
c75df6f9 | 1764 | PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */ |
342d3db7 PM |
1765 | bne 1f /* if no SLB entry found */ |
1766 | 4: | |
1767 | /* Search the hash table. */ | |
1768 | mr r3, r9 /* vcpu pointer */ | |
1769 | mr r4, r10 | |
1770 | mr r6, r11 | |
1771 | li r7, 0 /* instruction fault */ | |
b1576fec | 1772 | bl kvmppc_hpte_hv_fault |
342d3db7 PM |
1773 | ld r9, HSTATE_KVM_VCPU(r13) |
1774 | ld r10, VCPU_PC(r9) | |
1775 | ld r11, VCPU_MSR(r9) | |
1776 | li r12, BOOK3S_INTERRUPT_H_INST_STORAGE | |
1777 | cmpdi r3, 0 /* retry the instruction */ | |
b4072df4 | 1778 | beq fast_interrupt_c_return |
342d3db7 | 1779 | cmpdi r3, -1 /* handle in kernel mode */ |
b4072df4 | 1780 | beq guest_exit_cont |
342d3db7 PM |
1781 | |
1782 | /* Synthesize an ISI for the guest */ | |
1783 | mr r11, r3 | |
1784 | 1: mtspr SPRN_SRR0, r10 | |
1785 | mtspr SPRN_SRR1, r11 | |
1786 | li r10, BOOK3S_INTERRUPT_INST_STORAGE | |
e4e38121 | 1787 | bl kvmppc_msr_interrupt |
b4072df4 | 1788 | b fast_interrupt_c_return |
342d3db7 PM |
1789 | |
1790 | 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */ | |
1791 | ld r5, KVM_VRMA_SLB_V(r6) | |
1792 | b 4b | |
1793 | ||
a8606e20 PM |
1794 | /* |
1795 | * Try to handle an hcall in real mode. | |
1796 | * Returns to the guest if we handle it, or continues on up to | |
1797 | * the kernel if we can't (i.e. if we don't have a handler for | |
1798 | * it, or if the handler returns H_TOO_HARD). | |
1f09c3ed PM |
1799 | * |
1800 | * r5 - r8 contain hcall args, | |
1801 | * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca | |
a8606e20 | 1802 | */ |
a8606e20 | 1803 | hcall_try_real_mode: |
c75df6f9 | 1804 | ld r3,VCPU_GPR(R3)(r9) |
a8606e20 | 1805 | andi. r0,r11,MSR_PR |
27025a60 LPF |
1806 | /* sc 1 from userspace - reflect to guest syscall */ |
1807 | bne sc_1_fast_return | |
a8606e20 PM |
1808 | clrrdi r3,r3,2 |
1809 | cmpldi r3,hcall_real_table_end - hcall_real_table | |
b4072df4 | 1810 | bge guest_exit_cont |
699a0ea0 PM |
1811 | /* See if this hcall is enabled for in-kernel handling */ |
1812 | ld r4, VCPU_KVM(r9) | |
1813 | srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */ | |
1814 | sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */ | |
1815 | add r4, r4, r0 | |
1816 | ld r0, KVM_ENABLED_HCALLS(r4) | |
1817 | rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */ | |
1818 | srd r0, r0, r4 | |
1819 | andi. r0, r0, 1 | |
1820 | beq guest_exit_cont | |
1821 | /* Get pointer to handler, if any, and call it */ | |
a8606e20 | 1822 | LOAD_REG_ADDR(r4, hcall_real_table) |
4baa1d87 | 1823 | lwax r3,r3,r4 |
a8606e20 | 1824 | cmpwi r3,0 |
b4072df4 | 1825 | beq guest_exit_cont |
05a308c7 AB |
1826 | add r12,r3,r4 |
1827 | mtctr r12 | |
a8606e20 | 1828 | mr r3,r9 /* get vcpu pointer */ |
c75df6f9 | 1829 | ld r4,VCPU_GPR(R4)(r9) |
a8606e20 PM |
1830 | bctrl |
1831 | cmpdi r3,H_TOO_HARD | |
1832 | beq hcall_real_fallback | |
1833 | ld r4,HSTATE_KVM_VCPU(r13) | |
c75df6f9 | 1834 | std r3,VCPU_GPR(R3)(r4) |
a8606e20 PM |
1835 | ld r10,VCPU_PC(r4) |
1836 | ld r11,VCPU_MSR(r4) | |
1837 | b fast_guest_return | |
1838 | ||
27025a60 LPF |
1839 | sc_1_fast_return: |
1840 | mtspr SPRN_SRR0,r10 | |
1841 | mtspr SPRN_SRR1,r11 | |
1842 | li r10, BOOK3S_INTERRUPT_SYSCALL | |
e4e38121 | 1843 | bl kvmppc_msr_interrupt |
27025a60 LPF |
1844 | mr r4,r9 |
1845 | b fast_guest_return | |
1846 | ||
a8606e20 PM |
1847 | /* We've attempted a real mode hcall, but it's punted it back |
1848 | * to userspace. We need to restore some clobbered volatiles | |
1849 | * before resuming the pass-it-to-qemu path */ | |
1850 | hcall_real_fallback: | |
1851 | li r12,BOOK3S_INTERRUPT_SYSCALL | |
1852 | ld r9, HSTATE_KVM_VCPU(r13) | |
a8606e20 | 1853 | |
b4072df4 | 1854 | b guest_exit_cont |
a8606e20 PM |
1855 | |
1856 | .globl hcall_real_table | |
1857 | hcall_real_table: | |
1858 | .long 0 /* 0 - unused */ | |
c1fb0194 AB |
1859 | .long DOTSYM(kvmppc_h_remove) - hcall_real_table |
1860 | .long DOTSYM(kvmppc_h_enter) - hcall_real_table | |
1861 | .long DOTSYM(kvmppc_h_read) - hcall_real_table | |
a8606e20 PM |
1862 | .long 0 /* 0x10 - H_CLEAR_MOD */ |
1863 | .long 0 /* 0x14 - H_CLEAR_REF */ | |
c1fb0194 AB |
1864 | .long DOTSYM(kvmppc_h_protect) - hcall_real_table |
1865 | .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table | |
1866 | .long DOTSYM(kvmppc_h_put_tce) - hcall_real_table | |
a8606e20 | 1867 | .long 0 /* 0x24 - H_SET_SPRG0 */ |
c1fb0194 | 1868 | .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table |
a8606e20 PM |
1869 | .long 0 /* 0x2c */ |
1870 | .long 0 /* 0x30 */ | |
1871 | .long 0 /* 0x34 */ | |
1872 | .long 0 /* 0x38 */ | |
1873 | .long 0 /* 0x3c */ | |
1874 | .long 0 /* 0x40 */ | |
1875 | .long 0 /* 0x44 */ | |
1876 | .long 0 /* 0x48 */ | |
1877 | .long 0 /* 0x4c */ | |
1878 | .long 0 /* 0x50 */ | |
1879 | .long 0 /* 0x54 */ | |
1880 | .long 0 /* 0x58 */ | |
1881 | .long 0 /* 0x5c */ | |
1882 | .long 0 /* 0x60 */ | |
e7d26f28 | 1883 | #ifdef CONFIG_KVM_XICS |
c1fb0194 AB |
1884 | .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table |
1885 | .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table | |
1886 | .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table | |
e7d26f28 | 1887 | .long 0 /* 0x70 - H_IPOLL */ |
c1fb0194 | 1888 | .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table |
e7d26f28 BH |
1889 | #else |
1890 | .long 0 /* 0x64 - H_EOI */ | |
1891 | .long 0 /* 0x68 - H_CPPR */ | |
1892 | .long 0 /* 0x6c - H_IPI */ | |
1893 | .long 0 /* 0x70 - H_IPOLL */ | |
1894 | .long 0 /* 0x74 - H_XIRR */ | |
1895 | #endif | |
a8606e20 PM |
1896 | .long 0 /* 0x78 */ |
1897 | .long 0 /* 0x7c */ | |
1898 | .long 0 /* 0x80 */ | |
1899 | .long 0 /* 0x84 */ | |
1900 | .long 0 /* 0x88 */ | |
1901 | .long 0 /* 0x8c */ | |
1902 | .long 0 /* 0x90 */ | |
1903 | .long 0 /* 0x94 */ | |
1904 | .long 0 /* 0x98 */ | |
1905 | .long 0 /* 0x9c */ | |
1906 | .long 0 /* 0xa0 */ | |
1907 | .long 0 /* 0xa4 */ | |
1908 | .long 0 /* 0xa8 */ | |
1909 | .long 0 /* 0xac */ | |
1910 | .long 0 /* 0xb0 */ | |
1911 | .long 0 /* 0xb4 */ | |
1912 | .long 0 /* 0xb8 */ | |
1913 | .long 0 /* 0xbc */ | |
1914 | .long 0 /* 0xc0 */ | |
1915 | .long 0 /* 0xc4 */ | |
1916 | .long 0 /* 0xc8 */ | |
1917 | .long 0 /* 0xcc */ | |
1918 | .long 0 /* 0xd0 */ | |
1919 | .long 0 /* 0xd4 */ | |
1920 | .long 0 /* 0xd8 */ | |
1921 | .long 0 /* 0xdc */ | |
c1fb0194 | 1922 | .long DOTSYM(kvmppc_h_cede) - hcall_real_table |
90fd09f8 | 1923 | .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table |
a8606e20 PM |
1924 | .long 0 /* 0xe8 */ |
1925 | .long 0 /* 0xec */ | |
1926 | .long 0 /* 0xf0 */ | |
1927 | .long 0 /* 0xf4 */ | |
1928 | .long 0 /* 0xf8 */ | |
1929 | .long 0 /* 0xfc */ | |
1930 | .long 0 /* 0x100 */ | |
1931 | .long 0 /* 0x104 */ | |
1932 | .long 0 /* 0x108 */ | |
1933 | .long 0 /* 0x10c */ | |
1934 | .long 0 /* 0x110 */ | |
1935 | .long 0 /* 0x114 */ | |
1936 | .long 0 /* 0x118 */ | |
1937 | .long 0 /* 0x11c */ | |
1938 | .long 0 /* 0x120 */ | |
c1fb0194 | 1939 | .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table |
8563bf52 PM |
1940 | .long 0 /* 0x128 */ |
1941 | .long 0 /* 0x12c */ | |
1942 | .long 0 /* 0x130 */ | |
c1fb0194 | 1943 | .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table |
e928e9cb ME |
1944 | .long 0 /* 0x138 */ |
1945 | .long 0 /* 0x13c */ | |
1946 | .long 0 /* 0x140 */ | |
1947 | .long 0 /* 0x144 */ | |
1948 | .long 0 /* 0x148 */ | |
1949 | .long 0 /* 0x14c */ | |
1950 | .long 0 /* 0x150 */ | |
1951 | .long 0 /* 0x154 */ | |
1952 | .long 0 /* 0x158 */ | |
1953 | .long 0 /* 0x15c */ | |
1954 | .long 0 /* 0x160 */ | |
1955 | .long 0 /* 0x164 */ | |
1956 | .long 0 /* 0x168 */ | |
1957 | .long 0 /* 0x16c */ | |
1958 | .long 0 /* 0x170 */ | |
1959 | .long 0 /* 0x174 */ | |
1960 | .long 0 /* 0x178 */ | |
1961 | .long 0 /* 0x17c */ | |
1962 | .long 0 /* 0x180 */ | |
1963 | .long 0 /* 0x184 */ | |
1964 | .long 0 /* 0x188 */ | |
1965 | .long 0 /* 0x18c */ | |
1966 | .long 0 /* 0x190 */ | |
1967 | .long 0 /* 0x194 */ | |
1968 | .long 0 /* 0x198 */ | |
1969 | .long 0 /* 0x19c */ | |
1970 | .long 0 /* 0x1a0 */ | |
1971 | .long 0 /* 0x1a4 */ | |
1972 | .long 0 /* 0x1a8 */ | |
1973 | .long 0 /* 0x1ac */ | |
1974 | .long 0 /* 0x1b0 */ | |
1975 | .long 0 /* 0x1b4 */ | |
1976 | .long 0 /* 0x1b8 */ | |
1977 | .long 0 /* 0x1bc */ | |
1978 | .long 0 /* 0x1c0 */ | |
1979 | .long 0 /* 0x1c4 */ | |
1980 | .long 0 /* 0x1c8 */ | |
1981 | .long 0 /* 0x1cc */ | |
1982 | .long 0 /* 0x1d0 */ | |
1983 | .long 0 /* 0x1d4 */ | |
1984 | .long 0 /* 0x1d8 */ | |
1985 | .long 0 /* 0x1dc */ | |
1986 | .long 0 /* 0x1e0 */ | |
1987 | .long 0 /* 0x1e4 */ | |
1988 | .long 0 /* 0x1e8 */ | |
1989 | .long 0 /* 0x1ec */ | |
1990 | .long 0 /* 0x1f0 */ | |
1991 | .long 0 /* 0x1f4 */ | |
1992 | .long 0 /* 0x1f8 */ | |
1993 | .long 0 /* 0x1fc */ | |
1994 | .long 0 /* 0x200 */ | |
1995 | .long 0 /* 0x204 */ | |
1996 | .long 0 /* 0x208 */ | |
1997 | .long 0 /* 0x20c */ | |
1998 | .long 0 /* 0x210 */ | |
1999 | .long 0 /* 0x214 */ | |
2000 | .long 0 /* 0x218 */ | |
2001 | .long 0 /* 0x21c */ | |
2002 | .long 0 /* 0x220 */ | |
2003 | .long 0 /* 0x224 */ | |
2004 | .long 0 /* 0x228 */ | |
2005 | .long 0 /* 0x22c */ | |
2006 | .long 0 /* 0x230 */ | |
2007 | .long 0 /* 0x234 */ | |
2008 | .long 0 /* 0x238 */ | |
2009 | .long 0 /* 0x23c */ | |
2010 | .long 0 /* 0x240 */ | |
2011 | .long 0 /* 0x244 */ | |
2012 | .long 0 /* 0x248 */ | |
2013 | .long 0 /* 0x24c */ | |
2014 | .long 0 /* 0x250 */ | |
2015 | .long 0 /* 0x254 */ | |
2016 | .long 0 /* 0x258 */ | |
2017 | .long 0 /* 0x25c */ | |
2018 | .long 0 /* 0x260 */ | |
2019 | .long 0 /* 0x264 */ | |
2020 | .long 0 /* 0x268 */ | |
2021 | .long 0 /* 0x26c */ | |
2022 | .long 0 /* 0x270 */ | |
2023 | .long 0 /* 0x274 */ | |
2024 | .long 0 /* 0x278 */ | |
2025 | .long 0 /* 0x27c */ | |
2026 | .long 0 /* 0x280 */ | |
2027 | .long 0 /* 0x284 */ | |
2028 | .long 0 /* 0x288 */ | |
2029 | .long 0 /* 0x28c */ | |
2030 | .long 0 /* 0x290 */ | |
2031 | .long 0 /* 0x294 */ | |
2032 | .long 0 /* 0x298 */ | |
2033 | .long 0 /* 0x29c */ | |
2034 | .long 0 /* 0x2a0 */ | |
2035 | .long 0 /* 0x2a4 */ | |
2036 | .long 0 /* 0x2a8 */ | |
2037 | .long 0 /* 0x2ac */ | |
2038 | .long 0 /* 0x2b0 */ | |
2039 | .long 0 /* 0x2b4 */ | |
2040 | .long 0 /* 0x2b8 */ | |
2041 | .long 0 /* 0x2bc */ | |
2042 | .long 0 /* 0x2c0 */ | |
2043 | .long 0 /* 0x2c4 */ | |
2044 | .long 0 /* 0x2c8 */ | |
2045 | .long 0 /* 0x2cc */ | |
2046 | .long 0 /* 0x2d0 */ | |
2047 | .long 0 /* 0x2d4 */ | |
2048 | .long 0 /* 0x2d8 */ | |
2049 | .long 0 /* 0x2dc */ | |
2050 | .long 0 /* 0x2e0 */ | |
2051 | .long 0 /* 0x2e4 */ | |
2052 | .long 0 /* 0x2e8 */ | |
2053 | .long 0 /* 0x2ec */ | |
2054 | .long 0 /* 0x2f0 */ | |
2055 | .long 0 /* 0x2f4 */ | |
2056 | .long 0 /* 0x2f8 */ | |
2057 | .long 0 /* 0x2fc */ | |
2058 | .long DOTSYM(kvmppc_h_random) - hcall_real_table | |
ae2113a4 | 2059 | .globl hcall_real_table_end |
a8606e20 PM |
2060 | hcall_real_table_end: |
2061 | ||
8563bf52 PM |
2062 | _GLOBAL(kvmppc_h_set_xdabr) |
2063 | andi. r0, r5, DABRX_USER | DABRX_KERNEL | |
2064 | beq 6f | |
2065 | li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI | |
2066 | andc. r0, r5, r0 | |
2067 | beq 3f | |
2068 | 6: li r3, H_PARAMETER | |
2069 | blr | |
2070 | ||
a8606e20 | 2071 | _GLOBAL(kvmppc_h_set_dabr) |
8563bf52 PM |
2072 | li r5, DABRX_USER | DABRX_KERNEL |
2073 | 3: | |
eee7ff9d MN |
2074 | BEGIN_FTR_SECTION |
2075 | b 2f | |
2076 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
a8606e20 | 2077 | std r4,VCPU_DABR(r3) |
8563bf52 PM |
2078 | stw r5, VCPU_DABRX(r3) |
2079 | mtspr SPRN_DABRX, r5 | |
8943633c PM |
2080 | /* Work around P7 bug where DABR can get corrupted on mtspr */ |
2081 | 1: mtspr SPRN_DABR,r4 | |
2082 | mfspr r5, SPRN_DABR | |
2083 | cmpd r4, r5 | |
2084 | bne 1b | |
2085 | isync | |
a8606e20 PM |
2086 | li r3,0 |
2087 | blr | |
2088 | ||
8563bf52 PM |
2089 | /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */ |
2090 | 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW | |
2091 | rlwimi r5, r4, 1, DAWRX_WT | |
2092 | clrrdi r4, r4, 3 | |
2093 | std r4, VCPU_DAWR(r3) | |
2094 | std r5, VCPU_DAWRX(r3) | |
2095 | mtspr SPRN_DAWR, r4 | |
2096 | mtspr SPRN_DAWRX, r5 | |
2097 | li r3, 0 | |
a8606e20 PM |
2098 | blr |
2099 | ||
1f09c3ed | 2100 | _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */ |
19ccb76a PM |
2101 | ori r11,r11,MSR_EE |
2102 | std r11,VCPU_MSR(r3) | |
2103 | li r0,1 | |
2104 | stb r0,VCPU_CEDED(r3) | |
2105 | sync /* order setting ceded vs. testing prodded */ | |
2106 | lbz r5,VCPU_PRODDED(r3) | |
2107 | cmpwi r5,0 | |
04f995a5 | 2108 | bne kvm_cede_prodded |
6af27c84 PM |
2109 | li r12,0 /* set trap to 0 to say hcall is handled */ |
2110 | stw r12,VCPU_TRAP(r3) | |
19ccb76a | 2111 | li r0,H_SUCCESS |
c75df6f9 | 2112 | std r0,VCPU_GPR(R3)(r3) |
19ccb76a PM |
2113 | |
2114 | /* | |
2115 | * Set our bit in the bitmask of napping threads unless all the | |
2116 | * other threads are already napping, in which case we send this | |
2117 | * up to the host. | |
2118 | */ | |
2119 | ld r5,HSTATE_KVM_VCORE(r13) | |
e0b7ec05 | 2120 | lbz r6,HSTATE_PTID(r13) |
19ccb76a PM |
2121 | lwz r8,VCORE_ENTRY_EXIT(r5) |
2122 | clrldi r8,r8,56 | |
2123 | li r0,1 | |
2124 | sld r0,r0,r6 | |
2125 | addi r6,r5,VCORE_NAPPING_THREADS | |
2126 | 31: lwarx r4,0,r6 | |
2127 | or r4,r4,r0 | |
7d6c40da PM |
2128 | cmpw r4,r8 |
2129 | beq kvm_cede_exit | |
19ccb76a PM |
2130 | stwcx. r4,0,r6 |
2131 | bne 31b | |
7d6c40da | 2132 | /* order napping_threads update vs testing entry_exit_map */ |
f019b7ad | 2133 | isync |
e0b7ec05 | 2134 | li r0,NAPPING_CEDE |
19ccb76a | 2135 | stb r0,HSTATE_NAPPING(r13) |
19ccb76a PM |
2136 | lwz r7,VCORE_ENTRY_EXIT(r5) |
2137 | cmpwi r7,0x100 | |
2138 | bge 33f /* another thread already exiting */ | |
2139 | ||
2140 | /* | |
2141 | * Although not specifically required by the architecture, POWER7 | |
2142 | * preserves the following registers in nap mode, even if an SMT mode | |
2143 | * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3, | |
2144 | * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR. | |
2145 | */ | |
2146 | /* Save non-volatile GPRs */ | |
c75df6f9 MN |
2147 | std r14, VCPU_GPR(R14)(r3) |
2148 | std r15, VCPU_GPR(R15)(r3) | |
2149 | std r16, VCPU_GPR(R16)(r3) | |
2150 | std r17, VCPU_GPR(R17)(r3) | |
2151 | std r18, VCPU_GPR(R18)(r3) | |
2152 | std r19, VCPU_GPR(R19)(r3) | |
2153 | std r20, VCPU_GPR(R20)(r3) | |
2154 | std r21, VCPU_GPR(R21)(r3) | |
2155 | std r22, VCPU_GPR(R22)(r3) | |
2156 | std r23, VCPU_GPR(R23)(r3) | |
2157 | std r24, VCPU_GPR(R24)(r3) | |
2158 | std r25, VCPU_GPR(R25)(r3) | |
2159 | std r26, VCPU_GPR(R26)(r3) | |
2160 | std r27, VCPU_GPR(R27)(r3) | |
2161 | std r28, VCPU_GPR(R28)(r3) | |
2162 | std r29, VCPU_GPR(R29)(r3) | |
2163 | std r30, VCPU_GPR(R30)(r3) | |
2164 | std r31, VCPU_GPR(R31)(r3) | |
19ccb76a PM |
2165 | |
2166 | /* save FP state */ | |
595e4f7e | 2167 | bl kvmppc_save_fp |
19ccb76a | 2168 | |
fd6d53b1 PM |
2169 | /* |
2170 | * Set DEC to the smaller of DEC and HDEC, so that we wake | |
2171 | * no later than the end of our timeslice (HDEC interrupts | |
2172 | * don't wake us from nap). | |
2173 | */ | |
2174 | mfspr r3, SPRN_DEC | |
2175 | mfspr r4, SPRN_HDEC | |
2176 | mftb r5 | |
2177 | cmpw r3, r4 | |
2178 | ble 67f | |
2179 | mtspr SPRN_DEC, r4 | |
2180 | 67: | |
2181 | /* save expiry time of guest decrementer */ | |
2182 | extsw r3, r3 | |
2183 | add r3, r3, r5 | |
2184 | ld r4, HSTATE_KVM_VCPU(r13) | |
2185 | ld r5, HSTATE_KVM_VCORE(r13) | |
2186 | ld r6, VCORE_TB_OFFSET(r5) | |
2187 | subf r3, r6, r3 /* convert to host TB value */ | |
2188 | std r3, VCPU_DEC_EXPIRES(r4) | |
2189 | ||
b6c295df PM |
2190 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
2191 | ld r4, HSTATE_KVM_VCPU(r13) | |
2192 | addi r3, r4, VCPU_TB_CEDE | |
2193 | bl kvmhv_accumulate_time | |
2194 | #endif | |
2195 | ||
ccc07772 PM |
2196 | lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */ |
2197 | ||
19ccb76a | 2198 | /* |
aa31e843 | 2199 | * Take a nap until a decrementer or external or doobell interrupt |
ccc07772 PM |
2200 | * occurs, with PECE1 and PECE0 set in LPCR. |
2201 | * On POWER8, if we are ceding, also set PECEDP. | |
2202 | * Also clear the runlatch bit before napping. | |
19ccb76a | 2203 | */ |
56548fc0 | 2204 | kvm_do_nap: |
1f09c3ed PM |
2205 | mfspr r0, SPRN_CTRLF |
2206 | clrrdi r0, r0, 1 | |
2207 | mtspr SPRN_CTRLT, r0 | |
582b910e | 2208 | |
f0888f70 PM |
2209 | li r0,1 |
2210 | stb r0,HSTATE_HWTHREAD_REQ(r13) | |
19ccb76a PM |
2211 | mfspr r5,SPRN_LPCR |
2212 | ori r5,r5,LPCR_PECE0 | LPCR_PECE1 | |
aa31e843 | 2213 | BEGIN_FTR_SECTION |
ccc07772 | 2214 | rlwimi r5, r3, 0, LPCR_PECEDP |
aa31e843 | 2215 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
19ccb76a PM |
2216 | mtspr SPRN_LPCR,r5 |
2217 | isync | |
2218 | li r0, 0 | |
2219 | std r0, HSTATE_SCRATCH0(r13) | |
2220 | ptesync | |
2221 | ld r0, HSTATE_SCRATCH0(r13) | |
2222 | 1: cmpd r0, r0 | |
2223 | bne 1b | |
2224 | nap | |
2225 | b . | |
2226 | ||
e3bbbbfa PM |
2227 | 33: mr r4, r3 |
2228 | li r3, 0 | |
2229 | li r12, 0 | |
2230 | b 34f | |
2231 | ||
19ccb76a | 2232 | kvm_end_cede: |
4619ac88 PM |
2233 | /* get vcpu pointer */ |
2234 | ld r4, HSTATE_KVM_VCPU(r13) | |
2235 | ||
19ccb76a PM |
2236 | /* Woken by external or decrementer interrupt */ |
2237 | ld r1, HSTATE_HOST_R1(r13) | |
19ccb76a | 2238 | |
b6c295df PM |
2239 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING |
2240 | addi r3, r4, VCPU_TB_RMINTR | |
2241 | bl kvmhv_accumulate_time | |
2242 | #endif | |
2243 | ||
19ccb76a PM |
2244 | /* load up FP state */ |
2245 | bl kvmppc_load_fp | |
2246 | ||
fd6d53b1 PM |
2247 | /* Restore guest decrementer */ |
2248 | ld r3, VCPU_DEC_EXPIRES(r4) | |
2249 | ld r5, HSTATE_KVM_VCORE(r13) | |
2250 | ld r6, VCORE_TB_OFFSET(r5) | |
2251 | add r3, r3, r6 /* convert host TB to guest TB value */ | |
2252 | mftb r7 | |
2253 | subf r3, r7, r3 | |
2254 | mtspr SPRN_DEC, r3 | |
2255 | ||
19ccb76a | 2256 | /* Load NV GPRS */ |
c75df6f9 MN |
2257 | ld r14, VCPU_GPR(R14)(r4) |
2258 | ld r15, VCPU_GPR(R15)(r4) | |
2259 | ld r16, VCPU_GPR(R16)(r4) | |
2260 | ld r17, VCPU_GPR(R17)(r4) | |
2261 | ld r18, VCPU_GPR(R18)(r4) | |
2262 | ld r19, VCPU_GPR(R19)(r4) | |
2263 | ld r20, VCPU_GPR(R20)(r4) | |
2264 | ld r21, VCPU_GPR(R21)(r4) | |
2265 | ld r22, VCPU_GPR(R22)(r4) | |
2266 | ld r23, VCPU_GPR(R23)(r4) | |
2267 | ld r24, VCPU_GPR(R24)(r4) | |
2268 | ld r25, VCPU_GPR(R25)(r4) | |
2269 | ld r26, VCPU_GPR(R26)(r4) | |
2270 | ld r27, VCPU_GPR(R27)(r4) | |
2271 | ld r28, VCPU_GPR(R28)(r4) | |
2272 | ld r29, VCPU_GPR(R29)(r4) | |
2273 | ld r30, VCPU_GPR(R30)(r4) | |
2274 | ld r31, VCPU_GPR(R31)(r4) | |
e3bbbbfa PM |
2275 | |
2276 | /* Check the wake reason in SRR1 to see why we got here */ | |
2277 | bl kvmppc_check_wake_reason | |
19ccb76a PM |
2278 | |
2279 | /* clear our bit in vcore->napping_threads */ | |
e3bbbbfa PM |
2280 | 34: ld r5,HSTATE_KVM_VCORE(r13) |
2281 | lbz r7,HSTATE_PTID(r13) | |
19ccb76a | 2282 | li r0,1 |
e3bbbbfa | 2283 | sld r0,r0,r7 |
19ccb76a PM |
2284 | addi r6,r5,VCORE_NAPPING_THREADS |
2285 | 32: lwarx r7,0,r6 | |
2286 | andc r7,r7,r0 | |
2287 | stwcx. r7,0,r6 | |
2288 | bne 32b | |
2289 | li r0,0 | |
2290 | stb r0,HSTATE_NAPPING(r13) | |
2291 | ||
e3bbbbfa PM |
2292 | /* See if the wake reason means we need to exit */ |
2293 | stw r12, VCPU_TRAP(r4) | |
4619ac88 | 2294 | mr r9, r4 |
e3bbbbfa PM |
2295 | cmpdi r3, 0 |
2296 | bgt guest_exit_cont | |
4619ac88 | 2297 | |
19ccb76a PM |
2298 | /* see if any other thread is already exiting */ |
2299 | lwz r0,VCORE_ENTRY_EXIT(r5) | |
2300 | cmpwi r0,0x100 | |
e3bbbbfa | 2301 | bge guest_exit_cont |
19ccb76a | 2302 | |
e3bbbbfa | 2303 | b kvmppc_cede_reentry /* if not go back to guest */ |
19ccb76a PM |
2304 | |
2305 | /* cede when already previously prodded case */ | |
04f995a5 PM |
2306 | kvm_cede_prodded: |
2307 | li r0,0 | |
19ccb76a PM |
2308 | stb r0,VCPU_PRODDED(r3) |
2309 | sync /* order testing prodded vs. clearing ceded */ | |
2310 | stb r0,VCPU_CEDED(r3) | |
2311 | li r3,H_SUCCESS | |
2312 | blr | |
2313 | ||
2314 | /* we've ceded but we want to give control to the host */ | |
04f995a5 | 2315 | kvm_cede_exit: |
6af27c84 PM |
2316 | ld r9, HSTATE_KVM_VCPU(r13) |
2317 | b guest_exit_cont | |
19ccb76a | 2318 | |
b4072df4 PM |
2319 | /* Try to handle a machine check in real mode */ |
2320 | machine_check_realmode: | |
2321 | mr r3, r9 /* get vcpu pointer */ | |
b1576fec | 2322 | bl kvmppc_realmode_machine_check |
b4072df4 | 2323 | nop |
74845bc2 | 2324 | cmpdi r3, 0 /* Did we handle MCE ? */ |
b4072df4 PM |
2325 | ld r9, HSTATE_KVM_VCPU(r13) |
2326 | li r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
74845bc2 MS |
2327 | /* |
2328 | * Deliver unhandled/fatal (e.g. UE) MCE errors to guest through | |
2329 | * machine check interrupt (set HSRR0 to 0x200). And for handled | |
2330 | * errors (no-fatal), just go back to guest execution with current | |
2331 | * HSRR0 instead of exiting guest. This new approach will inject | |
2332 | * machine check to guest for fatal error causing guest to crash. | |
2333 | * | |
2334 | * The old code used to return to host for unhandled errors which | |
2335 | * was causing guest to hang with soft lockups inside guest and | |
2336 | * makes it difficult to recover guest instance. | |
2337 | */ | |
2338 | ld r10, VCPU_PC(r9) | |
2339 | ld r11, VCPU_MSR(r9) | |
2340 | bne 2f /* Continue guest execution. */ | |
b4072df4 PM |
2341 | /* If not, deliver a machine check. SRR0/1 are already set */ |
2342 | li r10, BOOK3S_INTERRUPT_MACHINE_CHECK | |
000a25dd | 2343 | ld r11, VCPU_MSR(r9) |
e4e38121 | 2344 | bl kvmppc_msr_interrupt |
74845bc2 | 2345 | 2: b fast_interrupt_c_return |
b4072df4 | 2346 | |
e3bbbbfa PM |
2347 | /* |
2348 | * Check the reason we woke from nap, and take appropriate action. | |
1f09c3ed | 2349 | * Returns (in r3): |
e3bbbbfa PM |
2350 | * 0 if nothing needs to be done |
2351 | * 1 if something happened that needs to be handled by the host | |
2352 | * -1 if there was a guest wakeup (IPI) | |
2353 | * | |
2354 | * Also sets r12 to the interrupt vector for any interrupt that needs | |
2355 | * to be handled now by the host (0x500 for external interrupt), or zero. | |
1f09c3ed | 2356 | * Modifies r0, r6, r7, r8. |
e3bbbbfa PM |
2357 | */ |
2358 | kvmppc_check_wake_reason: | |
2359 | mfspr r6, SPRN_SRR1 | |
aa31e843 PM |
2360 | BEGIN_FTR_SECTION |
2361 | rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */ | |
2362 | FTR_SECTION_ELSE | |
2363 | rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */ | |
2364 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S) | |
2365 | cmpwi r6, 8 /* was it an external interrupt? */ | |
e3bbbbfa PM |
2366 | li r12, BOOK3S_INTERRUPT_EXTERNAL |
2367 | beq kvmppc_read_intr /* if so, see what it was */ | |
2368 | li r3, 0 | |
2369 | li r12, 0 | |
2370 | cmpwi r6, 6 /* was it the decrementer? */ | |
2371 | beq 0f | |
aa31e843 PM |
2372 | BEGIN_FTR_SECTION |
2373 | cmpwi r6, 5 /* privileged doorbell? */ | |
2374 | beq 0f | |
5d00f66b PM |
2375 | cmpwi r6, 3 /* hypervisor doorbell? */ |
2376 | beq 3f | |
aa31e843 | 2377 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) |
e3bbbbfa PM |
2378 | li r3, 1 /* anything else, return 1 */ |
2379 | 0: blr | |
2380 | ||
5d00f66b PM |
2381 | /* hypervisor doorbell */ |
2382 | 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL | |
2383 | li r3, 1 | |
2384 | blr | |
2385 | ||
c934243c PM |
2386 | /* |
2387 | * Determine what sort of external interrupt is pending (if any). | |
2388 | * Returns: | |
2389 | * 0 if no interrupt is pending | |
2390 | * 1 if an interrupt is pending that needs to be handled by the host | |
2391 | * -1 if there was a guest wakeup IPI (which has now been cleared) | |
1f09c3ed | 2392 | * Modifies r0, r6, r7, r8, returns value in r3. |
c934243c PM |
2393 | */ |
2394 | kvmppc_read_intr: | |
2395 | /* see if a host IPI is pending */ | |
2396 | li r3, 1 | |
2397 | lbz r0, HSTATE_HOST_IPI(r13) | |
2398 | cmpwi r0, 0 | |
2399 | bne 1f | |
371fefd6 | 2400 | |
c934243c PM |
2401 | /* Now read the interrupt from the ICP */ |
2402 | ld r6, HSTATE_XICS_PHYS(r13) | |
19ccb76a | 2403 | li r7, XICS_XIRR |
c934243c PM |
2404 | cmpdi r6, 0 |
2405 | beq- 1f | |
2406 | lwzcix r0, r6, r7 | |
76d072fb AG |
2407 | /* |
2408 | * Save XIRR for later. Since we get in in reverse endian on LE | |
2409 | * systems, save it byte reversed and fetch it back in host endian. | |
2410 | */ | |
2411 | li r3, HSTATE_SAVED_XIRR | |
2412 | STWX_BE r0, r3, r13 | |
2413 | #ifdef __LITTLE_ENDIAN__ | |
2414 | lwz r3, HSTATE_SAVED_XIRR(r13) | |
2415 | #else | |
2416 | mr r3, r0 | |
2417 | #endif | |
2418 | rlwinm. r3, r3, 0, 0xffffff | |
19ccb76a | 2419 | sync |
c934243c | 2420 | beq 1f /* if nothing pending in the ICP */ |
371fefd6 | 2421 | |
c934243c PM |
2422 | /* We found something in the ICP... |
2423 | * | |
2424 | * If it's not an IPI, stash it in the PACA and return to | |
2425 | * the host, we don't (yet) handle directing real external | |
2426 | * interrupts directly to the guest | |
2427 | */ | |
2428 | cmpwi r3, XICS_IPI /* if there is, is it an IPI? */ | |
c934243c | 2429 | bne 42f |
371fefd6 | 2430 | |
c934243c PM |
2431 | /* It's an IPI, clear the MFRR and EOI it */ |
2432 | li r3, 0xff | |
2433 | li r8, XICS_MFRR | |
2434 | stbcix r3, r6, r8 /* clear the IPI */ | |
2435 | stwcix r0, r6, r7 /* EOI it */ | |
2436 | sync | |
f0888f70 | 2437 | |
c934243c PM |
2438 | /* We need to re-check host IPI now in case it got set in the |
2439 | * meantime. If it's clear, we bounce the interrupt to the | |
2440 | * guest | |
2441 | */ | |
2442 | lbz r0, HSTATE_HOST_IPI(r13) | |
2443 | cmpwi r0, 0 | |
2444 | bne- 43f | |
2445 | ||
2446 | /* OK, it's an IPI for us */ | |
6af27c84 | 2447 | li r12, 0 |
c934243c PM |
2448 | li r3, -1 |
2449 | 1: blr | |
2450 | ||
76d072fb AG |
2451 | 42: /* It's not an IPI and it's for the host. We saved a copy of XIRR in |
2452 | * the PACA earlier, it will be picked up by the host ICP driver | |
c934243c | 2453 | */ |
e3bbbbfa | 2454 | li r3, 1 |
c934243c PM |
2455 | b 1b |
2456 | ||
2457 | 43: /* We raced with the host, we need to resend that IPI, bummer */ | |
2458 | li r0, IPI_PRIORITY | |
2459 | stbcix r0, r6, r8 /* set the IPI */ | |
2460 | sync | |
e3bbbbfa | 2461 | li r3, 1 |
c934243c | 2462 | b 1b |
371fefd6 | 2463 | |
de56a948 PM |
2464 | /* |
2465 | * Save away FP, VMX and VSX registers. | |
2466 | * r3 = vcpu pointer | |
595e4f7e PM |
2467 | * N.B. r30 and r31 are volatile across this function, |
2468 | * thus it is not callable from C. | |
a8606e20 | 2469 | */ |
595e4f7e PM |
2470 | kvmppc_save_fp: |
2471 | mflr r30 | |
2472 | mr r31,r3 | |
8943633c PM |
2473 | mfmsr r5 |
2474 | ori r8,r5,MSR_FP | |
de56a948 PM |
2475 | #ifdef CONFIG_ALTIVEC |
2476 | BEGIN_FTR_SECTION | |
2477 | oris r8,r8,MSR_VEC@h | |
2478 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
2479 | #endif | |
2480 | #ifdef CONFIG_VSX | |
2481 | BEGIN_FTR_SECTION | |
2482 | oris r8,r8,MSR_VSX@h | |
2483 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
2484 | #endif | |
2485 | mtmsrd r8 | |
595e4f7e | 2486 | addi r3,r3,VCPU_FPRS |
9bf163f8 | 2487 | bl store_fp_state |
de56a948 PM |
2488 | #ifdef CONFIG_ALTIVEC |
2489 | BEGIN_FTR_SECTION | |
595e4f7e | 2490 | addi r3,r31,VCPU_VRS |
9bf163f8 | 2491 | bl store_vr_state |
de56a948 PM |
2492 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
2493 | #endif | |
2494 | mfspr r6,SPRN_VRSAVE | |
e724f080 | 2495 | stw r6,VCPU_VRSAVE(r31) |
595e4f7e | 2496 | mtlr r30 |
de56a948 PM |
2497 | blr |
2498 | ||
2499 | /* | |
2500 | * Load up FP, VMX and VSX registers | |
2501 | * r4 = vcpu pointer | |
595e4f7e PM |
2502 | * N.B. r30 and r31 are volatile across this function, |
2503 | * thus it is not callable from C. | |
de56a948 | 2504 | */ |
de56a948 | 2505 | kvmppc_load_fp: |
595e4f7e PM |
2506 | mflr r30 |
2507 | mr r31,r4 | |
de56a948 PM |
2508 | mfmsr r9 |
2509 | ori r8,r9,MSR_FP | |
2510 | #ifdef CONFIG_ALTIVEC | |
2511 | BEGIN_FTR_SECTION | |
2512 | oris r8,r8,MSR_VEC@h | |
2513 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
2514 | #endif | |
2515 | #ifdef CONFIG_VSX | |
2516 | BEGIN_FTR_SECTION | |
2517 | oris r8,r8,MSR_VSX@h | |
2518 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
2519 | #endif | |
2520 | mtmsrd r8 | |
595e4f7e | 2521 | addi r3,r4,VCPU_FPRS |
9bf163f8 | 2522 | bl load_fp_state |
de56a948 PM |
2523 | #ifdef CONFIG_ALTIVEC |
2524 | BEGIN_FTR_SECTION | |
595e4f7e | 2525 | addi r3,r31,VCPU_VRS |
9bf163f8 | 2526 | bl load_vr_state |
de56a948 PM |
2527 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
2528 | #endif | |
e724f080 | 2529 | lwz r7,VCPU_VRSAVE(r31) |
de56a948 | 2530 | mtspr SPRN_VRSAVE,r7 |
595e4f7e PM |
2531 | mtlr r30 |
2532 | mr r4,r31 | |
de56a948 | 2533 | blr |
44a3add8 PM |
2534 | |
2535 | /* | |
2536 | * We come here if we get any exception or interrupt while we are | |
2537 | * executing host real mode code while in guest MMU context. | |
2538 | * For now just spin, but we should do something better. | |
2539 | */ | |
2540 | kvmppc_bad_host_intr: | |
2541 | b . | |
e4e38121 MN |
2542 | |
2543 | /* | |
2544 | * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken | |
2545 | * from VCPU_INTR_MSR and is modified based on the required TM state changes. | |
2546 | * r11 has the guest MSR value (in/out) | |
2547 | * r9 has a vcpu pointer (in) | |
2548 | * r0 is used as a scratch register | |
2549 | */ | |
2550 | kvmppc_msr_interrupt: | |
2551 | rldicl r0, r11, 64 - MSR_TS_S_LG, 62 | |
2552 | cmpwi r0, 2 /* Check if we are in transactional state.. */ | |
2553 | ld r11, VCPU_INTR_MSR(r9) | |
2554 | bne 1f | |
2555 | /* ... if transactional, change to suspended */ | |
2556 | li r0, 1 | |
2557 | 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG | |
2558 | blr | |
9bc01a9b PM |
2559 | |
2560 | /* | |
2561 | * This works around a hardware bug on POWER8E processors, where | |
2562 | * writing a 1 to the MMCR0[PMAO] bit doesn't generate a | |
2563 | * performance monitor interrupt. Instead, when we need to have | |
2564 | * an interrupt pending, we have to arrange for a counter to overflow. | |
2565 | */ | |
2566 | kvmppc_fix_pmao: | |
2567 | li r3, 0 | |
2568 | mtspr SPRN_MMCR2, r3 | |
2569 | lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h | |
2570 | ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN | |
2571 | mtspr SPRN_MMCR0, r3 | |
2572 | lis r3, 0x7fff | |
2573 | ori r3, r3, 0xffff | |
2574 | mtspr SPRN_PMC6, r3 | |
2575 | isync | |
2576 | blr | |
b6c295df PM |
2577 | |
2578 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING | |
2579 | /* | |
2580 | * Start timing an activity | |
2581 | * r3 = pointer to time accumulation struct, r4 = vcpu | |
2582 | */ | |
2583 | kvmhv_start_timing: | |
2584 | ld r5, HSTATE_KVM_VCORE(r13) | |
2585 | lbz r6, VCORE_IN_GUEST(r5) | |
2586 | cmpwi r6, 0 | |
2587 | beq 5f /* if in guest, need to */ | |
2588 | ld r6, VCORE_TB_OFFSET(r5) /* subtract timebase offset */ | |
2589 | 5: mftb r5 | |
2590 | subf r5, r6, r5 | |
2591 | std r3, VCPU_CUR_ACTIVITY(r4) | |
2592 | std r5, VCPU_ACTIVITY_START(r4) | |
2593 | blr | |
2594 | ||
2595 | /* | |
2596 | * Accumulate time to one activity and start another. | |
2597 | * r3 = pointer to new time accumulation struct, r4 = vcpu | |
2598 | */ | |
2599 | kvmhv_accumulate_time: | |
2600 | ld r5, HSTATE_KVM_VCORE(r13) | |
2601 | lbz r8, VCORE_IN_GUEST(r5) | |
2602 | cmpwi r8, 0 | |
2603 | beq 4f /* if in guest, need to */ | |
2604 | ld r8, VCORE_TB_OFFSET(r5) /* subtract timebase offset */ | |
2605 | 4: ld r5, VCPU_CUR_ACTIVITY(r4) | |
2606 | ld r6, VCPU_ACTIVITY_START(r4) | |
2607 | std r3, VCPU_CUR_ACTIVITY(r4) | |
2608 | mftb r7 | |
2609 | subf r7, r8, r7 | |
2610 | std r7, VCPU_ACTIVITY_START(r4) | |
2611 | cmpdi r5, 0 | |
2612 | beqlr | |
2613 | subf r3, r6, r7 | |
2614 | ld r8, TAS_SEQCOUNT(r5) | |
2615 | cmpdi r8, 0 | |
2616 | addi r8, r8, 1 | |
2617 | std r8, TAS_SEQCOUNT(r5) | |
2618 | lwsync | |
2619 | ld r7, TAS_TOTAL(r5) | |
2620 | add r7, r7, r3 | |
2621 | std r7, TAS_TOTAL(r5) | |
2622 | ld r6, TAS_MIN(r5) | |
2623 | ld r7, TAS_MAX(r5) | |
2624 | beq 3f | |
2625 | cmpd r3, r6 | |
2626 | bge 1f | |
2627 | 3: std r3, TAS_MIN(r5) | |
2628 | 1: cmpd r3, r7 | |
2629 | ble 2f | |
2630 | std r3, TAS_MAX(r5) | |
2631 | 2: lwsync | |
2632 | addi r8, r8, 1 | |
2633 | std r8, TAS_SEQCOUNT(r5) | |
2634 | blr | |
2635 | #endif |