Commit | Line | Data |
---|---|---|
de56a948 PM |
1 | /* |
2 | * This program is free software; you can redistribute it and/or modify | |
3 | * it under the terms of the GNU General Public License, version 2, as | |
4 | * published by the Free Software Foundation. | |
5 | * | |
6 | * This program is distributed in the hope that it will be useful, | |
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
9 | * GNU General Public License for more details. | |
10 | * | |
11 | * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com> | |
12 | * | |
13 | * Derived from book3s_rmhandlers.S and other files, which are: | |
14 | * | |
15 | * Copyright SUSE Linux Products GmbH 2009 | |
16 | * | |
17 | * Authors: Alexander Graf <agraf@suse.de> | |
18 | */ | |
19 | ||
20 | #include <asm/ppc_asm.h> | |
21 | #include <asm/kvm_asm.h> | |
22 | #include <asm/reg.h> | |
177339d7 | 23 | #include <asm/mmu.h> |
de56a948 | 24 | #include <asm/page.h> |
177339d7 PM |
25 | #include <asm/ptrace.h> |
26 | #include <asm/hvcall.h> | |
de56a948 PM |
27 | #include <asm/asm-offsets.h> |
28 | #include <asm/exception-64s.h> | |
f0888f70 | 29 | #include <asm/kvm_book3s_asm.h> |
b4072df4 | 30 | #include <asm/mmu-hash64.h> |
de56a948 | 31 | |
7ffcf8ec AB |
32 | #ifdef __LITTLE_ENDIAN__ |
33 | #error Need to fix lppaca and SLB shadow accesses in little endian mode | |
34 | #endif | |
35 | ||
de56a948 PM |
36 | /***************************************************************************** |
37 | * * | |
38 | * Real Mode handlers that need to be in the linear mapping * | |
39 | * * | |
40 | ****************************************************************************/ | |
41 | ||
de56a948 PM |
42 | .globl kvmppc_skip_interrupt |
43 | kvmppc_skip_interrupt: | |
44 | mfspr r13,SPRN_SRR0 | |
45 | addi r13,r13,4 | |
46 | mtspr SPRN_SRR0,r13 | |
47 | GET_SCRATCH0(r13) | |
48 | rfid | |
49 | b . | |
50 | ||
51 | .globl kvmppc_skip_Hinterrupt | |
52 | kvmppc_skip_Hinterrupt: | |
53 | mfspr r13,SPRN_HSRR0 | |
54 | addi r13,r13,4 | |
55 | mtspr SPRN_HSRR0,r13 | |
56 | GET_SCRATCH0(r13) | |
57 | hrfid | |
58 | b . | |
59 | ||
60 | /* | |
19ccb76a | 61 | * Call kvmppc_hv_entry in real mode. |
de56a948 PM |
62 | * Must be called with interrupts hard-disabled. |
63 | * | |
64 | * Input Registers: | |
65 | * | |
66 | * LR = return address to continue at after eventually re-enabling MMU | |
67 | */ | |
68 | _GLOBAL(kvmppc_hv_entry_trampoline) | |
69 | mfmsr r10 | |
70 | LOAD_REG_ADDR(r5, kvmppc_hv_entry) | |
71 | li r0,MSR_RI | |
72 | andc r0,r10,r0 | |
73 | li r6,MSR_IR | MSR_DR | |
74 | andc r6,r10,r6 | |
75 | mtmsrd r0,1 /* clear RI in MSR */ | |
76 | mtsrr0 r5 | |
77 | mtsrr1 r6 | |
78 | RFI | |
79 | ||
de56a948 PM |
80 | /****************************************************************************** |
81 | * * | |
82 | * Entry code * | |
83 | * * | |
84 | *****************************************************************************/ | |
85 | ||
371fefd6 PM |
86 | /* |
87 | * We come in here when wakened from nap mode on a secondary hw thread. | |
88 | * Relocation is off and most register values are lost. | |
89 | * r13 points to the PACA. | |
90 | */ | |
91 | .globl kvm_start_guest | |
92 | kvm_start_guest: | |
93 | ld r1,PACAEMERGSP(r13) | |
94 | subi r1,r1,STACK_FRAME_OVERHEAD | |
19ccb76a PM |
95 | ld r2,PACATOC(r13) |
96 | ||
f0888f70 PM |
97 | li r0,KVM_HWTHREAD_IN_KVM |
98 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
371fefd6 | 99 | |
f0888f70 PM |
100 | /* NV GPR values from power7_idle() will no longer be valid */ |
101 | li r0,1 | |
102 | stb r0,PACA_NAPSTATELOST(r13) | |
371fefd6 | 103 | |
4619ac88 PM |
104 | /* were we napping due to cede? */ |
105 | lbz r0,HSTATE_NAPPING(r13) | |
106 | cmpwi r0,0 | |
107 | bne kvm_end_cede | |
108 | ||
109 | /* | |
110 | * We weren't napping due to cede, so this must be a secondary | |
111 | * thread being woken up to run a guest, or being woken up due | |
112 | * to a stray IPI. (Or due to some machine check or hypervisor | |
113 | * maintenance interrupt while the core is in KVM.) | |
114 | */ | |
f0888f70 PM |
115 | |
116 | /* Check the wake reason in SRR1 to see why we got here */ | |
117 | mfspr r3,SPRN_SRR1 | |
118 | rlwinm r3,r3,44-31,0x7 /* extract wake reason field */ | |
119 | cmpwi r3,4 /* was it an external interrupt? */ | |
4619ac88 PM |
120 | bne 27f /* if not */ |
121 | ld r5,HSTATE_XICS_PHYS(r13) | |
122 | li r7,XICS_XIRR /* if it was an external interrupt, */ | |
f0888f70 | 123 | lwzcix r8,r5,r7 /* get and ack the interrupt */ |
371fefd6 | 124 | sync |
f0888f70 | 125 | clrldi. r9,r8,40 /* get interrupt source ID. */ |
4619ac88 PM |
126 | beq 28f /* none there? */ |
127 | cmpwi r9,XICS_IPI /* was it an IPI? */ | |
128 | bne 29f | |
129 | li r0,0xff | |
130 | li r6,XICS_MFRR | |
f0888f70 | 131 | stbcix r0,r5,r6 /* clear IPI */ |
4619ac88 PM |
132 | stwcix r8,r5,r7 /* EOI the interrupt */ |
133 | sync /* order loading of vcpu after that */ | |
371fefd6 | 134 | |
4619ac88 | 135 | /* get vcpu pointer, NULL if we have no vcpu to run */ |
7b444c67 PM |
136 | ld r4,HSTATE_KVM_VCPU(r13) |
137 | cmpdi r4,0 | |
f0888f70 | 138 | /* if we have no vcpu to run, go back to sleep */ |
7b444c67 | 139 | beq kvm_no_guest |
4619ac88 | 140 | b kvmppc_hv_entry |
f0888f70 | 141 | |
4619ac88 PM |
142 | 27: /* XXX should handle hypervisor maintenance interrupts etc. here */ |
143 | b kvm_no_guest | |
144 | 28: /* SRR1 said external but ICP said nope?? */ | |
145 | b kvm_no_guest | |
146 | 29: /* External non-IPI interrupt to offline secondary thread? help?? */ | |
147 | stw r8,HSTATE_SAVED_XIRR(r13) | |
148 | b kvm_no_guest | |
2fde6d20 | 149 | |
de56a948 PM |
150 | .global kvmppc_hv_entry |
151 | kvmppc_hv_entry: | |
152 | ||
153 | /* Required state: | |
154 | * | |
155 | * R4 = vcpu pointer | |
156 | * MSR = ~IR|DR | |
157 | * R13 = PACA | |
158 | * R1 = host R1 | |
159 | * all other volatile GPRS = free | |
160 | */ | |
161 | mflr r0 | |
162 | std r0, HSTATE_VMHANDLER(r13) | |
163 | ||
8943633c PM |
164 | /* Set partition DABR */ |
165 | /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */ | |
166 | li r5,3 | |
167 | ld r6,VCPU_DABR(r4) | |
168 | mtspr SPRN_DABRX,r5 | |
169 | mtspr SPRN_DABR,r6 | |
170 | BEGIN_FTR_SECTION | |
171 | isync | |
172 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
de56a948 PM |
173 | |
174 | /* Load guest PMU registers */ | |
175 | /* R4 is live here (vcpu pointer) */ | |
176 | li r3, 1 | |
177 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
178 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ | |
179 | isync | |
180 | lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */ | |
181 | lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */ | |
182 | lwz r6, VCPU_PMC + 8(r4) | |
183 | lwz r7, VCPU_PMC + 12(r4) | |
184 | lwz r8, VCPU_PMC + 16(r4) | |
185 | lwz r9, VCPU_PMC + 20(r4) | |
9e368f29 PM |
186 | BEGIN_FTR_SECTION |
187 | lwz r10, VCPU_PMC + 24(r4) | |
188 | lwz r11, VCPU_PMC + 28(r4) | |
189 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
190 | mtspr SPRN_PMC1, r3 |
191 | mtspr SPRN_PMC2, r5 | |
192 | mtspr SPRN_PMC3, r6 | |
193 | mtspr SPRN_PMC4, r7 | |
194 | mtspr SPRN_PMC5, r8 | |
195 | mtspr SPRN_PMC6, r9 | |
9e368f29 PM |
196 | BEGIN_FTR_SECTION |
197 | mtspr SPRN_PMC7, r10 | |
198 | mtspr SPRN_PMC8, r11 | |
199 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
200 | ld r3, VCPU_MMCR(r4) |
201 | ld r5, VCPU_MMCR + 8(r4) | |
202 | ld r6, VCPU_MMCR + 16(r4) | |
14941789 PM |
203 | ld r7, VCPU_SIAR(r4) |
204 | ld r8, VCPU_SDAR(r4) | |
de56a948 PM |
205 | mtspr SPRN_MMCR1, r5 |
206 | mtspr SPRN_MMCRA, r6 | |
14941789 PM |
207 | mtspr SPRN_SIAR, r7 |
208 | mtspr SPRN_SDAR, r8 | |
de56a948 PM |
209 | mtspr SPRN_MMCR0, r3 |
210 | isync | |
211 | ||
212 | /* Load up FP, VMX and VSX registers */ | |
213 | bl kvmppc_load_fp | |
214 | ||
c75df6f9 MN |
215 | ld r14, VCPU_GPR(R14)(r4) |
216 | ld r15, VCPU_GPR(R15)(r4) | |
217 | ld r16, VCPU_GPR(R16)(r4) | |
218 | ld r17, VCPU_GPR(R17)(r4) | |
219 | ld r18, VCPU_GPR(R18)(r4) | |
220 | ld r19, VCPU_GPR(R19)(r4) | |
221 | ld r20, VCPU_GPR(R20)(r4) | |
222 | ld r21, VCPU_GPR(R21)(r4) | |
223 | ld r22, VCPU_GPR(R22)(r4) | |
224 | ld r23, VCPU_GPR(R23)(r4) | |
225 | ld r24, VCPU_GPR(R24)(r4) | |
226 | ld r25, VCPU_GPR(R25)(r4) | |
227 | ld r26, VCPU_GPR(R26)(r4) | |
228 | ld r27, VCPU_GPR(R27)(r4) | |
229 | ld r28, VCPU_GPR(R28)(r4) | |
230 | ld r29, VCPU_GPR(R29)(r4) | |
231 | ld r30, VCPU_GPR(R30)(r4) | |
232 | ld r31, VCPU_GPR(R31)(r4) | |
8943633c | 233 | |
9e368f29 | 234 | BEGIN_FTR_SECTION |
de56a948 PM |
235 | /* Switch DSCR to guest value */ |
236 | ld r5, VCPU_DSCR(r4) | |
237 | mtspr SPRN_DSCR, r5 | |
9e368f29 | 238 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 PM |
239 | |
240 | /* | |
241 | * Set the decrementer to the guest decrementer. | |
242 | */ | |
243 | ld r8,VCPU_DEC_EXPIRES(r4) | |
244 | mftb r7 | |
245 | subf r3,r7,r8 | |
246 | mtspr SPRN_DEC,r3 | |
247 | stw r3,VCPU_DEC(r4) | |
248 | ||
249 | ld r5, VCPU_SPRG0(r4) | |
250 | ld r6, VCPU_SPRG1(r4) | |
251 | ld r7, VCPU_SPRG2(r4) | |
252 | ld r8, VCPU_SPRG3(r4) | |
253 | mtspr SPRN_SPRG0, r5 | |
254 | mtspr SPRN_SPRG1, r6 | |
255 | mtspr SPRN_SPRG2, r7 | |
256 | mtspr SPRN_SPRG3, r8 | |
257 | ||
258 | /* Save R1 in the PACA */ | |
259 | std r1, HSTATE_HOST_R1(r13) | |
260 | ||
a8606e20 PM |
261 | /* Increment yield count if they have a VPA */ |
262 | ld r3, VCPU_VPA(r4) | |
263 | cmpdi r3, 0 | |
264 | beq 25f | |
265 | lwz r5, LPPACA_YIELDCOUNT(r3) | |
266 | addi r5, r5, 1 | |
267 | stw r5, LPPACA_YIELDCOUNT(r3) | |
c35635ef PM |
268 | li r6, 1 |
269 | stb r6, VCPU_VPA_DIRTY(r4) | |
a8606e20 | 270 | 25: |
de56a948 PM |
271 | /* Load up DAR and DSISR */ |
272 | ld r5, VCPU_DAR(r4) | |
273 | lwz r6, VCPU_DSISR(r4) | |
274 | mtspr SPRN_DAR, r5 | |
275 | mtspr SPRN_DSISR, r6 | |
276 | ||
9e368f29 | 277 | BEGIN_FTR_SECTION |
de56a948 PM |
278 | /* Restore AMR and UAMOR, set AMOR to all 1s */ |
279 | ld r5,VCPU_AMR(r4) | |
280 | ld r6,VCPU_UAMOR(r4) | |
281 | li r7,-1 | |
282 | mtspr SPRN_AMR,r5 | |
283 | mtspr SPRN_UAMOR,r6 | |
284 | mtspr SPRN_AMOR,r7 | |
9e368f29 | 285 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 PM |
286 | |
287 | /* Clear out SLB */ | |
288 | li r6,0 | |
289 | slbmte r6,r6 | |
290 | slbia | |
291 | ptesync | |
292 | ||
9e368f29 PM |
293 | BEGIN_FTR_SECTION |
294 | b 30f | |
295 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
296 | /* | |
297 | * POWER7 host -> guest partition switch code. | |
298 | * We don't have to lock against concurrent tlbies, | |
299 | * but we do have to coordinate across hardware threads. | |
300 | */ | |
371fefd6 PM |
301 | /* Increment entry count iff exit count is zero. */ |
302 | ld r5,HSTATE_KVM_VCORE(r13) | |
303 | addi r9,r5,VCORE_ENTRY_EXIT | |
304 | 21: lwarx r3,0,r9 | |
305 | cmpwi r3,0x100 /* any threads starting to exit? */ | |
306 | bge secondary_too_late /* if so we're too late to the party */ | |
307 | addi r3,r3,1 | |
308 | stwcx. r3,0,r9 | |
309 | bne 21b | |
310 | ||
311 | /* Primary thread switches to guest partition. */ | |
aa04b4cc | 312 | ld r9,VCPU_KVM(r4) /* pointer to struct kvm */ |
371fefd6 PM |
313 | lwz r6,VCPU_PTID(r4) |
314 | cmpwi r6,0 | |
315 | bne 20f | |
de56a948 PM |
316 | ld r6,KVM_SDR1(r9) |
317 | lwz r7,KVM_LPID(r9) | |
318 | li r0,LPID_RSVD /* switch to reserved LPID */ | |
319 | mtspr SPRN_LPID,r0 | |
320 | ptesync | |
321 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
322 | mtspr SPRN_LPID,r7 | |
323 | isync | |
1b400ba0 PM |
324 | |
325 | /* See if we need to flush the TLB */ | |
326 | lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */ | |
327 | clrldi r7,r6,64-6 /* extract bit number (6 bits) */ | |
328 | srdi r6,r6,6 /* doubleword number */ | |
329 | sldi r6,r6,3 /* address offset */ | |
330 | add r6,r6,r9 | |
331 | addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */ | |
371fefd6 | 332 | li r0,1 |
1b400ba0 PM |
333 | sld r0,r0,r7 |
334 | ld r7,0(r6) | |
335 | and. r7,r7,r0 | |
336 | beq 22f | |
337 | 23: ldarx r7,0,r6 /* if set, clear the bit */ | |
338 | andc r7,r7,r0 | |
339 | stdcx. r7,0,r6 | |
340 | bne 23b | |
341 | li r6,128 /* and flush the TLB */ | |
342 | mtctr r6 | |
343 | li r7,0x800 /* IS field = 0b10 */ | |
344 | ptesync | |
345 | 28: tlbiel r7 | |
346 | addi r7,r7,0x1000 | |
347 | bdnz 28b | |
348 | ptesync | |
349 | ||
350 | 22: li r0,1 | |
371fefd6 PM |
351 | stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */ |
352 | b 10f | |
353 | ||
354 | /* Secondary threads wait for primary to have done partition switch */ | |
355 | 20: lbz r0,VCORE_IN_GUEST(r5) | |
356 | cmpwi r0,0 | |
357 | beq 20b | |
aa04b4cc | 358 | |
19ccb76a | 359 | /* Set LPCR and RMOR. */ |
aa04b4cc | 360 | 10: ld r8,KVM_LPCR(r9) |
19ccb76a | 361 | mtspr SPRN_LPCR,r8 |
aa04b4cc PM |
362 | ld r8,KVM_RMOR(r9) |
363 | mtspr SPRN_RMOR,r8 | |
de56a948 PM |
364 | isync |
365 | ||
366 | /* Check if HDEC expires soon */ | |
367 | mfspr r3,SPRN_HDEC | |
368 | cmpwi r3,10 | |
369 | li r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
370 | mr r9,r4 | |
371 | blt hdec_soon | |
372 | ||
de56a948 PM |
373 | /* Save purr/spurr */ |
374 | mfspr r5,SPRN_PURR | |
375 | mfspr r6,SPRN_SPURR | |
376 | std r5,HSTATE_PURR(r13) | |
377 | std r6,HSTATE_SPURR(r13) | |
378 | ld r7,VCPU_PURR(r4) | |
379 | ld r8,VCPU_SPURR(r4) | |
380 | mtspr SPRN_PURR,r7 | |
381 | mtspr SPRN_SPURR,r8 | |
9e368f29 PM |
382 | b 31f |
383 | ||
384 | /* | |
385 | * PPC970 host -> guest partition switch code. | |
386 | * We have to lock against concurrent tlbies, | |
387 | * using native_tlbie_lock to lock against host tlbies | |
388 | * and kvm->arch.tlbie_lock to lock against guest tlbies. | |
389 | * We also have to invalidate the TLB since its | |
390 | * entries aren't tagged with the LPID. | |
391 | */ | |
392 | 30: ld r9,VCPU_KVM(r4) /* pointer to struct kvm */ | |
393 | ||
394 | /* first take native_tlbie_lock */ | |
395 | .section ".toc","aw" | |
396 | toc_tlbie_lock: | |
397 | .tc native_tlbie_lock[TC],native_tlbie_lock | |
398 | .previous | |
399 | ld r3,toc_tlbie_lock@toc(2) | |
54bb7f4b | 400 | #ifdef __BIG_ENDIAN__ |
9e368f29 | 401 | lwz r8,PACA_LOCK_TOKEN(r13) |
54bb7f4b AB |
402 | #else |
403 | lwz r8,PACAPACAINDEX(r13) | |
404 | #endif | |
9e368f29 PM |
405 | 24: lwarx r0,0,r3 |
406 | cmpwi r0,0 | |
407 | bne 24b | |
408 | stwcx. r8,0,r3 | |
409 | bne 24b | |
410 | isync | |
411 | ||
412 | ld r7,KVM_LPCR(r9) /* use kvm->arch.lpcr to store HID4 */ | |
413 | li r0,0x18f | |
414 | rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */ | |
415 | or r0,r7,r0 | |
416 | ptesync | |
417 | sync | |
418 | mtspr SPRN_HID4,r0 /* switch to reserved LPID */ | |
419 | isync | |
420 | li r0,0 | |
421 | stw r0,0(r3) /* drop native_tlbie_lock */ | |
422 | ||
423 | /* invalidate the whole TLB */ | |
424 | li r0,256 | |
425 | mtctr r0 | |
426 | li r6,0 | |
427 | 25: tlbiel r6 | |
428 | addi r6,r6,0x1000 | |
429 | bdnz 25b | |
430 | ptesync | |
431 | ||
432 | /* Take the guest's tlbie_lock */ | |
433 | addi r3,r9,KVM_TLBIE_LOCK | |
434 | 24: lwarx r0,0,r3 | |
435 | cmpwi r0,0 | |
436 | bne 24b | |
437 | stwcx. r8,0,r3 | |
438 | bne 24b | |
439 | isync | |
440 | ld r6,KVM_SDR1(r9) | |
441 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
442 | ||
443 | /* Set up HID4 with the guest's LPID etc. */ | |
444 | sync | |
445 | mtspr SPRN_HID4,r7 | |
446 | isync | |
447 | ||
448 | /* drop the guest's tlbie_lock */ | |
449 | li r0,0 | |
450 | stw r0,0(r3) | |
451 | ||
452 | /* Check if HDEC expires soon */ | |
453 | mfspr r3,SPRN_HDEC | |
454 | cmpwi r3,10 | |
455 | li r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
456 | mr r9,r4 | |
457 | blt hdec_soon | |
458 | ||
459 | /* Enable HDEC interrupts */ | |
460 | mfspr r0,SPRN_HID0 | |
461 | li r3,1 | |
462 | rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1 | |
463 | sync | |
464 | mtspr SPRN_HID0,r0 | |
465 | mfspr r0,SPRN_HID0 | |
466 | mfspr r0,SPRN_HID0 | |
467 | mfspr r0,SPRN_HID0 | |
468 | mfspr r0,SPRN_HID0 | |
469 | mfspr r0,SPRN_HID0 | |
470 | mfspr r0,SPRN_HID0 | |
de56a948 PM |
471 | |
472 | /* Load up guest SLB entries */ | |
9e368f29 | 473 | 31: lwz r5,VCPU_SLB_MAX(r4) |
de56a948 PM |
474 | cmpwi r5,0 |
475 | beq 9f | |
476 | mtctr r5 | |
477 | addi r6,r4,VCPU_SLB | |
478 | 1: ld r8,VCPU_SLB_E(r6) | |
479 | ld r9,VCPU_SLB_V(r6) | |
480 | slbmte r9,r8 | |
481 | addi r6,r6,VCPU_SLB_SIZE | |
482 | bdnz 1b | |
483 | 9: | |
484 | ||
485 | /* Restore state of CTRL run bit; assume 1 on entry */ | |
486 | lwz r5,VCPU_CTRL(r4) | |
487 | andi. r5,r5,1 | |
488 | bne 4f | |
489 | mfspr r6,SPRN_CTRLF | |
490 | clrrdi r6,r6,1 | |
491 | mtspr SPRN_CTRLT,r6 | |
492 | 4: | |
493 | ld r6, VCPU_CTR(r4) | |
494 | lwz r7, VCPU_XER(r4) | |
495 | ||
496 | mtctr r6 | |
497 | mtxer r7 | |
498 | ||
4619ac88 PM |
499 | ld r10, VCPU_PC(r4) |
500 | ld r11, VCPU_MSR(r4) | |
19ccb76a | 501 | kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */ |
de56a948 PM |
502 | ld r6, VCPU_SRR0(r4) |
503 | ld r7, VCPU_SRR1(r4) | |
de56a948 | 504 | |
4619ac88 | 505 | /* r11 = vcpu->arch.msr & ~MSR_HV */ |
de56a948 PM |
506 | rldicl r11, r11, 63 - MSR_HV_LG, 1 |
507 | rotldi r11, r11, 1 + MSR_HV_LG | |
508 | ori r11, r11, MSR_ME | |
509 | ||
19ccb76a PM |
510 | /* Check if we can deliver an external or decrementer interrupt now */ |
511 | ld r0,VCPU_PENDING_EXC(r4) | |
4619ac88 | 512 | lis r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h |
19ccb76a PM |
513 | and r0,r0,r8 |
514 | cmpdi cr1,r0,0 | |
515 | andi. r0,r11,MSR_EE | |
516 | beq cr1,11f | |
517 | BEGIN_FTR_SECTION | |
518 | mfspr r8,SPRN_LPCR | |
519 | ori r8,r8,LPCR_MER | |
520 | mtspr SPRN_LPCR,r8 | |
521 | isync | |
522 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
523 | beq 5f | |
524 | li r0,BOOK3S_INTERRUPT_EXTERNAL | |
525 | 12: mr r6,r10 | |
526 | mr r10,r0 | |
527 | mr r7,r11 | |
528 | li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
529 | rotldi r11,r11,63 | |
530 | b 5f | |
531 | 11: beq 5f | |
532 | mfspr r0,SPRN_DEC | |
533 | cmpwi r0,0 | |
534 | li r0,BOOK3S_INTERRUPT_DECREMENTER | |
535 | blt 12b | |
536 | ||
537 | /* Move SRR0 and SRR1 into the respective regs */ | |
538 | 5: mtspr SPRN_SRR0, r6 | |
539 | mtspr SPRN_SRR1, r7 | |
19ccb76a | 540 | |
de56a948 | 541 | fast_guest_return: |
4619ac88 PM |
542 | li r0,0 |
543 | stb r0,VCPU_CEDED(r4) /* cancel cede */ | |
de56a948 PM |
544 | mtspr SPRN_HSRR0,r10 |
545 | mtspr SPRN_HSRR1,r11 | |
546 | ||
547 | /* Activate guest mode, so faults get handled by KVM */ | |
548 | li r9, KVM_GUEST_MODE_GUEST | |
549 | stb r9, HSTATE_IN_GUEST(r13) | |
550 | ||
551 | /* Enter guest */ | |
552 | ||
0acb9111 PM |
553 | BEGIN_FTR_SECTION |
554 | ld r5, VCPU_CFAR(r4) | |
555 | mtspr SPRN_CFAR, r5 | |
556 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
557 | ||
de56a948 PM |
558 | ld r5, VCPU_LR(r4) |
559 | lwz r6, VCPU_CR(r4) | |
560 | mtlr r5 | |
561 | mtcr r6 | |
562 | ||
c75df6f9 MN |
563 | ld r0, VCPU_GPR(R0)(r4) |
564 | ld r1, VCPU_GPR(R1)(r4) | |
565 | ld r2, VCPU_GPR(R2)(r4) | |
566 | ld r3, VCPU_GPR(R3)(r4) | |
567 | ld r5, VCPU_GPR(R5)(r4) | |
568 | ld r6, VCPU_GPR(R6)(r4) | |
569 | ld r7, VCPU_GPR(R7)(r4) | |
570 | ld r8, VCPU_GPR(R8)(r4) | |
571 | ld r9, VCPU_GPR(R9)(r4) | |
572 | ld r10, VCPU_GPR(R10)(r4) | |
573 | ld r11, VCPU_GPR(R11)(r4) | |
574 | ld r12, VCPU_GPR(R12)(r4) | |
575 | ld r13, VCPU_GPR(R13)(r4) | |
576 | ||
577 | ld r4, VCPU_GPR(R4)(r4) | |
de56a948 PM |
578 | |
579 | hrfid | |
580 | b . | |
581 | ||
582 | /****************************************************************************** | |
583 | * * | |
584 | * Exit code * | |
585 | * * | |
586 | *****************************************************************************/ | |
587 | ||
588 | /* | |
589 | * We come here from the first-level interrupt handlers. | |
590 | */ | |
591 | .globl kvmppc_interrupt | |
592 | kvmppc_interrupt: | |
593 | /* | |
594 | * Register contents: | |
595 | * R12 = interrupt vector | |
596 | * R13 = PACA | |
597 | * guest CR, R12 saved in shadow VCPU SCRATCH1/0 | |
598 | * guest R13 saved in SPRN_SCRATCH0 | |
599 | */ | |
600 | /* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */ | |
601 | std r9, HSTATE_HOST_R2(r13) | |
602 | ld r9, HSTATE_KVM_VCPU(r13) | |
603 | ||
604 | /* Save registers */ | |
605 | ||
c75df6f9 MN |
606 | std r0, VCPU_GPR(R0)(r9) |
607 | std r1, VCPU_GPR(R1)(r9) | |
608 | std r2, VCPU_GPR(R2)(r9) | |
609 | std r3, VCPU_GPR(R3)(r9) | |
610 | std r4, VCPU_GPR(R4)(r9) | |
611 | std r5, VCPU_GPR(R5)(r9) | |
612 | std r6, VCPU_GPR(R6)(r9) | |
613 | std r7, VCPU_GPR(R7)(r9) | |
614 | std r8, VCPU_GPR(R8)(r9) | |
de56a948 | 615 | ld r0, HSTATE_HOST_R2(r13) |
c75df6f9 MN |
616 | std r0, VCPU_GPR(R9)(r9) |
617 | std r10, VCPU_GPR(R10)(r9) | |
618 | std r11, VCPU_GPR(R11)(r9) | |
de56a948 PM |
619 | ld r3, HSTATE_SCRATCH0(r13) |
620 | lwz r4, HSTATE_SCRATCH1(r13) | |
c75df6f9 | 621 | std r3, VCPU_GPR(R12)(r9) |
de56a948 | 622 | stw r4, VCPU_CR(r9) |
0acb9111 PM |
623 | BEGIN_FTR_SECTION |
624 | ld r3, HSTATE_CFAR(r13) | |
625 | std r3, VCPU_CFAR(r9) | |
626 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
de56a948 PM |
627 | |
628 | /* Restore R1/R2 so we can handle faults */ | |
629 | ld r1, HSTATE_HOST_R1(r13) | |
630 | ld r2, PACATOC(r13) | |
631 | ||
632 | mfspr r10, SPRN_SRR0 | |
633 | mfspr r11, SPRN_SRR1 | |
634 | std r10, VCPU_SRR0(r9) | |
635 | std r11, VCPU_SRR1(r9) | |
636 | andi. r0, r12, 2 /* need to read HSRR0/1? */ | |
637 | beq 1f | |
638 | mfspr r10, SPRN_HSRR0 | |
639 | mfspr r11, SPRN_HSRR1 | |
640 | clrrdi r12, r12, 2 | |
641 | 1: std r10, VCPU_PC(r9) | |
642 | std r11, VCPU_MSR(r9) | |
643 | ||
644 | GET_SCRATCH0(r3) | |
645 | mflr r4 | |
c75df6f9 | 646 | std r3, VCPU_GPR(R13)(r9) |
de56a948 PM |
647 | std r4, VCPU_LR(r9) |
648 | ||
649 | /* Unset guest mode */ | |
650 | li r0, KVM_GUEST_MODE_NONE | |
651 | stb r0, HSTATE_IN_GUEST(r13) | |
652 | ||
653 | stw r12,VCPU_TRAP(r9) | |
654 | ||
697d3899 PM |
655 | /* Save HEIR (HV emulation assist reg) in last_inst |
656 | if this is an HEI (HV emulation interrupt, e40) */ | |
657 | li r3,KVM_INST_FETCH_FAILED | |
658 | BEGIN_FTR_SECTION | |
659 | cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST | |
660 | bne 11f | |
661 | mfspr r3,SPRN_HEIR | |
662 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
663 | 11: stw r3,VCPU_LAST_INST(r9) | |
664 | ||
665 | /* these are volatile across C function calls */ | |
666 | mfctr r3 | |
667 | mfxer r4 | |
668 | std r3, VCPU_CTR(r9) | |
669 | stw r4, VCPU_XER(r9) | |
670 | ||
671 | BEGIN_FTR_SECTION | |
672 | /* If this is a page table miss then see if it's theirs or ours */ | |
673 | cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE | |
674 | beq kvmppc_hdsi | |
342d3db7 PM |
675 | cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE |
676 | beq kvmppc_hisi | |
697d3899 PM |
677 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
678 | ||
de56a948 PM |
679 | /* See if this is a leftover HDEC interrupt */ |
680 | cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER | |
681 | bne 2f | |
682 | mfspr r3,SPRN_HDEC | |
683 | cmpwi r3,0 | |
684 | bge ignore_hdec | |
685 | 2: | |
697d3899 | 686 | /* See if this is an hcall we can handle in real mode */ |
a8606e20 PM |
687 | cmpwi r12,BOOK3S_INTERRUPT_SYSCALL |
688 | beq hcall_try_real_mode | |
de56a948 | 689 | |
54695c30 | 690 | /* Only handle external interrupts here on arch 206 and later */ |
9e368f29 | 691 | BEGIN_FTR_SECTION |
54695c30 BH |
692 | b ext_interrupt_to_host |
693 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206) | |
694 | ||
695 | /* External interrupt ? */ | |
696 | cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL | |
697 | bne+ ext_interrupt_to_host | |
698 | ||
699 | /* External interrupt, first check for host_ipi. If this is | |
700 | * set, we know the host wants us out so let's do it now | |
701 | */ | |
4619ac88 | 702 | do_ext_interrupt: |
54695c30 BH |
703 | lbz r0, HSTATE_HOST_IPI(r13) |
704 | cmpwi r0, 0 | |
705 | bne ext_interrupt_to_host | |
706 | ||
707 | /* Now read the interrupt from the ICP */ | |
708 | ld r5, HSTATE_XICS_PHYS(r13) | |
709 | li r7, XICS_XIRR | |
710 | cmpdi r5, 0 | |
711 | beq- ext_interrupt_to_host | |
712 | lwzcix r3, r5, r7 | |
713 | rlwinm. r0, r3, 0, 0xffffff | |
714 | sync | |
4619ac88 | 715 | beq 3f /* if nothing pending in the ICP */ |
54695c30 | 716 | |
4619ac88 | 717 | /* We found something in the ICP... |
54695c30 BH |
718 | * |
719 | * If it's not an IPI, stash it in the PACA and return to | |
720 | * the host, we don't (yet) handle directing real external | |
721 | * interrupts directly to the guest | |
722 | */ | |
723 | cmpwi r0, XICS_IPI | |
724 | bne ext_stash_for_host | |
725 | ||
726 | /* It's an IPI, clear the MFRR and EOI it */ | |
727 | li r0, 0xff | |
728 | li r6, XICS_MFRR | |
729 | stbcix r0, r5, r6 /* clear the IPI */ | |
730 | stwcix r3, r5, r7 /* EOI it */ | |
731 | sync | |
732 | ||
733 | /* We need to re-check host IPI now in case it got set in the | |
734 | * meantime. If it's clear, we bounce the interrupt to the | |
735 | * guest | |
736 | */ | |
737 | lbz r0, HSTATE_HOST_IPI(r13) | |
738 | cmpwi r0, 0 | |
739 | bne- 1f | |
740 | ||
741 | /* Allright, looks like an IPI for the guest, we need to set MER */ | |
4619ac88 PM |
742 | 3: |
743 | /* Check if any CPU is heading out to the host, if so head out too */ | |
744 | ld r5, HSTATE_KVM_VCORE(r13) | |
745 | lwz r0, VCORE_ENTRY_EXIT(r5) | |
746 | cmpwi r0, 0x100 | |
747 | bge ext_interrupt_to_host | |
748 | ||
749 | /* See if there is a pending interrupt for the guest */ | |
750 | mfspr r8, SPRN_LPCR | |
751 | ld r0, VCPU_PENDING_EXC(r9) | |
752 | /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */ | |
753 | rldicl. r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63 | |
754 | rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH | |
755 | beq 2f | |
54695c30 BH |
756 | |
757 | /* And if the guest EE is set, we can deliver immediately, else | |
758 | * we return to the guest with MER set | |
759 | */ | |
760 | andi. r0, r11, MSR_EE | |
4619ac88 PM |
761 | beq 2f |
762 | mtspr SPRN_SRR0, r10 | |
763 | mtspr SPRN_SRR1, r11 | |
764 | li r10, BOOK3S_INTERRUPT_EXTERNAL | |
765 | li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
766 | rotldi r11, r11, 63 | |
767 | 2: mr r4, r9 | |
768 | mtspr SPRN_LPCR, r8 | |
54695c30 BH |
769 | b fast_guest_return |
770 | ||
771 | /* We raced with the host, we need to resend that IPI, bummer */ | |
772 | 1: li r0, IPI_PRIORITY | |
773 | stbcix r0, r5, r6 /* set the IPI */ | |
774 | sync | |
775 | b ext_interrupt_to_host | |
776 | ||
777 | ext_stash_for_host: | |
778 | /* It's not an IPI and it's for the host, stash it in the PACA | |
779 | * before exit, it will be picked up by the host ICP driver | |
780 | */ | |
781 | stw r3, HSTATE_SAVED_XIRR(r13) | |
782 | ext_interrupt_to_host: | |
de56a948 | 783 | |
b4072df4 | 784 | guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */ |
de56a948 PM |
785 | /* Save DEC */ |
786 | mfspr r5,SPRN_DEC | |
787 | mftb r6 | |
788 | extsw r5,r5 | |
789 | add r5,r5,r6 | |
790 | std r5,VCPU_DEC_EXPIRES(r9) | |
791 | ||
de56a948 | 792 | /* Save more register state */ |
de56a948 PM |
793 | mfdar r6 |
794 | mfdsisr r7 | |
de56a948 PM |
795 | std r6, VCPU_DAR(r9) |
796 | stw r7, VCPU_DSISR(r9) | |
9e368f29 | 797 | BEGIN_FTR_SECTION |
697d3899 | 798 | /* don't overwrite fault_dar/fault_dsisr if HDSI */ |
de56a948 PM |
799 | cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE |
800 | beq 6f | |
9e368f29 | 801 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
697d3899 | 802 | std r6, VCPU_FAULT_DAR(r9) |
de56a948 PM |
803 | stw r7, VCPU_FAULT_DSISR(r9) |
804 | ||
b4072df4 PM |
805 | /* See if it is a machine check */ |
806 | cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
807 | beq machine_check_realmode | |
808 | mc_cont: | |
809 | ||
de56a948 | 810 | /* Save guest CTRL register, set runlatch to 1 */ |
697d3899 | 811 | 6: mfspr r6,SPRN_CTRLF |
de56a948 PM |
812 | stw r6,VCPU_CTRL(r9) |
813 | andi. r0,r6,1 | |
814 | bne 4f | |
815 | ori r6,r6,1 | |
816 | mtspr SPRN_CTRLT,r6 | |
817 | 4: | |
818 | /* Read the guest SLB and save it away */ | |
819 | lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */ | |
820 | mtctr r0 | |
821 | li r6,0 | |
822 | addi r7,r9,VCPU_SLB | |
823 | li r5,0 | |
824 | 1: slbmfee r8,r6 | |
825 | andis. r0,r8,SLB_ESID_V@h | |
826 | beq 2f | |
827 | add r8,r8,r6 /* put index in */ | |
828 | slbmfev r3,r6 | |
829 | std r8,VCPU_SLB_E(r7) | |
830 | std r3,VCPU_SLB_V(r7) | |
831 | addi r7,r7,VCPU_SLB_SIZE | |
832 | addi r5,r5,1 | |
833 | 2: addi r6,r6,1 | |
834 | bdnz 1b | |
835 | stw r5,VCPU_SLB_MAX(r9) | |
836 | ||
837 | /* | |
838 | * Save the guest PURR/SPURR | |
839 | */ | |
9e368f29 | 840 | BEGIN_FTR_SECTION |
de56a948 PM |
841 | mfspr r5,SPRN_PURR |
842 | mfspr r6,SPRN_SPURR | |
843 | ld r7,VCPU_PURR(r9) | |
844 | ld r8,VCPU_SPURR(r9) | |
845 | std r5,VCPU_PURR(r9) | |
846 | std r6,VCPU_SPURR(r9) | |
847 | subf r5,r7,r5 | |
848 | subf r6,r8,r6 | |
849 | ||
850 | /* | |
851 | * Restore host PURR/SPURR and add guest times | |
852 | * so that the time in the guest gets accounted. | |
853 | */ | |
854 | ld r3,HSTATE_PURR(r13) | |
855 | ld r4,HSTATE_SPURR(r13) | |
856 | add r3,r3,r5 | |
857 | add r4,r4,r6 | |
858 | mtspr SPRN_PURR,r3 | |
859 | mtspr SPRN_SPURR,r4 | |
9e368f29 | 860 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201) |
de56a948 PM |
861 | |
862 | /* Clear out SLB */ | |
863 | li r5,0 | |
864 | slbmte r5,r5 | |
865 | slbia | |
866 | ptesync | |
867 | ||
19ccb76a | 868 | hdec_soon: /* r9 = vcpu, r12 = trap, r13 = paca */ |
9e368f29 PM |
869 | BEGIN_FTR_SECTION |
870 | b 32f | |
871 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
872 | /* | |
873 | * POWER7 guest -> host partition switch code. | |
874 | * We don't have to lock against tlbies but we do | |
875 | * have to coordinate the hardware threads. | |
876 | */ | |
371fefd6 PM |
877 | /* Increment the threads-exiting-guest count in the 0xff00 |
878 | bits of vcore->entry_exit_count */ | |
879 | lwsync | |
880 | ld r5,HSTATE_KVM_VCORE(r13) | |
881 | addi r6,r5,VCORE_ENTRY_EXIT | |
882 | 41: lwarx r3,0,r6 | |
883 | addi r0,r3,0x100 | |
884 | stwcx. r0,0,r6 | |
885 | bne 41b | |
19ccb76a | 886 | lwsync |
371fefd6 PM |
887 | |
888 | /* | |
889 | * At this point we have an interrupt that we have to pass | |
890 | * up to the kernel or qemu; we can't handle it in real mode. | |
891 | * Thus we have to do a partition switch, so we have to | |
892 | * collect the other threads, if we are the first thread | |
893 | * to take an interrupt. To do this, we set the HDEC to 0, | |
894 | * which causes an HDEC interrupt in all threads within 2ns | |
895 | * because the HDEC register is shared between all 4 threads. | |
896 | * However, we don't need to bother if this is an HDEC | |
897 | * interrupt, since the other threads will already be on their | |
898 | * way here in that case. | |
899 | */ | |
19ccb76a PM |
900 | cmpwi r3,0x100 /* Are we the first here? */ |
901 | bge 43f | |
902 | cmpwi r3,1 /* Are any other threads in the guest? */ | |
903 | ble 43f | |
371fefd6 PM |
904 | cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER |
905 | beq 40f | |
371fefd6 PM |
906 | li r0,0 |
907 | mtspr SPRN_HDEC,r0 | |
908 | 40: | |
19ccb76a PM |
909 | /* |
910 | * Send an IPI to any napping threads, since an HDEC interrupt | |
911 | * doesn't wake CPUs up from nap. | |
912 | */ | |
913 | lwz r3,VCORE_NAPPING_THREADS(r5) | |
914 | lwz r4,VCPU_PTID(r9) | |
915 | li r0,1 | |
2f584a14 | 916 | sld r0,r0,r4 |
19ccb76a PM |
917 | andc. r3,r3,r0 /* no sense IPI'ing ourselves */ |
918 | beq 43f | |
919 | mulli r4,r4,PACA_SIZE /* get paca for thread 0 */ | |
920 | subf r6,r4,r13 | |
921 | 42: andi. r0,r3,1 | |
922 | beq 44f | |
923 | ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */ | |
924 | li r0,IPI_PRIORITY | |
54695c30 | 925 | li r7,XICS_MFRR |
19ccb76a PM |
926 | stbcix r0,r7,r8 /* trigger the IPI */ |
927 | 44: srdi. r3,r3,1 | |
928 | addi r6,r6,PACA_SIZE | |
929 | bne 42b | |
371fefd6 PM |
930 | |
931 | /* Secondary threads wait for primary to do partition switch */ | |
19ccb76a | 932 | 43: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */ |
371fefd6 PM |
933 | ld r5,HSTATE_KVM_VCORE(r13) |
934 | lwz r3,VCPU_PTID(r9) | |
935 | cmpwi r3,0 | |
936 | beq 15f | |
937 | HMT_LOW | |
938 | 13: lbz r3,VCORE_IN_GUEST(r5) | |
939 | cmpwi r3,0 | |
940 | bne 13b | |
941 | HMT_MEDIUM | |
942 | b 16f | |
943 | ||
944 | /* Primary thread waits for all the secondaries to exit guest */ | |
945 | 15: lwz r3,VCORE_ENTRY_EXIT(r5) | |
946 | srwi r0,r3,8 | |
947 | clrldi r3,r3,56 | |
948 | cmpw r3,r0 | |
949 | bne 15b | |
950 | isync | |
951 | ||
952 | /* Primary thread switches back to host partition */ | |
de56a948 PM |
953 | ld r6,KVM_HOST_SDR1(r4) |
954 | lwz r7,KVM_HOST_LPID(r4) | |
955 | li r8,LPID_RSVD /* switch to reserved LPID */ | |
956 | mtspr SPRN_LPID,r8 | |
957 | ptesync | |
958 | mtspr SPRN_SDR1,r6 /* switch to partition page table */ | |
959 | mtspr SPRN_LPID,r7 | |
960 | isync | |
371fefd6 PM |
961 | li r0,0 |
962 | stb r0,VCORE_IN_GUEST(r5) | |
de56a948 PM |
963 | lis r8,0x7fff /* MAX_INT@h */ |
964 | mtspr SPRN_HDEC,r8 | |
965 | ||
371fefd6 | 966 | 16: ld r8,KVM_HOST_LPCR(r4) |
de56a948 PM |
967 | mtspr SPRN_LPCR,r8 |
968 | isync | |
9e368f29 PM |
969 | b 33f |
970 | ||
971 | /* | |
972 | * PPC970 guest -> host partition switch code. | |
973 | * We have to lock against concurrent tlbies, and | |
974 | * we have to flush the whole TLB. | |
975 | */ | |
976 | 32: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */ | |
977 | ||
978 | /* Take the guest's tlbie_lock */ | |
54bb7f4b | 979 | #ifdef __BIG_ENDIAN__ |
9e368f29 | 980 | lwz r8,PACA_LOCK_TOKEN(r13) |
54bb7f4b AB |
981 | #else |
982 | lwz r8,PACAPACAINDEX(r13) | |
983 | #endif | |
9e368f29 PM |
984 | addi r3,r4,KVM_TLBIE_LOCK |
985 | 24: lwarx r0,0,r3 | |
986 | cmpwi r0,0 | |
987 | bne 24b | |
988 | stwcx. r8,0,r3 | |
989 | bne 24b | |
990 | isync | |
991 | ||
992 | ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */ | |
993 | li r0,0x18f | |
994 | rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */ | |
995 | or r0,r7,r0 | |
996 | ptesync | |
997 | sync | |
998 | mtspr SPRN_HID4,r0 /* switch to reserved LPID */ | |
999 | isync | |
1000 | li r0,0 | |
1001 | stw r0,0(r3) /* drop guest tlbie_lock */ | |
1002 | ||
1003 | /* invalidate the whole TLB */ | |
1004 | li r0,256 | |
1005 | mtctr r0 | |
1006 | li r6,0 | |
1007 | 25: tlbiel r6 | |
1008 | addi r6,r6,0x1000 | |
1009 | bdnz 25b | |
1010 | ptesync | |
1011 | ||
1012 | /* take native_tlbie_lock */ | |
1013 | ld r3,toc_tlbie_lock@toc(2) | |
1014 | 24: lwarx r0,0,r3 | |
1015 | cmpwi r0,0 | |
1016 | bne 24b | |
1017 | stwcx. r8,0,r3 | |
1018 | bne 24b | |
1019 | isync | |
1020 | ||
1021 | ld r6,KVM_HOST_SDR1(r4) | |
1022 | mtspr SPRN_SDR1,r6 /* switch to host page table */ | |
1023 | ||
1024 | /* Set up host HID4 value */ | |
1025 | sync | |
1026 | mtspr SPRN_HID4,r7 | |
1027 | isync | |
1028 | li r0,0 | |
1029 | stw r0,0(r3) /* drop native_tlbie_lock */ | |
1030 | ||
1031 | lis r8,0x7fff /* MAX_INT@h */ | |
1032 | mtspr SPRN_HDEC,r8 | |
1033 | ||
1034 | /* Disable HDEC interrupts */ | |
1035 | mfspr r0,SPRN_HID0 | |
1036 | li r3,0 | |
1037 | rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1 | |
1038 | sync | |
1039 | mtspr SPRN_HID0,r0 | |
1040 | mfspr r0,SPRN_HID0 | |
1041 | mfspr r0,SPRN_HID0 | |
1042 | mfspr r0,SPRN_HID0 | |
1043 | mfspr r0,SPRN_HID0 | |
1044 | mfspr r0,SPRN_HID0 | |
1045 | mfspr r0,SPRN_HID0 | |
de56a948 PM |
1046 | |
1047 | /* load host SLB entries */ | |
9e368f29 | 1048 | 33: ld r8,PACA_SLBSHADOWPTR(r13) |
de56a948 PM |
1049 | |
1050 | .rept SLB_NUM_BOLTED | |
1051 | ld r5,SLBSHADOW_SAVEAREA(r8) | |
1052 | ld r6,SLBSHADOW_SAVEAREA+8(r8) | |
1053 | andis. r7,r5,SLB_ESID_V@h | |
1054 | beq 1f | |
1055 | slbmte r6,r5 | |
1056 | 1: addi r8,r8,16 | |
1057 | .endr | |
1058 | ||
1059 | /* Save and reset AMR and UAMOR before turning on the MMU */ | |
9e368f29 | 1060 | BEGIN_FTR_SECTION |
de56a948 PM |
1061 | mfspr r5,SPRN_AMR |
1062 | mfspr r6,SPRN_UAMOR | |
1063 | std r5,VCPU_AMR(r9) | |
1064 | std r6,VCPU_UAMOR(r9) | |
1065 | li r6,0 | |
1066 | mtspr SPRN_AMR,r6 | |
9e368f29 | 1067 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 | 1068 | |
de56a948 | 1069 | /* Switch DSCR back to host value */ |
9e368f29 | 1070 | BEGIN_FTR_SECTION |
de56a948 PM |
1071 | mfspr r8, SPRN_DSCR |
1072 | ld r7, HSTATE_DSCR(r13) | |
1073 | std r8, VCPU_DSCR(r7) | |
1074 | mtspr SPRN_DSCR, r7 | |
9e368f29 | 1075 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 PM |
1076 | |
1077 | /* Save non-volatile GPRs */ | |
c75df6f9 MN |
1078 | std r14, VCPU_GPR(R14)(r9) |
1079 | std r15, VCPU_GPR(R15)(r9) | |
1080 | std r16, VCPU_GPR(R16)(r9) | |
1081 | std r17, VCPU_GPR(R17)(r9) | |
1082 | std r18, VCPU_GPR(R18)(r9) | |
1083 | std r19, VCPU_GPR(R19)(r9) | |
1084 | std r20, VCPU_GPR(R20)(r9) | |
1085 | std r21, VCPU_GPR(R21)(r9) | |
1086 | std r22, VCPU_GPR(R22)(r9) | |
1087 | std r23, VCPU_GPR(R23)(r9) | |
1088 | std r24, VCPU_GPR(R24)(r9) | |
1089 | std r25, VCPU_GPR(R25)(r9) | |
1090 | std r26, VCPU_GPR(R26)(r9) | |
1091 | std r27, VCPU_GPR(R27)(r9) | |
1092 | std r28, VCPU_GPR(R28)(r9) | |
1093 | std r29, VCPU_GPR(R29)(r9) | |
1094 | std r30, VCPU_GPR(R30)(r9) | |
1095 | std r31, VCPU_GPR(R31)(r9) | |
de56a948 PM |
1096 | |
1097 | /* Save SPRGs */ | |
1098 | mfspr r3, SPRN_SPRG0 | |
1099 | mfspr r4, SPRN_SPRG1 | |
1100 | mfspr r5, SPRN_SPRG2 | |
1101 | mfspr r6, SPRN_SPRG3 | |
1102 | std r3, VCPU_SPRG0(r9) | |
1103 | std r4, VCPU_SPRG1(r9) | |
1104 | std r5, VCPU_SPRG2(r9) | |
1105 | std r6, VCPU_SPRG3(r9) | |
1106 | ||
8943633c PM |
1107 | /* save FP state */ |
1108 | mr r3, r9 | |
1109 | bl .kvmppc_save_fp | |
1110 | ||
a8606e20 PM |
1111 | /* Increment yield count if they have a VPA */ |
1112 | ld r8, VCPU_VPA(r9) /* do they have a VPA? */ | |
1113 | cmpdi r8, 0 | |
1114 | beq 25f | |
1115 | lwz r3, LPPACA_YIELDCOUNT(r8) | |
1116 | addi r3, r3, 1 | |
1117 | stw r3, LPPACA_YIELDCOUNT(r8) | |
c35635ef PM |
1118 | li r3, 1 |
1119 | stb r3, VCPU_VPA_DIRTY(r9) | |
a8606e20 PM |
1120 | 25: |
1121 | /* Save PMU registers if requested */ | |
1122 | /* r8 and cr0.eq are live here */ | |
de56a948 PM |
1123 | li r3, 1 |
1124 | sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */ | |
1125 | mfspr r4, SPRN_MMCR0 /* save MMCR0 */ | |
1126 | mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */ | |
8943633c PM |
1127 | mfspr r6, SPRN_MMCRA |
1128 | BEGIN_FTR_SECTION | |
1129 | /* On P7, clear MMCRA in order to disable SDAR updates */ | |
1130 | li r7, 0 | |
1131 | mtspr SPRN_MMCRA, r7 | |
1132 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) | |
de56a948 | 1133 | isync |
a8606e20 PM |
1134 | beq 21f /* if no VPA, save PMU stuff anyway */ |
1135 | lbz r7, LPPACA_PMCINUSE(r8) | |
1136 | cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */ | |
1137 | bne 21f | |
1138 | std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */ | |
1139 | b 22f | |
1140 | 21: mfspr r5, SPRN_MMCR1 | |
14941789 PM |
1141 | mfspr r7, SPRN_SIAR |
1142 | mfspr r8, SPRN_SDAR | |
de56a948 PM |
1143 | std r4, VCPU_MMCR(r9) |
1144 | std r5, VCPU_MMCR + 8(r9) | |
1145 | std r6, VCPU_MMCR + 16(r9) | |
14941789 PM |
1146 | std r7, VCPU_SIAR(r9) |
1147 | std r8, VCPU_SDAR(r9) | |
de56a948 PM |
1148 | mfspr r3, SPRN_PMC1 |
1149 | mfspr r4, SPRN_PMC2 | |
1150 | mfspr r5, SPRN_PMC3 | |
1151 | mfspr r6, SPRN_PMC4 | |
1152 | mfspr r7, SPRN_PMC5 | |
1153 | mfspr r8, SPRN_PMC6 | |
9e368f29 PM |
1154 | BEGIN_FTR_SECTION |
1155 | mfspr r10, SPRN_PMC7 | |
1156 | mfspr r11, SPRN_PMC8 | |
1157 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
1158 | stw r3, VCPU_PMC(r9) |
1159 | stw r4, VCPU_PMC + 4(r9) | |
1160 | stw r5, VCPU_PMC + 8(r9) | |
1161 | stw r6, VCPU_PMC + 12(r9) | |
1162 | stw r7, VCPU_PMC + 16(r9) | |
1163 | stw r8, VCPU_PMC + 20(r9) | |
9e368f29 PM |
1164 | BEGIN_FTR_SECTION |
1165 | stw r10, VCPU_PMC + 24(r9) | |
1166 | stw r11, VCPU_PMC + 28(r9) | |
1167 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 | 1168 | 22: |
de56a948 | 1169 | |
9e368f29 PM |
1170 | /* Secondary threads go off to take a nap on POWER7 */ |
1171 | BEGIN_FTR_SECTION | |
8943633c | 1172 | lwz r0,VCPU_PTID(r9) |
371fefd6 PM |
1173 | cmpwi r0,0 |
1174 | bne secondary_nap | |
9e368f29 | 1175 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
371fefd6 | 1176 | |
8943633c PM |
1177 | /* Restore host DABR and DABRX */ |
1178 | ld r5,HSTATE_DABR(r13) | |
1179 | li r6,7 | |
1180 | mtspr SPRN_DABR,r5 | |
1181 | mtspr SPRN_DABRX,r6 | |
1182 | ||
18ad51dd | 1183 | /* Restore SPRG3 */ |
0127262c | 1184 | ld r3,PACA_SPRG3(r13) |
18ad51dd AB |
1185 | mtspr SPRN_SPRG3,r3 |
1186 | ||
de56a948 PM |
1187 | /* |
1188 | * Reload DEC. HDEC interrupts were disabled when | |
1189 | * we reloaded the host's LPCR value. | |
1190 | */ | |
1191 | ld r3, HSTATE_DECEXP(r13) | |
1192 | mftb r4 | |
1193 | subf r4, r4, r3 | |
1194 | mtspr SPRN_DEC, r4 | |
1195 | ||
1196 | /* Reload the host's PMU registers */ | |
1197 | ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */ | |
1198 | lbz r4, LPPACA_PMCINUSE(r3) | |
1199 | cmpwi r4, 0 | |
1200 | beq 23f /* skip if not */ | |
1201 | lwz r3, HSTATE_PMC(r13) | |
1202 | lwz r4, HSTATE_PMC + 4(r13) | |
1203 | lwz r5, HSTATE_PMC + 8(r13) | |
1204 | lwz r6, HSTATE_PMC + 12(r13) | |
1205 | lwz r8, HSTATE_PMC + 16(r13) | |
1206 | lwz r9, HSTATE_PMC + 20(r13) | |
9e368f29 PM |
1207 | BEGIN_FTR_SECTION |
1208 | lwz r10, HSTATE_PMC + 24(r13) | |
1209 | lwz r11, HSTATE_PMC + 28(r13) | |
1210 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
1211 | mtspr SPRN_PMC1, r3 |
1212 | mtspr SPRN_PMC2, r4 | |
1213 | mtspr SPRN_PMC3, r5 | |
1214 | mtspr SPRN_PMC4, r6 | |
1215 | mtspr SPRN_PMC5, r8 | |
1216 | mtspr SPRN_PMC6, r9 | |
9e368f29 PM |
1217 | BEGIN_FTR_SECTION |
1218 | mtspr SPRN_PMC7, r10 | |
1219 | mtspr SPRN_PMC8, r11 | |
1220 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) | |
de56a948 PM |
1221 | ld r3, HSTATE_MMCR(r13) |
1222 | ld r4, HSTATE_MMCR + 8(r13) | |
1223 | ld r5, HSTATE_MMCR + 16(r13) | |
1224 | mtspr SPRN_MMCR1, r4 | |
1225 | mtspr SPRN_MMCRA, r5 | |
1226 | mtspr SPRN_MMCR0, r3 | |
1227 | isync | |
1228 | 23: | |
1229 | /* | |
1230 | * For external and machine check interrupts, we need | |
1231 | * to call the Linux handler to process the interrupt. | |
b4072df4 PM |
1232 | * We do that by jumping to absolute address 0x500 for |
1233 | * external interrupts, or the machine_check_fwnmi label | |
1234 | * for machine checks (since firmware might have patched | |
1235 | * the vector area at 0x200). The [h]rfid at the end of the | |
de56a948 PM |
1236 | * handler will return to the book3s_hv_interrupts.S code. |
1237 | * For other interrupts we do the rfid to get back | |
b4072df4 | 1238 | * to the book3s_hv_interrupts.S code here. |
de56a948 PM |
1239 | */ |
1240 | ld r8, HSTATE_VMHANDLER(r13) | |
1241 | ld r7, HSTATE_HOST_MSR(r13) | |
1242 | ||
b4072df4 | 1243 | cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK |
de56a948 | 1244 | cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL |
b4072df4 | 1245 | BEGIN_FTR_SECTION |
de56a948 | 1246 | beq 11f |
b4072df4 | 1247 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206) |
de56a948 PM |
1248 | |
1249 | /* RFI into the highmem handler, or branch to interrupt handler */ | |
b4072df4 | 1250 | mfmsr r6 |
de56a948 PM |
1251 | li r0, MSR_RI |
1252 | andc r6, r6, r0 | |
1253 | mtmsrd r6, 1 /* Clear RI in MSR */ | |
1254 | mtsrr0 r8 | |
1255 | mtsrr1 r7 | |
b4072df4 PM |
1256 | beqa 0x500 /* external interrupt (PPC970) */ |
1257 | beq cr1, 13f /* machine check */ | |
de56a948 PM |
1258 | RFI |
1259 | ||
b4072df4 PM |
1260 | /* On POWER7, we have external interrupts set to use HSRR0/1 */ |
1261 | 11: mtspr SPRN_HSRR0, r8 | |
de56a948 PM |
1262 | mtspr SPRN_HSRR1, r7 |
1263 | ba 0x500 | |
1264 | ||
b4072df4 PM |
1265 | 13: b machine_check_fwnmi |
1266 | ||
697d3899 PM |
1267 | /* |
1268 | * Check whether an HDSI is an HPTE not found fault or something else. | |
1269 | * If it is an HPTE not found fault that is due to the guest accessing | |
1270 | * a page that they have mapped but which we have paged out, then | |
1271 | * we continue on with the guest exit path. In all other cases, | |
1272 | * reflect the HDSI to the guest as a DSI. | |
1273 | */ | |
1274 | kvmppc_hdsi: | |
1275 | mfspr r4, SPRN_HDAR | |
1276 | mfspr r6, SPRN_HDSISR | |
4cf302bc PM |
1277 | /* HPTE not found fault or protection fault? */ |
1278 | andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h | |
697d3899 PM |
1279 | beq 1f /* if not, send it to the guest */ |
1280 | andi. r0, r11, MSR_DR /* data relocation enabled? */ | |
1281 | beq 3f | |
1282 | clrrdi r0, r4, 28 | |
c75df6f9 | 1283 | PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */ |
697d3899 PM |
1284 | bne 1f /* if no SLB entry found */ |
1285 | 4: std r4, VCPU_FAULT_DAR(r9) | |
1286 | stw r6, VCPU_FAULT_DSISR(r9) | |
1287 | ||
1288 | /* Search the hash table. */ | |
1289 | mr r3, r9 /* vcpu pointer */ | |
342d3db7 | 1290 | li r7, 1 /* data fault */ |
697d3899 PM |
1291 | bl .kvmppc_hpte_hv_fault |
1292 | ld r9, HSTATE_KVM_VCPU(r13) | |
1293 | ld r10, VCPU_PC(r9) | |
1294 | ld r11, VCPU_MSR(r9) | |
1295 | li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE | |
1296 | cmpdi r3, 0 /* retry the instruction */ | |
1297 | beq 6f | |
1298 | cmpdi r3, -1 /* handle in kernel mode */ | |
b4072df4 | 1299 | beq guest_exit_cont |
697d3899 PM |
1300 | cmpdi r3, -2 /* MMIO emulation; need instr word */ |
1301 | beq 2f | |
1302 | ||
1303 | /* Synthesize a DSI for the guest */ | |
1304 | ld r4, VCPU_FAULT_DAR(r9) | |
1305 | mr r6, r3 | |
1306 | 1: mtspr SPRN_DAR, r4 | |
1307 | mtspr SPRN_DSISR, r6 | |
1308 | mtspr SPRN_SRR0, r10 | |
1309 | mtspr SPRN_SRR1, r11 | |
1310 | li r10, BOOK3S_INTERRUPT_DATA_STORAGE | |
1311 | li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
1312 | rotldi r11, r11, 63 | |
b4072df4 | 1313 | fast_interrupt_c_return: |
697d3899 PM |
1314 | 6: ld r7, VCPU_CTR(r9) |
1315 | lwz r8, VCPU_XER(r9) | |
1316 | mtctr r7 | |
1317 | mtxer r8 | |
1318 | mr r4, r9 | |
1319 | b fast_guest_return | |
1320 | ||
1321 | 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */ | |
1322 | ld r5, KVM_VRMA_SLB_V(r5) | |
1323 | b 4b | |
1324 | ||
1325 | /* If this is for emulated MMIO, load the instruction word */ | |
1326 | 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */ | |
1327 | ||
1328 | /* Set guest mode to 'jump over instruction' so if lwz faults | |
1329 | * we'll just continue at the next IP. */ | |
1330 | li r0, KVM_GUEST_MODE_SKIP | |
1331 | stb r0, HSTATE_IN_GUEST(r13) | |
1332 | ||
1333 | /* Do the access with MSR:DR enabled */ | |
1334 | mfmsr r3 | |
1335 | ori r4, r3, MSR_DR /* Enable paging for data */ | |
1336 | mtmsrd r4 | |
1337 | lwz r8, 0(r10) | |
1338 | mtmsrd r3 | |
1339 | ||
1340 | /* Store the result */ | |
1341 | stw r8, VCPU_LAST_INST(r9) | |
1342 | ||
1343 | /* Unset guest mode. */ | |
1344 | li r0, KVM_GUEST_MODE_NONE | |
1345 | stb r0, HSTATE_IN_GUEST(r13) | |
b4072df4 | 1346 | b guest_exit_cont |
de56a948 | 1347 | |
342d3db7 PM |
1348 | /* |
1349 | * Similarly for an HISI, reflect it to the guest as an ISI unless | |
1350 | * it is an HPTE not found fault for a page that we have paged out. | |
1351 | */ | |
1352 | kvmppc_hisi: | |
1353 | andis. r0, r11, SRR1_ISI_NOPT@h | |
1354 | beq 1f | |
1355 | andi. r0, r11, MSR_IR /* instruction relocation enabled? */ | |
1356 | beq 3f | |
1357 | clrrdi r0, r10, 28 | |
c75df6f9 | 1358 | PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */ |
342d3db7 PM |
1359 | bne 1f /* if no SLB entry found */ |
1360 | 4: | |
1361 | /* Search the hash table. */ | |
1362 | mr r3, r9 /* vcpu pointer */ | |
1363 | mr r4, r10 | |
1364 | mr r6, r11 | |
1365 | li r7, 0 /* instruction fault */ | |
1366 | bl .kvmppc_hpte_hv_fault | |
1367 | ld r9, HSTATE_KVM_VCPU(r13) | |
1368 | ld r10, VCPU_PC(r9) | |
1369 | ld r11, VCPU_MSR(r9) | |
1370 | li r12, BOOK3S_INTERRUPT_H_INST_STORAGE | |
1371 | cmpdi r3, 0 /* retry the instruction */ | |
b4072df4 | 1372 | beq fast_interrupt_c_return |
342d3db7 | 1373 | cmpdi r3, -1 /* handle in kernel mode */ |
b4072df4 | 1374 | beq guest_exit_cont |
342d3db7 PM |
1375 | |
1376 | /* Synthesize an ISI for the guest */ | |
1377 | mr r11, r3 | |
1378 | 1: mtspr SPRN_SRR0, r10 | |
1379 | mtspr SPRN_SRR1, r11 | |
1380 | li r10, BOOK3S_INTERRUPT_INST_STORAGE | |
1381 | li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
1382 | rotldi r11, r11, 63 | |
b4072df4 | 1383 | b fast_interrupt_c_return |
342d3db7 PM |
1384 | |
1385 | 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */ | |
1386 | ld r5, KVM_VRMA_SLB_V(r6) | |
1387 | b 4b | |
1388 | ||
a8606e20 PM |
1389 | /* |
1390 | * Try to handle an hcall in real mode. | |
1391 | * Returns to the guest if we handle it, or continues on up to | |
1392 | * the kernel if we can't (i.e. if we don't have a handler for | |
1393 | * it, or if the handler returns H_TOO_HARD). | |
1394 | */ | |
1395 | .globl hcall_try_real_mode | |
1396 | hcall_try_real_mode: | |
c75df6f9 | 1397 | ld r3,VCPU_GPR(R3)(r9) |
a8606e20 | 1398 | andi. r0,r11,MSR_PR |
b4072df4 | 1399 | bne guest_exit_cont |
a8606e20 PM |
1400 | clrrdi r3,r3,2 |
1401 | cmpldi r3,hcall_real_table_end - hcall_real_table | |
b4072df4 | 1402 | bge guest_exit_cont |
a8606e20 | 1403 | LOAD_REG_ADDR(r4, hcall_real_table) |
4baa1d87 | 1404 | lwax r3,r3,r4 |
a8606e20 | 1405 | cmpwi r3,0 |
b4072df4 | 1406 | beq guest_exit_cont |
a8606e20 PM |
1407 | add r3,r3,r4 |
1408 | mtctr r3 | |
1409 | mr r3,r9 /* get vcpu pointer */ | |
c75df6f9 | 1410 | ld r4,VCPU_GPR(R4)(r9) |
a8606e20 PM |
1411 | bctrl |
1412 | cmpdi r3,H_TOO_HARD | |
1413 | beq hcall_real_fallback | |
1414 | ld r4,HSTATE_KVM_VCPU(r13) | |
c75df6f9 | 1415 | std r3,VCPU_GPR(R3)(r4) |
a8606e20 PM |
1416 | ld r10,VCPU_PC(r4) |
1417 | ld r11,VCPU_MSR(r4) | |
1418 | b fast_guest_return | |
1419 | ||
1420 | /* We've attempted a real mode hcall, but it's punted it back | |
1421 | * to userspace. We need to restore some clobbered volatiles | |
1422 | * before resuming the pass-it-to-qemu path */ | |
1423 | hcall_real_fallback: | |
1424 | li r12,BOOK3S_INTERRUPT_SYSCALL | |
1425 | ld r9, HSTATE_KVM_VCPU(r13) | |
a8606e20 | 1426 | |
b4072df4 | 1427 | b guest_exit_cont |
a8606e20 PM |
1428 | |
1429 | .globl hcall_real_table | |
1430 | hcall_real_table: | |
1431 | .long 0 /* 0 - unused */ | |
1432 | .long .kvmppc_h_remove - hcall_real_table | |
1433 | .long .kvmppc_h_enter - hcall_real_table | |
1434 | .long .kvmppc_h_read - hcall_real_table | |
1435 | .long 0 /* 0x10 - H_CLEAR_MOD */ | |
1436 | .long 0 /* 0x14 - H_CLEAR_REF */ | |
1437 | .long .kvmppc_h_protect - hcall_real_table | |
1438 | .long 0 /* 0x1c - H_GET_TCE */ | |
54738c09 | 1439 | .long .kvmppc_h_put_tce - hcall_real_table |
a8606e20 PM |
1440 | .long 0 /* 0x24 - H_SET_SPRG0 */ |
1441 | .long .kvmppc_h_set_dabr - hcall_real_table | |
1442 | .long 0 /* 0x2c */ | |
1443 | .long 0 /* 0x30 */ | |
1444 | .long 0 /* 0x34 */ | |
1445 | .long 0 /* 0x38 */ | |
1446 | .long 0 /* 0x3c */ | |
1447 | .long 0 /* 0x40 */ | |
1448 | .long 0 /* 0x44 */ | |
1449 | .long 0 /* 0x48 */ | |
1450 | .long 0 /* 0x4c */ | |
1451 | .long 0 /* 0x50 */ | |
1452 | .long 0 /* 0x54 */ | |
1453 | .long 0 /* 0x58 */ | |
1454 | .long 0 /* 0x5c */ | |
1455 | .long 0 /* 0x60 */ | |
e7d26f28 BH |
1456 | #ifdef CONFIG_KVM_XICS |
1457 | .long .kvmppc_rm_h_eoi - hcall_real_table | |
1458 | .long .kvmppc_rm_h_cppr - hcall_real_table | |
1459 | .long .kvmppc_rm_h_ipi - hcall_real_table | |
1460 | .long 0 /* 0x70 - H_IPOLL */ | |
1461 | .long .kvmppc_rm_h_xirr - hcall_real_table | |
1462 | #else | |
1463 | .long 0 /* 0x64 - H_EOI */ | |
1464 | .long 0 /* 0x68 - H_CPPR */ | |
1465 | .long 0 /* 0x6c - H_IPI */ | |
1466 | .long 0 /* 0x70 - H_IPOLL */ | |
1467 | .long 0 /* 0x74 - H_XIRR */ | |
1468 | #endif | |
a8606e20 PM |
1469 | .long 0 /* 0x78 */ |
1470 | .long 0 /* 0x7c */ | |
1471 | .long 0 /* 0x80 */ | |
1472 | .long 0 /* 0x84 */ | |
1473 | .long 0 /* 0x88 */ | |
1474 | .long 0 /* 0x8c */ | |
1475 | .long 0 /* 0x90 */ | |
1476 | .long 0 /* 0x94 */ | |
1477 | .long 0 /* 0x98 */ | |
1478 | .long 0 /* 0x9c */ | |
1479 | .long 0 /* 0xa0 */ | |
1480 | .long 0 /* 0xa4 */ | |
1481 | .long 0 /* 0xa8 */ | |
1482 | .long 0 /* 0xac */ | |
1483 | .long 0 /* 0xb0 */ | |
1484 | .long 0 /* 0xb4 */ | |
1485 | .long 0 /* 0xb8 */ | |
1486 | .long 0 /* 0xbc */ | |
1487 | .long 0 /* 0xc0 */ | |
1488 | .long 0 /* 0xc4 */ | |
1489 | .long 0 /* 0xc8 */ | |
1490 | .long 0 /* 0xcc */ | |
1491 | .long 0 /* 0xd0 */ | |
1492 | .long 0 /* 0xd4 */ | |
1493 | .long 0 /* 0xd8 */ | |
1494 | .long 0 /* 0xdc */ | |
19ccb76a | 1495 | .long .kvmppc_h_cede - hcall_real_table |
a8606e20 PM |
1496 | .long 0 /* 0xe4 */ |
1497 | .long 0 /* 0xe8 */ | |
1498 | .long 0 /* 0xec */ | |
1499 | .long 0 /* 0xf0 */ | |
1500 | .long 0 /* 0xf4 */ | |
1501 | .long 0 /* 0xf8 */ | |
1502 | .long 0 /* 0xfc */ | |
1503 | .long 0 /* 0x100 */ | |
1504 | .long 0 /* 0x104 */ | |
1505 | .long 0 /* 0x108 */ | |
1506 | .long 0 /* 0x10c */ | |
1507 | .long 0 /* 0x110 */ | |
1508 | .long 0 /* 0x114 */ | |
1509 | .long 0 /* 0x118 */ | |
1510 | .long 0 /* 0x11c */ | |
1511 | .long 0 /* 0x120 */ | |
1512 | .long .kvmppc_h_bulk_remove - hcall_real_table | |
1513 | hcall_real_table_end: | |
1514 | ||
de56a948 PM |
1515 | ignore_hdec: |
1516 | mr r4,r9 | |
1517 | b fast_guest_return | |
1518 | ||
a8606e20 PM |
1519 | _GLOBAL(kvmppc_h_set_dabr) |
1520 | std r4,VCPU_DABR(r3) | |
8943633c PM |
1521 | /* Work around P7 bug where DABR can get corrupted on mtspr */ |
1522 | 1: mtspr SPRN_DABR,r4 | |
1523 | mfspr r5, SPRN_DABR | |
1524 | cmpd r4, r5 | |
1525 | bne 1b | |
1526 | isync | |
a8606e20 PM |
1527 | li r3,0 |
1528 | blr | |
1529 | ||
19ccb76a PM |
1530 | _GLOBAL(kvmppc_h_cede) |
1531 | ori r11,r11,MSR_EE | |
1532 | std r11,VCPU_MSR(r3) | |
1533 | li r0,1 | |
1534 | stb r0,VCPU_CEDED(r3) | |
1535 | sync /* order setting ceded vs. testing prodded */ | |
1536 | lbz r5,VCPU_PRODDED(r3) | |
1537 | cmpwi r5,0 | |
04f995a5 | 1538 | bne kvm_cede_prodded |
19ccb76a PM |
1539 | li r0,0 /* set trap to 0 to say hcall is handled */ |
1540 | stw r0,VCPU_TRAP(r3) | |
1541 | li r0,H_SUCCESS | |
c75df6f9 | 1542 | std r0,VCPU_GPR(R3)(r3) |
19ccb76a | 1543 | BEGIN_FTR_SECTION |
04f995a5 | 1544 | b kvm_cede_exit /* just send it up to host on 970 */ |
19ccb76a PM |
1545 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206) |
1546 | ||
1547 | /* | |
1548 | * Set our bit in the bitmask of napping threads unless all the | |
1549 | * other threads are already napping, in which case we send this | |
1550 | * up to the host. | |
1551 | */ | |
1552 | ld r5,HSTATE_KVM_VCORE(r13) | |
1553 | lwz r6,VCPU_PTID(r3) | |
1554 | lwz r8,VCORE_ENTRY_EXIT(r5) | |
1555 | clrldi r8,r8,56 | |
1556 | li r0,1 | |
1557 | sld r0,r0,r6 | |
1558 | addi r6,r5,VCORE_NAPPING_THREADS | |
1559 | 31: lwarx r4,0,r6 | |
1560 | or r4,r4,r0 | |
c75df6f9 | 1561 | PPC_POPCNTW(R7,R4) |
19ccb76a | 1562 | cmpw r7,r8 |
04f995a5 | 1563 | bge kvm_cede_exit |
19ccb76a PM |
1564 | stwcx. r4,0,r6 |
1565 | bne 31b | |
1566 | li r0,1 | |
1567 | stb r0,HSTATE_NAPPING(r13) | |
1568 | /* order napping_threads update vs testing entry_exit_count */ | |
1569 | lwsync | |
1570 | mr r4,r3 | |
1571 | lwz r7,VCORE_ENTRY_EXIT(r5) | |
1572 | cmpwi r7,0x100 | |
1573 | bge 33f /* another thread already exiting */ | |
1574 | ||
1575 | /* | |
1576 | * Although not specifically required by the architecture, POWER7 | |
1577 | * preserves the following registers in nap mode, even if an SMT mode | |
1578 | * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3, | |
1579 | * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR. | |
1580 | */ | |
1581 | /* Save non-volatile GPRs */ | |
c75df6f9 MN |
1582 | std r14, VCPU_GPR(R14)(r3) |
1583 | std r15, VCPU_GPR(R15)(r3) | |
1584 | std r16, VCPU_GPR(R16)(r3) | |
1585 | std r17, VCPU_GPR(R17)(r3) | |
1586 | std r18, VCPU_GPR(R18)(r3) | |
1587 | std r19, VCPU_GPR(R19)(r3) | |
1588 | std r20, VCPU_GPR(R20)(r3) | |
1589 | std r21, VCPU_GPR(R21)(r3) | |
1590 | std r22, VCPU_GPR(R22)(r3) | |
1591 | std r23, VCPU_GPR(R23)(r3) | |
1592 | std r24, VCPU_GPR(R24)(r3) | |
1593 | std r25, VCPU_GPR(R25)(r3) | |
1594 | std r26, VCPU_GPR(R26)(r3) | |
1595 | std r27, VCPU_GPR(R27)(r3) | |
1596 | std r28, VCPU_GPR(R28)(r3) | |
1597 | std r29, VCPU_GPR(R29)(r3) | |
1598 | std r30, VCPU_GPR(R30)(r3) | |
1599 | std r31, VCPU_GPR(R31)(r3) | |
19ccb76a PM |
1600 | |
1601 | /* save FP state */ | |
1602 | bl .kvmppc_save_fp | |
1603 | ||
1604 | /* | |
1605 | * Take a nap until a decrementer or external interrupt occurs, | |
1606 | * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR | |
1607 | */ | |
f0888f70 PM |
1608 | li r0,1 |
1609 | stb r0,HSTATE_HWTHREAD_REQ(r13) | |
19ccb76a PM |
1610 | mfspr r5,SPRN_LPCR |
1611 | ori r5,r5,LPCR_PECE0 | LPCR_PECE1 | |
1612 | mtspr SPRN_LPCR,r5 | |
1613 | isync | |
1614 | li r0, 0 | |
1615 | std r0, HSTATE_SCRATCH0(r13) | |
1616 | ptesync | |
1617 | ld r0, HSTATE_SCRATCH0(r13) | |
1618 | 1: cmpd r0, r0 | |
1619 | bne 1b | |
1620 | nap | |
1621 | b . | |
1622 | ||
1623 | kvm_end_cede: | |
4619ac88 PM |
1624 | /* get vcpu pointer */ |
1625 | ld r4, HSTATE_KVM_VCPU(r13) | |
1626 | ||
19ccb76a PM |
1627 | /* Woken by external or decrementer interrupt */ |
1628 | ld r1, HSTATE_HOST_R1(r13) | |
19ccb76a | 1629 | |
19ccb76a PM |
1630 | /* load up FP state */ |
1631 | bl kvmppc_load_fp | |
1632 | ||
1633 | /* Load NV GPRS */ | |
c75df6f9 MN |
1634 | ld r14, VCPU_GPR(R14)(r4) |
1635 | ld r15, VCPU_GPR(R15)(r4) | |
1636 | ld r16, VCPU_GPR(R16)(r4) | |
1637 | ld r17, VCPU_GPR(R17)(r4) | |
1638 | ld r18, VCPU_GPR(R18)(r4) | |
1639 | ld r19, VCPU_GPR(R19)(r4) | |
1640 | ld r20, VCPU_GPR(R20)(r4) | |
1641 | ld r21, VCPU_GPR(R21)(r4) | |
1642 | ld r22, VCPU_GPR(R22)(r4) | |
1643 | ld r23, VCPU_GPR(R23)(r4) | |
1644 | ld r24, VCPU_GPR(R24)(r4) | |
1645 | ld r25, VCPU_GPR(R25)(r4) | |
1646 | ld r26, VCPU_GPR(R26)(r4) | |
1647 | ld r27, VCPU_GPR(R27)(r4) | |
1648 | ld r28, VCPU_GPR(R28)(r4) | |
1649 | ld r29, VCPU_GPR(R29)(r4) | |
1650 | ld r30, VCPU_GPR(R30)(r4) | |
1651 | ld r31, VCPU_GPR(R31)(r4) | |
19ccb76a PM |
1652 | |
1653 | /* clear our bit in vcore->napping_threads */ | |
1654 | 33: ld r5,HSTATE_KVM_VCORE(r13) | |
1655 | lwz r3,VCPU_PTID(r4) | |
1656 | li r0,1 | |
1657 | sld r0,r0,r3 | |
1658 | addi r6,r5,VCORE_NAPPING_THREADS | |
1659 | 32: lwarx r7,0,r6 | |
1660 | andc r7,r7,r0 | |
1661 | stwcx. r7,0,r6 | |
1662 | bne 32b | |
1663 | li r0,0 | |
1664 | stb r0,HSTATE_NAPPING(r13) | |
1665 | ||
4619ac88 PM |
1666 | /* Check the wake reason in SRR1 to see why we got here */ |
1667 | mfspr r3, SPRN_SRR1 | |
1668 | rlwinm r3, r3, 44-31, 0x7 /* extract wake reason field */ | |
1669 | cmpwi r3, 4 /* was it an external interrupt? */ | |
1670 | li r12, BOOK3S_INTERRUPT_EXTERNAL | |
1671 | mr r9, r4 | |
1672 | ld r10, VCPU_PC(r9) | |
1673 | ld r11, VCPU_MSR(r9) | |
1674 | beq do_ext_interrupt /* if so */ | |
1675 | ||
19ccb76a PM |
1676 | /* see if any other thread is already exiting */ |
1677 | lwz r0,VCORE_ENTRY_EXIT(r5) | |
1678 | cmpwi r0,0x100 | |
1679 | blt kvmppc_cede_reentry /* if not go back to guest */ | |
1680 | ||
1681 | /* some threads are exiting, so go to the guest exit path */ | |
1682 | b hcall_real_fallback | |
1683 | ||
1684 | /* cede when already previously prodded case */ | |
04f995a5 PM |
1685 | kvm_cede_prodded: |
1686 | li r0,0 | |
19ccb76a PM |
1687 | stb r0,VCPU_PRODDED(r3) |
1688 | sync /* order testing prodded vs. clearing ceded */ | |
1689 | stb r0,VCPU_CEDED(r3) | |
1690 | li r3,H_SUCCESS | |
1691 | blr | |
1692 | ||
1693 | /* we've ceded but we want to give control to the host */ | |
04f995a5 | 1694 | kvm_cede_exit: |
4619ac88 | 1695 | b hcall_real_fallback |
19ccb76a | 1696 | |
b4072df4 PM |
1697 | /* Try to handle a machine check in real mode */ |
1698 | machine_check_realmode: | |
1699 | mr r3, r9 /* get vcpu pointer */ | |
1700 | bl .kvmppc_realmode_machine_check | |
1701 | nop | |
1702 | cmpdi r3, 0 /* continue exiting from guest? */ | |
1703 | ld r9, HSTATE_KVM_VCPU(r13) | |
1704 | li r12, BOOK3S_INTERRUPT_MACHINE_CHECK | |
1705 | beq mc_cont | |
1706 | /* If not, deliver a machine check. SRR0/1 are already set */ | |
1707 | li r10, BOOK3S_INTERRUPT_MACHINE_CHECK | |
1708 | li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */ | |
1709 | rotldi r11, r11, 63 | |
1710 | b fast_interrupt_c_return | |
1711 | ||
371fefd6 PM |
1712 | secondary_too_late: |
1713 | ld r5,HSTATE_KVM_VCORE(r13) | |
1714 | HMT_LOW | |
1715 | 13: lbz r3,VCORE_IN_GUEST(r5) | |
1716 | cmpwi r3,0 | |
1717 | bne 13b | |
1718 | HMT_MEDIUM | |
1719 | ld r11,PACA_SLBSHADOWPTR(r13) | |
1720 | ||
1721 | .rept SLB_NUM_BOLTED | |
1722 | ld r5,SLBSHADOW_SAVEAREA(r11) | |
1723 | ld r6,SLBSHADOW_SAVEAREA+8(r11) | |
1724 | andis. r7,r5,SLB_ESID_V@h | |
1725 | beq 1f | |
1726 | slbmte r6,r5 | |
1727 | 1: addi r11,r11,16 | |
1728 | .endr | |
371fefd6 PM |
1729 | |
1730 | secondary_nap: | |
7b444c67 PM |
1731 | /* Clear our vcpu pointer so we don't come back in early */ |
1732 | li r0, 0 | |
1733 | std r0, HSTATE_KVM_VCPU(r13) | |
1734 | lwsync | |
19ccb76a PM |
1735 | /* Clear any pending IPI - assume we're a secondary thread */ |
1736 | ld r5, HSTATE_XICS_PHYS(r13) | |
1737 | li r7, XICS_XIRR | |
1738 | lwzcix r3, r5, r7 /* ack any pending interrupt */ | |
1739 | rlwinm. r0, r3, 0, 0xffffff /* any pending? */ | |
1740 | beq 37f | |
1741 | sync | |
371fefd6 | 1742 | li r0, 0xff |
54695c30 | 1743 | li r6, XICS_MFRR |
19ccb76a PM |
1744 | stbcix r0, r5, r6 /* clear the IPI */ |
1745 | stwcix r3, r5, r7 /* EOI it */ | |
1746 | 37: sync | |
371fefd6 PM |
1747 | |
1748 | /* increment the nap count and then go to nap mode */ | |
1749 | ld r4, HSTATE_KVM_VCORE(r13) | |
1750 | addi r4, r4, VCORE_NAP_COUNT | |
1751 | lwsync /* make previous updates visible */ | |
1752 | 51: lwarx r3, 0, r4 | |
1753 | addi r3, r3, 1 | |
1754 | stwcx. r3, 0, r4 | |
1755 | bne 51b | |
371fefd6 | 1756 | |
f0888f70 PM |
1757 | kvm_no_guest: |
1758 | li r0, KVM_HWTHREAD_IN_NAP | |
1759 | stb r0, HSTATE_HWTHREAD_STATE(r13) | |
f0888f70 | 1760 | |
19ccb76a | 1761 | li r3, LPCR_PECE0 |
371fefd6 | 1762 | mfspr r4, SPRN_LPCR |
19ccb76a | 1763 | rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1 |
371fefd6 | 1764 | mtspr SPRN_LPCR, r4 |
19ccb76a | 1765 | isync |
371fefd6 PM |
1766 | std r0, HSTATE_SCRATCH0(r13) |
1767 | ptesync | |
1768 | ld r0, HSTATE_SCRATCH0(r13) | |
1769 | 1: cmpd r0, r0 | |
1770 | bne 1b | |
1771 | nap | |
1772 | b . | |
1773 | ||
de56a948 PM |
1774 | /* |
1775 | * Save away FP, VMX and VSX registers. | |
1776 | * r3 = vcpu pointer | |
a8606e20 | 1777 | */ |
de56a948 | 1778 | _GLOBAL(kvmppc_save_fp) |
8943633c PM |
1779 | mfmsr r5 |
1780 | ori r8,r5,MSR_FP | |
de56a948 PM |
1781 | #ifdef CONFIG_ALTIVEC |
1782 | BEGIN_FTR_SECTION | |
1783 | oris r8,r8,MSR_VEC@h | |
1784 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1785 | #endif | |
1786 | #ifdef CONFIG_VSX | |
1787 | BEGIN_FTR_SECTION | |
1788 | oris r8,r8,MSR_VSX@h | |
1789 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1790 | #endif | |
1791 | mtmsrd r8 | |
1792 | isync | |
1793 | #ifdef CONFIG_VSX | |
1794 | BEGIN_FTR_SECTION | |
1795 | reg = 0 | |
1796 | .rept 32 | |
1797 | li r6,reg*16+VCPU_VSRS | |
c75df6f9 | 1798 | STXVD2X(reg,R6,R3) |
de56a948 PM |
1799 | reg = reg + 1 |
1800 | .endr | |
1801 | FTR_SECTION_ELSE | |
1802 | #endif | |
1803 | reg = 0 | |
1804 | .rept 32 | |
1805 | stfd reg,reg*8+VCPU_FPRS(r3) | |
1806 | reg = reg + 1 | |
1807 | .endr | |
1808 | #ifdef CONFIG_VSX | |
1809 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX) | |
1810 | #endif | |
1811 | mffs fr0 | |
1812 | stfd fr0,VCPU_FPSCR(r3) | |
1813 | ||
1814 | #ifdef CONFIG_ALTIVEC | |
1815 | BEGIN_FTR_SECTION | |
1816 | reg = 0 | |
1817 | .rept 32 | |
1818 | li r6,reg*16+VCPU_VRS | |
1819 | stvx reg,r6,r3 | |
1820 | reg = reg + 1 | |
1821 | .endr | |
1822 | mfvscr vr0 | |
1823 | li r6,VCPU_VSCR | |
1824 | stvx vr0,r6,r3 | |
1825 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1826 | #endif | |
1827 | mfspr r6,SPRN_VRSAVE | |
1828 | stw r6,VCPU_VRSAVE(r3) | |
8943633c | 1829 | mtmsrd r5 |
de56a948 PM |
1830 | isync |
1831 | blr | |
1832 | ||
1833 | /* | |
1834 | * Load up FP, VMX and VSX registers | |
1835 | * r4 = vcpu pointer | |
1836 | */ | |
1837 | .globl kvmppc_load_fp | |
1838 | kvmppc_load_fp: | |
1839 | mfmsr r9 | |
1840 | ori r8,r9,MSR_FP | |
1841 | #ifdef CONFIG_ALTIVEC | |
1842 | BEGIN_FTR_SECTION | |
1843 | oris r8,r8,MSR_VEC@h | |
1844 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1845 | #endif | |
1846 | #ifdef CONFIG_VSX | |
1847 | BEGIN_FTR_SECTION | |
1848 | oris r8,r8,MSR_VSX@h | |
1849 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1850 | #endif | |
1851 | mtmsrd r8 | |
1852 | isync | |
1853 | lfd fr0,VCPU_FPSCR(r4) | |
1854 | MTFSF_L(fr0) | |
1855 | #ifdef CONFIG_VSX | |
1856 | BEGIN_FTR_SECTION | |
1857 | reg = 0 | |
1858 | .rept 32 | |
1859 | li r7,reg*16+VCPU_VSRS | |
c75df6f9 | 1860 | LXVD2X(reg,R7,R4) |
de56a948 PM |
1861 | reg = reg + 1 |
1862 | .endr | |
1863 | FTR_SECTION_ELSE | |
1864 | #endif | |
1865 | reg = 0 | |
1866 | .rept 32 | |
1867 | lfd reg,reg*8+VCPU_FPRS(r4) | |
1868 | reg = reg + 1 | |
1869 | .endr | |
1870 | #ifdef CONFIG_VSX | |
1871 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX) | |
1872 | #endif | |
1873 | ||
1874 | #ifdef CONFIG_ALTIVEC | |
1875 | BEGIN_FTR_SECTION | |
1876 | li r7,VCPU_VSCR | |
1877 | lvx vr0,r7,r4 | |
1878 | mtvscr vr0 | |
1879 | reg = 0 | |
1880 | .rept 32 | |
1881 | li r7,reg*16+VCPU_VRS | |
1882 | lvx reg,r7,r4 | |
1883 | reg = reg + 1 | |
1884 | .endr | |
1885 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1886 | #endif | |
1887 | lwz r7,VCPU_VRSAVE(r4) | |
1888 | mtspr SPRN_VRSAVE,r7 | |
1889 | blr |