[linux-2.6-block.git] / arch / powerpc / kvm / book3s_emulate.c

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 *
 * Copyright SUSE Linux Products GmbH 2009
 *
 * Authors: Alexander Graf <agraf@suse.de>
 */

#include <asm/kvm_ppc.h>
#include <asm/disassemble.h>
#include <asm/kvm_book3s.h>
#include <asm/reg.h>

#define OP_19_XOP_RFID		18
#define OP_19_XOP_RFI		50

#define OP_31_XOP_MFMSR		83
#define OP_31_XOP_MTMSR		146
#define OP_31_XOP_MTMSRD	178
#define OP_31_XOP_MTSR		210
#define OP_31_XOP_MTSRIN	242
#define OP_31_XOP_TLBIEL	274
#define OP_31_XOP_TLBIE		306
#define OP_31_XOP_SLBMTE	402
#define OP_31_XOP_SLBIE		434
#define OP_31_XOP_SLBIA		498
#define OP_31_XOP_MFSR		595
#define OP_31_XOP_MFSRIN	659
#define OP_31_XOP_DCBA		758
#define OP_31_XOP_SLBMFEV	851
#define OP_31_XOP_EIOIO		854
#define OP_31_XOP_SLBMFEE	915

/* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */
#define OP_31_XOP_DCBZ		1010

#define OP_LFS			48
#define OP_LFD			50
#define OP_STFS			52
#define OP_STFD			54

#define SPRN_GQR0		912
#define SPRN_GQR1		913
#define SPRN_GQR2		914
#define SPRN_GQR3		915
#define SPRN_GQR4		916
#define SPRN_GQR5		917
#define SPRN_GQR6		918
#define SPRN_GQR7		919

/* Book3S_32 defines mfsrin(v) - but that messes up our abstract
 * function pointers, so let's just disable the define. */
#undef mfsrin

int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
                           unsigned int inst, int *advance)
{
	int emulated = EMULATE_DONE;

	switch (get_op(inst)) {
	case 19:
		switch (get_xop(inst)) {
		case OP_19_XOP_RFID:
		case OP_19_XOP_RFI:
			kvmppc_set_pc(vcpu, vcpu->arch.shared->srr0);
			kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
			*advance = 0;
			break;

		default:
			emulated = EMULATE_FAIL;
			break;
		}
		break;
	case 31:
		switch (get_xop(inst)) {
		case OP_31_XOP_MFMSR:
			kvmppc_set_gpr(vcpu, get_rt(inst),
				       vcpu->arch.shared->msr);
			break;
		case OP_31_XOP_MTMSRD:
		{
			ulong rs = kvmppc_get_gpr(vcpu, get_rs(inst));
			if (inst & 0x10000) {
				vcpu->arch.shared->msr &= ~(MSR_RI | MSR_EE);
				vcpu->arch.shared->msr |= rs & (MSR_RI | MSR_EE);
			} else
				kvmppc_set_msr(vcpu, rs);
			break;
		}
		case OP_31_XOP_MTMSR:
			kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, get_rs(inst)));
			break;
		case OP_31_XOP_MFSR:
		{
			int srnum;

			srnum = kvmppc_get_field(inst, 12 + 32, 15 + 32);
			if (vcpu->arch.mmu.mfsrin) {
				u32 sr;
				sr = vcpu->arch.mmu.mfsrin(vcpu, srnum);
				kvmppc_set_gpr(vcpu, get_rt(inst), sr);
			}
			break;
		}
		case OP_31_XOP_MFSRIN:
		{
			int srnum;

			srnum = (kvmppc_get_gpr(vcpu, get_rb(inst)) >> 28) & 0xf;
			if (vcpu->arch.mmu.mfsrin) {
				u32 sr;
				sr = vcpu->arch.mmu.mfsrin(vcpu, srnum);
				kvmppc_set_gpr(vcpu, get_rt(inst), sr);
			}
			break;
		}
		case OP_31_XOP_MTSR:
			vcpu->arch.mmu.mtsrin(vcpu,
				(inst >> 16) & 0xf,
				kvmppc_get_gpr(vcpu, get_rs(inst)));
			break;
		case OP_31_XOP_MTSRIN:
			vcpu->arch.mmu.mtsrin(vcpu,
				(kvmppc_get_gpr(vcpu, get_rb(inst)) >> 28) & 0xf,
				kvmppc_get_gpr(vcpu, get_rs(inst)));
			break;
		case OP_31_XOP_TLBIE:
		case OP_31_XOP_TLBIEL:
		{
			bool large = (inst & 0x00200000) ? true : false;
			ulong addr = kvmppc_get_gpr(vcpu, get_rb(inst));
			vcpu->arch.mmu.tlbie(vcpu, addr, large);
			break;
		}
		case OP_31_XOP_EIOIO:
			break;
		case OP_31_XOP_SLBMTE:
			if (!vcpu->arch.mmu.slbmte)
				return EMULATE_FAIL;

			vcpu->arch.mmu.slbmte(vcpu,
					kvmppc_get_gpr(vcpu, get_rs(inst)),
					kvmppc_get_gpr(vcpu, get_rb(inst)));
			break;
		case OP_31_XOP_SLBIE:
			if (!vcpu->arch.mmu.slbie)
				return EMULATE_FAIL;

			vcpu->arch.mmu.slbie(vcpu,
					kvmppc_get_gpr(vcpu, get_rb(inst)));
			break;
		case OP_31_XOP_SLBIA:
			if (!vcpu->arch.mmu.slbia)
				return EMULATE_FAIL;

			vcpu->arch.mmu.slbia(vcpu);
			break;
		case OP_31_XOP_SLBMFEE:
			if (!vcpu->arch.mmu.slbmfee) {
				emulated = EMULATE_FAIL;
			} else {
				ulong t, rb;

				rb = kvmppc_get_gpr(vcpu, get_rb(inst));
				t = vcpu->arch.mmu.slbmfee(vcpu, rb);
				kvmppc_set_gpr(vcpu, get_rt(inst), t);
			}
			break;
		case OP_31_XOP_SLBMFEV:
			if (!vcpu->arch.mmu.slbmfev) {
				emulated = EMULATE_FAIL;
			} else {
				ulong t, rb;

				rb = kvmppc_get_gpr(vcpu, get_rb(inst));
				t = vcpu->arch.mmu.slbmfev(vcpu, rb);
				kvmppc_set_gpr(vcpu, get_rt(inst), t);
			}
			break;
		case OP_31_XOP_DCBA:
			/* Gets treated as NOP */
			break;
		case OP_31_XOP_DCBZ:
		{
			ulong rb = kvmppc_get_gpr(vcpu, get_rb(inst));
			ulong ra = 0;
			ulong addr, vaddr;
			u32 zeros[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
			u32 dsisr;
			int r;

			if (get_ra(inst))
				ra = kvmppc_get_gpr(vcpu, get_ra(inst));

			addr = (ra + rb) & ~31ULL;
			if (!(vcpu->arch.shared->msr & MSR_SF))
				addr &= 0xffffffff;
			vaddr = addr;

			r = kvmppc_st(vcpu, &addr, 32, zeros, true);
			if ((r == -ENOENT) || (r == -EPERM)) {
				*advance = 0;
				vcpu->arch.shared->dar = vaddr;
				to_svcpu(vcpu)->fault_dar = vaddr;

				dsisr = DSISR_ISSTORE;
				if (r == -ENOENT)
					dsisr |= DSISR_NOHPTE;
				else if (r == -EPERM)
					dsisr |= DSISR_PROTFAULT;

				vcpu->arch.shared->dsisr = dsisr;
				to_svcpu(vcpu)->fault_dsisr = dsisr;

				kvmppc_book3s_queue_irqprio(vcpu,
					BOOK3S_INTERRUPT_DATA_STORAGE);
			}

			break;
		}
		default:
			emulated = EMULATE_FAIL;
		}
		break;
	default:
		emulated = EMULATE_FAIL;
	}

	if (emulated == EMULATE_FAIL)
		emulated = kvmppc_emulate_paired_single(run, vcpu);

	return emulated;
}

void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat, bool upper,
                    u32 val)
{
	if (upper) {
		/* Upper BAT */
		u32 bl = (val >> 2) & 0x7ff;
		bat->bepi_mask = (~bl << 17);
		bat->bepi = val & 0xfffe0000;
		bat->vs = (val & 2) ? 1 : 0;
		bat->vp = (val & 1) ? 1 : 0;
		bat->raw = (bat->raw & 0xffffffff00000000ULL) | val;
	} else {
		/* Lower BAT */
		bat->brpn = val & 0xfffe0000;
		bat->wimg = (val >> 3) & 0xf;
		bat->pp = val & 3;
		bat->raw = (bat->raw & 0x00000000ffffffffULL) | ((u64)val << 32);
	}
}

static struct kvmppc_bat *kvmppc_find_bat(struct kvm_vcpu *vcpu, int sprn)
{
	struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
	struct kvmppc_bat *bat;

	switch (sprn) {
	case SPRN_IBAT0U ... SPRN_IBAT3L:
		bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT0U) / 2];
		break;
	case SPRN_IBAT4U ... SPRN_IBAT7L:
		bat = &vcpu_book3s->ibat[4 + ((sprn - SPRN_IBAT4U) / 2)];
		break;
	case SPRN_DBAT0U ... SPRN_DBAT3L:
		bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT0U) / 2];
		break;
	case SPRN_DBAT4U ... SPRN_DBAT7L:
		bat = &vcpu_book3s->dbat[4 + ((sprn - SPRN_DBAT4U) / 2)];
		break;
	default:
		BUG();
	}

	return bat;
}

int kvmppc_core_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs)
{
	int emulated = EMULATE_DONE;
	ulong spr_val = kvmppc_get_gpr(vcpu, rs);

	switch (sprn) {
	case SPRN_SDR1:
		to_book3s(vcpu)->sdr1 = spr_val;
		break;
	case SPRN_DSISR:
		vcpu->arch.shared->dsisr = spr_val;
		break;
	case SPRN_DAR:
		vcpu->arch.shared->dar = spr_val;
		break;
	case SPRN_HIOR:
		to_book3s(vcpu)->hior = spr_val;
		break;
	case SPRN_IBAT0U ... SPRN_IBAT3L:
	case SPRN_IBAT4U ... SPRN_IBAT7L:
	case SPRN_DBAT0U ... SPRN_DBAT3L:
	case SPRN_DBAT4U ... SPRN_DBAT7L:
	{
		struct kvmppc_bat *bat = kvmppc_find_bat(vcpu, sprn);

		kvmppc_set_bat(vcpu, bat, !(sprn % 2), (u32)spr_val);
		/* BAT writes happen so rarely that we're ok to flush
		 * everything here */
		kvmppc_mmu_pte_flush(vcpu, 0, 0);
		kvmppc_mmu_flush_segments(vcpu);
		break;
	}
	case SPRN_HID0:
		to_book3s(vcpu)->hid[0] = spr_val;
		break;
	case SPRN_HID1:
		to_book3s(vcpu)->hid[1] = spr_val;
		break;
	case SPRN_HID2:
		to_book3s(vcpu)->hid[2] = spr_val;
		break;
	case SPRN_HID2_GEKKO:
		to_book3s(vcpu)->hid[2] = spr_val;
		/* HID2.PSE controls paired single on gekko */
		switch (vcpu->arch.pvr) {
		case 0x00080200:	/* lonestar 2.0 */
		case 0x00088202:	/* lonestar 2.2 */
		case 0x70000100:	/* gekko 1.0 */
		case 0x00080100:	/* gekko 2.0 */
		case 0x00083203:	/* gekko 2.3a */
		case 0x00083213:	/* gekko 2.3b */
		case 0x00083204:	/* gekko 2.4 */
		case 0x00083214:	/* gekko 2.4e (8SE) - retail HW2 */
		case 0x00087200:	/* broadway */
			if (vcpu->arch.hflags & BOOK3S_HFLAG_NATIVE_PS) {
				/* Native paired singles */
			} else if (spr_val & (1 << 29)) { /* HID2.PSE */
				vcpu->arch.hflags |= BOOK3S_HFLAG_PAIRED_SINGLE;
				kvmppc_giveup_ext(vcpu, MSR_FP);
			} else {
				vcpu->arch.hflags &= ~BOOK3S_HFLAG_PAIRED_SINGLE;
			}
			break;
		}
		break;
	case SPRN_HID4:
	case SPRN_HID4_GEKKO:
		to_book3s(vcpu)->hid[4] = spr_val;
		break;
	case SPRN_HID5:
		to_book3s(vcpu)->hid[5] = spr_val;
		/* guest HID5 set can change is_dcbz32 */
		if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
		    (mfmsr() & MSR_HV))
			vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32;
		break;
	case SPRN_GQR0:
	case SPRN_GQR1:
	case SPRN_GQR2:
	case SPRN_GQR3:
	case SPRN_GQR4:
	case SPRN_GQR5:
	case SPRN_GQR6:
	case SPRN_GQR7:
		to_book3s(vcpu)->gqr[sprn - SPRN_GQR0] = spr_val;
		break;
	case SPRN_ICTC:
	case SPRN_THRM1:
	case SPRN_THRM2:
	case SPRN_THRM3:
	case SPRN_CTRLF:
	case SPRN_CTRLT:
	case SPRN_L2CR:
	case SPRN_MMCR0_GEKKO:
	case SPRN_MMCR1_GEKKO:
	case SPRN_PMC1_GEKKO:
	case SPRN_PMC2_GEKKO:
	case SPRN_PMC3_GEKKO:
	case SPRN_PMC4_GEKKO:
	case SPRN_WPAR_GEKKO:
		break;
	default:
		printk(KERN_INFO "KVM: invalid SPR write: %d\n", sprn);
#ifndef DEBUG_SPR
		emulated = EMULATE_FAIL;
#endif
		break;
	}

	return emulated;
}

int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt)
{
	int emulated = EMULATE_DONE;

	switch (sprn) {
	case SPRN_IBAT0U ... SPRN_IBAT3L:
	case SPRN_IBAT4U ... SPRN_IBAT7L:
	case SPRN_DBAT0U ... SPRN_DBAT3L:
	case SPRN_DBAT4U ... SPRN_DBAT7L:
	{
		struct kvmppc_bat *bat = kvmppc_find_bat(vcpu, sprn);

		if (sprn % 2)
			kvmppc_set_gpr(vcpu, rt, bat->raw >> 32);
		else
			kvmppc_set_gpr(vcpu, rt, bat->raw);

		break;
	}
	case SPRN_SDR1:
		kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->sdr1);
		break;
	case SPRN_DSISR:
		kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->dsisr);
		break;
	case SPRN_DAR:
		kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->dar);
		break;
	case SPRN_HIOR:
		kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hior);
		break;
	case SPRN_HID0:
		kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[0]);
		break;
	case SPRN_HID1:
		kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[1]);
		break;
	case SPRN_HID2:
	case SPRN_HID2_GEKKO:
		kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[2]);
		break;
	case SPRN_HID4:
	case SPRN_HID4_GEKKO:
		kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[4]);
		break;
	case SPRN_HID5:
		kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[5]);
		break;
	case SPRN_GQR0:
	case SPRN_GQR1:
	case SPRN_GQR2:
	case SPRN_GQR3:
	case SPRN_GQR4:
	case SPRN_GQR5:
	case SPRN_GQR6:
	case SPRN_GQR7:
		kvmppc_set_gpr(vcpu, rt,
			       to_book3s(vcpu)->gqr[sprn - SPRN_GQR0]);
		break;
	case SPRN_THRM1:
	case SPRN_THRM2:
	case SPRN_THRM3:
	case SPRN_CTRLF:
	case SPRN_CTRLT:
	case SPRN_L2CR:
	case SPRN_MMCR0_GEKKO:
	case SPRN_MMCR1_GEKKO:
	case SPRN_PMC1_GEKKO:
	case SPRN_PMC2_GEKKO:
	case SPRN_PMC3_GEKKO:
	case SPRN_PMC4_GEKKO:
	case SPRN_WPAR_GEKKO:
		kvmppc_set_gpr(vcpu, rt, 0);
		break;
	default:
		printk(KERN_INFO "KVM: invalid SPR read: %d\n", sprn);
#ifndef DEBUG_SPR
		emulated = EMULATE_FAIL;
#endif
		break;
	}

	return emulated;
}

u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst)
{
	u32 dsisr = 0;

	/*
	 * This is what the spec says about DSISR bits (not mentioned = 0):
	 *
	 * 12:13		[DS]	Set to bits 30:31
	 * 15:16		[X]	Set to bits 29:30
	 * 17			[X]	Set to bit 25
	 *			[D/DS]	Set to bit 5
	 * 18:21		[X]	Set to bits 21:24
	 *			[D/DS]	Set to bits 1:4
	 * 22:26			Set to bits 6:10 (RT/RS/FRT/FRS)
	 * 27:31			Set to bits 11:15 (RA)
	 */

	switch (get_op(inst)) {
	/* D-form */
	case OP_LFS:
	case OP_LFD:
	case OP_STFD:
	case OP_STFS:
		dsisr |= (inst >> 12) & 0x4000;	/* bit 17 */
		dsisr |= (inst >> 17) & 0x3c00; /* bits 18:21 */
		break;
	/* X-form */
	case 31:
		dsisr |= (inst << 14) & 0x18000; /* bits 15:16 */
		dsisr |= (inst << 8)  & 0x04000; /* bit 17 */
		dsisr |= (inst << 3)  & 0x03c00; /* bits 18:21 */
		break;
	default:
		printk(KERN_INFO "KVM: Unaligned instruction 0x%x\n", inst);
		break;
	}

	dsisr |= (inst >> 16) & 0x03ff; /* bits 22:31 */

	return dsisr;
}

ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst)
{
	ulong dar = 0;
	ulong ra;

	switch (get_op(inst)) {
	case OP_LFS:
	case OP_LFD:
	case OP_STFD:
	case OP_STFS:
		ra = get_ra(inst);
		if (ra)
			dar = kvmppc_get_gpr(vcpu, ra);
		dar += (s32)((s16)inst);
		break;
	case 31:
		ra = get_ra(inst);
		if (ra)
			dar = kvmppc_get_gpr(vcpu, ra);
		dar += kvmppc_get_gpr(vcpu, get_rb(inst));
		break;
	default:
		printk(KERN_INFO "KVM: Unaligned instruction 0x%x\n", inst);
		break;
	}

	return dar;
}
Commit	Line	Data
c215c6e4 AG	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License, version 2, as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
	12	* along with this program; if not, write to the Free Software
	13	* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	14	*
	15	* Copyright SUSE Linux Products GmbH 2009
	16	*
	17	* Authors: Alexander Graf <agraf@suse.de>
	18	*/
	19
	20	#include <asm/kvm_ppc.h>
	21	#include <asm/disassemble.h>
	22	#include <asm/kvm_book3s.h>
	23	#include <asm/reg.h>
	24
	25	#define OP_19_XOP_RFID 18
	26	#define OP_19_XOP_RFI 50
	27
	28	#define OP_31_XOP_MFMSR 83
	29	#define OP_31_XOP_MTMSR 146
	30	#define OP_31_XOP_MTMSRD 178
71db4089	31	#define OP_31_XOP_MTSR 210
c215c6e4 AG	32	#define OP_31_XOP_MTSRIN 242
	33	#define OP_31_XOP_TLBIEL 274
	34	#define OP_31_XOP_TLBIE 306
	35	#define OP_31_XOP_SLBMTE 402
	36	#define OP_31_XOP_SLBIE 434
	37	#define OP_31_XOP_SLBIA 498
c664876c	38	#define OP_31_XOP_MFSR 595
c215c6e4	39	#define OP_31_XOP_MFSRIN 659
bd7cdbb7	40	#define OP_31_XOP_DCBA 758
c215c6e4 AG	41	#define OP_31_XOP_SLBMFEV 851
	42	#define OP_31_XOP_EIOIO 854
	43	#define OP_31_XOP_SLBMFEE 915
	44
	45	/* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */
	46	#define OP_31_XOP_DCBZ 1010
	47
ca7f4203 AG	48	#define OP_LFS 48
	49	#define OP_LFD 50
	50	#define OP_STFS 52
	51	#define OP_STFD 54
	52
d6d549b2 AG	53	#define SPRN_GQR0 912
	54	#define SPRN_GQR1 913
	55	#define SPRN_GQR2 914
	56	#define SPRN_GQR3 915
	57	#define SPRN_GQR4 916
	58	#define SPRN_GQR5 917
	59	#define SPRN_GQR6 918
	60	#define SPRN_GQR7 919
	61
07b0907d AG	62	/* Book3S_32 defines mfsrin(v) - but that messes up our abstract
	63	* function pointers, so let's just disable the define. */
	64	#undef mfsrin
	65
c215c6e4 AG	66	int kvmppc_core_emulate_op(struct kvm_run run, struct kvm_vcpu vcpu,
	67	unsigned int inst, int *advance)
	68	{
	69	int emulated = EMULATE_DONE;
	70
	71	switch (get_op(inst)) {
	72	case 19:
	73	switch (get_xop(inst)) {
	74	case OP_19_XOP_RFID:
	75	case OP_19_XOP_RFI:
de7906c3 AG	76	kvmppc_set_pc(vcpu, vcpu->arch.shared->srr0);
de7906c3 AG	77	kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
c215c6e4 AG	78	*advance = 0;
	79	break;
	80
	81	default:
	82	emulated = EMULATE_FAIL;
	83	break;
	84	}
	85	break;
	86	case 31:
	87	switch (get_xop(inst)) {
	88	case OP_31_XOP_MFMSR:
666e7252 AG	89	kvmppc_set_gpr(vcpu, get_rt(inst),
666e7252 AG	90	vcpu->arch.shared->msr);
c215c6e4 AG	91	break;
	92	case OP_31_XOP_MTMSRD:
	93	{
8e5b26b5	94	ulong rs = kvmppc_get_gpr(vcpu, get_rs(inst));
c215c6e4	95	if (inst & 0x10000) {
666e7252 AG	96	vcpu->arch.shared->msr &= ~(MSR_RI \| MSR_EE);
666e7252 AG	97	vcpu->arch.shared->msr \|= rs & (MSR_RI \| MSR_EE);
c215c6e4 AG	98	} else
	99	kvmppc_set_msr(vcpu, rs);
	100	break;
	101	}
	102	case OP_31_XOP_MTMSR:
8e5b26b5	103	kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, get_rs(inst)));
c215c6e4	104	break;
c664876c AG	105	case OP_31_XOP_MFSR:
	106	{
	107	int srnum;
	108
	109	srnum = kvmppc_get_field(inst, 12 + 32, 15 + 32);
	110	if (vcpu->arch.mmu.mfsrin) {
	111	u32 sr;
	112	sr = vcpu->arch.mmu.mfsrin(vcpu, srnum);
	113	kvmppc_set_gpr(vcpu, get_rt(inst), sr);
	114	}
	115	break;
	116	}
c215c6e4 AG	117	case OP_31_XOP_MFSRIN:
	118	{
	119	int srnum;
	120
8e5b26b5	121	srnum = (kvmppc_get_gpr(vcpu, get_rb(inst)) >> 28) & 0xf;
c215c6e4 AG	122	if (vcpu->arch.mmu.mfsrin) {
	123	u32 sr;
	124	sr = vcpu->arch.mmu.mfsrin(vcpu, srnum);
8e5b26b5	125	kvmppc_set_gpr(vcpu, get_rt(inst), sr);
c215c6e4 AG	126	}
	127	break;
	128	}
71db4089 AG	129	case OP_31_XOP_MTSR:
	130	vcpu->arch.mmu.mtsrin(vcpu,
	131	(inst >> 16) & 0xf,
	132	kvmppc_get_gpr(vcpu, get_rs(inst)));
	133	break;
c215c6e4 AG	134	case OP_31_XOP_MTSRIN:
c215c6e4 AG	135	vcpu->arch.mmu.mtsrin(vcpu,
8e5b26b5 AG	136	(kvmppc_get_gpr(vcpu, get_rb(inst)) >> 28) & 0xf,
8e5b26b5 AG	137	kvmppc_get_gpr(vcpu, get_rs(inst)));
c215c6e4 AG	138	break;
	139	case OP_31_XOP_TLBIE:
	140	case OP_31_XOP_TLBIEL:
	141	{
	142	bool large = (inst & 0x00200000) ? true : false;
8e5b26b5	143	ulong addr = kvmppc_get_gpr(vcpu, get_rb(inst));
c215c6e4 AG	144	vcpu->arch.mmu.tlbie(vcpu, addr, large);
	145	break;
	146	}
	147	case OP_31_XOP_EIOIO:
	148	break;
	149	case OP_31_XOP_SLBMTE:
	150	if (!vcpu->arch.mmu.slbmte)
	151	return EMULATE_FAIL;
	152
8e5b26b5 AG	153	vcpu->arch.mmu.slbmte(vcpu,
	154	kvmppc_get_gpr(vcpu, get_rs(inst)),
	155	kvmppc_get_gpr(vcpu, get_rb(inst)));
c215c6e4 AG	156	break;
	157	case OP_31_XOP_SLBIE:
	158	if (!vcpu->arch.mmu.slbie)
	159	return EMULATE_FAIL;
	160
8e5b26b5 AG	161	vcpu->arch.mmu.slbie(vcpu,
8e5b26b5 AG	162	kvmppc_get_gpr(vcpu, get_rb(inst)));
c215c6e4 AG	163	break;
	164	case OP_31_XOP_SLBIA:
	165	if (!vcpu->arch.mmu.slbia)
	166	return EMULATE_FAIL;
	167
	168	vcpu->arch.mmu.slbia(vcpu);
	169	break;
	170	case OP_31_XOP_SLBMFEE:
	171	if (!vcpu->arch.mmu.slbmfee) {
	172	emulated = EMULATE_FAIL;
	173	} else {
	174	ulong t, rb;
	175
8e5b26b5	176	rb = kvmppc_get_gpr(vcpu, get_rb(inst));
c215c6e4	177	t = vcpu->arch.mmu.slbmfee(vcpu, rb);
8e5b26b5	178	kvmppc_set_gpr(vcpu, get_rt(inst), t);
c215c6e4 AG	179	}
	180	break;
	181	case OP_31_XOP_SLBMFEV:
	182	if (!vcpu->arch.mmu.slbmfev) {
	183	emulated = EMULATE_FAIL;
	184	} else {
	185	ulong t, rb;
	186
8e5b26b5	187	rb = kvmppc_get_gpr(vcpu, get_rb(inst));
c215c6e4	188	t = vcpu->arch.mmu.slbmfev(vcpu, rb);
8e5b26b5	189	kvmppc_set_gpr(vcpu, get_rt(inst), t);
c215c6e4 AG	190	}
c215c6e4 AG	191	break;
bd7cdbb7 AG	192	case OP_31_XOP_DCBA:
	193	/* Gets treated as NOP */
	194	break;
c215c6e4 AG	195	case OP_31_XOP_DCBZ:
c215c6e4 AG	196	{
8e5b26b5	197	ulong rb = kvmppc_get_gpr(vcpu, get_rb(inst));
c215c6e4	198	ulong ra = 0;
5467a97d	199	ulong addr, vaddr;
c215c6e4	200	u32 zeros[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
9fb244a2 AG	201	u32 dsisr;
9fb244a2 AG	202	int r;
c215c6e4 AG	203
c215c6e4 AG	204	if (get_ra(inst))
8e5b26b5	205	ra = kvmppc_get_gpr(vcpu, get_ra(inst));
c215c6e4 AG	206
c215c6e4 AG	207	addr = (ra + rb) & ~31ULL;
666e7252	208	if (!(vcpu->arch.shared->msr & MSR_SF))
c215c6e4	209	addr &= 0xffffffff;
5467a97d	210	vaddr = addr;
c215c6e4	211
9fb244a2 AG	212	r = kvmppc_st(vcpu, &addr, 32, zeros, true);
	213	if ((r == -ENOENT) \|\| (r == -EPERM)) {
	214	*advance = 0;
5e030186	215	vcpu->arch.shared->dar = vaddr;
c7f38f46	216	to_svcpu(vcpu)->fault_dar = vaddr;
9fb244a2 AG	217
	218	dsisr = DSISR_ISSTORE;
	219	if (r == -ENOENT)
	220	dsisr \|= DSISR_NOHPTE;
	221	else if (r == -EPERM)
	222	dsisr \|= DSISR_PROTFAULT;
	223
d562de48	224	vcpu->arch.shared->dsisr = dsisr;
c7f38f46	225	to_svcpu(vcpu)->fault_dsisr = dsisr;
9fb244a2	226
c215c6e4 AG	227	kvmppc_book3s_queue_irqprio(vcpu,
c215c6e4 AG	228	BOOK3S_INTERRUPT_DATA_STORAGE);
c215c6e4 AG	229	}
	230
	231	break;
	232	}
	233	default:
	234	emulated = EMULATE_FAIL;
	235	}
	236	break;
	237	default:
	238	emulated = EMULATE_FAIL;
	239	}
	240
831317b6 AG	241	if (emulated == EMULATE_FAIL)
	242	emulated = kvmppc_emulate_paired_single(run, vcpu);
	243
c215c6e4 AG	244	return emulated;
	245	}
	246
e15a1137 AG	247	void kvmppc_set_bat(struct kvm_vcpu vcpu, struct kvmppc_bat bat, bool upper,
	248	u32 val)
	249	{
	250	if (upper) {
	251	/* Upper BAT */
	252	u32 bl = (val >> 2) & 0x7ff;
	253	bat->bepi_mask = (~bl << 17);
	254	bat->bepi = val & 0xfffe0000;
	255	bat->vs = (val & 2) ? 1 : 0;
	256	bat->vp = (val & 1) ? 1 : 0;
	257	bat->raw = (bat->raw & 0xffffffff00000000ULL) \| val;
	258	} else {
	259	/* Lower BAT */
	260	bat->brpn = val & 0xfffe0000;
	261	bat->wimg = (val >> 3) & 0xf;
	262	bat->pp = val & 3;
	263	bat->raw = (bat->raw & 0x00000000ffffffffULL) \| ((u64)val << 32);
	264	}
	265	}
	266
c1c88e2f	267	static struct kvmppc_bat kvmppc_find_bat(struct kvm_vcpu vcpu, int sprn)
c04a695a AG	268	{
	269	struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
	270	struct kvmppc_bat *bat;
	271
	272	switch (sprn) {
	273	case SPRN_IBAT0U ... SPRN_IBAT3L:
	274	bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT0U) / 2];
	275	break;
	276	case SPRN_IBAT4U ... SPRN_IBAT7L:
	277	bat = &vcpu_book3s->ibat[4 + ((sprn - SPRN_IBAT4U) / 2)];
	278	break;
	279	case SPRN_DBAT0U ... SPRN_DBAT3L:
	280	bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT0U) / 2];
	281	break;
	282	case SPRN_DBAT4U ... SPRN_DBAT7L:
	283	bat = &vcpu_book3s->dbat[4 + ((sprn - SPRN_DBAT4U) / 2)];
	284	break;
	285	default:
	286	BUG();
	287	}
	288
c1c88e2f	289	return bat;
c215c6e4 AG	290	}
	291
	292	int kvmppc_core_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs)
	293	{
	294	int emulated = EMULATE_DONE;
8e5b26b5	295	ulong spr_val = kvmppc_get_gpr(vcpu, rs);
c215c6e4 AG	296
	297	switch (sprn) {
	298	case SPRN_SDR1:
8e5b26b5	299	to_book3s(vcpu)->sdr1 = spr_val;
c215c6e4 AG	300	break;
c215c6e4 AG	301	case SPRN_DSISR:
d562de48	302	vcpu->arch.shared->dsisr = spr_val;
c215c6e4 AG	303	break;
c215c6e4 AG	304	case SPRN_DAR:
5e030186	305	vcpu->arch.shared->dar = spr_val;
c215c6e4 AG	306	break;
c215c6e4 AG	307	case SPRN_HIOR:
8e5b26b5	308	to_book3s(vcpu)->hior = spr_val;
c215c6e4 AG	309	break;
	310	case SPRN_IBAT0U ... SPRN_IBAT3L:
	311	case SPRN_IBAT4U ... SPRN_IBAT7L:
	312	case SPRN_DBAT0U ... SPRN_DBAT3L:
	313	case SPRN_DBAT4U ... SPRN_DBAT7L:
c1c88e2f AG	314	{
	315	struct kvmppc_bat *bat = kvmppc_find_bat(vcpu, sprn);
	316
	317	kvmppc_set_bat(vcpu, bat, !(sprn % 2), (u32)spr_val);
c215c6e4 AG	318	/* BAT writes happen so rarely that we're ok to flush
	319	* everything here */
	320	kvmppc_mmu_pte_flush(vcpu, 0, 0);
c04a695a	321	kvmppc_mmu_flush_segments(vcpu);
c215c6e4	322	break;
c1c88e2f	323	}
c215c6e4	324	case SPRN_HID0:
8e5b26b5	325	to_book3s(vcpu)->hid[0] = spr_val;
c215c6e4 AG	326	break;
c215c6e4 AG	327	case SPRN_HID1:
8e5b26b5	328	to_book3s(vcpu)->hid[1] = spr_val;
c215c6e4 AG	329	break;
c215c6e4 AG	330	case SPRN_HID2:
8e5b26b5	331	to_book3s(vcpu)->hid[2] = spr_val;
c215c6e4	332	break;
d6d549b2 AG	333	case SPRN_HID2_GEKKO:
	334	to_book3s(vcpu)->hid[2] = spr_val;
	335	/* HID2.PSE controls paired single on gekko */
	336	switch (vcpu->arch.pvr) {
	337	case 0x00080200: /* lonestar 2.0 */
	338	case 0x00088202: /* lonestar 2.2 */
	339	case 0x70000100: /* gekko 1.0 */
	340	case 0x00080100: /* gekko 2.0 */
	341	case 0x00083203: /* gekko 2.3a */
	342	case 0x00083213: /* gekko 2.3b */
	343	case 0x00083204: /* gekko 2.4 */
	344	case 0x00083214: /* gekko 2.4e (8SE) - retail HW2 */
b83d4a9c AG	345	case 0x00087200: /* broadway */
	346	if (vcpu->arch.hflags & BOOK3S_HFLAG_NATIVE_PS) {
	347	/* Native paired singles */
	348	} else if (spr_val & (1 << 29)) { /* HID2.PSE */
d6d549b2 AG	349	vcpu->arch.hflags \|= BOOK3S_HFLAG_PAIRED_SINGLE;
	350	kvmppc_giveup_ext(vcpu, MSR_FP);
	351	} else {
	352	vcpu->arch.hflags &= ~BOOK3S_HFLAG_PAIRED_SINGLE;
	353	}
	354	break;
	355	}
	356	break;
c215c6e4	357	case SPRN_HID4:
d6d549b2	358	case SPRN_HID4_GEKKO:
8e5b26b5	359	to_book3s(vcpu)->hid[4] = spr_val;
c215c6e4 AG	360	break;
c215c6e4 AG	361	case SPRN_HID5:
8e5b26b5	362	to_book3s(vcpu)->hid[5] = spr_val;
c215c6e4 AG	363	/* guest HID5 set can change is_dcbz32 */
	364	if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
	365	(mfmsr() & MSR_HV))
	366	vcpu->arch.hflags \|= BOOK3S_HFLAG_DCBZ32;
	367	break;
d6d549b2 AG	368	case SPRN_GQR0:
	369	case SPRN_GQR1:
	370	case SPRN_GQR2:
	371	case SPRN_GQR3:
	372	case SPRN_GQR4:
	373	case SPRN_GQR5:
	374	case SPRN_GQR6:
	375	case SPRN_GQR7:
	376	to_book3s(vcpu)->gqr[sprn - SPRN_GQR0] = spr_val;
	377	break;
c215c6e4 AG	378	case SPRN_ICTC:
	379	case SPRN_THRM1:
	380	case SPRN_THRM2:
	381	case SPRN_THRM3:
	382	case SPRN_CTRLF:
	383	case SPRN_CTRLT:
d6d549b2 AG	384	case SPRN_L2CR:
	385	case SPRN_MMCR0_GEKKO:
	386	case SPRN_MMCR1_GEKKO:
	387	case SPRN_PMC1_GEKKO:
	388	case SPRN_PMC2_GEKKO:
	389	case SPRN_PMC3_GEKKO:
	390	case SPRN_PMC4_GEKKO:
	391	case SPRN_WPAR_GEKKO:
c215c6e4 AG	392	break;
	393	default:
	394	printk(KERN_INFO "KVM: invalid SPR write: %d\n", sprn);
	395	#ifndef DEBUG_SPR
	396	emulated = EMULATE_FAIL;
	397	#endif
	398	break;
	399	}
	400
	401	return emulated;
	402	}
	403
	404	int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt)
	405	{
	406	int emulated = EMULATE_DONE;
	407
	408	switch (sprn) {
c04a695a AG	409	case SPRN_IBAT0U ... SPRN_IBAT3L:
	410	case SPRN_IBAT4U ... SPRN_IBAT7L:
	411	case SPRN_DBAT0U ... SPRN_DBAT3L:
	412	case SPRN_DBAT4U ... SPRN_DBAT7L:
c1c88e2f AG	413	{
	414	struct kvmppc_bat *bat = kvmppc_find_bat(vcpu, sprn);
	415
	416	if (sprn % 2)
	417	kvmppc_set_gpr(vcpu, rt, bat->raw >> 32);
	418	else
	419	kvmppc_set_gpr(vcpu, rt, bat->raw);
	420
c04a695a	421	break;
c1c88e2f	422	}
c215c6e4	423	case SPRN_SDR1:
8e5b26b5	424	kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->sdr1);
c215c6e4 AG	425	break;
c215c6e4 AG	426	case SPRN_DSISR:
d562de48	427	kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->dsisr);
c215c6e4 AG	428	break;
c215c6e4 AG	429	case SPRN_DAR:
5e030186	430	kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->dar);
c215c6e4 AG	431	break;
c215c6e4 AG	432	case SPRN_HIOR:
8e5b26b5	433	kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hior);
c215c6e4 AG	434	break;
c215c6e4 AG	435	case SPRN_HID0:
8e5b26b5	436	kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[0]);
c215c6e4 AG	437	break;
c215c6e4 AG	438	case SPRN_HID1:
8e5b26b5	439	kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[1]);
c215c6e4 AG	440	break;
c215c6e4 AG	441	case SPRN_HID2:
d6d549b2	442	case SPRN_HID2_GEKKO:
8e5b26b5	443	kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[2]);
c215c6e4 AG	444	break;
c215c6e4 AG	445	case SPRN_HID4:
d6d549b2	446	case SPRN_HID4_GEKKO:
8e5b26b5	447	kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[4]);
c215c6e4 AG	448	break;
c215c6e4 AG	449	case SPRN_HID5:
8e5b26b5	450	kvmppc_set_gpr(vcpu, rt, to_book3s(vcpu)->hid[5]);
c215c6e4	451	break;
d6d549b2 AG	452	case SPRN_GQR0:
	453	case SPRN_GQR1:
	454	case SPRN_GQR2:
	455	case SPRN_GQR3:
	456	case SPRN_GQR4:
	457	case SPRN_GQR5:
	458	case SPRN_GQR6:
	459	case SPRN_GQR7:
	460	kvmppc_set_gpr(vcpu, rt,
	461	to_book3s(vcpu)->gqr[sprn - SPRN_GQR0]);
	462	break;
c215c6e4 AG	463	case SPRN_THRM1:
	464	case SPRN_THRM2:
	465	case SPRN_THRM3:
	466	case SPRN_CTRLF:
	467	case SPRN_CTRLT:
d6d549b2 AG	468	case SPRN_L2CR:
	469	case SPRN_MMCR0_GEKKO:
	470	case SPRN_MMCR1_GEKKO:
	471	case SPRN_PMC1_GEKKO:
	472	case SPRN_PMC2_GEKKO:
	473	case SPRN_PMC3_GEKKO:
	474	case SPRN_PMC4_GEKKO:
	475	case SPRN_WPAR_GEKKO:
8e5b26b5	476	kvmppc_set_gpr(vcpu, rt, 0);
c215c6e4 AG	477	break;
	478	default:
	479	printk(KERN_INFO "KVM: invalid SPR read: %d\n", sprn);
	480	#ifndef DEBUG_SPR
	481	emulated = EMULATE_FAIL;
	482	#endif
	483	break;
	484	}
	485
	486	return emulated;
	487	}
	488
ca7f4203 AG	489	u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst)
	490	{
	491	u32 dsisr = 0;
	492
	493	/*
	494	* This is what the spec says about DSISR bits (not mentioned = 0):
	495	*
	496	* 12:13 [DS] Set to bits 30:31
	497	* 15:16 [X] Set to bits 29:30
	498	* 17 [X] Set to bit 25
	499	* [D/DS] Set to bit 5
	500	* 18:21 [X] Set to bits 21:24
	501	* [D/DS] Set to bits 1:4
	502	* 22:26 Set to bits 6:10 (RT/RS/FRT/FRS)
	503	* 27:31 Set to bits 11:15 (RA)
	504	*/
	505
	506	switch (get_op(inst)) {
	507	/* D-form */
	508	case OP_LFS:
	509	case OP_LFD:
	510	case OP_STFD:
	511	case OP_STFS:
	512	dsisr \|= (inst >> 12) & 0x4000; /* bit 17 */
	513	dsisr \|= (inst >> 17) & 0x3c00; /* bits 18:21 */
	514	break;
	515	/* X-form */
	516	case 31:
	517	dsisr \|= (inst << 14) & 0x18000; /* bits 15:16 */
	518	dsisr \|= (inst << 8) & 0x04000; /* bit 17 */
	519	dsisr \|= (inst << 3) & 0x03c00; /* bits 18:21 */
	520	break;
	521	default:
	522	printk(KERN_INFO "KVM: Unaligned instruction 0x%x\n", inst);
	523	break;
	524	}
	525
	526	dsisr \|= (inst >> 16) & 0x03ff; /* bits 22:31 */
	527
	528	return dsisr;
	529	}
	530
	531	ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst)
	532	{
	533	ulong dar = 0;
	534	ulong ra;
	535
	536	switch (get_op(inst)) {
	537	case OP_LFS:
	538	case OP_LFD:
	539	case OP_STFD:
	540	case OP_STFS:
	541	ra = get_ra(inst);
	542	if (ra)
	543	dar = kvmppc_get_gpr(vcpu, ra);
	544	dar += (s32)((s16)inst);
	545	break;
	546	case 31:
	547	ra = get_ra(inst);
	548	if (ra)
	549	dar = kvmppc_get_gpr(vcpu, ra);
	550	dar += kvmppc_get_gpr(vcpu, get_rb(inst));
	551	break;
	552	default:
553	printk(KERN_INFO "KVM: Unaligned instruction 0x%x\n", inst);
554	break;
555	}
556
557	return dar;
558	}