[linux-2.6-block.git] / arch / powerpc / kvm / book3s_64_mmu.c

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 *
 * Copyright SUSE Linux Products GmbH 2009
 *
 * Authors: Alexander Graf <agraf@suse.de>
 */

#include <linux/types.h>
#include <linux/string.h>
#include <linux/kvm.h>
#include <linux/kvm_host.h>
#include <linux/highmem.h>

#include <asm/tlbflush.h>
#include <asm/kvm_ppc.h>
#include <asm/kvm_book3s.h>
#include <asm/mmu-hash64.h>

/* #define DEBUG_MMU */

#ifdef DEBUG_MMU
#define dprintk(X...) printk(KERN_INFO X)
#else
#define dprintk(X...) do { } while(0)
#endif

static void kvmppc_mmu_book3s_64_reset_msr(struct kvm_vcpu *vcpu)
{
	kvmppc_set_msr(vcpu, MSR_SF);
}

static struct kvmppc_slb *kvmppc_mmu_book3s_64_find_slbe(
				struct kvm_vcpu *vcpu,
				gva_t eaddr)
{
	int i;
	u64 esid = GET_ESID(eaddr);
	u64 esid_1t = GET_ESID_1T(eaddr);

	for (i = 0; i < vcpu->arch.slb_nr; i++) {
		u64 cmp_esid = esid;

		if (!vcpu->arch.slb[i].valid)
			continue;

		if (vcpu->arch.slb[i].tb)
			cmp_esid = esid_1t;

		if (vcpu->arch.slb[i].esid == cmp_esid)
			return &vcpu->arch.slb[i];
	}

	dprintk("KVM: No SLB entry found for 0x%lx [%llx | %llx]\n",
		eaddr, esid, esid_1t);
	for (i = 0; i < vcpu->arch.slb_nr; i++) {
	    if (vcpu->arch.slb[i].vsid)
		dprintk("  %d: %c%c%c %llx %llx\n", i,
			vcpu->arch.slb[i].valid ? 'v' : ' ',
			vcpu->arch.slb[i].large ? 'l' : ' ',
			vcpu->arch.slb[i].tb    ? 't' : ' ',
			vcpu->arch.slb[i].esid,
			vcpu->arch.slb[i].vsid);
	}

	return NULL;
}

static int kvmppc_slb_sid_shift(struct kvmppc_slb *slbe)
{
	return slbe->tb ? SID_SHIFT_1T : SID_SHIFT;
}

static u64 kvmppc_slb_offset_mask(struct kvmppc_slb *slbe)
{
	return (1ul << kvmppc_slb_sid_shift(slbe)) - 1;
}

static u64 kvmppc_slb_calc_vpn(struct kvmppc_slb *slb, gva_t eaddr)
{
	eaddr &= kvmppc_slb_offset_mask(slb);

	return (eaddr >> VPN_SHIFT) |
		((slb->vsid) << (kvmppc_slb_sid_shift(slb) - VPN_SHIFT));
}

static u64 kvmppc_mmu_book3s_64_ea_to_vp(struct kvm_vcpu *vcpu, gva_t eaddr,
					 bool data)
{
	struct kvmppc_slb *slb;

	slb = kvmppc_mmu_book3s_64_find_slbe(vcpu, eaddr);
	if (!slb)
		return 0;

	return kvmppc_slb_calc_vpn(slb, eaddr);
}

static int mmu_pagesize(int mmu_pg)
{
	switch (mmu_pg) {
	case MMU_PAGE_64K:
		return 16;
	case MMU_PAGE_16M:
		return 24;
	}
	return 12;
}

static int kvmppc_mmu_book3s_64_get_pagesize(struct kvmppc_slb *slbe)
{
	return mmu_pagesize(slbe->base_page_size);
}

static u32 kvmppc_mmu_book3s_64_get_page(struct kvmppc_slb *slbe, gva_t eaddr)
{
	int p = kvmppc_mmu_book3s_64_get_pagesize(slbe);

	return ((eaddr & kvmppc_slb_offset_mask(slbe)) >> p);
}

static hva_t kvmppc_mmu_book3s_64_get_pteg(
				struct kvmppc_vcpu_book3s *vcpu_book3s,
				struct kvmppc_slb *slbe, gva_t eaddr,
				bool second)
{
	u64 hash, pteg, htabsize;
	u32 ssize;
	hva_t r;
	u64 vpn;

	htabsize = ((1 << ((vcpu_book3s->sdr1 & 0x1f) + 11)) - 1);

	vpn = kvmppc_slb_calc_vpn(slbe, eaddr);
	ssize = slbe->tb ? MMU_SEGSIZE_1T : MMU_SEGSIZE_256M;
	hash = hpt_hash(vpn, kvmppc_mmu_book3s_64_get_pagesize(slbe), ssize);
	if (second)
		hash = ~hash;
	hash &= ((1ULL << 39ULL) - 1ULL);
	hash &= htabsize;
	hash <<= 7ULL;

	pteg = vcpu_book3s->sdr1 & 0xfffffffffffc0000ULL;
	pteg |= hash;

	dprintk("MMU: page=0x%x sdr1=0x%llx pteg=0x%llx vsid=0x%llx\n",
		page, vcpu_book3s->sdr1, pteg, slbe->vsid);

	/* When running a PAPR guest, SDR1 contains a HVA address instead
           of a GPA */
	if (vcpu_book3s->vcpu.arch.papr_enabled)
		r = pteg;
	else
		r = gfn_to_hva(vcpu_book3s->vcpu.kvm, pteg >> PAGE_SHIFT);

	if (kvm_is_error_hva(r))
		return r;
	return r | (pteg & ~PAGE_MASK);
}

static u64 kvmppc_mmu_book3s_64_get_avpn(struct kvmppc_slb *slbe, gva_t eaddr)
{
	int p = kvmppc_mmu_book3s_64_get_pagesize(slbe);
	u64 avpn;

	avpn = kvmppc_mmu_book3s_64_get_page(slbe, eaddr);
	avpn |= slbe->vsid << (kvmppc_slb_sid_shift(slbe) - p);

	if (p < 16)
		avpn >>= ((80 - p) - 56) - 8;	/* 16 - p */
	else
		avpn <<= p - 16;

	return avpn;
}

/*
 * Return page size encoded in the second word of a HPTE, or
 * -1 for an invalid encoding for the base page size indicated by
 * the SLB entry.  This doesn't handle mixed pagesize segments yet.
 */
static int decode_pagesize(struct kvmppc_slb *slbe, u64 r)
{
	switch (slbe->base_page_size) {
	case MMU_PAGE_64K:
		if ((r & 0xf000) == 0x1000)
			return MMU_PAGE_64K;
		break;
	case MMU_PAGE_16M:
		if ((r & 0xff000) == 0)
			return MMU_PAGE_16M;
		break;
	}
	return -1;
}

static int kvmppc_mmu_book3s_64_xlate(struct kvm_vcpu *vcpu, gva_t eaddr,
				struct kvmppc_pte *gpte, bool data)
{
	struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
	struct kvmppc_slb *slbe;
	hva_t ptegp;
	u64 pteg[16];
	u64 avpn = 0;
	u64 v, r;
	u64 v_val, v_mask;
	u64 eaddr_mask;
	int i;
	u8 pp, key = 0;
	bool found = false;
	bool second = false;
	int pgsize;
	ulong mp_ea = vcpu->arch.magic_page_ea;

	/* Magic page override */
	if (unlikely(mp_ea) &&
	    unlikely((eaddr & ~0xfffULL) == (mp_ea & ~0xfffULL)) &&
	    !(vcpu->arch.shared->msr & MSR_PR)) {
		gpte->eaddr = eaddr;
		gpte->vpage = kvmppc_mmu_book3s_64_ea_to_vp(vcpu, eaddr, data);
		gpte->raddr = vcpu->arch.magic_page_pa | (gpte->raddr & 0xfff);
		gpte->raddr &= KVM_PAM;
		gpte->may_execute = true;
		gpte->may_read = true;
		gpte->may_write = true;
		gpte->page_size = MMU_PAGE_4K;

		return 0;
	}

	slbe = kvmppc_mmu_book3s_64_find_slbe(vcpu, eaddr);
	if (!slbe)
		goto no_seg_found;

	avpn = kvmppc_mmu_book3s_64_get_avpn(slbe, eaddr);
	v_val = avpn & HPTE_V_AVPN;

	if (slbe->tb)
		v_val |= SLB_VSID_B_1T;
	if (slbe->large)
		v_val |= HPTE_V_LARGE;
	v_val |= HPTE_V_VALID;

	v_mask = SLB_VSID_B | HPTE_V_AVPN | HPTE_V_LARGE | HPTE_V_VALID |
		HPTE_V_SECONDARY;

	pgsize = slbe->large ? MMU_PAGE_16M : MMU_PAGE_4K;

do_second:
	ptegp = kvmppc_mmu_book3s_64_get_pteg(vcpu_book3s, slbe, eaddr, second);
	if (kvm_is_error_hva(ptegp))
		goto no_page_found;

	if(copy_from_user(pteg, (void __user *)ptegp, sizeof(pteg))) {
		printk(KERN_ERR "KVM can't copy data from 0x%lx!\n", ptegp);
		goto no_page_found;
	}

	if ((vcpu->arch.shared->msr & MSR_PR) && slbe->Kp)
		key = 4;
	else if (!(vcpu->arch.shared->msr & MSR_PR) && slbe->Ks)
		key = 4;

	for (i=0; i<16; i+=2) {
		/* Check all relevant fields of 1st dword */
		if ((pteg[i] & v_mask) == v_val) {
			/* If large page bit is set, check pgsize encoding */
			if (slbe->large &&
			    (vcpu->arch.hflags & BOOK3S_HFLAG_MULTI_PGSIZE)) {
				pgsize = decode_pagesize(slbe, pteg[i+1]);
				if (pgsize < 0)
					continue;
			}
			found = true;
			break;
		}
	}

	if (!found) {
		if (second)
			goto no_page_found;
		v_val |= HPTE_V_SECONDARY;
		second = true;
		goto do_second;
	}

	v = pteg[i];
	r = pteg[i+1];
	pp = (r & HPTE_R_PP) | key;
	if (r & HPTE_R_PP0)
		pp |= 8;

	gpte->eaddr = eaddr;
	gpte->vpage = kvmppc_mmu_book3s_64_ea_to_vp(vcpu, eaddr, data);

	eaddr_mask = (1ull << mmu_pagesize(pgsize)) - 1;
	gpte->raddr = (r & HPTE_R_RPN & ~eaddr_mask) | (eaddr & eaddr_mask);
	gpte->page_size = pgsize;
	gpte->may_execute = ((r & HPTE_R_N) ? false : true);
	gpte->may_read = false;
	gpte->may_write = false;

	switch (pp) {
	case 0:
	case 1:
	case 2:
	case 6:
		gpte->may_write = true;
		/* fall through */
	case 3:
	case 5:
	case 7:
	case 10:
		gpte->may_read = true;
		break;
	}

	dprintk("KVM MMU: Translated 0x%lx [0x%llx] -> 0x%llx "
		"-> 0x%lx\n",
		eaddr, avpn, gpte->vpage, gpte->raddr);

	/* Update PTE R and C bits, so the guest's swapper knows we used the
	 * page */
	if (gpte->may_read) {
		/* Set the accessed flag */
		r |= HPTE_R_R;
	}
	if (data && gpte->may_write) {
		/* Set the dirty flag -- XXX even if not writing */
		r |= HPTE_R_C;
	}

	/* Write back into the PTEG */
	if (pteg[i+1] != r) {
		pteg[i+1] = r;
		copy_to_user((void __user *)ptegp, pteg, sizeof(pteg));
	}

	if (!gpte->may_read)
		return -EPERM;
	return 0;

no_page_found:
	return -ENOENT;

no_seg_found:

	dprintk("KVM MMU: Trigger segment fault\n");
	return -EINVAL;
}

static void kvmppc_mmu_book3s_64_slbmte(struct kvm_vcpu *vcpu, u64 rs, u64 rb)
{
	struct kvmppc_vcpu_book3s *vcpu_book3s;
	u64 esid, esid_1t;
	int slb_nr;
	struct kvmppc_slb *slbe;

	dprintk("KVM MMU: slbmte(0x%llx, 0x%llx)\n", rs, rb);

	vcpu_book3s = to_book3s(vcpu);

	esid = GET_ESID(rb);
	esid_1t = GET_ESID_1T(rb);
	slb_nr = rb & 0xfff;

	if (slb_nr > vcpu->arch.slb_nr)
		return;

	slbe = &vcpu->arch.slb[slb_nr];

	slbe->large = (rs & SLB_VSID_L) ? 1 : 0;
	slbe->tb    = (rs & SLB_VSID_B_1T) ? 1 : 0;
	slbe->esid  = slbe->tb ? esid_1t : esid;
	slbe->vsid  = (rs & ~SLB_VSID_B) >> (kvmppc_slb_sid_shift(slbe) - 16);
	slbe->valid = (rb & SLB_ESID_V) ? 1 : 0;
	slbe->Ks    = (rs & SLB_VSID_KS) ? 1 : 0;
	slbe->Kp    = (rs & SLB_VSID_KP) ? 1 : 0;
	slbe->nx    = (rs & SLB_VSID_N) ? 1 : 0;
	slbe->class = (rs & SLB_VSID_C) ? 1 : 0;

	slbe->base_page_size = MMU_PAGE_4K;
	if (slbe->large) {
		if (vcpu->arch.hflags & BOOK3S_HFLAG_MULTI_PGSIZE) {
			switch (rs & SLB_VSID_LP) {
			case SLB_VSID_LP_00:
				slbe->base_page_size = MMU_PAGE_16M;
				break;
			case SLB_VSID_LP_01:
				slbe->base_page_size = MMU_PAGE_64K;
				break;
			}
		} else
			slbe->base_page_size = MMU_PAGE_16M;
	}

	slbe->orige = rb & (ESID_MASK | SLB_ESID_V);
	slbe->origv = rs;

	/* Map the new segment */
	kvmppc_mmu_map_segment(vcpu, esid << SID_SHIFT);
}

static u64 kvmppc_mmu_book3s_64_slbmfee(struct kvm_vcpu *vcpu, u64 slb_nr)
{
	struct kvmppc_slb *slbe;

	if (slb_nr > vcpu->arch.slb_nr)
		return 0;

	slbe = &vcpu->arch.slb[slb_nr];

	return slbe->orige;
}

static u64 kvmppc_mmu_book3s_64_slbmfev(struct kvm_vcpu *vcpu, u64 slb_nr)
{
	struct kvmppc_slb *slbe;

	if (slb_nr > vcpu->arch.slb_nr)
		return 0;

	slbe = &vcpu->arch.slb[slb_nr];

	return slbe->origv;
}

static void kvmppc_mmu_book3s_64_slbie(struct kvm_vcpu *vcpu, u64 ea)
{
	struct kvmppc_slb *slbe;
	u64 seg_size;

	dprintk("KVM MMU: slbie(0x%llx)\n", ea);

	slbe = kvmppc_mmu_book3s_64_find_slbe(vcpu, ea);

	if (!slbe)
		return;

	dprintk("KVM MMU: slbie(0x%llx, 0x%llx)\n", ea, slbe->esid);

	slbe->valid = false;
	slbe->orige = 0;
	slbe->origv = 0;

	seg_size = 1ull << kvmppc_slb_sid_shift(slbe);
	kvmppc_mmu_flush_segment(vcpu, ea & ~(seg_size - 1), seg_size);
}

static void kvmppc_mmu_book3s_64_slbia(struct kvm_vcpu *vcpu)
{
	int i;

	dprintk("KVM MMU: slbia()\n");

	for (i = 1; i < vcpu->arch.slb_nr; i++) {
		vcpu->arch.slb[i].valid = false;
		vcpu->arch.slb[i].orige = 0;
		vcpu->arch.slb[i].origv = 0;
	}

	if (vcpu->arch.shared->msr & MSR_IR) {
		kvmppc_mmu_flush_segments(vcpu);
		kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu));
	}
}

static void kvmppc_mmu_book3s_64_mtsrin(struct kvm_vcpu *vcpu, u32 srnum,
					ulong value)
{
	u64 rb = 0, rs = 0;

	/*
	 * According to Book3 2.01 mtsrin is implemented as:
	 *
	 * The SLB entry specified by (RB)32:35 is loaded from register
	 * RS, as follows.
	 *
	 * SLBE Bit	Source			SLB Field
	 *
	 * 0:31		0x0000_0000		ESID-0:31
	 * 32:35	(RB)32:35		ESID-32:35
	 * 36		0b1			V
	 * 37:61	0x00_0000|| 0b0		VSID-0:24
	 * 62:88	(RS)37:63		VSID-25:51
	 * 89:91	(RS)33:35		Ks Kp N
	 * 92		(RS)36			L ((RS)36 must be 0b0)
	 * 93		0b0			C
	 */

	dprintk("KVM MMU: mtsrin(0x%x, 0x%lx)\n", srnum, value);

	/* ESID = srnum */
	rb |= (srnum & 0xf) << 28;
	/* Set the valid bit */
	rb |= 1 << 27;
	/* Index = ESID */
	rb |= srnum;

	/* VSID = VSID */
	rs |= (value & 0xfffffff) << 12;
	/* flags = flags */
	rs |= ((value >> 28) & 0x7) << 9;

	kvmppc_mmu_book3s_64_slbmte(vcpu, rs, rb);
}

static void kvmppc_mmu_book3s_64_tlbie(struct kvm_vcpu *vcpu, ulong va,
				       bool large)
{
	u64 mask = 0xFFFFFFFFFULL;

	dprintk("KVM MMU: tlbie(0x%lx)\n", va);

	/*
	 * The tlbie instruction changed behaviour starting with
	 * POWER6.  POWER6 and later don't have the large page flag
	 * in the instruction but in the RB value, along with bits
	 * indicating page and segment sizes.
	 */
	if (vcpu->arch.hflags & BOOK3S_HFLAG_NEW_TLBIE) {
		/* POWER6 or later */
		if (va & 1) {		/* L bit */
			if ((va & 0xf000) == 0x1000)
				mask = 0xFFFFFFFF0ULL;	/* 64k page */
			else
				mask = 0xFFFFFF000ULL;	/* 16M page */
		}
	} else {
		/* older processors, e.g. PPC970 */
		if (large)
			mask = 0xFFFFFF000ULL;
	}
	kvmppc_mmu_pte_vflush(vcpu, va >> 12, mask);
}

#ifdef CONFIG_PPC_64K_PAGES
static int segment_contains_magic_page(struct kvm_vcpu *vcpu, ulong esid)
{
	ulong mp_ea = vcpu->arch.magic_page_ea;

	return mp_ea && !(vcpu->arch.shared->msr & MSR_PR) &&
		(mp_ea >> SID_SHIFT) == esid;
}
#endif

static int kvmppc_mmu_book3s_64_esid_to_vsid(struct kvm_vcpu *vcpu, ulong esid,
					     u64 *vsid)
{
	ulong ea = esid << SID_SHIFT;
	struct kvmppc_slb *slb;
	u64 gvsid = esid;
	ulong mp_ea = vcpu->arch.magic_page_ea;
	int pagesize = MMU_PAGE_64K;

	if (vcpu->arch.shared->msr & (MSR_DR|MSR_IR)) {
		slb = kvmppc_mmu_book3s_64_find_slbe(vcpu, ea);
		if (slb) {
			gvsid = slb->vsid;
			pagesize = slb->base_page_size;
			if (slb->tb) {
				gvsid <<= SID_SHIFT_1T - SID_SHIFT;
				gvsid |= esid & ((1ul << (SID_SHIFT_1T - SID_SHIFT)) - 1);
				gvsid |= VSID_1T;
			}
		}
	}

	switch (vcpu->arch.shared->msr & (MSR_DR|MSR_IR)) {
	case 0:
		gvsid = VSID_REAL | esid;
		break;
	case MSR_IR:
		gvsid |= VSID_REAL_IR;
		break;
	case MSR_DR:
		gvsid |= VSID_REAL_DR;
		break;
	case MSR_DR|MSR_IR:
		if (!slb)
			goto no_slb;

		break;
	default:
		BUG();
		break;
	}

#ifdef CONFIG_PPC_64K_PAGES
	/*
	 * Mark this as a 64k segment if the host is using
	 * 64k pages, the host MMU supports 64k pages and
	 * the guest segment page size is >= 64k,
	 * but not if this segment contains the magic page.
	 */
	if (pagesize >= MMU_PAGE_64K &&
	    mmu_psize_defs[MMU_PAGE_64K].shift &&
	    !segment_contains_magic_page(vcpu, esid))
		gvsid |= VSID_64K;
#endif

	if (vcpu->arch.shared->msr & MSR_PR)
		gvsid |= VSID_PR;

	*vsid = gvsid;
	return 0;

no_slb:
	/* Catch magic page case */
	if (unlikely(mp_ea) &&
	    unlikely(esid == (mp_ea >> SID_SHIFT)) &&
	    !(vcpu->arch.shared->msr & MSR_PR)) {
		*vsid = VSID_REAL | esid;
		return 0;
	}

	return -EINVAL;
}

static bool kvmppc_mmu_book3s_64_is_dcbz32(struct kvm_vcpu *vcpu)
{
	return (to_book3s(vcpu)->hid[5] & 0x80);
}

void kvmppc_mmu_book3s_64_init(struct kvm_vcpu *vcpu)
{
	struct kvmppc_mmu *mmu = &vcpu->arch.mmu;

	mmu->mfsrin = NULL;
	mmu->mtsrin = kvmppc_mmu_book3s_64_mtsrin;
	mmu->slbmte = kvmppc_mmu_book3s_64_slbmte;
	mmu->slbmfee = kvmppc_mmu_book3s_64_slbmfee;
	mmu->slbmfev = kvmppc_mmu_book3s_64_slbmfev;
	mmu->slbie = kvmppc_mmu_book3s_64_slbie;
	mmu->slbia = kvmppc_mmu_book3s_64_slbia;
	mmu->xlate = kvmppc_mmu_book3s_64_xlate;
	mmu->reset_msr = kvmppc_mmu_book3s_64_reset_msr;
	mmu->tlbie = kvmppc_mmu_book3s_64_tlbie;
	mmu->esid_to_vsid = kvmppc_mmu_book3s_64_esid_to_vsid;
	mmu->ea_to_vp = kvmppc_mmu_book3s_64_ea_to_vp;
	mmu->is_dcbz32 = kvmppc_mmu_book3s_64_is_dcbz32;

	vcpu->arch.hflags |= BOOK3S_HFLAG_SLB;
}
Commit	Line	Data
e71b2a39 AG	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License, version 2, as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
	12	* along with this program; if not, write to the Free Software
	13	* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	14	*
	15	* Copyright SUSE Linux Products GmbH 2009
	16	*
	17	* Authors: Alexander Graf <agraf@suse.de>
	18	*/
	19
	20	#include <linux/types.h>
	21	#include <linux/string.h>
	22	#include <linux/kvm.h>
	23	#include <linux/kvm_host.h>
	24	#include <linux/highmem.h>
	25
	26	#include <asm/tlbflush.h>
	27	#include <asm/kvm_ppc.h>
	28	#include <asm/kvm_book3s.h>
0f296829	29	#include <asm/mmu-hash64.h>
e71b2a39 AG	30
	31	/* #define DEBUG_MMU */
	32
	33	#ifdef DEBUG_MMU
	34	#define dprintk(X...) printk(KERN_INFO X)
	35	#else
	36	#define dprintk(X...) do { } while(0)
	37	#endif
	38
	39	static void kvmppc_mmu_book3s_64_reset_msr(struct kvm_vcpu *vcpu)
	40	{
	41	kvmppc_set_msr(vcpu, MSR_SF);
	42	}
	43
	44	static struct kvmppc_slb *kvmppc_mmu_book3s_64_find_slbe(
c4befc58	45	struct kvm_vcpu *vcpu,
e71b2a39 AG	46	gva_t eaddr)
	47	{
	48	int i;
	49	u64 esid = GET_ESID(eaddr);
	50	u64 esid_1t = GET_ESID_1T(eaddr);
	51
c4befc58	52	for (i = 0; i < vcpu->arch.slb_nr; i++) {
e71b2a39 AG	53	u64 cmp_esid = esid;
e71b2a39 AG	54
c4befc58	55	if (!vcpu->arch.slb[i].valid)
e71b2a39 AG	56	continue;
e71b2a39 AG	57
c4befc58	58	if (vcpu->arch.slb[i].tb)
e71b2a39 AG	59	cmp_esid = esid_1t;
e71b2a39 AG	60
c4befc58 PM	61	if (vcpu->arch.slb[i].esid == cmp_esid)
c4befc58 PM	62	return &vcpu->arch.slb[i];
e71b2a39 AG	63	}
	64
	65	dprintk("KVM: No SLB entry found for 0x%lx [%llx \| %llx]\n",
	66	eaddr, esid, esid_1t);
c4befc58 PM	67	for (i = 0; i < vcpu->arch.slb_nr; i++) {
c4befc58 PM	68	if (vcpu->arch.slb[i].vsid)
4b5c9b7f	69	dprintk(" %d: %c%c%c %llx %llx\n", i,
c4befc58 PM	70	vcpu->arch.slb[i].valid ? 'v' : ' ',
	71	vcpu->arch.slb[i].large ? 'l' : ' ',
	72	vcpu->arch.slb[i].tb ? 't' : ' ',
	73	vcpu->arch.slb[i].esid,
	74	vcpu->arch.slb[i].vsid);
e71b2a39 AG	75	}
	76
	77	return NULL;
	78	}
	79
0f296829 PM	80	static int kvmppc_slb_sid_shift(struct kvmppc_slb *slbe)
	81	{
	82	return slbe->tb ? SID_SHIFT_1T : SID_SHIFT;
	83	}
	84
	85	static u64 kvmppc_slb_offset_mask(struct kvmppc_slb *slbe)
	86	{
	87	return (1ul << kvmppc_slb_sid_shift(slbe)) - 1;
	88	}
	89
	90	static u64 kvmppc_slb_calc_vpn(struct kvmppc_slb *slb, gva_t eaddr)
	91	{
	92	eaddr &= kvmppc_slb_offset_mask(slb);
	93
	94	return (eaddr >> VPN_SHIFT) \|
	95	((slb->vsid) << (kvmppc_slb_sid_shift(slb) - VPN_SHIFT));
	96	}
	97
e71b2a39 AG	98	static u64 kvmppc_mmu_book3s_64_ea_to_vp(struct kvm_vcpu *vcpu, gva_t eaddr,
	99	bool data)
	100	{
	101	struct kvmppc_slb *slb;
	102
c4befc58	103	slb = kvmppc_mmu_book3s_64_find_slbe(vcpu, eaddr);
e71b2a39 AG	104	if (!slb)
	105	return 0;
	106
0f296829	107	return kvmppc_slb_calc_vpn(slb, eaddr);
e71b2a39 AG	108	}
e71b2a39 AG	109
a4a0f252 PM	110	static int mmu_pagesize(int mmu_pg)
	111	{
	112	switch (mmu_pg) {
	113	case MMU_PAGE_64K:
	114	return 16;
	115	case MMU_PAGE_16M:
	116	return 24;
	117	}
	118	return 12;
	119	}
	120
e71b2a39 AG	121	static int kvmppc_mmu_book3s_64_get_pagesize(struct kvmppc_slb *slbe)
e71b2a39 AG	122	{
a4a0f252	123	return mmu_pagesize(slbe->base_page_size);
e71b2a39 AG	124	}
	125
	126	static u32 kvmppc_mmu_book3s_64_get_page(struct kvmppc_slb *slbe, gva_t eaddr)
	127	{
	128	int p = kvmppc_mmu_book3s_64_get_pagesize(slbe);
0f296829 PM	129
0f296829 PM	130	return ((eaddr & kvmppc_slb_offset_mask(slbe)) >> p);
e71b2a39 AG	131	}
	132
	133	static hva_t kvmppc_mmu_book3s_64_get_pteg(
	134	struct kvmppc_vcpu_book3s *vcpu_book3s,
	135	struct kvmppc_slb *slbe, gva_t eaddr,
	136	bool second)
	137	{
	138	u64 hash, pteg, htabsize;
0f296829	139	u32 ssize;
e71b2a39	140	hva_t r;
0f296829	141	u64 vpn;
e71b2a39	142
e71b2a39 AG	143	htabsize = ((1 << ((vcpu_book3s->sdr1 & 0x1f) + 11)) - 1);
e71b2a39 AG	144
0f296829 PM	145	vpn = kvmppc_slb_calc_vpn(slbe, eaddr);
	146	ssize = slbe->tb ? MMU_SEGSIZE_1T : MMU_SEGSIZE_256M;
	147	hash = hpt_hash(vpn, kvmppc_mmu_book3s_64_get_pagesize(slbe), ssize);
e71b2a39 AG	148	if (second)
	149	hash = ~hash;
	150	hash &= ((1ULL << 39ULL) - 1ULL);
	151	hash &= htabsize;
	152	hash <<= 7ULL;
	153
	154	pteg = vcpu_book3s->sdr1 & 0xfffffffffffc0000ULL;
	155	pteg \|= hash;
	156
	157	dprintk("MMU: page=0x%x sdr1=0x%llx pteg=0x%llx vsid=0x%llx\n",
	158	page, vcpu_book3s->sdr1, pteg, slbe->vsid);
	159
04fcc11b AG	160	/* When running a PAPR guest, SDR1 contains a HVA address instead
	161	of a GPA */
	162	if (vcpu_book3s->vcpu.arch.papr_enabled)
	163	r = pteg;
	164	else
	165	r = gfn_to_hva(vcpu_book3s->vcpu.kvm, pteg >> PAGE_SHIFT);
	166
e71b2a39 AG	167	if (kvm_is_error_hva(r))
	168	return r;
	169	return r \| (pteg & ~PAGE_MASK);
	170	}
	171
	172	static u64 kvmppc_mmu_book3s_64_get_avpn(struct kvmppc_slb *slbe, gva_t eaddr)
	173	{
	174	int p = kvmppc_mmu_book3s_64_get_pagesize(slbe);
	175	u64 avpn;
	176
	177	avpn = kvmppc_mmu_book3s_64_get_page(slbe, eaddr);
0f296829	178	avpn \|= slbe->vsid << (kvmppc_slb_sid_shift(slbe) - p);
e71b2a39	179
a4a0f252 PM	180	if (p < 16)
a4a0f252 PM	181	avpn >>= ((80 - p) - 56) - 8; /* 16 - p */
e71b2a39	182	else
a4a0f252	183	avpn <<= p - 16;
e71b2a39 AG	184
	185	return avpn;
	186	}
	187
a4a0f252 PM	188	/*
	189	* Return page size encoded in the second word of a HPTE, or
	190	* -1 for an invalid encoding for the base page size indicated by
	191	* the SLB entry. This doesn't handle mixed pagesize segments yet.
	192	*/
	193	static int decode_pagesize(struct kvmppc_slb *slbe, u64 r)
	194	{
	195	switch (slbe->base_page_size) {
	196	case MMU_PAGE_64K:
	197	if ((r & 0xf000) == 0x1000)
	198	return MMU_PAGE_64K;
	199	break;
	200	case MMU_PAGE_16M:
	201	if ((r & 0xff000) == 0)
	202	return MMU_PAGE_16M;
	203	break;
	204	}
	205	return -1;
	206	}
	207
e71b2a39 AG	208	static int kvmppc_mmu_book3s_64_xlate(struct kvm_vcpu *vcpu, gva_t eaddr,
	209	struct kvmppc_pte *gpte, bool data)
	210	{
	211	struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
	212	struct kvmppc_slb *slbe;
	213	hva_t ptegp;
	214	u64 pteg[16];
	215	u64 avpn = 0;
7e48c101 PM	216	u64 v, r;
	217	u64 v_val, v_mask;
	218	u64 eaddr_mask;
e71b2a39	219	int i;
7e48c101	220	u8 pp, key = 0;
e71b2a39	221	bool found = false;
7e48c101	222	bool second = false;
a4a0f252	223	int pgsize;
e8508940 AG	224	ulong mp_ea = vcpu->arch.magic_page_ea;
	225
	226	/* Magic page override */
	227	if (unlikely(mp_ea) &&
	228	unlikely((eaddr & ~0xfffULL) == (mp_ea & ~0xfffULL)) &&
	229	!(vcpu->arch.shared->msr & MSR_PR)) {
	230	gpte->eaddr = eaddr;
	231	gpte->vpage = kvmppc_mmu_book3s_64_ea_to_vp(vcpu, eaddr, data);
	232	gpte->raddr = vcpu->arch.magic_page_pa \| (gpte->raddr & 0xfff);
	233	gpte->raddr &= KVM_PAM;
	234	gpte->may_execute = true;
	235	gpte->may_read = true;
	236	gpte->may_write = true;
a4a0f252	237	gpte->page_size = MMU_PAGE_4K;
e8508940 AG	238
	239	return 0;
	240	}
e71b2a39	241
c4befc58	242	slbe = kvmppc_mmu_book3s_64_find_slbe(vcpu, eaddr);
e71b2a39 AG	243	if (!slbe)
	244	goto no_seg_found;
	245
0f296829	246	avpn = kvmppc_mmu_book3s_64_get_avpn(slbe, eaddr);
7e48c101 PM	247	v_val = avpn & HPTE_V_AVPN;
7e48c101 PM	248
0f296829	249	if (slbe->tb)
7e48c101 PM	250	v_val \|= SLB_VSID_B_1T;
	251	if (slbe->large)
	252	v_val \|= HPTE_V_LARGE;
	253	v_val \|= HPTE_V_VALID;
	254
	255	v_mask = SLB_VSID_B \| HPTE_V_AVPN \| HPTE_V_LARGE \| HPTE_V_VALID \|
	256	HPTE_V_SECONDARY;
0f296829	257
a4a0f252 PM	258	pgsize = slbe->large ? MMU_PAGE_16M : MMU_PAGE_4K;
a4a0f252 PM	259
e71b2a39 AG	260	do_second:
	261	ptegp = kvmppc_mmu_book3s_64_get_pteg(vcpu_book3s, slbe, eaddr, second);
	262	if (kvm_is_error_hva(ptegp))
	263	goto no_page_found;
	264
e71b2a39 AG	265	if(copy_from_user(pteg, (void __user *)ptegp, sizeof(pteg))) {
	266	printk(KERN_ERR "KVM can't copy data from 0x%lx!\n", ptegp);
	267	goto no_page_found;
	268	}
	269
666e7252	270	if ((vcpu->arch.shared->msr & MSR_PR) && slbe->Kp)
e71b2a39	271	key = 4;
666e7252	272	else if (!(vcpu->arch.shared->msr & MSR_PR) && slbe->Ks)
e71b2a39 AG	273	key = 4;
	274
	275	for (i=0; i<16; i+=2) {
7e48c101 PM	276	/* Check all relevant fields of 1st dword */
7e48c101 PM	277	if ((pteg[i] & v_mask) == v_val) {
a4a0f252 PM	278	/* If large page bit is set, check pgsize encoding */
	279	if (slbe->large &&
	280	(vcpu->arch.hflags & BOOK3S_HFLAG_MULTI_PGSIZE)) {
	281	pgsize = decode_pagesize(slbe, pteg[i+1]);
	282	if (pgsize < 0)
	283	continue;
	284	}
e71b2a39 AG	285	found = true;
	286	break;
	287	}
	288	}
	289
7e48c101 PM	290	if (!found) {
	291	if (second)
	292	goto no_page_found;
	293	v_val \|= HPTE_V_SECONDARY;
	294	second = true;
	295	goto do_second;
	296	}
e71b2a39	297
7e48c101 PM	298	v = pteg[i];
	299	r = pteg[i+1];
	300	pp = (r & HPTE_R_PP) \| key;
03a9c903 PM	301	if (r & HPTE_R_PP0)
03a9c903 PM	302	pp \|= 8;
7e48c101 PM	303
	304	gpte->eaddr = eaddr;
	305	gpte->vpage = kvmppc_mmu_book3s_64_ea_to_vp(vcpu, eaddr, data);
a4a0f252 PM	306
a4a0f252 PM	307	eaddr_mask = (1ull << mmu_pagesize(pgsize)) - 1;
7e48c101	308	gpte->raddr = (r & HPTE_R_RPN & ~eaddr_mask) \| (eaddr & eaddr_mask);
a4a0f252	309	gpte->page_size = pgsize;
7e48c101 PM	310	gpte->may_execute = ((r & HPTE_R_N) ? false : true);
	311	gpte->may_read = false;
	312	gpte->may_write = false;
	313
	314	switch (pp) {
	315	case 0:
	316	case 1:
	317	case 2:
	318	case 6:
	319	gpte->may_write = true;
	320	/* fall through */
	321	case 3:
	322	case 5:
	323	case 7:
03a9c903	324	case 10:
7e48c101 PM	325	gpte->may_read = true;
	326	break;
	327	}
e71b2a39	328
7e48c101 PM	329	dprintk("KVM MMU: Translated 0x%lx [0x%llx] -> 0x%llx "
	330	"-> 0x%lx\n",
	331	eaddr, avpn, gpte->vpage, gpte->raddr);
e71b2a39	332
7e48c101 PM	333	/* Update PTE R and C bits, so the guest's swapper knows we used the
	334	* page */
	335	if (gpte->may_read) {
	336	/* Set the accessed flag */
	337	r \|= HPTE_R_R;
	338	}
	339	if (data && gpte->may_write) {
	340	/* Set the dirty flag -- XXX even if not writing */
	341	r \|= HPTE_R_C;
e71b2a39 AG	342	}
e71b2a39 AG	343
7e48c101 PM	344	/* Write back into the PTEG */
	345	if (pteg[i+1] != r) {
	346	pteg[i+1] = r;
	347	copy_to_user((void __user *)ptegp, pteg, sizeof(pteg));
	348	}
	349
	350	if (!gpte->may_read)
	351	return -EPERM;
	352	return 0;
	353
e71b2a39	354	no_page_found:
e71b2a39 AG	355	return -ENOENT;
	356
	357	no_seg_found:
	358
	359	dprintk("KVM MMU: Trigger segment fault\n");
	360	return -EINVAL;
	361	}
	362
	363	static void kvmppc_mmu_book3s_64_slbmte(struct kvm_vcpu *vcpu, u64 rs, u64 rb)
	364	{
	365	struct kvmppc_vcpu_book3s *vcpu_book3s;
	366	u64 esid, esid_1t;
	367	int slb_nr;
	368	struct kvmppc_slb *slbe;
	369
	370	dprintk("KVM MMU: slbmte(0x%llx, 0x%llx)\n", rs, rb);
	371
	372	vcpu_book3s = to_book3s(vcpu);
	373
	374	esid = GET_ESID(rb);
	375	esid_1t = GET_ESID_1T(rb);
	376	slb_nr = rb & 0xfff;
	377
c4befc58	378	if (slb_nr > vcpu->arch.slb_nr)
e71b2a39 AG	379	return;
e71b2a39 AG	380
c4befc58	381	slbe = &vcpu->arch.slb[slb_nr];
e71b2a39 AG	382
e71b2a39 AG	383	slbe->large = (rs & SLB_VSID_L) ? 1 : 0;
4b5c9b7f AG	384	slbe->tb = (rs & SLB_VSID_B_1T) ? 1 : 0;
4b5c9b7f AG	385	slbe->esid = slbe->tb ? esid_1t : esid;
0f296829	386	slbe->vsid = (rs & ~SLB_VSID_B) >> (kvmppc_slb_sid_shift(slbe) - 16);
e71b2a39 AG	387	slbe->valid = (rb & SLB_ESID_V) ? 1 : 0;
	388	slbe->Ks = (rs & SLB_VSID_KS) ? 1 : 0;
	389	slbe->Kp = (rs & SLB_VSID_KP) ? 1 : 0;
	390	slbe->nx = (rs & SLB_VSID_N) ? 1 : 0;
	391	slbe->class = (rs & SLB_VSID_C) ? 1 : 0;
	392
a4a0f252 PM	393	slbe->base_page_size = MMU_PAGE_4K;
	394	if (slbe->large) {
	395	if (vcpu->arch.hflags & BOOK3S_HFLAG_MULTI_PGSIZE) {
	396	switch (rs & SLB_VSID_LP) {
	397	case SLB_VSID_LP_00:
	398	slbe->base_page_size = MMU_PAGE_16M;
	399	break;
	400	case SLB_VSID_LP_01:
	401	slbe->base_page_size = MMU_PAGE_64K;
	402	break;
	403	}
	404	} else
	405	slbe->base_page_size = MMU_PAGE_16M;
	406	}
	407
e71b2a39 AG	408	slbe->orige = rb & (ESID_MASK \| SLB_ESID_V);
	409	slbe->origv = rs;
	410
	411	/* Map the new segment */
	412	kvmppc_mmu_map_segment(vcpu, esid << SID_SHIFT);
	413	}
	414
	415	static u64 kvmppc_mmu_book3s_64_slbmfee(struct kvm_vcpu *vcpu, u64 slb_nr)
	416	{
e71b2a39 AG	417	struct kvmppc_slb *slbe;
e71b2a39 AG	418
c4befc58	419	if (slb_nr > vcpu->arch.slb_nr)
e71b2a39 AG	420	return 0;
e71b2a39 AG	421
c4befc58	422	slbe = &vcpu->arch.slb[slb_nr];
e71b2a39 AG	423
	424	return slbe->orige;
	425	}
	426
	427	static u64 kvmppc_mmu_book3s_64_slbmfev(struct kvm_vcpu *vcpu, u64 slb_nr)
	428	{
e71b2a39 AG	429	struct kvmppc_slb *slbe;
e71b2a39 AG	430
c4befc58	431	if (slb_nr > vcpu->arch.slb_nr)
e71b2a39 AG	432	return 0;
e71b2a39 AG	433
c4befc58	434	slbe = &vcpu->arch.slb[slb_nr];
e71b2a39 AG	435
	436	return slbe->origv;
	437	}
	438
	439	static void kvmppc_mmu_book3s_64_slbie(struct kvm_vcpu *vcpu, u64 ea)
	440	{
e71b2a39	441	struct kvmppc_slb *slbe;
0f296829	442	u64 seg_size;
e71b2a39 AG	443
	444	dprintk("KVM MMU: slbie(0x%llx)\n", ea);
	445
c4befc58	446	slbe = kvmppc_mmu_book3s_64_find_slbe(vcpu, ea);
e71b2a39 AG	447
	448	if (!slbe)
	449	return;
	450
	451	dprintk("KVM MMU: slbie(0x%llx, 0x%llx)\n", ea, slbe->esid);
	452
	453	slbe->valid = false;
681562cd PM	454	slbe->orige = 0;
681562cd PM	455	slbe->origv = 0;
e71b2a39	456
0f296829 PM	457	seg_size = 1ull << kvmppc_slb_sid_shift(slbe);
0f296829 PM	458	kvmppc_mmu_flush_segment(vcpu, ea & ~(seg_size - 1), seg_size);
e71b2a39 AG	459	}
	460
	461	static void kvmppc_mmu_book3s_64_slbia(struct kvm_vcpu *vcpu)
	462	{
e71b2a39 AG	463	int i;
	464
	465	dprintk("KVM MMU: slbia()\n");
	466
681562cd	467	for (i = 1; i < vcpu->arch.slb_nr; i++) {
c4befc58	468	vcpu->arch.slb[i].valid = false;
681562cd PM	469	vcpu->arch.slb[i].orige = 0;
	470	vcpu->arch.slb[i].origv = 0;
	471	}
e71b2a39	472
666e7252	473	if (vcpu->arch.shared->msr & MSR_IR) {
e71b2a39	474	kvmppc_mmu_flush_segments(vcpu);
c7f38f46	475	kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu));
e71b2a39 AG	476	}
	477	}
	478
	479	static void kvmppc_mmu_book3s_64_mtsrin(struct kvm_vcpu *vcpu, u32 srnum,
	480	ulong value)
	481	{
	482	u64 rb = 0, rs = 0;
	483
5279aeb4 AG	484	/*
	485	* According to Book3 2.01 mtsrin is implemented as:
	486	*
	487	* The SLB entry specified by (RB)32:35 is loaded from register
	488	* RS, as follows.
	489	*
	490	* SLBE Bit Source SLB Field
	491	*
	492	* 0:31 0x0000_0000 ESID-0:31
	493	* 32:35 (RB)32:35 ESID-32:35
	494	* 36 0b1 V
	495	* 37:61 0x00_0000\|\| 0b0 VSID-0:24
	496	* 62:88 (RS)37:63 VSID-25:51
	497	* 89:91 (RS)33:35 Ks Kp N
	498	* 92 (RS)36 L ((RS)36 must be 0b0)
	499	* 93 0b0 C
	500	*/
	501
	502	dprintk("KVM MMU: mtsrin(0x%x, 0x%lx)\n", srnum, value);
	503
e71b2a39 AG	504	/* ESID = srnum */
	505	rb \|= (srnum & 0xf) << 28;
	506	/* Set the valid bit */
	507	rb \|= 1 << 27;
	508	/* Index = ESID */
	509	rb \|= srnum;
	510
	511	/* VSID = VSID */
	512	rs \|= (value & 0xfffffff) << 12;
	513	/* flags = flags */
5279aeb4	514	rs \|= ((value >> 28) & 0x7) << 9;
e71b2a39 AG	515
	516	kvmppc_mmu_book3s_64_slbmte(vcpu, rs, rb);
	517	}
	518
	519	static void kvmppc_mmu_book3s_64_tlbie(struct kvm_vcpu *vcpu, ulong va,
	520	bool large)
	521	{
	522	u64 mask = 0xFFFFFFFFFULL;
	523
	524	dprintk("KVM MMU: tlbie(0x%lx)\n", va);
	525
a4a0f252 PM	526	/*
	527	* The tlbie instruction changed behaviour starting with
	528	* POWER6. POWER6 and later don't have the large page flag
	529	* in the instruction but in the RB value, along with bits
	530	* indicating page and segment sizes.
	531	*/
	532	if (vcpu->arch.hflags & BOOK3S_HFLAG_NEW_TLBIE) {
	533	/* POWER6 or later */
	534	if (va & 1) { /* L bit */
	535	if ((va & 0xf000) == 0x1000)
	536	mask = 0xFFFFFFFF0ULL; /* 64k page */
	537	else
	538	mask = 0xFFFFFF000ULL; /* 16M page */
	539	}
	540	} else {
	541	/* older processors, e.g. PPC970 */
	542	if (large)
	543	mask = 0xFFFFFF000ULL;
	544	}
e71b2a39 AG	545	kvmppc_mmu_pte_vflush(vcpu, va >> 12, mask);
	546	}
	547
c9029c34 PM	548	#ifdef CONFIG_PPC_64K_PAGES
	549	static int segment_contains_magic_page(struct kvm_vcpu *vcpu, ulong esid)
	550	{
	551	ulong mp_ea = vcpu->arch.magic_page_ea;
	552
	553	return mp_ea && !(vcpu->arch.shared->msr & MSR_PR) &&
	554	(mp_ea >> SID_SHIFT) == esid;
	555	}
	556	#endif
	557
af7b4d10	558	static int kvmppc_mmu_book3s_64_esid_to_vsid(struct kvm_vcpu *vcpu, ulong esid,
e71b2a39 AG	559	u64 *vsid)
e71b2a39 AG	560	{
f7bc74e1 AG	561	ulong ea = esid << SID_SHIFT;
	562	struct kvmppc_slb *slb;
	563	u64 gvsid = esid;
e8508940	564	ulong mp_ea = vcpu->arch.magic_page_ea;
c9029c34	565	int pagesize = MMU_PAGE_64K;
f7bc74e1	566
666e7252	567	if (vcpu->arch.shared->msr & (MSR_DR\|MSR_IR)) {
c4befc58	568	slb = kvmppc_mmu_book3s_64_find_slbe(vcpu, ea);
0f296829	569	if (slb) {
f7bc74e1	570	gvsid = slb->vsid;
c9029c34	571	pagesize = slb->base_page_size;
0f296829 PM	572	if (slb->tb) {
	573	gvsid <<= SID_SHIFT_1T - SID_SHIFT;
	574	gvsid \|= esid & ((1ul << (SID_SHIFT_1T - SID_SHIFT)) - 1);
	575	gvsid \|= VSID_1T;
	576	}
	577	}
f7bc74e1 AG	578	}
f7bc74e1 AG	579
666e7252	580	switch (vcpu->arch.shared->msr & (MSR_DR\|MSR_IR)) {
e71b2a39	581	case 0:
c9029c34	582	gvsid = VSID_REAL \| esid;
e71b2a39 AG	583	break;
e71b2a39 AG	584	case MSR_IR:
c9029c34	585	gvsid \|= VSID_REAL_IR;
e71b2a39 AG	586	break;
e71b2a39 AG	587	case MSR_DR:
c9029c34	588	gvsid \|= VSID_REAL_DR;
e71b2a39 AG	589	break;
e71b2a39 AG	590	case MSR_DR\|MSR_IR:
f7bc74e1	591	if (!slb)
e8508940	592	goto no_slb;
e71b2a39 AG	593
e71b2a39 AG	594	break;
e71b2a39 AG	595	default:
	596	BUG();
	597	break;
	598	}
	599
c9029c34 PM	600	#ifdef CONFIG_PPC_64K_PAGES
	601	/*
	602	* Mark this as a 64k segment if the host is using
	603	* 64k pages, the host MMU supports 64k pages and
	604	* the guest segment page size is >= 64k,
	605	* but not if this segment contains the magic page.
	606	*/
	607	if (pagesize >= MMU_PAGE_64K &&
	608	mmu_psize_defs[MMU_PAGE_64K].shift &&
	609	!segment_contains_magic_page(vcpu, esid))
	610	gvsid \|= VSID_64K;
	611	#endif
	612
666e7252	613	if (vcpu->arch.shared->msr & MSR_PR)
c9029c34	614	gvsid \|= VSID_PR;
63556441	615
c9029c34	616	*vsid = gvsid;
e71b2a39	617	return 0;
e8508940 AG	618
	619	no_slb:
	620	/* Catch magic page case */
	621	if (unlikely(mp_ea) &&
	622	unlikely(esid == (mp_ea >> SID_SHIFT)) &&
	623	!(vcpu->arch.shared->msr & MSR_PR)) {
	624	*vsid = VSID_REAL \| esid;
	625	return 0;
	626	}
	627
	628	return -EINVAL;
e71b2a39 AG	629	}
	630
	631	static bool kvmppc_mmu_book3s_64_is_dcbz32(struct kvm_vcpu *vcpu)
	632	{
	633	return (to_book3s(vcpu)->hid[5] & 0x80);
	634	}
	635
	636	void kvmppc_mmu_book3s_64_init(struct kvm_vcpu *vcpu)
	637	{
	638	struct kvmppc_mmu *mmu = &vcpu->arch.mmu;
	639
	640	mmu->mfsrin = NULL;
	641	mmu->mtsrin = kvmppc_mmu_book3s_64_mtsrin;
	642	mmu->slbmte = kvmppc_mmu_book3s_64_slbmte;
	643	mmu->slbmfee = kvmppc_mmu_book3s_64_slbmfee;
	644	mmu->slbmfev = kvmppc_mmu_book3s_64_slbmfev;
	645	mmu->slbie = kvmppc_mmu_book3s_64_slbie;
	646	mmu->slbia = kvmppc_mmu_book3s_64_slbia;
	647	mmu->xlate = kvmppc_mmu_book3s_64_xlate;
	648	mmu->reset_msr = kvmppc_mmu_book3s_64_reset_msr;
	649	mmu->tlbie = kvmppc_mmu_book3s_64_tlbie;
	650	mmu->esid_to_vsid = kvmppc_mmu_book3s_64_esid_to_vsid;
	651	mmu->ea_to_vp = kvmppc_mmu_book3s_64_ea_to_vp;
	652	mmu->is_dcbz32 = kvmppc_mmu_book3s_64_is_dcbz32;
e15a1137 AG	653
e15a1137 AG	654	vcpu->arch.hflags \|= BOOK3S_HFLAG_SLB;
e71b2a39	655	}