Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
2104180a NP |
2 | /* |
3 | * Watchdog support on powerpc systems. | |
4 | * | |
5 | * Copyright 2017, IBM Corporation. | |
6 | * | |
7 | * This uses code from arch/sparc/kernel/nmi.c and kernel/watchdog.c | |
8 | */ | |
d8fa82e0 ME |
9 | |
10 | #define pr_fmt(fmt) "watchdog: " fmt | |
11 | ||
2104180a NP |
12 | #include <linux/kernel.h> |
13 | #include <linux/param.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/percpu.h> | |
16 | #include <linux/cpu.h> | |
17 | #include <linux/nmi.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/export.h> | |
20 | #include <linux/kprobes.h> | |
21 | #include <linux/hardirq.h> | |
22 | #include <linux/reboot.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/kdebug.h> | |
25 | #include <linux/sched/debug.h> | |
26 | #include <linux/delay.h> | |
2400c13c | 27 | #include <linux/processor.h> |
2104180a NP |
28 | #include <linux/smp.h> |
29 | ||
3a96570f | 30 | #include <asm/interrupt.h> |
2104180a | 31 | #include <asm/paca.h> |
9ae440fb | 32 | #include <asm/nmi.h> |
2104180a NP |
33 | |
34 | /* | |
723b1133 NP |
35 | * The powerpc watchdog ensures that each CPU is able to service timers. |
36 | * The watchdog sets up a simple timer on each CPU to run once per timer | |
37 | * period, and updates a per-cpu timestamp and a "pending" cpumask. This is | |
38 | * the heartbeat. | |
2104180a | 39 | * |
723b1133 NP |
40 | * Then there are two systems to check that the heartbeat is still running. |
41 | * The local soft-NMI, and the SMP checker. | |
2104180a | 42 | * |
723b1133 NP |
43 | * The soft-NMI checker can detect lockups on the local CPU. When interrupts |
44 | * are disabled with local_irq_disable(), platforms that use soft-masking | |
45 | * can leave hardware interrupts enabled and handle them with a masked | |
46 | * interrupt handler. The masked handler can send the timer interrupt to the | |
47 | * watchdog's soft_nmi_interrupt(), which appears to Linux as an NMI | |
48 | * interrupt, and can be used to detect CPUs stuck with IRQs disabled. | |
49 | * | |
50 | * The soft-NMI checker will compare the heartbeat timestamp for this CPU | |
51 | * with the current time, and take action if the difference exceeds the | |
52 | * watchdog threshold. | |
53 | * | |
54 | * The limitation of the soft-NMI watchdog is that it does not work when | |
55 | * interrupts are hard disabled or otherwise not being serviced. This is | |
56 | * solved by also having a SMP watchdog where all CPUs check all other | |
57 | * CPUs heartbeat. | |
58 | * | |
1fd02f66 | 59 | * The SMP checker can detect lockups on other CPUs. A global "pending" |
723b1133 NP |
60 | * cpumask is kept, containing all CPUs which enable the watchdog. Each |
61 | * CPU clears their pending bit in their heartbeat timer. When the bitmask | |
62 | * becomes empty, the last CPU to clear its pending bit updates a global | |
63 | * timestamp and refills the pending bitmask. | |
64 | * | |
65 | * In the heartbeat timer, if any CPU notices that the global timestamp has | |
66 | * not been updated for a period exceeding the watchdog threshold, then it | |
67 | * means the CPU(s) with their bit still set in the pending mask have had | |
68 | * their heartbeat stop, and action is taken. | |
69 | * | |
7c18659d | 70 | * Some platforms implement true NMI IPIs, which can be used by the SMP |
723b1133 NP |
71 | * watchdog to detect an unresponsive CPU and pull it out of its stuck |
72 | * state with the NMI IPI, to get crash/debug data from it. This way the | |
73 | * SMP watchdog can detect hardware interrupts off lockups. | |
2104180a NP |
74 | */ |
75 | ||
76 | static cpumask_t wd_cpus_enabled __read_mostly; | |
77 | ||
78 | static u64 wd_panic_timeout_tb __read_mostly; /* timebase ticks until panic */ | |
79 | static u64 wd_smp_panic_timeout_tb __read_mostly; /* panic other CPUs */ | |
80 | ||
81 | static u64 wd_timer_period_ms __read_mostly; /* interval between heartbeat */ | |
82 | ||
7ae3f6e1 | 83 | static DEFINE_PER_CPU(struct hrtimer, wd_hrtimer); |
2104180a NP |
84 | static DEFINE_PER_CPU(u64, wd_timer_tb); |
85 | ||
723b1133 | 86 | /* SMP checker bits */ |
2104180a | 87 | static unsigned long __wd_smp_lock; |
76521c4b | 88 | static unsigned long __wd_reporting; |
e012c499 | 89 | static unsigned long __wd_nmi_output; |
2104180a NP |
90 | static cpumask_t wd_smp_cpus_pending; |
91 | static cpumask_t wd_smp_cpus_stuck; | |
92 | static u64 wd_smp_last_reset_tb; | |
93 | ||
f5e74e83 LD |
94 | #ifdef CONFIG_PPC_PSERIES |
95 | static u64 wd_timeout_pct; | |
96 | #endif | |
97 | ||
76521c4b NP |
98 | /* |
99 | * Try to take the exclusive watchdog action / NMI IPI / printing lock. | |
100 | * wd_smp_lock must be held. If this fails, we should return and wait | |
101 | * for the watchdog to kick in again (or another CPU to trigger it). | |
102 | * | |
103 | * Importantly, if hardlockup_panic is set, wd_try_report failure should | |
104 | * not delay the panic, because whichever other CPU is reporting will | |
105 | * call panic. | |
106 | */ | |
107 | static bool wd_try_report(void) | |
108 | { | |
109 | if (__wd_reporting) | |
110 | return false; | |
111 | __wd_reporting = 1; | |
112 | return true; | |
113 | } | |
114 | ||
115 | /* End printing after successful wd_try_report. wd_smp_lock not required. */ | |
116 | static void wd_end_reporting(void) | |
117 | { | |
118 | smp_mb(); /* End printing "critical section" */ | |
119 | WARN_ON_ONCE(__wd_reporting == 0); | |
120 | WRITE_ONCE(__wd_reporting, 0); | |
121 | } | |
122 | ||
2104180a NP |
123 | static inline void wd_smp_lock(unsigned long *flags) |
124 | { | |
125 | /* | |
126 | * Avoid locking layers if possible. | |
127 | * This may be called from low level interrupt handlers at some | |
128 | * point in future. | |
129 | */ | |
d8e2a405 NP |
130 | raw_local_irq_save(*flags); |
131 | hard_irq_disable(); /* Make it soft-NMI safe */ | |
132 | while (unlikely(test_and_set_bit_lock(0, &__wd_smp_lock))) { | |
133 | raw_local_irq_restore(*flags); | |
134 | spin_until_cond(!test_bit(0, &__wd_smp_lock)); | |
135 | raw_local_irq_save(*flags); | |
136 | hard_irq_disable(); | |
137 | } | |
2104180a NP |
138 | } |
139 | ||
140 | static inline void wd_smp_unlock(unsigned long *flags) | |
141 | { | |
142 | clear_bit_unlock(0, &__wd_smp_lock); | |
d8e2a405 | 143 | raw_local_irq_restore(*flags); |
2104180a NP |
144 | } |
145 | ||
146 | static void wd_lockup_ipi(struct pt_regs *regs) | |
147 | { | |
4e49226e NP |
148 | int cpu = raw_smp_processor_id(); |
149 | u64 tb = get_tb(); | |
150 | ||
151 | pr_emerg("CPU %d Hard LOCKUP\n", cpu); | |
152 | pr_emerg("CPU %d TB:%lld, last heartbeat TB:%lld (%lldms ago)\n", | |
153 | cpu, tb, per_cpu(wd_timer_tb, cpu), | |
154 | tb_to_ns(tb - per_cpu(wd_timer_tb, cpu)) / 1000000); | |
2104180a NP |
155 | print_modules(); |
156 | print_irqtrace_events(current); | |
157 | if (regs) | |
158 | show_regs(regs); | |
159 | else | |
160 | dump_stack(); | |
161 | ||
e012c499 NP |
162 | /* |
163 | * __wd_nmi_output must be set after we printk from NMI context. | |
164 | * | |
165 | * printk from NMI context defers printing to the console to irq_work. | |
166 | * If that NMI was taken in some code that is hard-locked, then irqs | |
167 | * are disabled so irq_work will never fire. That can result in the | |
168 | * hard lockup messages being delayed (indefinitely, until something | |
169 | * else kicks the console drivers). | |
170 | * | |
171 | * Setting __wd_nmi_output will cause another CPU to notice and kick | |
172 | * the console drivers for us. | |
173 | * | |
174 | * xchg is not needed here (it could be a smp_mb and store), but xchg | |
175 | * gives the memory ordering and atomicity required. | |
176 | */ | |
177 | xchg(&__wd_nmi_output, 1); | |
178 | ||
842dc1db | 179 | /* Do not panic from here because that can recurse into NMI IPI layer */ |
2104180a NP |
180 | } |
181 | ||
1f01bf90 | 182 | static bool set_cpu_stuck(int cpu) |
2104180a | 183 | { |
858c93c3 NP |
184 | cpumask_set_cpu(cpu, &wd_smp_cpus_stuck); |
185 | cpumask_clear_cpu(cpu, &wd_smp_cpus_pending); | |
5dad4ba6 NP |
186 | /* |
187 | * See wd_smp_clear_cpu_pending() | |
188 | */ | |
189 | smp_mb(); | |
2104180a | 190 | if (cpumask_empty(&wd_smp_cpus_pending)) { |
1f01bf90 | 191 | wd_smp_last_reset_tb = get_tb(); |
2104180a NP |
192 | cpumask_andnot(&wd_smp_cpus_pending, |
193 | &wd_cpus_enabled, | |
194 | &wd_smp_cpus_stuck); | |
858c93c3 | 195 | return true; |
2104180a | 196 | } |
858c93c3 | 197 | return false; |
87607a30 | 198 | } |
2104180a | 199 | |
1f01bf90 | 200 | static void watchdog_smp_panic(int cpu) |
2104180a | 201 | { |
76521c4b | 202 | static cpumask_t wd_smp_cpus_ipi; // protected by reporting |
2104180a | 203 | unsigned long flags; |
3d030e30 | 204 | u64 tb, last_reset; |
2104180a NP |
205 | int c; |
206 | ||
207 | wd_smp_lock(&flags); | |
208 | /* Double check some things under lock */ | |
1f01bf90 | 209 | tb = get_tb(); |
3d030e30 NP |
210 | last_reset = wd_smp_last_reset_tb; |
211 | if ((s64)(tb - last_reset) < (s64)wd_smp_panic_timeout_tb) | |
2104180a NP |
212 | goto out; |
213 | if (cpumask_test_cpu(cpu, &wd_smp_cpus_pending)) | |
214 | goto out; | |
76521c4b | 215 | if (!wd_try_report()) |
2104180a | 216 | goto out; |
76521c4b NP |
217 | for_each_online_cpu(c) { |
218 | if (!cpumask_test_cpu(c, &wd_smp_cpus_pending)) | |
219 | continue; | |
220 | if (c == cpu) | |
221 | continue; // should not happen | |
222 | ||
223 | __cpumask_set_cpu(c, &wd_smp_cpus_ipi); | |
1f01bf90 | 224 | if (set_cpu_stuck(c)) |
76521c4b NP |
225 | break; |
226 | } | |
227 | if (cpumask_empty(&wd_smp_cpus_ipi)) { | |
228 | wd_end_reporting(); | |
229 | goto out; | |
230 | } | |
231 | wd_smp_unlock(&flags); | |
2104180a | 232 | |
d8fa82e0 | 233 | pr_emerg("CPU %d detected hard LOCKUP on other CPUs %*pbl\n", |
76521c4b | 234 | cpu, cpumask_pr_args(&wd_smp_cpus_ipi)); |
4e49226e | 235 | pr_emerg("CPU %d TB:%lld, last SMP heartbeat TB:%lld (%lldms ago)\n", |
3d030e30 | 236 | cpu, tb, last_reset, tb_to_ns(tb - last_reset) / 1000000); |
2104180a | 237 | |
d58fdd9d NP |
238 | if (!sysctl_hardlockup_all_cpu_backtrace) { |
239 | /* | |
240 | * Try to trigger the stuck CPUs, unless we are going to | |
241 | * get a backtrace on all of them anyway. | |
242 | */ | |
76521c4b | 243 | for_each_cpu(c, &wd_smp_cpus_ipi) { |
d58fdd9d | 244 | smp_send_nmi_ipi(c, wd_lockup_ipi, 1000000); |
76521c4b | 245 | __cpumask_clear_cpu(c, &wd_smp_cpus_ipi); |
d58fdd9d | 246 | } |
76521c4b | 247 | } else { |
8d539b84 | 248 | trigger_allbutcpu_cpu_backtrace(cpu); |
76521c4b NP |
249 | cpumask_clear(&wd_smp_cpus_ipi); |
250 | } | |
2104180a NP |
251 | |
252 | if (hardlockup_panic) | |
253 | nmi_panic(NULL, "Hard LOCKUP"); | |
8e236921 | 254 | |
76521c4b NP |
255 | wd_end_reporting(); |
256 | ||
8e236921 NP |
257 | return; |
258 | ||
259 | out: | |
260 | wd_smp_unlock(&flags); | |
2104180a NP |
261 | } |
262 | ||
1f01bf90 | 263 | static void wd_smp_clear_cpu_pending(int cpu) |
2104180a NP |
264 | { |
265 | if (!cpumask_test_cpu(cpu, &wd_smp_cpus_pending)) { | |
266 | if (unlikely(cpumask_test_cpu(cpu, &wd_smp_cpus_stuck))) { | |
4e49226e | 267 | struct pt_regs *regs = get_irq_regs(); |
2104180a NP |
268 | unsigned long flags; |
269 | ||
4e49226e | 270 | pr_emerg("CPU %d became unstuck TB:%lld\n", |
1f01bf90 | 271 | cpu, get_tb()); |
4e49226e NP |
272 | print_irqtrace_events(current); |
273 | if (regs) | |
274 | show_regs(regs); | |
275 | else | |
276 | dump_stack(); | |
277 | ||
76521c4b | 278 | wd_smp_lock(&flags); |
2104180a NP |
279 | cpumask_clear_cpu(cpu, &wd_smp_cpus_stuck); |
280 | wd_smp_unlock(&flags); | |
5dad4ba6 NP |
281 | } else { |
282 | /* | |
283 | * The last CPU to clear pending should have reset the | |
284 | * watchdog so we generally should not find it empty | |
285 | * here if our CPU was clear. However it could happen | |
286 | * due to a rare race with another CPU taking the | |
287 | * last CPU out of the mask concurrently. | |
288 | * | |
289 | * We can't add a warning for it. But just in case | |
290 | * there is a problem with the watchdog that is causing | |
291 | * the mask to not be reset, try to kick it along here. | |
292 | */ | |
293 | if (unlikely(cpumask_empty(&wd_smp_cpus_pending))) | |
294 | goto none_pending; | |
2104180a NP |
295 | } |
296 | return; | |
297 | } | |
5dad4ba6 | 298 | |
858c93c3 NP |
299 | /* |
300 | * All other updates to wd_smp_cpus_pending are performed under | |
301 | * wd_smp_lock. All of them are atomic except the case where the | |
302 | * mask becomes empty and is reset. This will not happen here because | |
303 | * cpu was tested to be in the bitmap (above), and a CPU only clears | |
304 | * its own bit. _Except_ in the case where another CPU has detected a | |
305 | * hard lockup on our CPU and takes us out of the pending mask. So in | |
306 | * normal operation there will be no race here, no problem. | |
307 | * | |
308 | * In the lockup case, this atomic clear-bit vs a store that refills | |
309 | * other bits in the accessed word wll not be a problem. The bit clear | |
310 | * is atomic so it will not cause the store to get lost, and the store | |
311 | * will never set this bit so it will not overwrite the bit clear. The | |
312 | * only way for a stuck CPU to return to the pending bitmap is to | |
313 | * become unstuck itself. | |
314 | */ | |
2104180a | 315 | cpumask_clear_cpu(cpu, &wd_smp_cpus_pending); |
5dad4ba6 NP |
316 | |
317 | /* | |
318 | * Order the store to clear pending with the load(s) to check all | |
319 | * words in the pending mask to check they are all empty. This orders | |
320 | * with the same barrier on another CPU. This prevents two CPUs | |
321 | * clearing the last 2 pending bits, but neither seeing the other's | |
322 | * store when checking if the mask is empty, and missing an empty | |
323 | * mask, which ends with a false positive. | |
324 | */ | |
325 | smp_mb(); | |
2104180a NP |
326 | if (cpumask_empty(&wd_smp_cpus_pending)) { |
327 | unsigned long flags; | |
328 | ||
5dad4ba6 NP |
329 | none_pending: |
330 | /* | |
331 | * Double check under lock because more than one CPU could see | |
332 | * a clear mask with the lockless check after clearing their | |
333 | * pending bits. | |
334 | */ | |
2104180a NP |
335 | wd_smp_lock(&flags); |
336 | if (cpumask_empty(&wd_smp_cpus_pending)) { | |
1f01bf90 | 337 | wd_smp_last_reset_tb = get_tb(); |
2104180a NP |
338 | cpumask_andnot(&wd_smp_cpus_pending, |
339 | &wd_cpus_enabled, | |
340 | &wd_smp_cpus_stuck); | |
341 | } | |
342 | wd_smp_unlock(&flags); | |
343 | } | |
344 | } | |
345 | ||
346 | static void watchdog_timer_interrupt(int cpu) | |
347 | { | |
348 | u64 tb = get_tb(); | |
349 | ||
350 | per_cpu(wd_timer_tb, cpu) = tb; | |
351 | ||
1f01bf90 | 352 | wd_smp_clear_cpu_pending(cpu); |
2104180a NP |
353 | |
354 | if ((s64)(tb - wd_smp_last_reset_tb) >= (s64)wd_smp_panic_timeout_tb) | |
1f01bf90 | 355 | watchdog_smp_panic(cpu); |
e012c499 NP |
356 | |
357 | if (__wd_nmi_output && xchg(&__wd_nmi_output, 0)) { | |
358 | /* | |
359 | * Something has called printk from NMI context. It might be | |
2b461880 | 360 | * stuck, so this triggers a flush that will get that |
e012c499 NP |
361 | * printk output to the console. |
362 | * | |
363 | * See wd_lockup_ipi. | |
364 | */ | |
365 | printk_trigger_flush(); | |
366 | } | |
2104180a NP |
367 | } |
368 | ||
3a96570f | 369 | DEFINE_INTERRUPT_HANDLER_NMI(soft_nmi_interrupt) |
2104180a NP |
370 | { |
371 | unsigned long flags; | |
372 | int cpu = raw_smp_processor_id(); | |
373 | u64 tb; | |
374 | ||
118178e6 NP |
375 | /* should only arrive from kernel, with irqs disabled */ |
376 | WARN_ON_ONCE(!arch_irq_disabled_regs(regs)); | |
377 | ||
2104180a | 378 | if (!cpumask_test_cpu(cpu, &wd_cpus_enabled)) |
3a96570f | 379 | return 0; |
2104180a | 380 | |
04019bf8 NP |
381 | __this_cpu_inc(irq_stat.soft_nmi_irqs); |
382 | ||
2104180a NP |
383 | tb = get_tb(); |
384 | if (tb - per_cpu(wd_timer_tb, cpu) >= wd_panic_timeout_tb) { | |
76521c4b NP |
385 | /* |
386 | * Taking wd_smp_lock here means it is a soft-NMI lock, which | |
387 | * means we can't take any regular or irqsafe spin locks while | |
388 | * holding this lock. This is why timers can't printk while | |
389 | * holding the lock. | |
390 | */ | |
2104180a NP |
391 | wd_smp_lock(&flags); |
392 | if (cpumask_test_cpu(cpu, &wd_smp_cpus_stuck)) { | |
393 | wd_smp_unlock(&flags); | |
118178e6 | 394 | return 0; |
2104180a | 395 | } |
76521c4b NP |
396 | if (!wd_try_report()) { |
397 | wd_smp_unlock(&flags); | |
398 | /* Couldn't report, try again in 100ms */ | |
399 | mtspr(SPRN_DEC, 100 * tb_ticks_per_usec * 1000); | |
400 | return 0; | |
401 | } | |
402 | ||
1f01bf90 | 403 | set_cpu_stuck(cpu); |
2104180a | 404 | |
76521c4b NP |
405 | wd_smp_unlock(&flags); |
406 | ||
4e49226e NP |
407 | pr_emerg("CPU %d self-detected hard LOCKUP @ %pS\n", |
408 | cpu, (void *)regs->nip); | |
409 | pr_emerg("CPU %d TB:%lld, last heartbeat TB:%lld (%lldms ago)\n", | |
410 | cpu, tb, per_cpu(wd_timer_tb, cpu), | |
411 | tb_to_ns(tb - per_cpu(wd_timer_tb, cpu)) / 1000000); | |
2104180a NP |
412 | print_modules(); |
413 | print_irqtrace_events(current); | |
3ba45b7e | 414 | show_regs(regs); |
2104180a | 415 | |
e012c499 NP |
416 | xchg(&__wd_nmi_output, 1); // see wd_lockup_ipi |
417 | ||
2104180a | 418 | if (sysctl_hardlockup_all_cpu_backtrace) |
8d539b84 | 419 | trigger_allbutcpu_cpu_backtrace(cpu); |
2104180a NP |
420 | |
421 | if (hardlockup_panic) | |
422 | nmi_panic(regs, "Hard LOCKUP"); | |
76521c4b NP |
423 | |
424 | wd_end_reporting(); | |
2104180a | 425 | } |
76521c4b NP |
426 | /* |
427 | * We are okay to change DEC in soft_nmi_interrupt because the masked | |
428 | * handler has marked a DEC as pending, so the timer interrupt will be | |
429 | * replayed as soon as local irqs are enabled again. | |
430 | */ | |
2104180a NP |
431 | if (wd_panic_timeout_tb < 0x7fffffff) |
432 | mtspr(SPRN_DEC, wd_panic_timeout_tb); | |
433 | ||
3a96570f | 434 | return 0; |
2104180a NP |
435 | } |
436 | ||
7ae3f6e1 | 437 | static enum hrtimer_restart watchdog_timer_fn(struct hrtimer *hrtimer) |
2104180a | 438 | { |
2104180a NP |
439 | int cpu = smp_processor_id(); |
440 | ||
df95d308 | 441 | if (!(watchdog_enabled & WATCHDOG_HARDLOCKUP_ENABLED)) |
7ae3f6e1 NP |
442 | return HRTIMER_NORESTART; |
443 | ||
444 | if (!cpumask_test_cpu(cpu, &watchdog_cpumask)) | |
445 | return HRTIMER_NORESTART; | |
446 | ||
2104180a NP |
447 | watchdog_timer_interrupt(cpu); |
448 | ||
7ae3f6e1 NP |
449 | hrtimer_forward_now(hrtimer, ms_to_ktime(wd_timer_period_ms)); |
450 | ||
451 | return HRTIMER_RESTART; | |
2104180a NP |
452 | } |
453 | ||
454 | void arch_touch_nmi_watchdog(void) | |
455 | { | |
26c5c6e1 | 456 | unsigned long ticks = tb_ticks_per_usec * wd_timer_period_ms * 1000; |
2104180a | 457 | int cpu = smp_processor_id(); |
5dad4ba6 | 458 | u64 tb; |
2104180a | 459 | |
5dad4ba6 NP |
460 | if (!cpumask_test_cpu(cpu, &watchdog_cpumask)) |
461 | return; | |
462 | ||
463 | tb = get_tb(); | |
80e4d70b NP |
464 | if (tb - per_cpu(wd_timer_tb, cpu) >= ticks) { |
465 | per_cpu(wd_timer_tb, cpu) = tb; | |
1f01bf90 | 466 | wd_smp_clear_cpu_pending(cpu); |
80e4d70b | 467 | } |
2104180a NP |
468 | } |
469 | EXPORT_SYMBOL(arch_touch_nmi_watchdog); | |
470 | ||
7ae3f6e1 | 471 | static void start_watchdog(void *arg) |
2104180a | 472 | { |
7ae3f6e1 NP |
473 | struct hrtimer *hrtimer = this_cpu_ptr(&wd_hrtimer); |
474 | int cpu = smp_processor_id(); | |
96ea91e7 NP |
475 | unsigned long flags; |
476 | ||
2104180a NP |
477 | if (cpumask_test_cpu(cpu, &wd_cpus_enabled)) { |
478 | WARN_ON(1); | |
7ae3f6e1 | 479 | return; |
2104180a NP |
480 | } |
481 | ||
df95d308 | 482 | if (!(watchdog_enabled & WATCHDOG_HARDLOCKUP_ENABLED)) |
7ae3f6e1 | 483 | return; |
2104180a | 484 | |
2104180a | 485 | if (!cpumask_test_cpu(cpu, &watchdog_cpumask)) |
7ae3f6e1 | 486 | return; |
2104180a | 487 | |
96ea91e7 | 488 | wd_smp_lock(&flags); |
2104180a NP |
489 | cpumask_set_cpu(cpu, &wd_cpus_enabled); |
490 | if (cpumask_weight(&wd_cpus_enabled) == 1) { | |
491 | cpumask_set_cpu(cpu, &wd_smp_cpus_pending); | |
492 | wd_smp_last_reset_tb = get_tb(); | |
493 | } | |
96ea91e7 NP |
494 | wd_smp_unlock(&flags); |
495 | ||
7ae3f6e1 | 496 | *this_cpu_ptr(&wd_timer_tb) = get_tb(); |
2104180a | 497 | |
7ae3f6e1 NP |
498 | hrtimer_init(hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); |
499 | hrtimer->function = watchdog_timer_fn; | |
500 | hrtimer_start(hrtimer, ms_to_ktime(wd_timer_period_ms), | |
501 | HRTIMER_MODE_REL_PINNED); | |
2104180a NP |
502 | } |
503 | ||
7ae3f6e1 | 504 | static int start_watchdog_on_cpu(unsigned int cpu) |
2104180a | 505 | { |
7ae3f6e1 NP |
506 | return smp_call_function_single(cpu, start_watchdog, NULL, true); |
507 | } | |
508 | ||
509 | static void stop_watchdog(void *arg) | |
510 | { | |
511 | struct hrtimer *hrtimer = this_cpu_ptr(&wd_hrtimer); | |
512 | int cpu = smp_processor_id(); | |
96ea91e7 NP |
513 | unsigned long flags; |
514 | ||
2104180a | 515 | if (!cpumask_test_cpu(cpu, &wd_cpus_enabled)) |
7ae3f6e1 | 516 | return; /* Can happen in CPU unplug case */ |
2104180a | 517 | |
7ae3f6e1 | 518 | hrtimer_cancel(hrtimer); |
2104180a | 519 | |
96ea91e7 | 520 | wd_smp_lock(&flags); |
2104180a | 521 | cpumask_clear_cpu(cpu, &wd_cpus_enabled); |
96ea91e7 NP |
522 | wd_smp_unlock(&flags); |
523 | ||
1f01bf90 | 524 | wd_smp_clear_cpu_pending(cpu); |
7ae3f6e1 | 525 | } |
2104180a | 526 | |
7ae3f6e1 NP |
527 | static int stop_watchdog_on_cpu(unsigned int cpu) |
528 | { | |
529 | return smp_call_function_single(cpu, stop_watchdog, NULL, true); | |
2104180a NP |
530 | } |
531 | ||
532 | static void watchdog_calc_timeouts(void) | |
533 | { | |
f5e74e83 LD |
534 | u64 threshold = watchdog_thresh; |
535 | ||
536 | #ifdef CONFIG_PPC_PSERIES | |
537 | threshold += (READ_ONCE(wd_timeout_pct) * threshold) / 100; | |
538 | #endif | |
539 | ||
540 | wd_panic_timeout_tb = threshold * ppc_tb_freq; | |
2104180a NP |
541 | |
542 | /* Have the SMP detector trigger a bit later */ | |
543 | wd_smp_panic_timeout_tb = wd_panic_timeout_tb * 3 / 2; | |
544 | ||
545 | /* 2/5 is the factor that the perf based detector uses */ | |
546 | wd_timer_period_ms = watchdog_thresh * 1000 * 2 / 5; | |
547 | } | |
548 | ||
df95d308 | 549 | void watchdog_hardlockup_stop(void) |
2104180a NP |
550 | { |
551 | int cpu; | |
552 | ||
6b9dc480 | 553 | for_each_cpu(cpu, &wd_cpus_enabled) |
7ae3f6e1 | 554 | stop_watchdog_on_cpu(cpu); |
6b9dc480 TG |
555 | } |
556 | ||
df95d308 | 557 | void watchdog_hardlockup_start(void) |
6b9dc480 TG |
558 | { |
559 | int cpu; | |
560 | ||
6b9dc480 TG |
561 | watchdog_calc_timeouts(); |
562 | for_each_cpu_and(cpu, cpu_online_mask, &watchdog_cpumask) | |
7ae3f6e1 | 563 | start_watchdog_on_cpu(cpu); |
2104180a NP |
564 | } |
565 | ||
566 | /* | |
34ddaa3e | 567 | * Invoked from core watchdog init. |
2104180a | 568 | */ |
df95d308 | 569 | int __init watchdog_hardlockup_probe(void) |
2104180a NP |
570 | { |
571 | int err; | |
572 | ||
34ddaa3e TG |
573 | err = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, |
574 | "powerpc/watchdog:online", | |
7ae3f6e1 NP |
575 | start_watchdog_on_cpu, |
576 | stop_watchdog_on_cpu); | |
34ddaa3e | 577 | if (err < 0) { |
d8fa82e0 | 578 | pr_warn("could not be initialized"); |
34ddaa3e TG |
579 | return err; |
580 | } | |
2104180a NP |
581 | return 0; |
582 | } | |
f5e74e83 LD |
583 | |
584 | #ifdef CONFIG_PPC_PSERIES | |
df95d308 | 585 | void watchdog_hardlockup_set_timeout_pct(u64 pct) |
f5e74e83 LD |
586 | { |
587 | pr_info("Set the NMI watchdog timeout factor to %llu%%\n", pct); | |
588 | WRITE_ONCE(wd_timeout_pct, pct); | |
589 | lockup_detector_reconfigure(); | |
590 | } | |
591 | #endif |