Commit | Line | Data |
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14cf11af | 1 | /* |
14cf11af | 2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
fe04b112 | 3 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
14cf11af PM |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | * | |
10 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
11 | * and Paul Mackerras (paulus@samba.org) | |
12 | */ | |
13 | ||
14 | /* | |
15 | * This file handles the architecture-dependent parts of hardware exceptions | |
16 | */ | |
17 | ||
14cf11af PM |
18 | #include <linux/errno.h> |
19 | #include <linux/sched.h> | |
b17b0153 | 20 | #include <linux/sched/debug.h> |
14cf11af PM |
21 | #include <linux/kernel.h> |
22 | #include <linux/mm.h> | |
23 | #include <linux/stddef.h> | |
24 | #include <linux/unistd.h> | |
8dad3f92 | 25 | #include <linux/ptrace.h> |
14cf11af | 26 | #include <linux/user.h> |
14cf11af | 27 | #include <linux/interrupt.h> |
14cf11af | 28 | #include <linux/init.h> |
8a39b05f PG |
29 | #include <linux/extable.h> |
30 | #include <linux/module.h> /* print_modules */ | |
8dad3f92 | 31 | #include <linux/prctl.h> |
14cf11af PM |
32 | #include <linux/delay.h> |
33 | #include <linux/kprobes.h> | |
cc532915 | 34 | #include <linux/kexec.h> |
5474c120 | 35 | #include <linux/backlight.h> |
73c9ceab | 36 | #include <linux/bug.h> |
1eeb66a1 | 37 | #include <linux/kdebug.h> |
76462232 | 38 | #include <linux/ratelimit.h> |
ba12eede | 39 | #include <linux/context_tracking.h> |
14cf11af | 40 | |
80947e7c | 41 | #include <asm/emulated_ops.h> |
14cf11af | 42 | #include <asm/pgtable.h> |
7c0f6ba6 | 43 | #include <linux/uaccess.h> |
7644d581 | 44 | #include <asm/debugfs.h> |
14cf11af | 45 | #include <asm/io.h> |
86417780 PM |
46 | #include <asm/machdep.h> |
47 | #include <asm/rtas.h> | |
f7f6f4fe | 48 | #include <asm/pmc.h> |
14cf11af | 49 | #include <asm/reg.h> |
14cf11af PM |
50 | #ifdef CONFIG_PMAC_BACKLIGHT |
51 | #include <asm/backlight.h> | |
52 | #endif | |
dc1c1ca3 | 53 | #ifdef CONFIG_PPC64 |
86417780 | 54 | #include <asm/firmware.h> |
dc1c1ca3 | 55 | #include <asm/processor.h> |
6ce6c629 | 56 | #include <asm/tm.h> |
dc1c1ca3 | 57 | #endif |
c0ce7d08 | 58 | #include <asm/kexec.h> |
16c57b36 | 59 | #include <asm/ppc-opcode.h> |
cce1f106 | 60 | #include <asm/rio.h> |
ebaeb5ae | 61 | #include <asm/fadump.h> |
ae3a197e | 62 | #include <asm/switch_to.h> |
f54db641 | 63 | #include <asm/tm.h> |
ae3a197e | 64 | #include <asm/debug.h> |
42f5b4ca | 65 | #include <asm/asm-prototypes.h> |
fd7bacbc | 66 | #include <asm/hmi.h> |
4e0e3435 | 67 | #include <sysdev/fsl_pci.h> |
6cc89bad | 68 | #include <asm/kprobes.h> |
dc1c1ca3 | 69 | |
da665885 | 70 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) |
5be3492f AB |
71 | int (*__debugger)(struct pt_regs *regs) __read_mostly; |
72 | int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; | |
73 | int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; | |
74 | int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; | |
75 | int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; | |
9422de3e | 76 | int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; |
5be3492f | 77 | int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; |
14cf11af PM |
78 | |
79 | EXPORT_SYMBOL(__debugger); | |
80 | EXPORT_SYMBOL(__debugger_ipi); | |
81 | EXPORT_SYMBOL(__debugger_bpt); | |
82 | EXPORT_SYMBOL(__debugger_sstep); | |
83 | EXPORT_SYMBOL(__debugger_iabr_match); | |
9422de3e | 84 | EXPORT_SYMBOL(__debugger_break_match); |
14cf11af PM |
85 | EXPORT_SYMBOL(__debugger_fault_handler); |
86 | #endif | |
87 | ||
8b3c34cf MN |
88 | /* Transactional Memory trap debug */ |
89 | #ifdef TM_DEBUG_SW | |
90 | #define TM_DEBUG(x...) printk(KERN_INFO x) | |
91 | #else | |
92 | #define TM_DEBUG(x...) do { } while(0) | |
93 | #endif | |
94 | ||
14cf11af PM |
95 | /* |
96 | * Trap & Exception support | |
97 | */ | |
98 | ||
6031d9d9 | 99 | #ifdef CONFIG_PMAC_BACKLIGHT |
100 | static void pmac_backlight_unblank(void) | |
101 | { | |
102 | mutex_lock(&pmac_backlight_mutex); | |
103 | if (pmac_backlight) { | |
104 | struct backlight_properties *props; | |
105 | ||
106 | props = &pmac_backlight->props; | |
107 | props->brightness = props->max_brightness; | |
108 | props->power = FB_BLANK_UNBLANK; | |
109 | backlight_update_status(pmac_backlight); | |
110 | } | |
111 | mutex_unlock(&pmac_backlight_mutex); | |
112 | } | |
113 | #else | |
114 | static inline void pmac_backlight_unblank(void) { } | |
115 | #endif | |
116 | ||
760ca4dc AB |
117 | static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; |
118 | static int die_owner = -1; | |
119 | static unsigned int die_nest_count; | |
120 | static int die_counter; | |
121 | ||
03465f89 | 122 | static unsigned long oops_begin(struct pt_regs *regs) |
14cf11af | 123 | { |
760ca4dc | 124 | int cpu; |
34c2a14f | 125 | unsigned long flags; |
14cf11af | 126 | |
293e4688 | 127 | oops_enter(); |
128 | ||
760ca4dc AB |
129 | /* racy, but better than risking deadlock. */ |
130 | raw_local_irq_save(flags); | |
131 | cpu = smp_processor_id(); | |
132 | if (!arch_spin_trylock(&die_lock)) { | |
133 | if (cpu == die_owner) | |
134 | /* nested oops. should stop eventually */; | |
135 | else | |
136 | arch_spin_lock(&die_lock); | |
34c2a14f | 137 | } |
760ca4dc AB |
138 | die_nest_count++; |
139 | die_owner = cpu; | |
140 | console_verbose(); | |
141 | bust_spinlocks(1); | |
142 | if (machine_is(powermac)) | |
143 | pmac_backlight_unblank(); | |
144 | return flags; | |
145 | } | |
03465f89 | 146 | NOKPROBE_SYMBOL(oops_begin); |
e8222502 | 147 | |
03465f89 | 148 | static void oops_end(unsigned long flags, struct pt_regs *regs, |
760ca4dc AB |
149 | int signr) |
150 | { | |
14cf11af | 151 | bust_spinlocks(0); |
373d4d09 | 152 | add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); |
760ca4dc | 153 | die_nest_count--; |
58154c8c AB |
154 | oops_exit(); |
155 | printk("\n"); | |
7458e8b2 | 156 | if (!die_nest_count) { |
760ca4dc | 157 | /* Nest count reaches zero, release the lock. */ |
7458e8b2 | 158 | die_owner = -1; |
760ca4dc | 159 | arch_spin_unlock(&die_lock); |
7458e8b2 | 160 | } |
760ca4dc | 161 | raw_local_irq_restore(flags); |
cc532915 | 162 | |
ebaeb5ae MS |
163 | crash_fadump(regs, "die oops"); |
164 | ||
9b00ac06 AB |
165 | /* |
166 | * A system reset (0x100) is a request to dump, so we always send | |
167 | * it through the crashdump code. | |
168 | */ | |
169 | if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) { | |
cc532915 | 170 | crash_kexec(regs); |
9b00ac06 AB |
171 | |
172 | /* | |
173 | * We aren't the primary crash CPU. We need to send it | |
174 | * to a holding pattern to avoid it ending up in the panic | |
175 | * code. | |
176 | */ | |
177 | crash_kexec_secondary(regs); | |
178 | } | |
14cf11af | 179 | |
760ca4dc AB |
180 | if (!signr) |
181 | return; | |
182 | ||
58154c8c AB |
183 | /* |
184 | * While our oops output is serialised by a spinlock, output | |
185 | * from panic() called below can race and corrupt it. If we | |
186 | * know we are going to panic, delay for 1 second so we have a | |
187 | * chance to get clean backtraces from all CPUs that are oopsing. | |
188 | */ | |
189 | if (in_interrupt() || panic_on_oops || !current->pid || | |
190 | is_global_init(current)) { | |
191 | mdelay(MSEC_PER_SEC); | |
192 | } | |
193 | ||
14cf11af PM |
194 | if (in_interrupt()) |
195 | panic("Fatal exception in interrupt"); | |
cea6a4ba | 196 | if (panic_on_oops) |
012c437d | 197 | panic("Fatal exception"); |
760ca4dc AB |
198 | do_exit(signr); |
199 | } | |
03465f89 | 200 | NOKPROBE_SYMBOL(oops_end); |
cea6a4ba | 201 | |
03465f89 | 202 | static int __die(const char *str, struct pt_regs *regs, long err) |
760ca4dc AB |
203 | { |
204 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); | |
2e82ca3c ME |
205 | |
206 | if (IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN)) | |
207 | printk("LE "); | |
208 | else | |
209 | printk("BE "); | |
210 | ||
1c56cd8e ME |
211 | if (IS_ENABLED(CONFIG_PREEMPT)) |
212 | pr_cont("PREEMPT "); | |
213 | ||
214 | if (IS_ENABLED(CONFIG_SMP)) | |
215 | pr_cont("SMP NR_CPUS=%d ", NR_CPUS); | |
216 | ||
e7df0d88 | 217 | if (debug_pagealloc_enabled()) |
72c0d9ee | 218 | pr_cont("DEBUG_PAGEALLOC "); |
1c56cd8e ME |
219 | |
220 | if (IS_ENABLED(CONFIG_NUMA)) | |
221 | pr_cont("NUMA "); | |
222 | ||
72c0d9ee | 223 | pr_cont("%s\n", ppc_md.name ? ppc_md.name : ""); |
760ca4dc AB |
224 | |
225 | if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) | |
226 | return 1; | |
227 | ||
228 | print_modules(); | |
229 | show_regs(regs); | |
14cf11af PM |
230 | |
231 | return 0; | |
232 | } | |
03465f89 | 233 | NOKPROBE_SYMBOL(__die); |
14cf11af | 234 | |
760ca4dc AB |
235 | void die(const char *str, struct pt_regs *regs, long err) |
236 | { | |
6f44b20e NP |
237 | unsigned long flags; |
238 | ||
239 | if (debugger(regs)) | |
240 | return; | |
760ca4dc | 241 | |
6f44b20e | 242 | flags = oops_begin(regs); |
760ca4dc AB |
243 | if (__die(str, regs, err)) |
244 | err = 0; | |
245 | oops_end(flags, regs, err); | |
246 | } | |
15770a13 | 247 | NOKPROBE_SYMBOL(die); |
760ca4dc | 248 | |
25baa35b ON |
249 | void user_single_step_siginfo(struct task_struct *tsk, |
250 | struct pt_regs *regs, siginfo_t *info) | |
251 | { | |
252 | memset(info, 0, sizeof(*info)); | |
253 | info->si_signo = SIGTRAP; | |
254 | info->si_code = TRAP_TRACE; | |
255 | info->si_addr = (void __user *)regs->nip; | |
256 | } | |
257 | ||
14cf11af PM |
258 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) |
259 | { | |
260 | siginfo_t info; | |
d0c3d534 OJ |
261 | const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ |
262 | "at %08lx nip %08lx lr %08lx code %x\n"; | |
263 | const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ | |
264 | "at %016lx nip %016lx lr %016lx code %x\n"; | |
14cf11af PM |
265 | |
266 | if (!user_mode(regs)) { | |
760ca4dc AB |
267 | die("Exception in kernel mode", regs, signr); |
268 | return; | |
269 | } | |
270 | ||
271 | if (show_unhandled_signals && unhandled_signal(current, signr)) { | |
76462232 CD |
272 | printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, |
273 | current->comm, current->pid, signr, | |
274 | addr, regs->nip, regs->link, code); | |
275 | } | |
14cf11af | 276 | |
a3512b2d | 277 | if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) |
9f2f79e3 BH |
278 | local_irq_enable(); |
279 | ||
41ab5266 | 280 | current->thread.trap_nr = code; |
14cf11af PM |
281 | memset(&info, 0, sizeof(info)); |
282 | info.si_signo = signr; | |
283 | info.si_code = code; | |
284 | info.si_addr = (void __user *) addr; | |
285 | force_sig_info(signr, &info, current); | |
14cf11af PM |
286 | } |
287 | ||
14cf11af PM |
288 | void system_reset_exception(struct pt_regs *regs) |
289 | { | |
2b4f3ac5 NP |
290 | /* |
291 | * Avoid crashes in case of nested NMI exceptions. Recoverability | |
292 | * is determined by RI and in_nmi | |
293 | */ | |
294 | bool nested = in_nmi(); | |
295 | if (!nested) | |
296 | nmi_enter(); | |
297 | ||
ca41ad43 NP |
298 | __this_cpu_inc(irq_stat.sreset_irqs); |
299 | ||
14cf11af | 300 | /* See if any machine dependent calls */ |
c902be71 AB |
301 | if (ppc_md.system_reset_exception) { |
302 | if (ppc_md.system_reset_exception(regs)) | |
c4f3b52c | 303 | goto out; |
c902be71 | 304 | } |
14cf11af | 305 | |
8dad3f92 | 306 | die("System Reset", regs, SIGABRT); |
14cf11af | 307 | |
c4f3b52c NP |
308 | out: |
309 | #ifdef CONFIG_PPC_BOOK3S_64 | |
310 | BUG_ON(get_paca()->in_nmi == 0); | |
311 | if (get_paca()->in_nmi > 1) | |
312 | panic("Unrecoverable nested System Reset"); | |
313 | #endif | |
14cf11af PM |
314 | /* Must die if the interrupt is not recoverable */ |
315 | if (!(regs->msr & MSR_RI)) | |
316 | panic("Unrecoverable System Reset"); | |
317 | ||
2b4f3ac5 NP |
318 | if (!nested) |
319 | nmi_exit(); | |
320 | ||
14cf11af PM |
321 | /* What should we do here? We could issue a shutdown or hard reset. */ |
322 | } | |
1e9b4507 | 323 | |
14cf11af PM |
324 | /* |
325 | * I/O accesses can cause machine checks on powermacs. | |
326 | * Check if the NIP corresponds to the address of a sync | |
327 | * instruction for which there is an entry in the exception | |
328 | * table. | |
329 | * Note that the 601 only takes a machine check on TEA | |
330 | * (transfer error ack) signal assertion, and does not | |
331 | * set any of the top 16 bits of SRR1. | |
332 | * -- paulus. | |
333 | */ | |
334 | static inline int check_io_access(struct pt_regs *regs) | |
335 | { | |
68a64357 | 336 | #ifdef CONFIG_PPC32 |
14cf11af PM |
337 | unsigned long msr = regs->msr; |
338 | const struct exception_table_entry *entry; | |
339 | unsigned int *nip = (unsigned int *)regs->nip; | |
340 | ||
341 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
342 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
343 | /* | |
344 | * Check that it's a sync instruction, or somewhere | |
345 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
346 | * As the address is in the exception table | |
347 | * we should be able to read the instr there. | |
348 | * For the debug message, we look at the preceding | |
349 | * load or store. | |
350 | */ | |
ddc6cd0d | 351 | if (*nip == PPC_INST_NOP) |
14cf11af | 352 | nip -= 2; |
ddc6cd0d | 353 | else if (*nip == PPC_INST_ISYNC) |
14cf11af | 354 | --nip; |
ddc6cd0d | 355 | if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) { |
14cf11af PM |
356 | unsigned int rb; |
357 | ||
358 | --nip; | |
359 | rb = (*nip >> 11) & 0x1f; | |
360 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
361 | (*nip & 0x100)? "OUT to": "IN from", | |
362 | regs->gpr[rb] - _IO_BASE, nip); | |
363 | regs->msr |= MSR_RI; | |
61a92f70 | 364 | regs->nip = extable_fixup(entry); |
14cf11af PM |
365 | return 1; |
366 | } | |
367 | } | |
68a64357 | 368 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
369 | return 0; |
370 | } | |
371 | ||
172ae2e7 | 372 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
14cf11af PM |
373 | /* On 4xx, the reason for the machine check or program exception |
374 | is in the ESR. */ | |
375 | #define get_reason(regs) ((regs)->dsisr) | |
14cf11af PM |
376 | #define REASON_FP ESR_FP |
377 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) | |
378 | #define REASON_PRIVILEGED ESR_PPR | |
379 | #define REASON_TRAP ESR_PTR | |
380 | ||
381 | /* single-step stuff */ | |
51ae8d4a BB |
382 | #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) |
383 | #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) | |
14cf11af PM |
384 | |
385 | #else | |
386 | /* On non-4xx, the reason for the machine check or program | |
387 | exception is in the MSR. */ | |
388 | #define get_reason(regs) ((regs)->msr) | |
d30a5a52 ME |
389 | #define REASON_TM SRR1_PROGTM |
390 | #define REASON_FP SRR1_PROGFPE | |
391 | #define REASON_ILLEGAL SRR1_PROGILL | |
392 | #define REASON_PRIVILEGED SRR1_PROGPRIV | |
393 | #define REASON_TRAP SRR1_PROGTRAP | |
14cf11af PM |
394 | |
395 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
396 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
397 | #endif | |
398 | ||
0d0935b3 | 399 | #if defined(CONFIG_E500) |
fe04b112 SW |
400 | int machine_check_e500mc(struct pt_regs *regs) |
401 | { | |
402 | unsigned long mcsr = mfspr(SPRN_MCSR); | |
403 | unsigned long reason = mcsr; | |
404 | int recoverable = 1; | |
405 | ||
82a9a480 | 406 | if (reason & MCSR_LD) { |
cce1f106 SX |
407 | recoverable = fsl_rio_mcheck_exception(regs); |
408 | if (recoverable == 1) | |
409 | goto silent_out; | |
410 | } | |
411 | ||
fe04b112 SW |
412 | printk("Machine check in kernel mode.\n"); |
413 | printk("Caused by (from MCSR=%lx): ", reason); | |
414 | ||
415 | if (reason & MCSR_MCP) | |
416 | printk("Machine Check Signal\n"); | |
417 | ||
418 | if (reason & MCSR_ICPERR) { | |
419 | printk("Instruction Cache Parity Error\n"); | |
420 | ||
421 | /* | |
422 | * This is recoverable by invalidating the i-cache. | |
423 | */ | |
424 | mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); | |
425 | while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) | |
426 | ; | |
427 | ||
428 | /* | |
429 | * This will generally be accompanied by an instruction | |
430 | * fetch error report -- only treat MCSR_IF as fatal | |
431 | * if it wasn't due to an L1 parity error. | |
432 | */ | |
433 | reason &= ~MCSR_IF; | |
434 | } | |
435 | ||
436 | if (reason & MCSR_DCPERR_MC) { | |
437 | printk("Data Cache Parity Error\n"); | |
37caf9f2 KG |
438 | |
439 | /* | |
440 | * In write shadow mode we auto-recover from the error, but it | |
441 | * may still get logged and cause a machine check. We should | |
442 | * only treat the non-write shadow case as non-recoverable. | |
443 | */ | |
444 | if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) | |
445 | recoverable = 0; | |
fe04b112 SW |
446 | } |
447 | ||
448 | if (reason & MCSR_L2MMU_MHIT) { | |
449 | printk("Hit on multiple TLB entries\n"); | |
450 | recoverable = 0; | |
451 | } | |
452 | ||
453 | if (reason & MCSR_NMI) | |
454 | printk("Non-maskable interrupt\n"); | |
455 | ||
456 | if (reason & MCSR_IF) { | |
457 | printk("Instruction Fetch Error Report\n"); | |
458 | recoverable = 0; | |
459 | } | |
460 | ||
461 | if (reason & MCSR_LD) { | |
462 | printk("Load Error Report\n"); | |
463 | recoverable = 0; | |
464 | } | |
465 | ||
466 | if (reason & MCSR_ST) { | |
467 | printk("Store Error Report\n"); | |
468 | recoverable = 0; | |
469 | } | |
470 | ||
471 | if (reason & MCSR_LDG) { | |
472 | printk("Guarded Load Error Report\n"); | |
473 | recoverable = 0; | |
474 | } | |
475 | ||
476 | if (reason & MCSR_TLBSYNC) | |
477 | printk("Simultaneous tlbsync operations\n"); | |
478 | ||
479 | if (reason & MCSR_BSL2_ERR) { | |
480 | printk("Level 2 Cache Error\n"); | |
481 | recoverable = 0; | |
482 | } | |
483 | ||
484 | if (reason & MCSR_MAV) { | |
485 | u64 addr; | |
486 | ||
487 | addr = mfspr(SPRN_MCAR); | |
488 | addr |= (u64)mfspr(SPRN_MCARU) << 32; | |
489 | ||
490 | printk("Machine Check %s Address: %#llx\n", | |
491 | reason & MCSR_MEA ? "Effective" : "Physical", addr); | |
492 | } | |
493 | ||
cce1f106 | 494 | silent_out: |
fe04b112 SW |
495 | mtspr(SPRN_MCSR, mcsr); |
496 | return mfspr(SPRN_MCSR) == 0 && recoverable; | |
497 | } | |
498 | ||
47c0bd1a BH |
499 | int machine_check_e500(struct pt_regs *regs) |
500 | { | |
42bff234 | 501 | unsigned long reason = mfspr(SPRN_MCSR); |
47c0bd1a | 502 | |
cce1f106 SX |
503 | if (reason & MCSR_BUS_RBERR) { |
504 | if (fsl_rio_mcheck_exception(regs)) | |
505 | return 1; | |
4e0e3435 HJ |
506 | if (fsl_pci_mcheck_exception(regs)) |
507 | return 1; | |
cce1f106 SX |
508 | } |
509 | ||
14cf11af PM |
510 | printk("Machine check in kernel mode.\n"); |
511 | printk("Caused by (from MCSR=%lx): ", reason); | |
512 | ||
513 | if (reason & MCSR_MCP) | |
514 | printk("Machine Check Signal\n"); | |
515 | if (reason & MCSR_ICPERR) | |
516 | printk("Instruction Cache Parity Error\n"); | |
517 | if (reason & MCSR_DCP_PERR) | |
518 | printk("Data Cache Push Parity Error\n"); | |
519 | if (reason & MCSR_DCPERR) | |
520 | printk("Data Cache Parity Error\n"); | |
14cf11af PM |
521 | if (reason & MCSR_BUS_IAERR) |
522 | printk("Bus - Instruction Address Error\n"); | |
523 | if (reason & MCSR_BUS_RAERR) | |
524 | printk("Bus - Read Address Error\n"); | |
525 | if (reason & MCSR_BUS_WAERR) | |
526 | printk("Bus - Write Address Error\n"); | |
527 | if (reason & MCSR_BUS_IBERR) | |
528 | printk("Bus - Instruction Data Error\n"); | |
529 | if (reason & MCSR_BUS_RBERR) | |
530 | printk("Bus - Read Data Bus Error\n"); | |
531 | if (reason & MCSR_BUS_WBERR) | |
c1528339 | 532 | printk("Bus - Write Data Bus Error\n"); |
14cf11af PM |
533 | if (reason & MCSR_BUS_IPERR) |
534 | printk("Bus - Instruction Parity Error\n"); | |
535 | if (reason & MCSR_BUS_RPERR) | |
536 | printk("Bus - Read Parity Error\n"); | |
47c0bd1a BH |
537 | |
538 | return 0; | |
539 | } | |
4490c06b KG |
540 | |
541 | int machine_check_generic(struct pt_regs *regs) | |
542 | { | |
543 | return 0; | |
544 | } | |
47c0bd1a BH |
545 | #elif defined(CONFIG_E200) |
546 | int machine_check_e200(struct pt_regs *regs) | |
547 | { | |
42bff234 | 548 | unsigned long reason = mfspr(SPRN_MCSR); |
47c0bd1a | 549 | |
14cf11af PM |
550 | printk("Machine check in kernel mode.\n"); |
551 | printk("Caused by (from MCSR=%lx): ", reason); | |
552 | ||
553 | if (reason & MCSR_MCP) | |
554 | printk("Machine Check Signal\n"); | |
555 | if (reason & MCSR_CP_PERR) | |
556 | printk("Cache Push Parity Error\n"); | |
557 | if (reason & MCSR_CPERR) | |
558 | printk("Cache Parity Error\n"); | |
559 | if (reason & MCSR_EXCP_ERR) | |
560 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | |
561 | if (reason & MCSR_BUS_IRERR) | |
562 | printk("Bus - Read Bus Error on instruction fetch\n"); | |
563 | if (reason & MCSR_BUS_DRERR) | |
564 | printk("Bus - Read Bus Error on data load\n"); | |
565 | if (reason & MCSR_BUS_WRERR) | |
566 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | |
47c0bd1a BH |
567 | |
568 | return 0; | |
569 | } | |
7f3f819e | 570 | #elif defined(CONFIG_PPC32) |
47c0bd1a BH |
571 | int machine_check_generic(struct pt_regs *regs) |
572 | { | |
42bff234 | 573 | unsigned long reason = regs->msr; |
47c0bd1a | 574 | |
14cf11af PM |
575 | printk("Machine check in kernel mode.\n"); |
576 | printk("Caused by (from SRR1=%lx): ", reason); | |
577 | switch (reason & 0x601F0000) { | |
578 | case 0x80000: | |
579 | printk("Machine check signal\n"); | |
580 | break; | |
581 | case 0: /* for 601 */ | |
582 | case 0x40000: | |
583 | case 0x140000: /* 7450 MSS error and TEA */ | |
584 | printk("Transfer error ack signal\n"); | |
585 | break; | |
586 | case 0x20000: | |
587 | printk("Data parity error signal\n"); | |
588 | break; | |
589 | case 0x10000: | |
590 | printk("Address parity error signal\n"); | |
591 | break; | |
592 | case 0x20000000: | |
593 | printk("L1 Data Cache error\n"); | |
594 | break; | |
595 | case 0x40000000: | |
596 | printk("L1 Instruction Cache error\n"); | |
597 | break; | |
598 | case 0x00100000: | |
599 | printk("L2 data cache parity error\n"); | |
600 | break; | |
601 | default: | |
602 | printk("Unknown values in msr\n"); | |
603 | } | |
75918a4b OJ |
604 | return 0; |
605 | } | |
47c0bd1a | 606 | #endif /* everything else */ |
75918a4b OJ |
607 | |
608 | void machine_check_exception(struct pt_regs *regs) | |
609 | { | |
ba12eede | 610 | enum ctx_state prev_state = exception_enter(); |
75918a4b OJ |
611 | int recover = 0; |
612 | ||
f886f0f6 NP |
613 | /* 64s accounts the mce in machine_check_early when in HVMODE */ |
614 | if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64) || !cpu_has_feature(CPU_FTR_HVMODE)) | |
615 | __this_cpu_inc(irq_stat.mce_exceptions); | |
89713ed1 | 616 | |
d93b0ac0 MS |
617 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); |
618 | ||
47c0bd1a BH |
619 | /* See if any machine dependent calls. In theory, we would want |
620 | * to call the CPU first, and call the ppc_md. one if the CPU | |
621 | * one returns a positive number. However there is existing code | |
622 | * that assumes the board gets a first chance, so let's keep it | |
623 | * that way for now and fix things later. --BenH. | |
624 | */ | |
75918a4b OJ |
625 | if (ppc_md.machine_check_exception) |
626 | recover = ppc_md.machine_check_exception(regs); | |
47c0bd1a BH |
627 | else if (cur_cpu_spec->machine_check) |
628 | recover = cur_cpu_spec->machine_check(regs); | |
75918a4b | 629 | |
47c0bd1a | 630 | if (recover > 0) |
ba12eede | 631 | goto bail; |
75918a4b | 632 | |
a443506b | 633 | if (debugger_fault_handler(regs)) |
ba12eede | 634 | goto bail; |
75918a4b OJ |
635 | |
636 | if (check_io_access(regs)) | |
ba12eede | 637 | goto bail; |
75918a4b | 638 | |
8dad3f92 | 639 | die("Machine check", regs, SIGBUS); |
14cf11af PM |
640 | |
641 | /* Must die if the interrupt is not recoverable */ | |
642 | if (!(regs->msr & MSR_RI)) | |
643 | panic("Unrecoverable Machine check"); | |
ba12eede LZ |
644 | |
645 | bail: | |
646 | exception_exit(prev_state); | |
14cf11af PM |
647 | } |
648 | ||
649 | void SMIException(struct pt_regs *regs) | |
650 | { | |
651 | die("System Management Interrupt", regs, SIGABRT); | |
652 | } | |
653 | ||
0869b6fd MS |
654 | void handle_hmi_exception(struct pt_regs *regs) |
655 | { | |
656 | struct pt_regs *old_regs; | |
657 | ||
658 | old_regs = set_irq_regs(regs); | |
659 | irq_enter(); | |
660 | ||
661 | if (ppc_md.handle_hmi_exception) | |
662 | ppc_md.handle_hmi_exception(regs); | |
663 | ||
664 | irq_exit(); | |
665 | set_irq_regs(old_regs); | |
666 | } | |
667 | ||
dc1c1ca3 | 668 | void unknown_exception(struct pt_regs *regs) |
14cf11af | 669 | { |
ba12eede LZ |
670 | enum ctx_state prev_state = exception_enter(); |
671 | ||
14cf11af PM |
672 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", |
673 | regs->nip, regs->msr, regs->trap); | |
674 | ||
675 | _exception(SIGTRAP, regs, 0, 0); | |
ba12eede LZ |
676 | |
677 | exception_exit(prev_state); | |
14cf11af PM |
678 | } |
679 | ||
dc1c1ca3 | 680 | void instruction_breakpoint_exception(struct pt_regs *regs) |
14cf11af | 681 | { |
ba12eede LZ |
682 | enum ctx_state prev_state = exception_enter(); |
683 | ||
14cf11af PM |
684 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, |
685 | 5, SIGTRAP) == NOTIFY_STOP) | |
ba12eede | 686 | goto bail; |
14cf11af | 687 | if (debugger_iabr_match(regs)) |
ba12eede | 688 | goto bail; |
14cf11af | 689 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
ba12eede LZ |
690 | |
691 | bail: | |
692 | exception_exit(prev_state); | |
14cf11af PM |
693 | } |
694 | ||
695 | void RunModeException(struct pt_regs *regs) | |
696 | { | |
697 | _exception(SIGTRAP, regs, 0, 0); | |
698 | } | |
699 | ||
03465f89 | 700 | void single_step_exception(struct pt_regs *regs) |
14cf11af | 701 | { |
ba12eede LZ |
702 | enum ctx_state prev_state = exception_enter(); |
703 | ||
2538c2d0 | 704 | clear_single_step(regs); |
14cf11af | 705 | |
6cc89bad NR |
706 | if (kprobe_post_handler(regs)) |
707 | return; | |
708 | ||
14cf11af PM |
709 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, |
710 | 5, SIGTRAP) == NOTIFY_STOP) | |
ba12eede | 711 | goto bail; |
14cf11af | 712 | if (debugger_sstep(regs)) |
ba12eede | 713 | goto bail; |
14cf11af PM |
714 | |
715 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
ba12eede LZ |
716 | |
717 | bail: | |
718 | exception_exit(prev_state); | |
14cf11af | 719 | } |
03465f89 | 720 | NOKPROBE_SYMBOL(single_step_exception); |
14cf11af PM |
721 | |
722 | /* | |
723 | * After we have successfully emulated an instruction, we have to | |
724 | * check if the instruction was being single-stepped, and if so, | |
725 | * pretend we got a single-step exception. This was pointed out | |
726 | * by Kumar Gala. -- paulus | |
727 | */ | |
8dad3f92 | 728 | static void emulate_single_step(struct pt_regs *regs) |
14cf11af | 729 | { |
2538c2d0 P |
730 | if (single_stepping(regs)) |
731 | single_step_exception(regs); | |
14cf11af PM |
732 | } |
733 | ||
5fad293b | 734 | static inline int __parse_fpscr(unsigned long fpscr) |
dc1c1ca3 | 735 | { |
5fad293b | 736 | int ret = 0; |
dc1c1ca3 SR |
737 | |
738 | /* Invalid operation */ | |
739 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) | |
5fad293b | 740 | ret = FPE_FLTINV; |
dc1c1ca3 SR |
741 | |
742 | /* Overflow */ | |
743 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) | |
5fad293b | 744 | ret = FPE_FLTOVF; |
dc1c1ca3 SR |
745 | |
746 | /* Underflow */ | |
747 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) | |
5fad293b | 748 | ret = FPE_FLTUND; |
dc1c1ca3 SR |
749 | |
750 | /* Divide by zero */ | |
751 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) | |
5fad293b | 752 | ret = FPE_FLTDIV; |
dc1c1ca3 SR |
753 | |
754 | /* Inexact result */ | |
755 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) | |
5fad293b KG |
756 | ret = FPE_FLTRES; |
757 | ||
758 | return ret; | |
759 | } | |
760 | ||
761 | static void parse_fpe(struct pt_regs *regs) | |
762 | { | |
763 | int code = 0; | |
764 | ||
765 | flush_fp_to_thread(current); | |
766 | ||
de79f7b9 | 767 | code = __parse_fpscr(current->thread.fp_state.fpscr); |
dc1c1ca3 SR |
768 | |
769 | _exception(SIGFPE, regs, code, regs->nip); | |
770 | } | |
771 | ||
772 | /* | |
773 | * Illegal instruction emulation support. Originally written to | |
14cf11af PM |
774 | * provide the PVR to user applications using the mfspr rd, PVR. |
775 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
776 | * memory access caused an access fault. Return zero on success. | |
777 | * | |
778 | * There are a couple of ways to do this, either "decode" the instruction | |
779 | * or directly match lots of bits. In this case, matching lots of | |
780 | * bits is faster and easier. | |
86417780 | 781 | * |
14cf11af | 782 | */ |
14cf11af PM |
783 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) |
784 | { | |
785 | u8 rT = (instword >> 21) & 0x1f; | |
786 | u8 rA = (instword >> 16) & 0x1f; | |
787 | u8 NB_RB = (instword >> 11) & 0x1f; | |
788 | u32 num_bytes; | |
789 | unsigned long EA; | |
790 | int pos = 0; | |
791 | ||
792 | /* Early out if we are an invalid form of lswx */ | |
16c57b36 | 793 | if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) |
14cf11af PM |
794 | if ((rT == rA) || (rT == NB_RB)) |
795 | return -EINVAL; | |
796 | ||
797 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
798 | ||
16c57b36 KG |
799 | switch (instword & PPC_INST_STRING_MASK) { |
800 | case PPC_INST_LSWX: | |
801 | case PPC_INST_STSWX: | |
14cf11af PM |
802 | EA += NB_RB; |
803 | num_bytes = regs->xer & 0x7f; | |
804 | break; | |
16c57b36 KG |
805 | case PPC_INST_LSWI: |
806 | case PPC_INST_STSWI: | |
14cf11af PM |
807 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; |
808 | break; | |
809 | default: | |
810 | return -EINVAL; | |
811 | } | |
812 | ||
813 | while (num_bytes != 0) | |
814 | { | |
815 | u8 val; | |
816 | u32 shift = 8 * (3 - (pos & 0x3)); | |
817 | ||
80aa0fb4 JY |
818 | /* if process is 32-bit, clear upper 32 bits of EA */ |
819 | if ((regs->msr & MSR_64BIT) == 0) | |
820 | EA &= 0xFFFFFFFF; | |
821 | ||
16c57b36 KG |
822 | switch ((instword & PPC_INST_STRING_MASK)) { |
823 | case PPC_INST_LSWX: | |
824 | case PPC_INST_LSWI: | |
14cf11af PM |
825 | if (get_user(val, (u8 __user *)EA)) |
826 | return -EFAULT; | |
827 | /* first time updating this reg, | |
828 | * zero it out */ | |
829 | if (pos == 0) | |
830 | regs->gpr[rT] = 0; | |
831 | regs->gpr[rT] |= val << shift; | |
832 | break; | |
16c57b36 KG |
833 | case PPC_INST_STSWI: |
834 | case PPC_INST_STSWX: | |
14cf11af PM |
835 | val = regs->gpr[rT] >> shift; |
836 | if (put_user(val, (u8 __user *)EA)) | |
837 | return -EFAULT; | |
838 | break; | |
839 | } | |
840 | /* move EA to next address */ | |
841 | EA += 1; | |
842 | num_bytes--; | |
843 | ||
844 | /* manage our position within the register */ | |
845 | if (++pos == 4) { | |
846 | pos = 0; | |
847 | if (++rT == 32) | |
848 | rT = 0; | |
849 | } | |
850 | } | |
851 | ||
852 | return 0; | |
853 | } | |
854 | ||
c3412dcb WS |
855 | static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) |
856 | { | |
857 | u32 ra,rs; | |
858 | unsigned long tmp; | |
859 | ||
860 | ra = (instword >> 16) & 0x1f; | |
861 | rs = (instword >> 21) & 0x1f; | |
862 | ||
863 | tmp = regs->gpr[rs]; | |
864 | tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); | |
865 | tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); | |
866 | tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; | |
867 | regs->gpr[ra] = tmp; | |
868 | ||
869 | return 0; | |
870 | } | |
871 | ||
c1469f13 KG |
872 | static int emulate_isel(struct pt_regs *regs, u32 instword) |
873 | { | |
874 | u8 rT = (instword >> 21) & 0x1f; | |
875 | u8 rA = (instword >> 16) & 0x1f; | |
876 | u8 rB = (instword >> 11) & 0x1f; | |
877 | u8 BC = (instword >> 6) & 0x1f; | |
878 | u8 bit; | |
879 | unsigned long tmp; | |
880 | ||
881 | tmp = (rA == 0) ? 0 : regs->gpr[rA]; | |
882 | bit = (regs->ccr >> (31 - BC)) & 0x1; | |
883 | ||
884 | regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; | |
885 | ||
886 | return 0; | |
887 | } | |
888 | ||
6ce6c629 MN |
889 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
890 | static inline bool tm_abort_check(struct pt_regs *regs, int cause) | |
891 | { | |
892 | /* If we're emulating a load/store in an active transaction, we cannot | |
893 | * emulate it as the kernel operates in transaction suspended context. | |
894 | * We need to abort the transaction. This creates a persistent TM | |
895 | * abort so tell the user what caused it with a new code. | |
896 | */ | |
897 | if (MSR_TM_TRANSACTIONAL(regs->msr)) { | |
898 | tm_enable(); | |
899 | tm_abort(cause); | |
900 | return true; | |
901 | } | |
902 | return false; | |
903 | } | |
904 | #else | |
905 | static inline bool tm_abort_check(struct pt_regs *regs, int reason) | |
906 | { | |
907 | return false; | |
908 | } | |
909 | #endif | |
910 | ||
14cf11af PM |
911 | static int emulate_instruction(struct pt_regs *regs) |
912 | { | |
913 | u32 instword; | |
914 | u32 rd; | |
915 | ||
4288e343 | 916 | if (!user_mode(regs)) |
14cf11af PM |
917 | return -EINVAL; |
918 | CHECK_FULL_REGS(regs); | |
919 | ||
920 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
921 | return -EFAULT; | |
922 | ||
923 | /* Emulate the mfspr rD, PVR. */ | |
16c57b36 | 924 | if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { |
eecff81d | 925 | PPC_WARN_EMULATED(mfpvr, regs); |
14cf11af PM |
926 | rd = (instword >> 21) & 0x1f; |
927 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
928 | return 0; | |
929 | } | |
930 | ||
931 | /* Emulating the dcba insn is just a no-op. */ | |
80947e7c | 932 | if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { |
eecff81d | 933 | PPC_WARN_EMULATED(dcba, regs); |
14cf11af | 934 | return 0; |
80947e7c | 935 | } |
14cf11af PM |
936 | |
937 | /* Emulate the mcrxr insn. */ | |
16c57b36 | 938 | if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { |
86417780 | 939 | int shift = (instword >> 21) & 0x1c; |
14cf11af PM |
940 | unsigned long msk = 0xf0000000UL >> shift; |
941 | ||
eecff81d | 942 | PPC_WARN_EMULATED(mcrxr, regs); |
14cf11af PM |
943 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); |
944 | regs->xer &= ~0xf0000000UL; | |
945 | return 0; | |
946 | } | |
947 | ||
948 | /* Emulate load/store string insn. */ | |
80947e7c | 949 | if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { |
6ce6c629 MN |
950 | if (tm_abort_check(regs, |
951 | TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) | |
952 | return -EINVAL; | |
eecff81d | 953 | PPC_WARN_EMULATED(string, regs); |
14cf11af | 954 | return emulate_string_inst(regs, instword); |
80947e7c | 955 | } |
14cf11af | 956 | |
c3412dcb | 957 | /* Emulate the popcntb (Population Count Bytes) instruction. */ |
16c57b36 | 958 | if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { |
eecff81d | 959 | PPC_WARN_EMULATED(popcntb, regs); |
c3412dcb WS |
960 | return emulate_popcntb_inst(regs, instword); |
961 | } | |
962 | ||
c1469f13 | 963 | /* Emulate isel (Integer Select) instruction */ |
16c57b36 | 964 | if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { |
eecff81d | 965 | PPC_WARN_EMULATED(isel, regs); |
c1469f13 KG |
966 | return emulate_isel(regs, instword); |
967 | } | |
968 | ||
9863c28a JY |
969 | /* Emulate sync instruction variants */ |
970 | if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) { | |
971 | PPC_WARN_EMULATED(sync, regs); | |
972 | asm volatile("sync"); | |
973 | return 0; | |
974 | } | |
975 | ||
efcac658 AK |
976 | #ifdef CONFIG_PPC64 |
977 | /* Emulate the mfspr rD, DSCR. */ | |
73d2fb75 AB |
978 | if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == |
979 | PPC_INST_MFSPR_DSCR_USER) || | |
980 | ((instword & PPC_INST_MFSPR_DSCR_MASK) == | |
981 | PPC_INST_MFSPR_DSCR)) && | |
efcac658 AK |
982 | cpu_has_feature(CPU_FTR_DSCR)) { |
983 | PPC_WARN_EMULATED(mfdscr, regs); | |
984 | rd = (instword >> 21) & 0x1f; | |
985 | regs->gpr[rd] = mfspr(SPRN_DSCR); | |
986 | return 0; | |
987 | } | |
988 | /* Emulate the mtspr DSCR, rD. */ | |
73d2fb75 AB |
989 | if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == |
990 | PPC_INST_MTSPR_DSCR_USER) || | |
991 | ((instword & PPC_INST_MTSPR_DSCR_MASK) == | |
992 | PPC_INST_MTSPR_DSCR)) && | |
efcac658 AK |
993 | cpu_has_feature(CPU_FTR_DSCR)) { |
994 | PPC_WARN_EMULATED(mtdscr, regs); | |
995 | rd = (instword >> 21) & 0x1f; | |
00ca0de0 | 996 | current->thread.dscr = regs->gpr[rd]; |
efcac658 | 997 | current->thread.dscr_inherit = 1; |
00ca0de0 | 998 | mtspr(SPRN_DSCR, current->thread.dscr); |
efcac658 AK |
999 | return 0; |
1000 | } | |
1001 | #endif | |
1002 | ||
14cf11af PM |
1003 | return -EINVAL; |
1004 | } | |
1005 | ||
73c9ceab | 1006 | int is_valid_bugaddr(unsigned long addr) |
14cf11af | 1007 | { |
73c9ceab | 1008 | return is_kernel_addr(addr); |
14cf11af PM |
1009 | } |
1010 | ||
3a3b5aa6 KH |
1011 | #ifdef CONFIG_MATH_EMULATION |
1012 | static int emulate_math(struct pt_regs *regs) | |
1013 | { | |
1014 | int ret; | |
1015 | extern int do_mathemu(struct pt_regs *regs); | |
1016 | ||
1017 | ret = do_mathemu(regs); | |
1018 | if (ret >= 0) | |
1019 | PPC_WARN_EMULATED(math, regs); | |
1020 | ||
1021 | switch (ret) { | |
1022 | case 0: | |
1023 | emulate_single_step(regs); | |
1024 | return 0; | |
1025 | case 1: { | |
1026 | int code = 0; | |
de79f7b9 | 1027 | code = __parse_fpscr(current->thread.fp_state.fpscr); |
3a3b5aa6 KH |
1028 | _exception(SIGFPE, regs, code, regs->nip); |
1029 | return 0; | |
1030 | } | |
1031 | case -EFAULT: | |
1032 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1033 | return 0; | |
1034 | } | |
1035 | ||
1036 | return -1; | |
1037 | } | |
1038 | #else | |
1039 | static inline int emulate_math(struct pt_regs *regs) { return -1; } | |
1040 | #endif | |
1041 | ||
03465f89 | 1042 | void program_check_exception(struct pt_regs *regs) |
14cf11af | 1043 | { |
ba12eede | 1044 | enum ctx_state prev_state = exception_enter(); |
14cf11af | 1045 | unsigned int reason = get_reason(regs); |
14cf11af | 1046 | |
aa42c69c | 1047 | /* We can now get here via a FP Unavailable exception if the core |
04903a30 | 1048 | * has no FPU, in that case the reason flags will be 0 */ |
14cf11af | 1049 | |
dc1c1ca3 SR |
1050 | if (reason & REASON_FP) { |
1051 | /* IEEE FP exception */ | |
1052 | parse_fpe(regs); | |
ba12eede | 1053 | goto bail; |
8dad3f92 PM |
1054 | } |
1055 | if (reason & REASON_TRAP) { | |
a4c3f909 | 1056 | unsigned long bugaddr; |
ba797b28 JW |
1057 | /* Debugger is first in line to stop recursive faults in |
1058 | * rcu_lock, notify_die, or atomic_notifier_call_chain */ | |
1059 | if (debugger_bpt(regs)) | |
ba12eede | 1060 | goto bail; |
ba797b28 | 1061 | |
6cc89bad NR |
1062 | if (kprobe_handler(regs)) |
1063 | goto bail; | |
1064 | ||
14cf11af | 1065 | /* trap exception */ |
dc1c1ca3 SR |
1066 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
1067 | == NOTIFY_STOP) | |
ba12eede | 1068 | goto bail; |
73c9ceab | 1069 | |
a4c3f909 BS |
1070 | bugaddr = regs->nip; |
1071 | /* | |
1072 | * Fixup bugaddr for BUG_ON() in real mode | |
1073 | */ | |
1074 | if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) | |
1075 | bugaddr += PAGE_OFFSET; | |
1076 | ||
73c9ceab | 1077 | if (!(regs->msr & MSR_PR) && /* not user-mode */ |
a4c3f909 | 1078 | report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { |
14cf11af | 1079 | regs->nip += 4; |
ba12eede | 1080 | goto bail; |
14cf11af | 1081 | } |
8dad3f92 | 1082 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
ba12eede | 1083 | goto bail; |
8dad3f92 | 1084 | } |
bc2a9408 MN |
1085 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1086 | if (reason & REASON_TM) { | |
1087 | /* This is a TM "Bad Thing Exception" program check. | |
1088 | * This occurs when: | |
1089 | * - An rfid/hrfid/mtmsrd attempts to cause an illegal | |
1090 | * transition in TM states. | |
1091 | * - A trechkpt is attempted when transactional. | |
1092 | * - A treclaim is attempted when non transactional. | |
1093 | * - A tend is illegally attempted. | |
1094 | * - writing a TM SPR when transactional. | |
1095 | */ | |
1096 | if (!user_mode(regs) && | |
1097 | report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { | |
1098 | regs->nip += 4; | |
ba12eede | 1099 | goto bail; |
bc2a9408 MN |
1100 | } |
1101 | /* If usermode caused this, it's done something illegal and | |
1102 | * gets a SIGILL slap on the wrist. We call it an illegal | |
1103 | * operand to distinguish from the instruction just being bad | |
1104 | * (e.g. executing a 'tend' on a CPU without TM!); it's an | |
1105 | * illegal /placement/ of a valid instruction. | |
1106 | */ | |
1107 | if (user_mode(regs)) { | |
1108 | _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); | |
ba12eede | 1109 | goto bail; |
bc2a9408 MN |
1110 | } else { |
1111 | printk(KERN_EMERG "Unexpected TM Bad Thing exception " | |
1112 | "at %lx (msr 0x%x)\n", regs->nip, reason); | |
1113 | die("Unrecoverable exception", regs, SIGABRT); | |
1114 | } | |
1115 | } | |
1116 | #endif | |
8dad3f92 | 1117 | |
b3f6a459 ME |
1118 | /* |
1119 | * If we took the program check in the kernel skip down to sending a | |
1120 | * SIGILL. The subsequent cases all relate to emulating instructions | |
1121 | * which we should only do for userspace. We also do not want to enable | |
1122 | * interrupts for kernel faults because that might lead to further | |
1123 | * faults, and loose the context of the original exception. | |
1124 | */ | |
1125 | if (!user_mode(regs)) | |
1126 | goto sigill; | |
1127 | ||
a3512b2d BH |
1128 | /* We restore the interrupt state now */ |
1129 | if (!arch_irq_disabled_regs(regs)) | |
1130 | local_irq_enable(); | |
cd8a5673 | 1131 | |
04903a30 KG |
1132 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, |
1133 | * but there seems to be a hardware bug on the 405GP (RevD) | |
1134 | * that means ESR is sometimes set incorrectly - either to | |
1135 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
1136 | * hardware people - not sure if it can happen on any illegal | |
1137 | * instruction or only on FP instructions, whether there is a | |
4e63f8ed BH |
1138 | * pattern to occurrences etc. -dgibson 31/Mar/2003 |
1139 | */ | |
3a3b5aa6 | 1140 | if (!emulate_math(regs)) |
ba12eede | 1141 | goto bail; |
04903a30 | 1142 | |
8dad3f92 PM |
1143 | /* Try to emulate it if we should. */ |
1144 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
14cf11af PM |
1145 | switch (emulate_instruction(regs)) { |
1146 | case 0: | |
1147 | regs->nip += 4; | |
1148 | emulate_single_step(regs); | |
ba12eede | 1149 | goto bail; |
14cf11af PM |
1150 | case -EFAULT: |
1151 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
ba12eede | 1152 | goto bail; |
14cf11af PM |
1153 | } |
1154 | } | |
8dad3f92 | 1155 | |
b3f6a459 | 1156 | sigill: |
8dad3f92 PM |
1157 | if (reason & REASON_PRIVILEGED) |
1158 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1159 | else | |
1160 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
ba12eede LZ |
1161 | |
1162 | bail: | |
1163 | exception_exit(prev_state); | |
14cf11af | 1164 | } |
03465f89 | 1165 | NOKPROBE_SYMBOL(program_check_exception); |
14cf11af | 1166 | |
bf593907 PM |
1167 | /* |
1168 | * This occurs when running in hypervisor mode on POWER6 or later | |
1169 | * and an illegal instruction is encountered. | |
1170 | */ | |
03465f89 | 1171 | void emulation_assist_interrupt(struct pt_regs *regs) |
bf593907 PM |
1172 | { |
1173 | regs->msr |= REASON_ILLEGAL; | |
1174 | program_check_exception(regs); | |
1175 | } | |
03465f89 | 1176 | NOKPROBE_SYMBOL(emulation_assist_interrupt); |
bf593907 | 1177 | |
dc1c1ca3 | 1178 | void alignment_exception(struct pt_regs *regs) |
14cf11af | 1179 | { |
ba12eede | 1180 | enum ctx_state prev_state = exception_enter(); |
4393c4f6 | 1181 | int sig, code, fixed = 0; |
14cf11af | 1182 | |
a3512b2d BH |
1183 | /* We restore the interrupt state now */ |
1184 | if (!arch_irq_disabled_regs(regs)) | |
1185 | local_irq_enable(); | |
1186 | ||
6ce6c629 MN |
1187 | if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) |
1188 | goto bail; | |
1189 | ||
e9370ae1 PM |
1190 | /* we don't implement logging of alignment exceptions */ |
1191 | if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) | |
1192 | fixed = fix_alignment(regs); | |
14cf11af PM |
1193 | |
1194 | if (fixed == 1) { | |
1195 | regs->nip += 4; /* skip over emulated instruction */ | |
1196 | emulate_single_step(regs); | |
ba12eede | 1197 | goto bail; |
14cf11af PM |
1198 | } |
1199 | ||
dc1c1ca3 | 1200 | /* Operand address was bad */ |
14cf11af | 1201 | if (fixed == -EFAULT) { |
4393c4f6 BH |
1202 | sig = SIGSEGV; |
1203 | code = SEGV_ACCERR; | |
1204 | } else { | |
1205 | sig = SIGBUS; | |
1206 | code = BUS_ADRALN; | |
14cf11af | 1207 | } |
4393c4f6 BH |
1208 | if (user_mode(regs)) |
1209 | _exception(sig, regs, code, regs->dar); | |
1210 | else | |
1211 | bad_page_fault(regs, regs->dar, sig); | |
ba12eede LZ |
1212 | |
1213 | bail: | |
1214 | exception_exit(prev_state); | |
14cf11af PM |
1215 | } |
1216 | ||
f0f558b1 PM |
1217 | void slb_miss_bad_addr(struct pt_regs *regs) |
1218 | { | |
1219 | enum ctx_state prev_state = exception_enter(); | |
1220 | ||
1221 | if (user_mode(regs)) | |
1222 | _exception(SIGSEGV, regs, SEGV_BNDERR, regs->dar); | |
1223 | else | |
1224 | bad_page_fault(regs, regs->dar, SIGSEGV); | |
1225 | ||
1226 | exception_exit(prev_state); | |
1227 | } | |
1228 | ||
14cf11af PM |
1229 | void StackOverflow(struct pt_regs *regs) |
1230 | { | |
1231 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
1232 | current, regs->gpr[1]); | |
1233 | debugger(regs); | |
1234 | show_regs(regs); | |
1235 | panic("kernel stack overflow"); | |
1236 | } | |
1237 | ||
1238 | void nonrecoverable_exception(struct pt_regs *regs) | |
1239 | { | |
1240 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
1241 | regs->nip, regs->msr); | |
1242 | debugger(regs); | |
1243 | die("nonrecoverable exception", regs, SIGKILL); | |
1244 | } | |
1245 | ||
dc1c1ca3 SR |
1246 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
1247 | { | |
ba12eede LZ |
1248 | enum ctx_state prev_state = exception_enter(); |
1249 | ||
dc1c1ca3 SR |
1250 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " |
1251 | "%lx at %lx\n", regs->trap, regs->nip); | |
1252 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); | |
ba12eede LZ |
1253 | |
1254 | exception_exit(prev_state); | |
dc1c1ca3 | 1255 | } |
dc1c1ca3 SR |
1256 | |
1257 | void altivec_unavailable_exception(struct pt_regs *regs) | |
1258 | { | |
ba12eede LZ |
1259 | enum ctx_state prev_state = exception_enter(); |
1260 | ||
dc1c1ca3 SR |
1261 | if (user_mode(regs)) { |
1262 | /* A user program has executed an altivec instruction, | |
1263 | but this kernel doesn't support altivec. */ | |
1264 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
ba12eede | 1265 | goto bail; |
dc1c1ca3 | 1266 | } |
6c4841c2 | 1267 | |
dc1c1ca3 SR |
1268 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
1269 | "%lx at %lx\n", regs->trap, regs->nip); | |
1270 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); | |
ba12eede LZ |
1271 | |
1272 | bail: | |
1273 | exception_exit(prev_state); | |
dc1c1ca3 SR |
1274 | } |
1275 | ||
ce48b210 MN |
1276 | void vsx_unavailable_exception(struct pt_regs *regs) |
1277 | { | |
1278 | if (user_mode(regs)) { | |
1279 | /* A user program has executed an vsx instruction, | |
1280 | but this kernel doesn't support vsx. */ | |
1281 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1282 | return; | |
1283 | } | |
1284 | ||
1285 | printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " | |
1286 | "%lx at %lx\n", regs->trap, regs->nip); | |
1287 | die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); | |
1288 | } | |
1289 | ||
2517617e | 1290 | #ifdef CONFIG_PPC64 |
172f7aaa CB |
1291 | static void tm_unavailable(struct pt_regs *regs) |
1292 | { | |
5d176f75 CB |
1293 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1294 | if (user_mode(regs)) { | |
1295 | current->thread.load_tm++; | |
1296 | regs->msr |= MSR_TM; | |
1297 | tm_enable(); | |
1298 | tm_restore_sprs(¤t->thread); | |
1299 | return; | |
1300 | } | |
1301 | #endif | |
172f7aaa CB |
1302 | pr_emerg("Unrecoverable TM Unavailable Exception " |
1303 | "%lx at %lx\n", regs->trap, regs->nip); | |
1304 | die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); | |
1305 | } | |
1306 | ||
021424a1 | 1307 | void facility_unavailable_exception(struct pt_regs *regs) |
d0c0c9a1 | 1308 | { |
021424a1 | 1309 | static char *facility_strings[] = { |
2517617e MN |
1310 | [FSCR_FP_LG] = "FPU", |
1311 | [FSCR_VECVSX_LG] = "VMX/VSX", | |
1312 | [FSCR_DSCR_LG] = "DSCR", | |
1313 | [FSCR_PM_LG] = "PMU SPRs", | |
1314 | [FSCR_BHRB_LG] = "BHRB", | |
1315 | [FSCR_TM_LG] = "TM", | |
1316 | [FSCR_EBB_LG] = "EBB", | |
1317 | [FSCR_TAR_LG] = "TAR", | |
794464f4 | 1318 | [FSCR_MSGP_LG] = "MSGP", |
9b7ff0c6 | 1319 | [FSCR_SCV_LG] = "SCV", |
021424a1 | 1320 | }; |
2517617e | 1321 | char *facility = "unknown"; |
021424a1 | 1322 | u64 value; |
c952c1c4 | 1323 | u32 instword, rd; |
2517617e MN |
1324 | u8 status; |
1325 | bool hv; | |
021424a1 | 1326 | |
2517617e MN |
1327 | hv = (regs->trap == 0xf80); |
1328 | if (hv) | |
b14b6260 | 1329 | value = mfspr(SPRN_HFSCR); |
2517617e MN |
1330 | else |
1331 | value = mfspr(SPRN_FSCR); | |
1332 | ||
1333 | status = value >> 56; | |
1334 | if (status == FSCR_DSCR_LG) { | |
c952c1c4 AK |
1335 | /* |
1336 | * User is accessing the DSCR register using the problem | |
1337 | * state only SPR number (0x03) either through a mfspr or | |
1338 | * a mtspr instruction. If it is a write attempt through | |
1339 | * a mtspr, then we set the inherit bit. This also allows | |
1340 | * the user to write or read the register directly in the | |
1341 | * future by setting via the FSCR DSCR bit. But in case it | |
1342 | * is a read DSCR attempt through a mfspr instruction, we | |
1343 | * just emulate the instruction instead. This code path will | |
1344 | * always emulate all the mfspr instructions till the user | |
446957ba | 1345 | * has attempted at least one mtspr instruction. This way it |
c952c1c4 AK |
1346 | * preserves the same behaviour when the user is accessing |
1347 | * the DSCR through privilege level only SPR number (0x11) | |
1348 | * which is emulated through illegal instruction exception. | |
1349 | * We always leave HFSCR DSCR set. | |
2517617e | 1350 | */ |
c952c1c4 AK |
1351 | if (get_user(instword, (u32 __user *)(regs->nip))) { |
1352 | pr_err("Failed to fetch the user instruction\n"); | |
1353 | return; | |
1354 | } | |
1355 | ||
1356 | /* Write into DSCR (mtspr 0x03, RS) */ | |
1357 | if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK) | |
1358 | == PPC_INST_MTSPR_DSCR_USER) { | |
1359 | rd = (instword >> 21) & 0x1f; | |
1360 | current->thread.dscr = regs->gpr[rd]; | |
1361 | current->thread.dscr_inherit = 1; | |
b57bd2de MN |
1362 | current->thread.fscr |= FSCR_DSCR; |
1363 | mtspr(SPRN_FSCR, current->thread.fscr); | |
c952c1c4 AK |
1364 | } |
1365 | ||
1366 | /* Read from DSCR (mfspr RT, 0x03) */ | |
1367 | if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK) | |
1368 | == PPC_INST_MFSPR_DSCR_USER) { | |
1369 | if (emulate_instruction(regs)) { | |
1370 | pr_err("DSCR based mfspr emulation failed\n"); | |
1371 | return; | |
1372 | } | |
1373 | regs->nip += 4; | |
1374 | emulate_single_step(regs); | |
1375 | } | |
2517617e | 1376 | return; |
b14b6260 ME |
1377 | } |
1378 | ||
172f7aaa CB |
1379 | if (status == FSCR_TM_LG) { |
1380 | /* | |
1381 | * If we're here then the hardware is TM aware because it | |
1382 | * generated an exception with FSRM_TM set. | |
1383 | * | |
1384 | * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware | |
1385 | * told us not to do TM, or the kernel is not built with TM | |
1386 | * support. | |
1387 | * | |
1388 | * If both of those things are true, then userspace can spam the | |
1389 | * console by triggering the printk() below just by continually | |
1390 | * doing tbegin (or any TM instruction). So in that case just | |
1391 | * send the process a SIGILL immediately. | |
1392 | */ | |
1393 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1394 | goto out; | |
1395 | ||
1396 | tm_unavailable(regs); | |
1397 | return; | |
1398 | } | |
1399 | ||
93c2ec0f BS |
1400 | if ((hv || status >= 2) && |
1401 | (status < ARRAY_SIZE(facility_strings)) && | |
2517617e MN |
1402 | facility_strings[status]) |
1403 | facility = facility_strings[status]; | |
021424a1 | 1404 | |
d0c0c9a1 MN |
1405 | /* We restore the interrupt state now */ |
1406 | if (!arch_irq_disabled_regs(regs)) | |
1407 | local_irq_enable(); | |
1408 | ||
93c2ec0f BS |
1409 | pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n", |
1410 | hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr); | |
d0c0c9a1 | 1411 | |
172f7aaa | 1412 | out: |
d0c0c9a1 MN |
1413 | if (user_mode(regs)) { |
1414 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1415 | return; | |
1416 | } | |
1417 | ||
021424a1 | 1418 | die("Unexpected facility unavailable exception", regs, SIGABRT); |
d0c0c9a1 | 1419 | } |
2517617e | 1420 | #endif |
d0c0c9a1 | 1421 | |
f54db641 MN |
1422 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1423 | ||
f54db641 MN |
1424 | void fp_unavailable_tm(struct pt_regs *regs) |
1425 | { | |
1426 | /* Note: This does not handle any kind of FP laziness. */ | |
1427 | ||
1428 | TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", | |
1429 | regs->nip, regs->msr); | |
f54db641 MN |
1430 | |
1431 | /* We can only have got here if the task started using FP after | |
1432 | * beginning the transaction. So, the transactional regs are just a | |
1433 | * copy of the checkpointed ones. But, we still need to recheckpoint | |
1434 | * as we're enabling FP for the process; it will return, abort the | |
1435 | * transaction, and probably retry but now with FP enabled. So the | |
1436 | * checkpointed FP registers need to be loaded. | |
1437 | */ | |
d31626f7 | 1438 | tm_reclaim_current(TM_CAUSE_FAC_UNAV); |
f54db641 MN |
1439 | /* Reclaim didn't save out any FPRs to transact_fprs. */ |
1440 | ||
1441 | /* Enable FP for the task: */ | |
1442 | regs->msr |= (MSR_FP | current->thread.fpexc_mode); | |
1443 | ||
1444 | /* This loads and recheckpoints the FP registers from | |
1445 | * thread.fpr[]. They will remain in registers after the | |
1446 | * checkpoint so we don't need to reload them after. | |
3ac8ff1c PM |
1447 | * If VMX is in use, the VRs now hold checkpointed values, |
1448 | * so we don't want to load the VRs from the thread_struct. | |
f54db641 | 1449 | */ |
3ac8ff1c PM |
1450 | tm_recheckpoint(¤t->thread, MSR_FP); |
1451 | ||
1452 | /* If VMX is in use, get the transactional values back */ | |
1453 | if (regs->msr & MSR_VEC) { | |
dc310669 CB |
1454 | msr_check_and_set(MSR_VEC); |
1455 | load_vr_state(¤t->thread.vr_state); | |
3ac8ff1c PM |
1456 | /* At this point all the VSX state is loaded, so enable it */ |
1457 | regs->msr |= MSR_VSX; | |
1458 | } | |
f54db641 MN |
1459 | } |
1460 | ||
f54db641 MN |
1461 | void altivec_unavailable_tm(struct pt_regs *regs) |
1462 | { | |
1463 | /* See the comments in fp_unavailable_tm(). This function operates | |
1464 | * the same way. | |
1465 | */ | |
1466 | ||
1467 | TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," | |
1468 | "MSR=%lx\n", | |
1469 | regs->nip, regs->msr); | |
d31626f7 | 1470 | tm_reclaim_current(TM_CAUSE_FAC_UNAV); |
f54db641 | 1471 | regs->msr |= MSR_VEC; |
3ac8ff1c | 1472 | tm_recheckpoint(¤t->thread, MSR_VEC); |
f54db641 | 1473 | current->thread.used_vr = 1; |
3ac8ff1c PM |
1474 | |
1475 | if (regs->msr & MSR_FP) { | |
dc310669 CB |
1476 | msr_check_and_set(MSR_FP); |
1477 | load_fp_state(¤t->thread.fp_state); | |
3ac8ff1c PM |
1478 | regs->msr |= MSR_VSX; |
1479 | } | |
f54db641 | 1480 | } |
f54db641 | 1481 | |
f54db641 MN |
1482 | void vsx_unavailable_tm(struct pt_regs *regs) |
1483 | { | |
3ac8ff1c PM |
1484 | unsigned long orig_msr = regs->msr; |
1485 | ||
f54db641 MN |
1486 | /* See the comments in fp_unavailable_tm(). This works similarly, |
1487 | * though we're loading both FP and VEC registers in here. | |
1488 | * | |
1489 | * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC | |
1490 | * regs. Either way, set MSR_VSX. | |
1491 | */ | |
1492 | ||
1493 | TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," | |
1494 | "MSR=%lx\n", | |
1495 | regs->nip, regs->msr); | |
1496 | ||
3ac8ff1c PM |
1497 | current->thread.used_vsr = 1; |
1498 | ||
1499 | /* If FP and VMX are already loaded, we have all the state we need */ | |
1500 | if ((orig_msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC)) { | |
1501 | regs->msr |= MSR_VSX; | |
1502 | return; | |
1503 | } | |
1504 | ||
f54db641 | 1505 | /* This reclaims FP and/or VR regs if they're already enabled */ |
d31626f7 | 1506 | tm_reclaim_current(TM_CAUSE_FAC_UNAV); |
f54db641 MN |
1507 | |
1508 | regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode | | |
1509 | MSR_VSX; | |
3ac8ff1c PM |
1510 | |
1511 | /* This loads & recheckpoints FP and VRs; but we have | |
1512 | * to be sure not to overwrite previously-valid state. | |
1513 | */ | |
1514 | tm_recheckpoint(¤t->thread, regs->msr & ~orig_msr); | |
1515 | ||
dc310669 CB |
1516 | msr_check_and_set(orig_msr & (MSR_FP | MSR_VEC)); |
1517 | ||
3ac8ff1c | 1518 | if (orig_msr & MSR_FP) |
dc310669 | 1519 | load_fp_state(¤t->thread.fp_state); |
3ac8ff1c | 1520 | if (orig_msr & MSR_VEC) |
dc310669 | 1521 | load_vr_state(¤t->thread.vr_state); |
f54db641 | 1522 | } |
f54db641 MN |
1523 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
1524 | ||
dc1c1ca3 SR |
1525 | void performance_monitor_exception(struct pt_regs *regs) |
1526 | { | |
69111bac | 1527 | __this_cpu_inc(irq_stat.pmu_irqs); |
89713ed1 | 1528 | |
dc1c1ca3 SR |
1529 | perf_irq(regs); |
1530 | } | |
dc1c1ca3 | 1531 | |
172ae2e7 | 1532 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3bffb652 DK |
1533 | static void handle_debug(struct pt_regs *regs, unsigned long debug_status) |
1534 | { | |
1535 | int changed = 0; | |
1536 | /* | |
1537 | * Determine the cause of the debug event, clear the | |
1538 | * event flags and send a trap to the handler. Torez | |
1539 | */ | |
1540 | if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { | |
1541 | dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); | |
1542 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a | 1543 | current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; |
3bffb652 DK |
1544 | #endif |
1545 | do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, | |
1546 | 5); | |
1547 | changed |= 0x01; | |
1548 | } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { | |
1549 | dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); | |
1550 | do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT, | |
1551 | 6); | |
1552 | changed |= 0x01; | |
1553 | } else if (debug_status & DBSR_IAC1) { | |
51ae8d4a | 1554 | current->thread.debug.dbcr0 &= ~DBCR0_IAC1; |
3bffb652 DK |
1555 | dbcr_iac_range(current) &= ~DBCR_IAC12MODE; |
1556 | do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, | |
1557 | 1); | |
1558 | changed |= 0x01; | |
1559 | } else if (debug_status & DBSR_IAC2) { | |
51ae8d4a | 1560 | current->thread.debug.dbcr0 &= ~DBCR0_IAC2; |
3bffb652 DK |
1561 | do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, |
1562 | 2); | |
1563 | changed |= 0x01; | |
1564 | } else if (debug_status & DBSR_IAC3) { | |
51ae8d4a | 1565 | current->thread.debug.dbcr0 &= ~DBCR0_IAC3; |
3bffb652 DK |
1566 | dbcr_iac_range(current) &= ~DBCR_IAC34MODE; |
1567 | do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, | |
1568 | 3); | |
1569 | changed |= 0x01; | |
1570 | } else if (debug_status & DBSR_IAC4) { | |
51ae8d4a | 1571 | current->thread.debug.dbcr0 &= ~DBCR0_IAC4; |
3bffb652 DK |
1572 | do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, |
1573 | 4); | |
1574 | changed |= 0x01; | |
1575 | } | |
1576 | /* | |
1577 | * At the point this routine was called, the MSR(DE) was turned off. | |
1578 | * Check all other debug flags and see if that bit needs to be turned | |
1579 | * back on or not. | |
1580 | */ | |
51ae8d4a | 1581 | if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, |
95791988 | 1582 | current->thread.debug.dbcr1)) |
3bffb652 DK |
1583 | regs->msr |= MSR_DE; |
1584 | else | |
1585 | /* Make sure the IDM flag is off */ | |
51ae8d4a | 1586 | current->thread.debug.dbcr0 &= ~DBCR0_IDM; |
3bffb652 DK |
1587 | |
1588 | if (changed & 0x01) | |
51ae8d4a | 1589 | mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); |
3bffb652 | 1590 | } |
14cf11af | 1591 | |
03465f89 | 1592 | void DebugException(struct pt_regs *regs, unsigned long debug_status) |
14cf11af | 1593 | { |
51ae8d4a | 1594 | current->thread.debug.dbsr = debug_status; |
3bffb652 | 1595 | |
ec097c84 RM |
1596 | /* Hack alert: On BookE, Branch Taken stops on the branch itself, while |
1597 | * on server, it stops on the target of the branch. In order to simulate | |
1598 | * the server behaviour, we thus restart right away with a single step | |
1599 | * instead of stopping here when hitting a BT | |
1600 | */ | |
1601 | if (debug_status & DBSR_BT) { | |
1602 | regs->msr &= ~MSR_DE; | |
1603 | ||
1604 | /* Disable BT */ | |
1605 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); | |
1606 | /* Clear the BT event */ | |
1607 | mtspr(SPRN_DBSR, DBSR_BT); | |
1608 | ||
1609 | /* Do the single step trick only when coming from userspace */ | |
1610 | if (user_mode(regs)) { | |
51ae8d4a BB |
1611 | current->thread.debug.dbcr0 &= ~DBCR0_BT; |
1612 | current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
ec097c84 RM |
1613 | regs->msr |= MSR_DE; |
1614 | return; | |
1615 | } | |
1616 | ||
6cc89bad NR |
1617 | if (kprobe_post_handler(regs)) |
1618 | return; | |
1619 | ||
ec097c84 RM |
1620 | if (notify_die(DIE_SSTEP, "block_step", regs, 5, |
1621 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1622 | return; | |
1623 | } | |
1624 | if (debugger_sstep(regs)) | |
1625 | return; | |
1626 | } else if (debug_status & DBSR_IC) { /* Instruction complete */ | |
14cf11af | 1627 | regs->msr &= ~MSR_DE; |
f8279621 KG |
1628 | |
1629 | /* Disable instruction completion */ | |
1630 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
1631 | /* Clear the instruction completion event */ | |
1632 | mtspr(SPRN_DBSR, DBSR_IC); | |
1633 | ||
6cc89bad NR |
1634 | if (kprobe_post_handler(regs)) |
1635 | return; | |
1636 | ||
f8279621 KG |
1637 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, |
1638 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1639 | return; | |
1640 | } | |
1641 | ||
1642 | if (debugger_sstep(regs)) | |
1643 | return; | |
1644 | ||
d6a61bfc | 1645 | if (user_mode(regs)) { |
51ae8d4a BB |
1646 | current->thread.debug.dbcr0 &= ~DBCR0_IC; |
1647 | if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, | |
1648 | current->thread.debug.dbcr1)) | |
3bffb652 DK |
1649 | regs->msr |= MSR_DE; |
1650 | else | |
1651 | /* Make sure the IDM bit is off */ | |
51ae8d4a | 1652 | current->thread.debug.dbcr0 &= ~DBCR0_IDM; |
d6a61bfc | 1653 | } |
3bffb652 DK |
1654 | |
1655 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
1656 | } else | |
1657 | handle_debug(regs, debug_status); | |
14cf11af | 1658 | } |
03465f89 | 1659 | NOKPROBE_SYMBOL(DebugException); |
172ae2e7 | 1660 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
14cf11af PM |
1661 | |
1662 | #if !defined(CONFIG_TAU_INT) | |
1663 | void TAUException(struct pt_regs *regs) | |
1664 | { | |
1665 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
1666 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
1667 | } | |
1668 | #endif /* CONFIG_INT_TAU */ | |
14cf11af PM |
1669 | |
1670 | #ifdef CONFIG_ALTIVEC | |
dc1c1ca3 | 1671 | void altivec_assist_exception(struct pt_regs *regs) |
14cf11af PM |
1672 | { |
1673 | int err; | |
1674 | ||
14cf11af PM |
1675 | if (!user_mode(regs)) { |
1676 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" | |
1677 | " at %lx\n", regs->nip); | |
8dad3f92 | 1678 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
14cf11af PM |
1679 | } |
1680 | ||
dc1c1ca3 | 1681 | flush_altivec_to_thread(current); |
dc1c1ca3 | 1682 | |
eecff81d | 1683 | PPC_WARN_EMULATED(altivec, regs); |
14cf11af PM |
1684 | err = emulate_altivec(regs); |
1685 | if (err == 0) { | |
1686 | regs->nip += 4; /* skip emulated instruction */ | |
1687 | emulate_single_step(regs); | |
1688 | return; | |
1689 | } | |
1690 | ||
1691 | if (err == -EFAULT) { | |
1692 | /* got an error reading the instruction */ | |
1693 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1694 | } else { | |
1695 | /* didn't recognize the instruction */ | |
1696 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
76462232 CD |
1697 | printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " |
1698 | "in %s at %lx\n", current->comm, regs->nip); | |
de79f7b9 | 1699 | current->thread.vr_state.vscr.u[3] |= 0x10000; |
14cf11af PM |
1700 | } |
1701 | } | |
1702 | #endif /* CONFIG_ALTIVEC */ | |
1703 | ||
14cf11af PM |
1704 | #ifdef CONFIG_FSL_BOOKE |
1705 | void CacheLockingException(struct pt_regs *regs, unsigned long address, | |
1706 | unsigned long error_code) | |
1707 | { | |
1708 | /* We treat cache locking instructions from the user | |
1709 | * as priv ops, in the future we could try to do | |
1710 | * something smarter | |
1711 | */ | |
1712 | if (error_code & (ESR_DLK|ESR_ILK)) | |
1713 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1714 | return; | |
1715 | } | |
1716 | #endif /* CONFIG_FSL_BOOKE */ | |
1717 | ||
1718 | #ifdef CONFIG_SPE | |
1719 | void SPEFloatingPointException(struct pt_regs *regs) | |
1720 | { | |
6a800f36 | 1721 | extern int do_spe_mathemu(struct pt_regs *regs); |
14cf11af PM |
1722 | unsigned long spefscr; |
1723 | int fpexc_mode; | |
1724 | int code = 0; | |
6a800f36 LY |
1725 | int err; |
1726 | ||
685659ee | 1727 | flush_spe_to_thread(current); |
14cf11af PM |
1728 | |
1729 | spefscr = current->thread.spefscr; | |
1730 | fpexc_mode = current->thread.fpexc_mode; | |
1731 | ||
14cf11af PM |
1732 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { |
1733 | code = FPE_FLTOVF; | |
14cf11af PM |
1734 | } |
1735 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
1736 | code = FPE_FLTUND; | |
14cf11af PM |
1737 | } |
1738 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
1739 | code = FPE_FLTDIV; | |
1740 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
1741 | code = FPE_FLTINV; | |
14cf11af PM |
1742 | } |
1743 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
1744 | code = FPE_FLTRES; | |
1745 | ||
6a800f36 LY |
1746 | err = do_spe_mathemu(regs); |
1747 | if (err == 0) { | |
1748 | regs->nip += 4; /* skip emulated instruction */ | |
1749 | emulate_single_step(regs); | |
1750 | return; | |
1751 | } | |
1752 | ||
1753 | if (err == -EFAULT) { | |
1754 | /* got an error reading the instruction */ | |
1755 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1756 | } else if (err == -EINVAL) { | |
1757 | /* didn't recognize the instruction */ | |
1758 | printk(KERN_ERR "unrecognized spe instruction " | |
1759 | "in %s at %lx\n", current->comm, regs->nip); | |
1760 | } else { | |
1761 | _exception(SIGFPE, regs, code, regs->nip); | |
1762 | } | |
14cf11af | 1763 | |
14cf11af PM |
1764 | return; |
1765 | } | |
6a800f36 LY |
1766 | |
1767 | void SPEFloatingPointRoundException(struct pt_regs *regs) | |
1768 | { | |
1769 | extern int speround_handler(struct pt_regs *regs); | |
1770 | int err; | |
1771 | ||
1772 | preempt_disable(); | |
1773 | if (regs->msr & MSR_SPE) | |
1774 | giveup_spe(current); | |
1775 | preempt_enable(); | |
1776 | ||
1777 | regs->nip -= 4; | |
1778 | err = speround_handler(regs); | |
1779 | if (err == 0) { | |
1780 | regs->nip += 4; /* skip emulated instruction */ | |
1781 | emulate_single_step(regs); | |
1782 | return; | |
1783 | } | |
1784 | ||
1785 | if (err == -EFAULT) { | |
1786 | /* got an error reading the instruction */ | |
1787 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1788 | } else if (err == -EINVAL) { | |
1789 | /* didn't recognize the instruction */ | |
1790 | printk(KERN_ERR "unrecognized spe instruction " | |
1791 | "in %s at %lx\n", current->comm, regs->nip); | |
1792 | } else { | |
1793 | _exception(SIGFPE, regs, 0, regs->nip); | |
1794 | return; | |
1795 | } | |
1796 | } | |
14cf11af PM |
1797 | #endif |
1798 | ||
dc1c1ca3 SR |
1799 | /* |
1800 | * We enter here if we get an unrecoverable exception, that is, one | |
1801 | * that happened at a point where the RI (recoverable interrupt) bit | |
1802 | * in the MSR is 0. This indicates that SRR0/1 are live, and that | |
1803 | * we therefore lost state by taking this exception. | |
1804 | */ | |
1805 | void unrecoverable_exception(struct pt_regs *regs) | |
1806 | { | |
1807 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", | |
1808 | regs->trap, regs->nip); | |
1809 | die("Unrecoverable exception", regs, SIGABRT); | |
1810 | } | |
15770a13 | 1811 | NOKPROBE_SYMBOL(unrecoverable_exception); |
dc1c1ca3 | 1812 | |
1e18c17a | 1813 | #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) |
14cf11af PM |
1814 | /* |
1815 | * Default handler for a Watchdog exception, | |
1816 | * spins until a reboot occurs | |
1817 | */ | |
1818 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) | |
1819 | { | |
1820 | /* Generic WatchdogHandler, implement your own */ | |
1821 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); | |
1822 | return; | |
1823 | } | |
1824 | ||
1825 | void WatchdogException(struct pt_regs *regs) | |
1826 | { | |
1827 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); | |
1828 | WatchdogHandler(regs); | |
1829 | } | |
1830 | #endif | |
dc1c1ca3 | 1831 | |
dc1c1ca3 SR |
1832 | /* |
1833 | * We enter here if we discover during exception entry that we are | |
1834 | * running in supervisor mode with a userspace value in the stack pointer. | |
1835 | */ | |
1836 | void kernel_bad_stack(struct pt_regs *regs) | |
1837 | { | |
1838 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", | |
1839 | regs->gpr[1], regs->nip); | |
1840 | die("Bad kernel stack pointer", regs, SIGABRT); | |
1841 | } | |
15770a13 | 1842 | NOKPROBE_SYMBOL(kernel_bad_stack); |
14cf11af PM |
1843 | |
1844 | void __init trap_init(void) | |
1845 | { | |
1846 | } | |
80947e7c GU |
1847 | |
1848 | ||
1849 | #ifdef CONFIG_PPC_EMULATED_STATS | |
1850 | ||
1851 | #define WARN_EMULATED_SETUP(type) .type = { .name = #type } | |
1852 | ||
1853 | struct ppc_emulated ppc_emulated = { | |
1854 | #ifdef CONFIG_ALTIVEC | |
1855 | WARN_EMULATED_SETUP(altivec), | |
1856 | #endif | |
1857 | WARN_EMULATED_SETUP(dcba), | |
1858 | WARN_EMULATED_SETUP(dcbz), | |
1859 | WARN_EMULATED_SETUP(fp_pair), | |
1860 | WARN_EMULATED_SETUP(isel), | |
1861 | WARN_EMULATED_SETUP(mcrxr), | |
1862 | WARN_EMULATED_SETUP(mfpvr), | |
1863 | WARN_EMULATED_SETUP(multiple), | |
1864 | WARN_EMULATED_SETUP(popcntb), | |
1865 | WARN_EMULATED_SETUP(spe), | |
1866 | WARN_EMULATED_SETUP(string), | |
a3821b2a | 1867 | WARN_EMULATED_SETUP(sync), |
80947e7c GU |
1868 | WARN_EMULATED_SETUP(unaligned), |
1869 | #ifdef CONFIG_MATH_EMULATION | |
1870 | WARN_EMULATED_SETUP(math), | |
80947e7c GU |
1871 | #endif |
1872 | #ifdef CONFIG_VSX | |
1873 | WARN_EMULATED_SETUP(vsx), | |
1874 | #endif | |
efcac658 AK |
1875 | #ifdef CONFIG_PPC64 |
1876 | WARN_EMULATED_SETUP(mfdscr), | |
1877 | WARN_EMULATED_SETUP(mtdscr), | |
f83319d7 | 1878 | WARN_EMULATED_SETUP(lq_stq), |
efcac658 | 1879 | #endif |
80947e7c GU |
1880 | }; |
1881 | ||
1882 | u32 ppc_warn_emulated; | |
1883 | ||
1884 | void ppc_warn_emulated_print(const char *type) | |
1885 | { | |
76462232 CD |
1886 | pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, |
1887 | type); | |
80947e7c GU |
1888 | } |
1889 | ||
1890 | static int __init ppc_warn_emulated_init(void) | |
1891 | { | |
1892 | struct dentry *dir, *d; | |
1893 | unsigned int i; | |
1894 | struct ppc_emulated_entry *entries = (void *)&ppc_emulated; | |
1895 | ||
1896 | if (!powerpc_debugfs_root) | |
1897 | return -ENODEV; | |
1898 | ||
1899 | dir = debugfs_create_dir("emulated_instructions", | |
1900 | powerpc_debugfs_root); | |
1901 | if (!dir) | |
1902 | return -ENOMEM; | |
1903 | ||
1904 | d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, | |
1905 | &ppc_warn_emulated); | |
1906 | if (!d) | |
1907 | goto fail; | |
1908 | ||
1909 | for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { | |
1910 | d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, | |
1911 | (u32 *)&entries[i].val.counter); | |
1912 | if (!d) | |
1913 | goto fail; | |
1914 | } | |
1915 | ||
1916 | return 0; | |
1917 | ||
1918 | fail: | |
1919 | debugfs_remove_recursive(dir); | |
1920 | return -ENOMEM; | |
1921 | } | |
1922 | ||
1923 | device_initcall(ppc_warn_emulated_init); | |
1924 | ||
1925 | #endif /* CONFIG_PPC_EMULATED_STATS */ |