Commit | Line | Data |
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14cf11af | 1 | /* |
14cf11af PM |
2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | * | |
9 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
10 | * and Paul Mackerras (paulus@samba.org) | |
11 | */ | |
12 | ||
13 | /* | |
14 | * This file handles the architecture-dependent parts of hardware exceptions | |
15 | */ | |
16 | ||
14cf11af PM |
17 | #include <linux/errno.h> |
18 | #include <linux/sched.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/stddef.h> | |
22 | #include <linux/unistd.h> | |
8dad3f92 | 23 | #include <linux/ptrace.h> |
14cf11af | 24 | #include <linux/user.h> |
14cf11af | 25 | #include <linux/interrupt.h> |
14cf11af PM |
26 | #include <linux/init.h> |
27 | #include <linux/module.h> | |
8dad3f92 | 28 | #include <linux/prctl.h> |
14cf11af PM |
29 | #include <linux/delay.h> |
30 | #include <linux/kprobes.h> | |
cc532915 | 31 | #include <linux/kexec.h> |
5474c120 | 32 | #include <linux/backlight.h> |
73c9ceab | 33 | #include <linux/bug.h> |
1eeb66a1 | 34 | #include <linux/kdebug.h> |
80947e7c | 35 | #include <linux/debugfs.h> |
14cf11af | 36 | |
80947e7c | 37 | #include <asm/emulated_ops.h> |
14cf11af PM |
38 | #include <asm/pgtable.h> |
39 | #include <asm/uaccess.h> | |
40 | #include <asm/system.h> | |
41 | #include <asm/io.h> | |
86417780 PM |
42 | #include <asm/machdep.h> |
43 | #include <asm/rtas.h> | |
f7f6f4fe | 44 | #include <asm/pmc.h> |
dc1c1ca3 | 45 | #ifdef CONFIG_PPC32 |
14cf11af | 46 | #include <asm/reg.h> |
86417780 | 47 | #endif |
14cf11af PM |
48 | #ifdef CONFIG_PMAC_BACKLIGHT |
49 | #include <asm/backlight.h> | |
50 | #endif | |
dc1c1ca3 | 51 | #ifdef CONFIG_PPC64 |
86417780 | 52 | #include <asm/firmware.h> |
dc1c1ca3 | 53 | #include <asm/processor.h> |
dc1c1ca3 | 54 | #endif |
c0ce7d08 | 55 | #include <asm/kexec.h> |
16c57b36 | 56 | #include <asm/ppc-opcode.h> |
620165f9 KG |
57 | #ifdef CONFIG_FSL_BOOKE |
58 | #include <asm/dbell.h> | |
59 | #endif | |
dc1c1ca3 | 60 | |
7dbb922c | 61 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC) |
5be3492f AB |
62 | int (*__debugger)(struct pt_regs *regs) __read_mostly; |
63 | int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; | |
64 | int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; | |
65 | int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; | |
66 | int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; | |
67 | int (*__debugger_dabr_match)(struct pt_regs *regs) __read_mostly; | |
68 | int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; | |
14cf11af PM |
69 | |
70 | EXPORT_SYMBOL(__debugger); | |
71 | EXPORT_SYMBOL(__debugger_ipi); | |
72 | EXPORT_SYMBOL(__debugger_bpt); | |
73 | EXPORT_SYMBOL(__debugger_sstep); | |
74 | EXPORT_SYMBOL(__debugger_iabr_match); | |
75 | EXPORT_SYMBOL(__debugger_dabr_match); | |
76 | EXPORT_SYMBOL(__debugger_fault_handler); | |
77 | #endif | |
78 | ||
14cf11af PM |
79 | /* |
80 | * Trap & Exception support | |
81 | */ | |
82 | ||
6031d9d9 | 83 | #ifdef CONFIG_PMAC_BACKLIGHT |
84 | static void pmac_backlight_unblank(void) | |
85 | { | |
86 | mutex_lock(&pmac_backlight_mutex); | |
87 | if (pmac_backlight) { | |
88 | struct backlight_properties *props; | |
89 | ||
90 | props = &pmac_backlight->props; | |
91 | props->brightness = props->max_brightness; | |
92 | props->power = FB_BLANK_UNBLANK; | |
93 | backlight_update_status(pmac_backlight); | |
94 | } | |
95 | mutex_unlock(&pmac_backlight_mutex); | |
96 | } | |
97 | #else | |
98 | static inline void pmac_backlight_unblank(void) { } | |
99 | #endif | |
100 | ||
14cf11af PM |
101 | int die(const char *str, struct pt_regs *regs, long err) |
102 | { | |
34c2a14f | 103 | static struct { |
b8f87782 | 104 | raw_spinlock_t lock; |
34c2a14f | 105 | u32 lock_owner; |
106 | int lock_owner_depth; | |
107 | } die = { | |
b8f87782 | 108 | .lock = __RAW_SPIN_LOCK_UNLOCKED(die.lock), |
34c2a14f | 109 | .lock_owner = -1, |
110 | .lock_owner_depth = 0 | |
111 | }; | |
c0ce7d08 | 112 | static int die_counter; |
34c2a14f | 113 | unsigned long flags; |
14cf11af PM |
114 | |
115 | if (debugger(regs)) | |
116 | return 1; | |
117 | ||
293e4688 | 118 | oops_enter(); |
119 | ||
34c2a14f | 120 | if (die.lock_owner != raw_smp_processor_id()) { |
121 | console_verbose(); | |
b8f87782 | 122 | raw_spin_lock_irqsave(&die.lock, flags); |
34c2a14f | 123 | die.lock_owner = smp_processor_id(); |
124 | die.lock_owner_depth = 0; | |
125 | bust_spinlocks(1); | |
126 | if (machine_is(powermac)) | |
127 | pmac_backlight_unblank(); | |
128 | } else { | |
129 | local_save_flags(flags); | |
130 | } | |
5474c120 | 131 | |
34c2a14f | 132 | if (++die.lock_owner_depth < 3) { |
133 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); | |
14cf11af | 134 | #ifdef CONFIG_PREEMPT |
34c2a14f | 135 | printk("PREEMPT "); |
14cf11af PM |
136 | #endif |
137 | #ifdef CONFIG_SMP | |
34c2a14f | 138 | printk("SMP NR_CPUS=%d ", NR_CPUS); |
14cf11af PM |
139 | #endif |
140 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
34c2a14f | 141 | printk("DEBUG_PAGEALLOC "); |
14cf11af PM |
142 | #endif |
143 | #ifdef CONFIG_NUMA | |
34c2a14f | 144 | printk("NUMA "); |
14cf11af | 145 | #endif |
ae7f4463 | 146 | printk("%s\n", ppc_md.name ? ppc_md.name : ""); |
34c2a14f | 147 | |
66fcb105 AB |
148 | sysfs_printk_last_file(); |
149 | if (notify_die(DIE_OOPS, str, regs, err, 255, | |
150 | SIGSEGV) == NOTIFY_STOP) | |
151 | return 1; | |
152 | ||
34c2a14f | 153 | print_modules(); |
154 | show_regs(regs); | |
155 | } else { | |
156 | printk("Recursive die() failure, output suppressed\n"); | |
157 | } | |
e8222502 | 158 | |
14cf11af | 159 | bust_spinlocks(0); |
34c2a14f | 160 | die.lock_owner = -1; |
bcdcd8e7 | 161 | add_taint(TAINT_DIE); |
b8f87782 | 162 | raw_spin_unlock_irqrestore(&die.lock, flags); |
cc532915 | 163 | |
c0ce7d08 DW |
164 | if (kexec_should_crash(current) || |
165 | kexec_sr_activated(smp_processor_id())) | |
cc532915 | 166 | crash_kexec(regs); |
c0ce7d08 | 167 | crash_kexec_secondary(regs); |
14cf11af PM |
168 | |
169 | if (in_interrupt()) | |
170 | panic("Fatal exception in interrupt"); | |
171 | ||
cea6a4ba | 172 | if (panic_on_oops) |
012c437d | 173 | panic("Fatal exception"); |
cea6a4ba | 174 | |
293e4688 | 175 | oops_exit(); |
14cf11af PM |
176 | do_exit(err); |
177 | ||
178 | return 0; | |
179 | } | |
180 | ||
25baa35b ON |
181 | void user_single_step_siginfo(struct task_struct *tsk, |
182 | struct pt_regs *regs, siginfo_t *info) | |
183 | { | |
184 | memset(info, 0, sizeof(*info)); | |
185 | info->si_signo = SIGTRAP; | |
186 | info->si_code = TRAP_TRACE; | |
187 | info->si_addr = (void __user *)regs->nip; | |
188 | } | |
189 | ||
14cf11af PM |
190 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) |
191 | { | |
192 | siginfo_t info; | |
d0c3d534 OJ |
193 | const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ |
194 | "at %08lx nip %08lx lr %08lx code %x\n"; | |
195 | const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ | |
196 | "at %016lx nip %016lx lr %016lx code %x\n"; | |
14cf11af PM |
197 | |
198 | if (!user_mode(regs)) { | |
199 | if (die("Exception in kernel mode", regs, signr)) | |
200 | return; | |
d0c3d534 OJ |
201 | } else if (show_unhandled_signals && |
202 | unhandled_signal(current, signr) && | |
203 | printk_ratelimit()) { | |
204 | printk(regs->msr & MSR_SF ? fmt64 : fmt32, | |
205 | current->comm, current->pid, signr, | |
206 | addr, regs->nip, regs->link, code); | |
207 | } | |
14cf11af PM |
208 | |
209 | memset(&info, 0, sizeof(info)); | |
210 | info.si_signo = signr; | |
211 | info.si_code = code; | |
212 | info.si_addr = (void __user *) addr; | |
213 | force_sig_info(signr, &info, current); | |
14cf11af PM |
214 | } |
215 | ||
216 | #ifdef CONFIG_PPC64 | |
217 | void system_reset_exception(struct pt_regs *regs) | |
218 | { | |
219 | /* See if any machine dependent calls */ | |
c902be71 AB |
220 | if (ppc_md.system_reset_exception) { |
221 | if (ppc_md.system_reset_exception(regs)) | |
222 | return; | |
223 | } | |
14cf11af | 224 | |
c0ce7d08 DW |
225 | #ifdef CONFIG_KEXEC |
226 | cpu_set(smp_processor_id(), cpus_in_sr); | |
227 | #endif | |
228 | ||
8dad3f92 | 229 | die("System Reset", regs, SIGABRT); |
14cf11af | 230 | |
eac8392f DW |
231 | /* |
232 | * Some CPUs when released from the debugger will execute this path. | |
233 | * These CPUs entered the debugger via a soft-reset. If the CPU was | |
234 | * hung before entering the debugger it will return to the hung | |
235 | * state when exiting this function. This causes a problem in | |
236 | * kdump since the hung CPU(s) will not respond to the IPI sent | |
237 | * from kdump. To prevent the problem we call crash_kexec_secondary() | |
238 | * here. If a kdump had not been initiated or we exit the debugger | |
239 | * with the "exit and recover" command (x) crash_kexec_secondary() | |
240 | * will return after 5ms and the CPU returns to its previous state. | |
241 | */ | |
242 | crash_kexec_secondary(regs); | |
243 | ||
14cf11af PM |
244 | /* Must die if the interrupt is not recoverable */ |
245 | if (!(regs->msr & MSR_RI)) | |
246 | panic("Unrecoverable System Reset"); | |
247 | ||
248 | /* What should we do here? We could issue a shutdown or hard reset. */ | |
249 | } | |
250 | #endif | |
251 | ||
252 | /* | |
253 | * I/O accesses can cause machine checks on powermacs. | |
254 | * Check if the NIP corresponds to the address of a sync | |
255 | * instruction for which there is an entry in the exception | |
256 | * table. | |
257 | * Note that the 601 only takes a machine check on TEA | |
258 | * (transfer error ack) signal assertion, and does not | |
259 | * set any of the top 16 bits of SRR1. | |
260 | * -- paulus. | |
261 | */ | |
262 | static inline int check_io_access(struct pt_regs *regs) | |
263 | { | |
68a64357 | 264 | #ifdef CONFIG_PPC32 |
14cf11af PM |
265 | unsigned long msr = regs->msr; |
266 | const struct exception_table_entry *entry; | |
267 | unsigned int *nip = (unsigned int *)regs->nip; | |
268 | ||
269 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
270 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
271 | /* | |
272 | * Check that it's a sync instruction, or somewhere | |
273 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
274 | * As the address is in the exception table | |
275 | * we should be able to read the instr there. | |
276 | * For the debug message, we look at the preceding | |
277 | * load or store. | |
278 | */ | |
279 | if (*nip == 0x60000000) /* nop */ | |
280 | nip -= 2; | |
281 | else if (*nip == 0x4c00012c) /* isync */ | |
282 | --nip; | |
283 | if (*nip == 0x7c0004ac || (*nip >> 26) == 3) { | |
284 | /* sync or twi */ | |
285 | unsigned int rb; | |
286 | ||
287 | --nip; | |
288 | rb = (*nip >> 11) & 0x1f; | |
289 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
290 | (*nip & 0x100)? "OUT to": "IN from", | |
291 | regs->gpr[rb] - _IO_BASE, nip); | |
292 | regs->msr |= MSR_RI; | |
293 | regs->nip = entry->fixup; | |
294 | return 1; | |
295 | } | |
296 | } | |
68a64357 | 297 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
298 | return 0; |
299 | } | |
300 | ||
172ae2e7 | 301 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
14cf11af PM |
302 | /* On 4xx, the reason for the machine check or program exception |
303 | is in the ESR. */ | |
304 | #define get_reason(regs) ((regs)->dsisr) | |
305 | #ifndef CONFIG_FSL_BOOKE | |
306 | #define get_mc_reason(regs) ((regs)->dsisr) | |
307 | #else | |
86d7a9a9 | 308 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR) & MCSR_MASK) |
14cf11af PM |
309 | #endif |
310 | #define REASON_FP ESR_FP | |
311 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) | |
312 | #define REASON_PRIVILEGED ESR_PPR | |
313 | #define REASON_TRAP ESR_PTR | |
314 | ||
315 | /* single-step stuff */ | |
316 | #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) | |
317 | #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) | |
318 | ||
319 | #else | |
320 | /* On non-4xx, the reason for the machine check or program | |
321 | exception is in the MSR. */ | |
322 | #define get_reason(regs) ((regs)->msr) | |
323 | #define get_mc_reason(regs) ((regs)->msr) | |
324 | #define REASON_FP 0x100000 | |
325 | #define REASON_ILLEGAL 0x80000 | |
326 | #define REASON_PRIVILEGED 0x40000 | |
327 | #define REASON_TRAP 0x20000 | |
328 | ||
329 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
330 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
331 | #endif | |
332 | ||
47c0bd1a BH |
333 | #if defined(CONFIG_4xx) |
334 | int machine_check_4xx(struct pt_regs *regs) | |
14cf11af | 335 | { |
1a6a4ffe | 336 | unsigned long reason = get_mc_reason(regs); |
14cf11af | 337 | |
14cf11af PM |
338 | if (reason & ESR_IMCP) { |
339 | printk("Instruction"); | |
340 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
341 | } else | |
342 | printk("Data"); | |
343 | printk(" machine check in kernel mode.\n"); | |
47c0bd1a BH |
344 | |
345 | return 0; | |
346 | } | |
347 | ||
348 | int machine_check_440A(struct pt_regs *regs) | |
349 | { | |
350 | unsigned long reason = get_mc_reason(regs); | |
351 | ||
14cf11af PM |
352 | printk("Machine check in kernel mode.\n"); |
353 | if (reason & ESR_IMCP){ | |
354 | printk("Instruction Synchronous Machine Check exception\n"); | |
355 | mtspr(SPRN_ESR, reason & ~ESR_IMCP); | |
356 | } | |
357 | else { | |
358 | u32 mcsr = mfspr(SPRN_MCSR); | |
359 | if (mcsr & MCSR_IB) | |
360 | printk("Instruction Read PLB Error\n"); | |
361 | if (mcsr & MCSR_DRB) | |
362 | printk("Data Read PLB Error\n"); | |
363 | if (mcsr & MCSR_DWB) | |
364 | printk("Data Write PLB Error\n"); | |
365 | if (mcsr & MCSR_TLBP) | |
366 | printk("TLB Parity Error\n"); | |
367 | if (mcsr & MCSR_ICP){ | |
368 | flush_instruction_cache(); | |
369 | printk("I-Cache Parity Error\n"); | |
370 | } | |
371 | if (mcsr & MCSR_DCSP) | |
372 | printk("D-Cache Search Parity Error\n"); | |
373 | if (mcsr & MCSR_DCFP) | |
374 | printk("D-Cache Flush Parity Error\n"); | |
375 | if (mcsr & MCSR_IMPE) | |
376 | printk("Machine Check exception is imprecise\n"); | |
377 | ||
378 | /* Clear MCSR */ | |
379 | mtspr(SPRN_MCSR, mcsr); | |
380 | } | |
47c0bd1a BH |
381 | return 0; |
382 | } | |
383 | #elif defined(CONFIG_E500) | |
384 | int machine_check_e500(struct pt_regs *regs) | |
385 | { | |
386 | unsigned long reason = get_mc_reason(regs); | |
387 | ||
14cf11af PM |
388 | printk("Machine check in kernel mode.\n"); |
389 | printk("Caused by (from MCSR=%lx): ", reason); | |
390 | ||
391 | if (reason & MCSR_MCP) | |
392 | printk("Machine Check Signal\n"); | |
393 | if (reason & MCSR_ICPERR) | |
394 | printk("Instruction Cache Parity Error\n"); | |
395 | if (reason & MCSR_DCP_PERR) | |
396 | printk("Data Cache Push Parity Error\n"); | |
397 | if (reason & MCSR_DCPERR) | |
398 | printk("Data Cache Parity Error\n"); | |
14cf11af PM |
399 | if (reason & MCSR_BUS_IAERR) |
400 | printk("Bus - Instruction Address Error\n"); | |
401 | if (reason & MCSR_BUS_RAERR) | |
402 | printk("Bus - Read Address Error\n"); | |
403 | if (reason & MCSR_BUS_WAERR) | |
404 | printk("Bus - Write Address Error\n"); | |
405 | if (reason & MCSR_BUS_IBERR) | |
406 | printk("Bus - Instruction Data Error\n"); | |
407 | if (reason & MCSR_BUS_RBERR) | |
408 | printk("Bus - Read Data Bus Error\n"); | |
409 | if (reason & MCSR_BUS_WBERR) | |
410 | printk("Bus - Read Data Bus Error\n"); | |
411 | if (reason & MCSR_BUS_IPERR) | |
412 | printk("Bus - Instruction Parity Error\n"); | |
413 | if (reason & MCSR_BUS_RPERR) | |
414 | printk("Bus - Read Parity Error\n"); | |
47c0bd1a BH |
415 | |
416 | return 0; | |
417 | } | |
418 | #elif defined(CONFIG_E200) | |
419 | int machine_check_e200(struct pt_regs *regs) | |
420 | { | |
421 | unsigned long reason = get_mc_reason(regs); | |
422 | ||
14cf11af PM |
423 | printk("Machine check in kernel mode.\n"); |
424 | printk("Caused by (from MCSR=%lx): ", reason); | |
425 | ||
426 | if (reason & MCSR_MCP) | |
427 | printk("Machine Check Signal\n"); | |
428 | if (reason & MCSR_CP_PERR) | |
429 | printk("Cache Push Parity Error\n"); | |
430 | if (reason & MCSR_CPERR) | |
431 | printk("Cache Parity Error\n"); | |
432 | if (reason & MCSR_EXCP_ERR) | |
433 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | |
434 | if (reason & MCSR_BUS_IRERR) | |
435 | printk("Bus - Read Bus Error on instruction fetch\n"); | |
436 | if (reason & MCSR_BUS_DRERR) | |
437 | printk("Bus - Read Bus Error on data load\n"); | |
438 | if (reason & MCSR_BUS_WRERR) | |
439 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | |
47c0bd1a BH |
440 | |
441 | return 0; | |
442 | } | |
443 | #else | |
444 | int machine_check_generic(struct pt_regs *regs) | |
445 | { | |
446 | unsigned long reason = get_mc_reason(regs); | |
447 | ||
14cf11af PM |
448 | printk("Machine check in kernel mode.\n"); |
449 | printk("Caused by (from SRR1=%lx): ", reason); | |
450 | switch (reason & 0x601F0000) { | |
451 | case 0x80000: | |
452 | printk("Machine check signal\n"); | |
453 | break; | |
454 | case 0: /* for 601 */ | |
455 | case 0x40000: | |
456 | case 0x140000: /* 7450 MSS error and TEA */ | |
457 | printk("Transfer error ack signal\n"); | |
458 | break; | |
459 | case 0x20000: | |
460 | printk("Data parity error signal\n"); | |
461 | break; | |
462 | case 0x10000: | |
463 | printk("Address parity error signal\n"); | |
464 | break; | |
465 | case 0x20000000: | |
466 | printk("L1 Data Cache error\n"); | |
467 | break; | |
468 | case 0x40000000: | |
469 | printk("L1 Instruction Cache error\n"); | |
470 | break; | |
471 | case 0x00100000: | |
472 | printk("L2 data cache parity error\n"); | |
473 | break; | |
474 | default: | |
475 | printk("Unknown values in msr\n"); | |
476 | } | |
75918a4b OJ |
477 | return 0; |
478 | } | |
47c0bd1a | 479 | #endif /* everything else */ |
75918a4b OJ |
480 | |
481 | void machine_check_exception(struct pt_regs *regs) | |
482 | { | |
483 | int recover = 0; | |
484 | ||
89713ed1 AB |
485 | __get_cpu_var(irq_stat).mce_exceptions++; |
486 | ||
47c0bd1a BH |
487 | /* See if any machine dependent calls. In theory, we would want |
488 | * to call the CPU first, and call the ppc_md. one if the CPU | |
489 | * one returns a positive number. However there is existing code | |
490 | * that assumes the board gets a first chance, so let's keep it | |
491 | * that way for now and fix things later. --BenH. | |
492 | */ | |
75918a4b OJ |
493 | if (ppc_md.machine_check_exception) |
494 | recover = ppc_md.machine_check_exception(regs); | |
47c0bd1a BH |
495 | else if (cur_cpu_spec->machine_check) |
496 | recover = cur_cpu_spec->machine_check(regs); | |
75918a4b | 497 | |
47c0bd1a | 498 | if (recover > 0) |
75918a4b OJ |
499 | return; |
500 | ||
501 | if (user_mode(regs)) { | |
502 | regs->msr |= MSR_RI; | |
503 | _exception(SIGBUS, regs, BUS_ADRERR, regs->nip); | |
504 | return; | |
505 | } | |
506 | ||
507 | #if defined(CONFIG_8xx) && defined(CONFIG_PCI) | |
47c0bd1a BH |
508 | /* the qspan pci read routines can cause machine checks -- Cort |
509 | * | |
510 | * yuck !!! that totally needs to go away ! There are better ways | |
511 | * to deal with that than having a wart in the mcheck handler. | |
512 | * -- BenH | |
513 | */ | |
75918a4b OJ |
514 | bad_page_fault(regs, regs->dar, SIGBUS); |
515 | return; | |
516 | #endif | |
517 | ||
518 | if (debugger_fault_handler(regs)) { | |
519 | regs->msr |= MSR_RI; | |
520 | return; | |
521 | } | |
522 | ||
523 | if (check_io_access(regs)) | |
524 | return; | |
525 | ||
14cf11af PM |
526 | if (debugger_fault_handler(regs)) |
527 | return; | |
8dad3f92 | 528 | die("Machine check", regs, SIGBUS); |
14cf11af PM |
529 | |
530 | /* Must die if the interrupt is not recoverable */ | |
531 | if (!(regs->msr & MSR_RI)) | |
532 | panic("Unrecoverable Machine check"); | |
533 | } | |
534 | ||
535 | void SMIException(struct pt_regs *regs) | |
536 | { | |
537 | die("System Management Interrupt", regs, SIGABRT); | |
538 | } | |
539 | ||
dc1c1ca3 | 540 | void unknown_exception(struct pt_regs *regs) |
14cf11af PM |
541 | { |
542 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", | |
543 | regs->nip, regs->msr, regs->trap); | |
544 | ||
545 | _exception(SIGTRAP, regs, 0, 0); | |
546 | } | |
547 | ||
dc1c1ca3 | 548 | void instruction_breakpoint_exception(struct pt_regs *regs) |
14cf11af PM |
549 | { |
550 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, | |
551 | 5, SIGTRAP) == NOTIFY_STOP) | |
552 | return; | |
553 | if (debugger_iabr_match(regs)) | |
554 | return; | |
555 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); | |
556 | } | |
557 | ||
558 | void RunModeException(struct pt_regs *regs) | |
559 | { | |
560 | _exception(SIGTRAP, regs, 0, 0); | |
561 | } | |
562 | ||
8dad3f92 | 563 | void __kprobes single_step_exception(struct pt_regs *regs) |
14cf11af PM |
564 | { |
565 | regs->msr &= ~(MSR_SE | MSR_BE); /* Turn off 'trace' bits */ | |
566 | ||
567 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
568 | 5, SIGTRAP) == NOTIFY_STOP) | |
569 | return; | |
570 | if (debugger_sstep(regs)) | |
571 | return; | |
572 | ||
573 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
574 | } | |
575 | ||
576 | /* | |
577 | * After we have successfully emulated an instruction, we have to | |
578 | * check if the instruction was being single-stepped, and if so, | |
579 | * pretend we got a single-step exception. This was pointed out | |
580 | * by Kumar Gala. -- paulus | |
581 | */ | |
8dad3f92 | 582 | static void emulate_single_step(struct pt_regs *regs) |
14cf11af PM |
583 | { |
584 | if (single_stepping(regs)) { | |
585 | clear_single_step(regs); | |
586 | _exception(SIGTRAP, regs, TRAP_TRACE, 0); | |
587 | } | |
588 | } | |
589 | ||
5fad293b | 590 | static inline int __parse_fpscr(unsigned long fpscr) |
dc1c1ca3 | 591 | { |
5fad293b | 592 | int ret = 0; |
dc1c1ca3 SR |
593 | |
594 | /* Invalid operation */ | |
595 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) | |
5fad293b | 596 | ret = FPE_FLTINV; |
dc1c1ca3 SR |
597 | |
598 | /* Overflow */ | |
599 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) | |
5fad293b | 600 | ret = FPE_FLTOVF; |
dc1c1ca3 SR |
601 | |
602 | /* Underflow */ | |
603 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) | |
5fad293b | 604 | ret = FPE_FLTUND; |
dc1c1ca3 SR |
605 | |
606 | /* Divide by zero */ | |
607 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) | |
5fad293b | 608 | ret = FPE_FLTDIV; |
dc1c1ca3 SR |
609 | |
610 | /* Inexact result */ | |
611 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) | |
5fad293b KG |
612 | ret = FPE_FLTRES; |
613 | ||
614 | return ret; | |
615 | } | |
616 | ||
617 | static void parse_fpe(struct pt_regs *regs) | |
618 | { | |
619 | int code = 0; | |
620 | ||
621 | flush_fp_to_thread(current); | |
622 | ||
623 | code = __parse_fpscr(current->thread.fpscr.val); | |
dc1c1ca3 SR |
624 | |
625 | _exception(SIGFPE, regs, code, regs->nip); | |
626 | } | |
627 | ||
628 | /* | |
629 | * Illegal instruction emulation support. Originally written to | |
14cf11af PM |
630 | * provide the PVR to user applications using the mfspr rd, PVR. |
631 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
632 | * memory access caused an access fault. Return zero on success. | |
633 | * | |
634 | * There are a couple of ways to do this, either "decode" the instruction | |
635 | * or directly match lots of bits. In this case, matching lots of | |
636 | * bits is faster and easier. | |
86417780 | 637 | * |
14cf11af | 638 | */ |
14cf11af PM |
639 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) |
640 | { | |
641 | u8 rT = (instword >> 21) & 0x1f; | |
642 | u8 rA = (instword >> 16) & 0x1f; | |
643 | u8 NB_RB = (instword >> 11) & 0x1f; | |
644 | u32 num_bytes; | |
645 | unsigned long EA; | |
646 | int pos = 0; | |
647 | ||
648 | /* Early out if we are an invalid form of lswx */ | |
16c57b36 | 649 | if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) |
14cf11af PM |
650 | if ((rT == rA) || (rT == NB_RB)) |
651 | return -EINVAL; | |
652 | ||
653 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
654 | ||
16c57b36 KG |
655 | switch (instword & PPC_INST_STRING_MASK) { |
656 | case PPC_INST_LSWX: | |
657 | case PPC_INST_STSWX: | |
14cf11af PM |
658 | EA += NB_RB; |
659 | num_bytes = regs->xer & 0x7f; | |
660 | break; | |
16c57b36 KG |
661 | case PPC_INST_LSWI: |
662 | case PPC_INST_STSWI: | |
14cf11af PM |
663 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; |
664 | break; | |
665 | default: | |
666 | return -EINVAL; | |
667 | } | |
668 | ||
669 | while (num_bytes != 0) | |
670 | { | |
671 | u8 val; | |
672 | u32 shift = 8 * (3 - (pos & 0x3)); | |
673 | ||
16c57b36 KG |
674 | switch ((instword & PPC_INST_STRING_MASK)) { |
675 | case PPC_INST_LSWX: | |
676 | case PPC_INST_LSWI: | |
14cf11af PM |
677 | if (get_user(val, (u8 __user *)EA)) |
678 | return -EFAULT; | |
679 | /* first time updating this reg, | |
680 | * zero it out */ | |
681 | if (pos == 0) | |
682 | regs->gpr[rT] = 0; | |
683 | regs->gpr[rT] |= val << shift; | |
684 | break; | |
16c57b36 KG |
685 | case PPC_INST_STSWI: |
686 | case PPC_INST_STSWX: | |
14cf11af PM |
687 | val = regs->gpr[rT] >> shift; |
688 | if (put_user(val, (u8 __user *)EA)) | |
689 | return -EFAULT; | |
690 | break; | |
691 | } | |
692 | /* move EA to next address */ | |
693 | EA += 1; | |
694 | num_bytes--; | |
695 | ||
696 | /* manage our position within the register */ | |
697 | if (++pos == 4) { | |
698 | pos = 0; | |
699 | if (++rT == 32) | |
700 | rT = 0; | |
701 | } | |
702 | } | |
703 | ||
704 | return 0; | |
705 | } | |
706 | ||
c3412dcb WS |
707 | static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) |
708 | { | |
709 | u32 ra,rs; | |
710 | unsigned long tmp; | |
711 | ||
712 | ra = (instword >> 16) & 0x1f; | |
713 | rs = (instword >> 21) & 0x1f; | |
714 | ||
715 | tmp = regs->gpr[rs]; | |
716 | tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); | |
717 | tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); | |
718 | tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; | |
719 | regs->gpr[ra] = tmp; | |
720 | ||
721 | return 0; | |
722 | } | |
723 | ||
c1469f13 KG |
724 | static int emulate_isel(struct pt_regs *regs, u32 instword) |
725 | { | |
726 | u8 rT = (instword >> 21) & 0x1f; | |
727 | u8 rA = (instword >> 16) & 0x1f; | |
728 | u8 rB = (instword >> 11) & 0x1f; | |
729 | u8 BC = (instword >> 6) & 0x1f; | |
730 | u8 bit; | |
731 | unsigned long tmp; | |
732 | ||
733 | tmp = (rA == 0) ? 0 : regs->gpr[rA]; | |
734 | bit = (regs->ccr >> (31 - BC)) & 0x1; | |
735 | ||
736 | regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; | |
737 | ||
738 | return 0; | |
739 | } | |
740 | ||
14cf11af PM |
741 | static int emulate_instruction(struct pt_regs *regs) |
742 | { | |
743 | u32 instword; | |
744 | u32 rd; | |
745 | ||
fab5db97 | 746 | if (!user_mode(regs) || (regs->msr & MSR_LE)) |
14cf11af PM |
747 | return -EINVAL; |
748 | CHECK_FULL_REGS(regs); | |
749 | ||
750 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
751 | return -EFAULT; | |
752 | ||
753 | /* Emulate the mfspr rD, PVR. */ | |
16c57b36 | 754 | if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { |
eecff81d | 755 | PPC_WARN_EMULATED(mfpvr, regs); |
14cf11af PM |
756 | rd = (instword >> 21) & 0x1f; |
757 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
758 | return 0; | |
759 | } | |
760 | ||
761 | /* Emulating the dcba insn is just a no-op. */ | |
80947e7c | 762 | if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { |
eecff81d | 763 | PPC_WARN_EMULATED(dcba, regs); |
14cf11af | 764 | return 0; |
80947e7c | 765 | } |
14cf11af PM |
766 | |
767 | /* Emulate the mcrxr insn. */ | |
16c57b36 | 768 | if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { |
86417780 | 769 | int shift = (instword >> 21) & 0x1c; |
14cf11af PM |
770 | unsigned long msk = 0xf0000000UL >> shift; |
771 | ||
eecff81d | 772 | PPC_WARN_EMULATED(mcrxr, regs); |
14cf11af PM |
773 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); |
774 | regs->xer &= ~0xf0000000UL; | |
775 | return 0; | |
776 | } | |
777 | ||
778 | /* Emulate load/store string insn. */ | |
80947e7c | 779 | if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { |
eecff81d | 780 | PPC_WARN_EMULATED(string, regs); |
14cf11af | 781 | return emulate_string_inst(regs, instword); |
80947e7c | 782 | } |
14cf11af | 783 | |
c3412dcb | 784 | /* Emulate the popcntb (Population Count Bytes) instruction. */ |
16c57b36 | 785 | if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { |
eecff81d | 786 | PPC_WARN_EMULATED(popcntb, regs); |
c3412dcb WS |
787 | return emulate_popcntb_inst(regs, instword); |
788 | } | |
789 | ||
c1469f13 | 790 | /* Emulate isel (Integer Select) instruction */ |
16c57b36 | 791 | if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { |
eecff81d | 792 | PPC_WARN_EMULATED(isel, regs); |
c1469f13 KG |
793 | return emulate_isel(regs, instword); |
794 | } | |
795 | ||
14cf11af PM |
796 | return -EINVAL; |
797 | } | |
798 | ||
73c9ceab | 799 | int is_valid_bugaddr(unsigned long addr) |
14cf11af | 800 | { |
73c9ceab | 801 | return is_kernel_addr(addr); |
14cf11af PM |
802 | } |
803 | ||
8dad3f92 | 804 | void __kprobes program_check_exception(struct pt_regs *regs) |
14cf11af PM |
805 | { |
806 | unsigned int reason = get_reason(regs); | |
807 | extern int do_mathemu(struct pt_regs *regs); | |
808 | ||
aa42c69c | 809 | /* We can now get here via a FP Unavailable exception if the core |
04903a30 | 810 | * has no FPU, in that case the reason flags will be 0 */ |
14cf11af | 811 | |
dc1c1ca3 SR |
812 | if (reason & REASON_FP) { |
813 | /* IEEE FP exception */ | |
814 | parse_fpe(regs); | |
8dad3f92 PM |
815 | return; |
816 | } | |
817 | if (reason & REASON_TRAP) { | |
14cf11af | 818 | /* trap exception */ |
dc1c1ca3 SR |
819 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
820 | == NOTIFY_STOP) | |
821 | return; | |
14cf11af PM |
822 | if (debugger_bpt(regs)) |
823 | return; | |
73c9ceab JF |
824 | |
825 | if (!(regs->msr & MSR_PR) && /* not user-mode */ | |
608e2619 | 826 | report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) { |
14cf11af PM |
827 | regs->nip += 4; |
828 | return; | |
829 | } | |
8dad3f92 PM |
830 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
831 | return; | |
832 | } | |
833 | ||
cd8a5673 PM |
834 | local_irq_enable(); |
835 | ||
04903a30 KG |
836 | #ifdef CONFIG_MATH_EMULATION |
837 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, | |
838 | * but there seems to be a hardware bug on the 405GP (RevD) | |
839 | * that means ESR is sometimes set incorrectly - either to | |
840 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
841 | * hardware people - not sure if it can happen on any illegal | |
842 | * instruction or only on FP instructions, whether there is a | |
843 | * pattern to occurences etc. -dgibson 31/Mar/2003 */ | |
5fad293b KG |
844 | switch (do_mathemu(regs)) { |
845 | case 0: | |
04903a30 KG |
846 | emulate_single_step(regs); |
847 | return; | |
5fad293b KG |
848 | case 1: { |
849 | int code = 0; | |
850 | code = __parse_fpscr(current->thread.fpscr.val); | |
851 | _exception(SIGFPE, regs, code, regs->nip); | |
852 | return; | |
853 | } | |
854 | case -EFAULT: | |
855 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
856 | return; | |
04903a30 | 857 | } |
5fad293b | 858 | /* fall through on any other errors */ |
04903a30 KG |
859 | #endif /* CONFIG_MATH_EMULATION */ |
860 | ||
8dad3f92 PM |
861 | /* Try to emulate it if we should. */ |
862 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
14cf11af PM |
863 | switch (emulate_instruction(regs)) { |
864 | case 0: | |
865 | regs->nip += 4; | |
866 | emulate_single_step(regs); | |
8dad3f92 | 867 | return; |
14cf11af PM |
868 | case -EFAULT: |
869 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
8dad3f92 | 870 | return; |
14cf11af PM |
871 | } |
872 | } | |
8dad3f92 PM |
873 | |
874 | if (reason & REASON_PRIVILEGED) | |
875 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
876 | else | |
877 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
14cf11af PM |
878 | } |
879 | ||
dc1c1ca3 | 880 | void alignment_exception(struct pt_regs *regs) |
14cf11af | 881 | { |
4393c4f6 | 882 | int sig, code, fixed = 0; |
14cf11af | 883 | |
e9370ae1 PM |
884 | /* we don't implement logging of alignment exceptions */ |
885 | if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) | |
886 | fixed = fix_alignment(regs); | |
14cf11af PM |
887 | |
888 | if (fixed == 1) { | |
889 | regs->nip += 4; /* skip over emulated instruction */ | |
890 | emulate_single_step(regs); | |
891 | return; | |
892 | } | |
893 | ||
dc1c1ca3 | 894 | /* Operand address was bad */ |
14cf11af | 895 | if (fixed == -EFAULT) { |
4393c4f6 BH |
896 | sig = SIGSEGV; |
897 | code = SEGV_ACCERR; | |
898 | } else { | |
899 | sig = SIGBUS; | |
900 | code = BUS_ADRALN; | |
14cf11af | 901 | } |
4393c4f6 BH |
902 | if (user_mode(regs)) |
903 | _exception(sig, regs, code, regs->dar); | |
904 | else | |
905 | bad_page_fault(regs, regs->dar, sig); | |
14cf11af PM |
906 | } |
907 | ||
908 | void StackOverflow(struct pt_regs *regs) | |
909 | { | |
910 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
911 | current, regs->gpr[1]); | |
912 | debugger(regs); | |
913 | show_regs(regs); | |
914 | panic("kernel stack overflow"); | |
915 | } | |
916 | ||
917 | void nonrecoverable_exception(struct pt_regs *regs) | |
918 | { | |
919 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
920 | regs->nip, regs->msr); | |
921 | debugger(regs); | |
922 | die("nonrecoverable exception", regs, SIGKILL); | |
923 | } | |
924 | ||
925 | void trace_syscall(struct pt_regs *regs) | |
926 | { | |
927 | printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n", | |
19c5870c | 928 | current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0], |
14cf11af PM |
929 | regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted()); |
930 | } | |
dc1c1ca3 | 931 | |
dc1c1ca3 SR |
932 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
933 | { | |
934 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " | |
935 | "%lx at %lx\n", regs->trap, regs->nip); | |
936 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); | |
937 | } | |
dc1c1ca3 SR |
938 | |
939 | void altivec_unavailable_exception(struct pt_regs *regs) | |
940 | { | |
dc1c1ca3 SR |
941 | if (user_mode(regs)) { |
942 | /* A user program has executed an altivec instruction, | |
943 | but this kernel doesn't support altivec. */ | |
944 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
945 | return; | |
946 | } | |
6c4841c2 | 947 | |
dc1c1ca3 SR |
948 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
949 | "%lx at %lx\n", regs->trap, regs->nip); | |
950 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); | |
dc1c1ca3 SR |
951 | } |
952 | ||
ce48b210 MN |
953 | void vsx_unavailable_exception(struct pt_regs *regs) |
954 | { | |
955 | if (user_mode(regs)) { | |
956 | /* A user program has executed an vsx instruction, | |
957 | but this kernel doesn't support vsx. */ | |
958 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
959 | return; | |
960 | } | |
961 | ||
962 | printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " | |
963 | "%lx at %lx\n", regs->trap, regs->nip); | |
964 | die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); | |
965 | } | |
966 | ||
dc1c1ca3 SR |
967 | void performance_monitor_exception(struct pt_regs *regs) |
968 | { | |
89713ed1 AB |
969 | __get_cpu_var(irq_stat).pmu_irqs++; |
970 | ||
dc1c1ca3 SR |
971 | perf_irq(regs); |
972 | } | |
dc1c1ca3 | 973 | |
8dad3f92 | 974 | #ifdef CONFIG_8xx |
14cf11af PM |
975 | void SoftwareEmulation(struct pt_regs *regs) |
976 | { | |
977 | extern int do_mathemu(struct pt_regs *); | |
978 | extern int Soft_emulate_8xx(struct pt_regs *); | |
5dd57a13 | 979 | #if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU) |
14cf11af | 980 | int errcode; |
5dd57a13 | 981 | #endif |
14cf11af PM |
982 | |
983 | CHECK_FULL_REGS(regs); | |
984 | ||
985 | if (!user_mode(regs)) { | |
986 | debugger(regs); | |
987 | die("Kernel Mode Software FPU Emulation", regs, SIGFPE); | |
988 | } | |
989 | ||
990 | #ifdef CONFIG_MATH_EMULATION | |
991 | errcode = do_mathemu(regs); | |
80947e7c | 992 | if (errcode >= 0) |
eecff81d | 993 | PPC_WARN_EMULATED(math, regs); |
5fad293b KG |
994 | |
995 | switch (errcode) { | |
996 | case 0: | |
997 | emulate_single_step(regs); | |
998 | return; | |
999 | case 1: { | |
1000 | int code = 0; | |
1001 | code = __parse_fpscr(current->thread.fpscr.val); | |
1002 | _exception(SIGFPE, regs, code, regs->nip); | |
1003 | return; | |
1004 | } | |
1005 | case -EFAULT: | |
1006 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1007 | return; | |
1008 | default: | |
1009 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1010 | return; | |
1011 | } | |
1012 | ||
5dd57a13 | 1013 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) |
14cf11af | 1014 | errcode = Soft_emulate_8xx(regs); |
80947e7c | 1015 | if (errcode >= 0) |
eecff81d | 1016 | PPC_WARN_EMULATED(8xx, regs); |
80947e7c | 1017 | |
5fad293b KG |
1018 | switch (errcode) { |
1019 | case 0: | |
14cf11af | 1020 | emulate_single_step(regs); |
5fad293b KG |
1021 | return; |
1022 | case 1: | |
1023 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1024 | return; | |
1025 | case -EFAULT: | |
1026 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1027 | return; | |
1028 | } | |
5dd57a13 SW |
1029 | #else |
1030 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
5fad293b | 1031 | #endif |
14cf11af | 1032 | } |
8dad3f92 | 1033 | #endif /* CONFIG_8xx */ |
14cf11af | 1034 | |
172ae2e7 | 1035 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3bffb652 DK |
1036 | static void handle_debug(struct pt_regs *regs, unsigned long debug_status) |
1037 | { | |
1038 | int changed = 0; | |
1039 | /* | |
1040 | * Determine the cause of the debug event, clear the | |
1041 | * event flags and send a trap to the handler. Torez | |
1042 | */ | |
1043 | if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { | |
1044 | dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); | |
1045 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
1046 | current->thread.dbcr2 &= ~DBCR2_DAC12MODE; | |
1047 | #endif | |
1048 | do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, | |
1049 | 5); | |
1050 | changed |= 0x01; | |
1051 | } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { | |
1052 | dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); | |
1053 | do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT, | |
1054 | 6); | |
1055 | changed |= 0x01; | |
1056 | } else if (debug_status & DBSR_IAC1) { | |
1057 | current->thread.dbcr0 &= ~DBCR0_IAC1; | |
1058 | dbcr_iac_range(current) &= ~DBCR_IAC12MODE; | |
1059 | do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, | |
1060 | 1); | |
1061 | changed |= 0x01; | |
1062 | } else if (debug_status & DBSR_IAC2) { | |
1063 | current->thread.dbcr0 &= ~DBCR0_IAC2; | |
1064 | do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, | |
1065 | 2); | |
1066 | changed |= 0x01; | |
1067 | } else if (debug_status & DBSR_IAC3) { | |
1068 | current->thread.dbcr0 &= ~DBCR0_IAC3; | |
1069 | dbcr_iac_range(current) &= ~DBCR_IAC34MODE; | |
1070 | do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, | |
1071 | 3); | |
1072 | changed |= 0x01; | |
1073 | } else if (debug_status & DBSR_IAC4) { | |
1074 | current->thread.dbcr0 &= ~DBCR0_IAC4; | |
1075 | do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, | |
1076 | 4); | |
1077 | changed |= 0x01; | |
1078 | } | |
1079 | /* | |
1080 | * At the point this routine was called, the MSR(DE) was turned off. | |
1081 | * Check all other debug flags and see if that bit needs to be turned | |
1082 | * back on or not. | |
1083 | */ | |
1084 | if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1)) | |
1085 | regs->msr |= MSR_DE; | |
1086 | else | |
1087 | /* Make sure the IDM flag is off */ | |
1088 | current->thread.dbcr0 &= ~DBCR0_IDM; | |
1089 | ||
1090 | if (changed & 0x01) | |
1091 | mtspr(SPRN_DBCR0, current->thread.dbcr0); | |
1092 | } | |
14cf11af | 1093 | |
f8279621 | 1094 | void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) |
14cf11af | 1095 | { |
3bffb652 DK |
1096 | current->thread.dbsr = debug_status; |
1097 | ||
ec097c84 RM |
1098 | /* Hack alert: On BookE, Branch Taken stops on the branch itself, while |
1099 | * on server, it stops on the target of the branch. In order to simulate | |
1100 | * the server behaviour, we thus restart right away with a single step | |
1101 | * instead of stopping here when hitting a BT | |
1102 | */ | |
1103 | if (debug_status & DBSR_BT) { | |
1104 | regs->msr &= ~MSR_DE; | |
1105 | ||
1106 | /* Disable BT */ | |
1107 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); | |
1108 | /* Clear the BT event */ | |
1109 | mtspr(SPRN_DBSR, DBSR_BT); | |
1110 | ||
1111 | /* Do the single step trick only when coming from userspace */ | |
1112 | if (user_mode(regs)) { | |
1113 | current->thread.dbcr0 &= ~DBCR0_BT; | |
1114 | current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
1115 | regs->msr |= MSR_DE; | |
1116 | return; | |
1117 | } | |
1118 | ||
1119 | if (notify_die(DIE_SSTEP, "block_step", regs, 5, | |
1120 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1121 | return; | |
1122 | } | |
1123 | if (debugger_sstep(regs)) | |
1124 | return; | |
1125 | } else if (debug_status & DBSR_IC) { /* Instruction complete */ | |
14cf11af | 1126 | regs->msr &= ~MSR_DE; |
f8279621 KG |
1127 | |
1128 | /* Disable instruction completion */ | |
1129 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
1130 | /* Clear the instruction completion event */ | |
1131 | mtspr(SPRN_DBSR, DBSR_IC); | |
1132 | ||
1133 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, | |
1134 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1135 | return; | |
1136 | } | |
1137 | ||
1138 | if (debugger_sstep(regs)) | |
1139 | return; | |
1140 | ||
d6a61bfc | 1141 | if (user_mode(regs)) { |
3bffb652 DK |
1142 | current->thread.dbcr0 &= ~DBCR0_IC; |
1143 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS | |
1144 | if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, | |
1145 | current->thread.dbcr1)) | |
1146 | regs->msr |= MSR_DE; | |
1147 | else | |
1148 | /* Make sure the IDM bit is off */ | |
1149 | current->thread.dbcr0 &= ~DBCR0_IDM; | |
1150 | #endif | |
d6a61bfc | 1151 | } |
3bffb652 DK |
1152 | |
1153 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
1154 | } else | |
1155 | handle_debug(regs, debug_status); | |
14cf11af | 1156 | } |
172ae2e7 | 1157 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
14cf11af PM |
1158 | |
1159 | #if !defined(CONFIG_TAU_INT) | |
1160 | void TAUException(struct pt_regs *regs) | |
1161 | { | |
1162 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
1163 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
1164 | } | |
1165 | #endif /* CONFIG_INT_TAU */ | |
14cf11af PM |
1166 | |
1167 | #ifdef CONFIG_ALTIVEC | |
dc1c1ca3 | 1168 | void altivec_assist_exception(struct pt_regs *regs) |
14cf11af PM |
1169 | { |
1170 | int err; | |
1171 | ||
14cf11af PM |
1172 | if (!user_mode(regs)) { |
1173 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" | |
1174 | " at %lx\n", regs->nip); | |
8dad3f92 | 1175 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
14cf11af PM |
1176 | } |
1177 | ||
dc1c1ca3 | 1178 | flush_altivec_to_thread(current); |
dc1c1ca3 | 1179 | |
eecff81d | 1180 | PPC_WARN_EMULATED(altivec, regs); |
14cf11af PM |
1181 | err = emulate_altivec(regs); |
1182 | if (err == 0) { | |
1183 | regs->nip += 4; /* skip emulated instruction */ | |
1184 | emulate_single_step(regs); | |
1185 | return; | |
1186 | } | |
1187 | ||
1188 | if (err == -EFAULT) { | |
1189 | /* got an error reading the instruction */ | |
1190 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1191 | } else { | |
1192 | /* didn't recognize the instruction */ | |
1193 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
1194 | if (printk_ratelimit()) | |
1195 | printk(KERN_ERR "Unrecognized altivec instruction " | |
1196 | "in %s at %lx\n", current->comm, regs->nip); | |
1197 | current->thread.vscr.u[3] |= 0x10000; | |
1198 | } | |
1199 | } | |
1200 | #endif /* CONFIG_ALTIVEC */ | |
1201 | ||
ce48b210 MN |
1202 | #ifdef CONFIG_VSX |
1203 | void vsx_assist_exception(struct pt_regs *regs) | |
1204 | { | |
1205 | if (!user_mode(regs)) { | |
1206 | printk(KERN_EMERG "VSX assist exception in kernel mode" | |
1207 | " at %lx\n", regs->nip); | |
1208 | die("Kernel VSX assist exception", regs, SIGILL); | |
1209 | } | |
1210 | ||
1211 | flush_vsx_to_thread(current); | |
1212 | printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip); | |
1213 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1214 | } | |
1215 | #endif /* CONFIG_VSX */ | |
1216 | ||
14cf11af | 1217 | #ifdef CONFIG_FSL_BOOKE |
620165f9 KG |
1218 | |
1219 | void doorbell_exception(struct pt_regs *regs) | |
1220 | { | |
1221 | #ifdef CONFIG_SMP | |
1222 | int cpu = smp_processor_id(); | |
1223 | int msg; | |
1224 | ||
1225 | if (num_online_cpus() < 2) | |
1226 | return; | |
1227 | ||
1228 | for (msg = 0; msg < 4; msg++) | |
1229 | if (test_and_clear_bit(msg, &dbell_smp_message[cpu])) | |
1230 | smp_message_recv(msg); | |
1231 | #else | |
1232 | printk(KERN_WARNING "Received doorbell on non-smp system\n"); | |
1233 | #endif | |
1234 | } | |
1235 | ||
14cf11af PM |
1236 | void CacheLockingException(struct pt_regs *regs, unsigned long address, |
1237 | unsigned long error_code) | |
1238 | { | |
1239 | /* We treat cache locking instructions from the user | |
1240 | * as priv ops, in the future we could try to do | |
1241 | * something smarter | |
1242 | */ | |
1243 | if (error_code & (ESR_DLK|ESR_ILK)) | |
1244 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1245 | return; | |
1246 | } | |
1247 | #endif /* CONFIG_FSL_BOOKE */ | |
1248 | ||
1249 | #ifdef CONFIG_SPE | |
1250 | void SPEFloatingPointException(struct pt_regs *regs) | |
1251 | { | |
6a800f36 | 1252 | extern int do_spe_mathemu(struct pt_regs *regs); |
14cf11af PM |
1253 | unsigned long spefscr; |
1254 | int fpexc_mode; | |
1255 | int code = 0; | |
6a800f36 LY |
1256 | int err; |
1257 | ||
1258 | preempt_disable(); | |
1259 | if (regs->msr & MSR_SPE) | |
1260 | giveup_spe(current); | |
1261 | preempt_enable(); | |
14cf11af PM |
1262 | |
1263 | spefscr = current->thread.spefscr; | |
1264 | fpexc_mode = current->thread.fpexc_mode; | |
1265 | ||
14cf11af PM |
1266 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { |
1267 | code = FPE_FLTOVF; | |
14cf11af PM |
1268 | } |
1269 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
1270 | code = FPE_FLTUND; | |
14cf11af PM |
1271 | } |
1272 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
1273 | code = FPE_FLTDIV; | |
1274 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
1275 | code = FPE_FLTINV; | |
14cf11af PM |
1276 | } |
1277 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
1278 | code = FPE_FLTRES; | |
1279 | ||
6a800f36 LY |
1280 | err = do_spe_mathemu(regs); |
1281 | if (err == 0) { | |
1282 | regs->nip += 4; /* skip emulated instruction */ | |
1283 | emulate_single_step(regs); | |
1284 | return; | |
1285 | } | |
1286 | ||
1287 | if (err == -EFAULT) { | |
1288 | /* got an error reading the instruction */ | |
1289 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1290 | } else if (err == -EINVAL) { | |
1291 | /* didn't recognize the instruction */ | |
1292 | printk(KERN_ERR "unrecognized spe instruction " | |
1293 | "in %s at %lx\n", current->comm, regs->nip); | |
1294 | } else { | |
1295 | _exception(SIGFPE, regs, code, regs->nip); | |
1296 | } | |
14cf11af | 1297 | |
14cf11af PM |
1298 | return; |
1299 | } | |
6a800f36 LY |
1300 | |
1301 | void SPEFloatingPointRoundException(struct pt_regs *regs) | |
1302 | { | |
1303 | extern int speround_handler(struct pt_regs *regs); | |
1304 | int err; | |
1305 | ||
1306 | preempt_disable(); | |
1307 | if (regs->msr & MSR_SPE) | |
1308 | giveup_spe(current); | |
1309 | preempt_enable(); | |
1310 | ||
1311 | regs->nip -= 4; | |
1312 | err = speround_handler(regs); | |
1313 | if (err == 0) { | |
1314 | regs->nip += 4; /* skip emulated instruction */ | |
1315 | emulate_single_step(regs); | |
1316 | return; | |
1317 | } | |
1318 | ||
1319 | if (err == -EFAULT) { | |
1320 | /* got an error reading the instruction */ | |
1321 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1322 | } else if (err == -EINVAL) { | |
1323 | /* didn't recognize the instruction */ | |
1324 | printk(KERN_ERR "unrecognized spe instruction " | |
1325 | "in %s at %lx\n", current->comm, regs->nip); | |
1326 | } else { | |
1327 | _exception(SIGFPE, regs, 0, regs->nip); | |
1328 | return; | |
1329 | } | |
1330 | } | |
14cf11af PM |
1331 | #endif |
1332 | ||
dc1c1ca3 SR |
1333 | /* |
1334 | * We enter here if we get an unrecoverable exception, that is, one | |
1335 | * that happened at a point where the RI (recoverable interrupt) bit | |
1336 | * in the MSR is 0. This indicates that SRR0/1 are live, and that | |
1337 | * we therefore lost state by taking this exception. | |
1338 | */ | |
1339 | void unrecoverable_exception(struct pt_regs *regs) | |
1340 | { | |
1341 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", | |
1342 | regs->trap, regs->nip); | |
1343 | die("Unrecoverable exception", regs, SIGABRT); | |
1344 | } | |
dc1c1ca3 | 1345 | |
14cf11af PM |
1346 | #ifdef CONFIG_BOOKE_WDT |
1347 | /* | |
1348 | * Default handler for a Watchdog exception, | |
1349 | * spins until a reboot occurs | |
1350 | */ | |
1351 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) | |
1352 | { | |
1353 | /* Generic WatchdogHandler, implement your own */ | |
1354 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); | |
1355 | return; | |
1356 | } | |
1357 | ||
1358 | void WatchdogException(struct pt_regs *regs) | |
1359 | { | |
1360 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); | |
1361 | WatchdogHandler(regs); | |
1362 | } | |
1363 | #endif | |
dc1c1ca3 | 1364 | |
dc1c1ca3 SR |
1365 | /* |
1366 | * We enter here if we discover during exception entry that we are | |
1367 | * running in supervisor mode with a userspace value in the stack pointer. | |
1368 | */ | |
1369 | void kernel_bad_stack(struct pt_regs *regs) | |
1370 | { | |
1371 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", | |
1372 | regs->gpr[1], regs->nip); | |
1373 | die("Bad kernel stack pointer", regs, SIGABRT); | |
1374 | } | |
14cf11af PM |
1375 | |
1376 | void __init trap_init(void) | |
1377 | { | |
1378 | } | |
80947e7c GU |
1379 | |
1380 | ||
1381 | #ifdef CONFIG_PPC_EMULATED_STATS | |
1382 | ||
1383 | #define WARN_EMULATED_SETUP(type) .type = { .name = #type } | |
1384 | ||
1385 | struct ppc_emulated ppc_emulated = { | |
1386 | #ifdef CONFIG_ALTIVEC | |
1387 | WARN_EMULATED_SETUP(altivec), | |
1388 | #endif | |
1389 | WARN_EMULATED_SETUP(dcba), | |
1390 | WARN_EMULATED_SETUP(dcbz), | |
1391 | WARN_EMULATED_SETUP(fp_pair), | |
1392 | WARN_EMULATED_SETUP(isel), | |
1393 | WARN_EMULATED_SETUP(mcrxr), | |
1394 | WARN_EMULATED_SETUP(mfpvr), | |
1395 | WARN_EMULATED_SETUP(multiple), | |
1396 | WARN_EMULATED_SETUP(popcntb), | |
1397 | WARN_EMULATED_SETUP(spe), | |
1398 | WARN_EMULATED_SETUP(string), | |
1399 | WARN_EMULATED_SETUP(unaligned), | |
1400 | #ifdef CONFIG_MATH_EMULATION | |
1401 | WARN_EMULATED_SETUP(math), | |
1402 | #elif defined(CONFIG_8XX_MINIMAL_FPEMU) | |
1403 | WARN_EMULATED_SETUP(8xx), | |
1404 | #endif | |
1405 | #ifdef CONFIG_VSX | |
1406 | WARN_EMULATED_SETUP(vsx), | |
1407 | #endif | |
1408 | }; | |
1409 | ||
1410 | u32 ppc_warn_emulated; | |
1411 | ||
1412 | void ppc_warn_emulated_print(const char *type) | |
1413 | { | |
1414 | if (printk_ratelimit()) | |
1415 | pr_warning("%s used emulated %s instruction\n", current->comm, | |
1416 | type); | |
1417 | } | |
1418 | ||
1419 | static int __init ppc_warn_emulated_init(void) | |
1420 | { | |
1421 | struct dentry *dir, *d; | |
1422 | unsigned int i; | |
1423 | struct ppc_emulated_entry *entries = (void *)&ppc_emulated; | |
1424 | ||
1425 | if (!powerpc_debugfs_root) | |
1426 | return -ENODEV; | |
1427 | ||
1428 | dir = debugfs_create_dir("emulated_instructions", | |
1429 | powerpc_debugfs_root); | |
1430 | if (!dir) | |
1431 | return -ENOMEM; | |
1432 | ||
1433 | d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir, | |
1434 | &ppc_warn_emulated); | |
1435 | if (!d) | |
1436 | goto fail; | |
1437 | ||
1438 | for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { | |
1439 | d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir, | |
1440 | (u32 *)&entries[i].val.counter); | |
1441 | if (!d) | |
1442 | goto fail; | |
1443 | } | |
1444 | ||
1445 | return 0; | |
1446 | ||
1447 | fail: | |
1448 | debugfs_remove_recursive(dir); | |
1449 | return -ENOMEM; | |
1450 | } | |
1451 | ||
1452 | device_initcall(ppc_warn_emulated_init); | |
1453 | ||
1454 | #endif /* CONFIG_PPC_EMULATED_STATS */ |