Commit | Line | Data |
---|---|---|
14cf11af | 1 | /* |
14cf11af | 2 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
fe04b112 | 3 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
14cf11af PM |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | * | |
10 | * Modified by Cort Dougan (cort@cs.nmt.edu) | |
11 | * and Paul Mackerras (paulus@samba.org) | |
12 | */ | |
13 | ||
14 | /* | |
15 | * This file handles the architecture-dependent parts of hardware exceptions | |
16 | */ | |
17 | ||
14cf11af PM |
18 | #include <linux/errno.h> |
19 | #include <linux/sched.h> | |
b17b0153 | 20 | #include <linux/sched/debug.h> |
14cf11af PM |
21 | #include <linux/kernel.h> |
22 | #include <linux/mm.h> | |
99cd1302 | 23 | #include <linux/pkeys.h> |
14cf11af PM |
24 | #include <linux/stddef.h> |
25 | #include <linux/unistd.h> | |
8dad3f92 | 26 | #include <linux/ptrace.h> |
14cf11af | 27 | #include <linux/user.h> |
14cf11af | 28 | #include <linux/interrupt.h> |
14cf11af | 29 | #include <linux/init.h> |
8a39b05f PG |
30 | #include <linux/extable.h> |
31 | #include <linux/module.h> /* print_modules */ | |
8dad3f92 | 32 | #include <linux/prctl.h> |
14cf11af PM |
33 | #include <linux/delay.h> |
34 | #include <linux/kprobes.h> | |
cc532915 | 35 | #include <linux/kexec.h> |
5474c120 | 36 | #include <linux/backlight.h> |
73c9ceab | 37 | #include <linux/bug.h> |
1eeb66a1 | 38 | #include <linux/kdebug.h> |
76462232 | 39 | #include <linux/ratelimit.h> |
ba12eede | 40 | #include <linux/context_tracking.h> |
5080332c | 41 | #include <linux/smp.h> |
35adacd6 NP |
42 | #include <linux/console.h> |
43 | #include <linux/kmsg_dump.h> | |
14cf11af | 44 | |
80947e7c | 45 | #include <asm/emulated_ops.h> |
14cf11af | 46 | #include <asm/pgtable.h> |
7c0f6ba6 | 47 | #include <linux/uaccess.h> |
7644d581 | 48 | #include <asm/debugfs.h> |
14cf11af | 49 | #include <asm/io.h> |
86417780 PM |
50 | #include <asm/machdep.h> |
51 | #include <asm/rtas.h> | |
f7f6f4fe | 52 | #include <asm/pmc.h> |
14cf11af | 53 | #include <asm/reg.h> |
14cf11af PM |
54 | #ifdef CONFIG_PMAC_BACKLIGHT |
55 | #include <asm/backlight.h> | |
56 | #endif | |
dc1c1ca3 | 57 | #ifdef CONFIG_PPC64 |
86417780 | 58 | #include <asm/firmware.h> |
dc1c1ca3 | 59 | #include <asm/processor.h> |
6ce6c629 | 60 | #include <asm/tm.h> |
dc1c1ca3 | 61 | #endif |
c0ce7d08 | 62 | #include <asm/kexec.h> |
16c57b36 | 63 | #include <asm/ppc-opcode.h> |
cce1f106 | 64 | #include <asm/rio.h> |
ebaeb5ae | 65 | #include <asm/fadump.h> |
ae3a197e | 66 | #include <asm/switch_to.h> |
f54db641 | 67 | #include <asm/tm.h> |
ae3a197e | 68 | #include <asm/debug.h> |
42f5b4ca | 69 | #include <asm/asm-prototypes.h> |
fd7bacbc | 70 | #include <asm/hmi.h> |
4e0e3435 | 71 | #include <sysdev/fsl_pci.h> |
6cc89bad | 72 | #include <asm/kprobes.h> |
dc1c1ca3 | 73 | |
da665885 | 74 | #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE) |
5be3492f AB |
75 | int (*__debugger)(struct pt_regs *regs) __read_mostly; |
76 | int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly; | |
77 | int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly; | |
78 | int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly; | |
79 | int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly; | |
9422de3e | 80 | int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly; |
5be3492f | 81 | int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly; |
14cf11af PM |
82 | |
83 | EXPORT_SYMBOL(__debugger); | |
84 | EXPORT_SYMBOL(__debugger_ipi); | |
85 | EXPORT_SYMBOL(__debugger_bpt); | |
86 | EXPORT_SYMBOL(__debugger_sstep); | |
87 | EXPORT_SYMBOL(__debugger_iabr_match); | |
9422de3e | 88 | EXPORT_SYMBOL(__debugger_break_match); |
14cf11af PM |
89 | EXPORT_SYMBOL(__debugger_fault_handler); |
90 | #endif | |
91 | ||
8b3c34cf MN |
92 | /* Transactional Memory trap debug */ |
93 | #ifdef TM_DEBUG_SW | |
94 | #define TM_DEBUG(x...) printk(KERN_INFO x) | |
95 | #else | |
96 | #define TM_DEBUG(x...) do { } while(0) | |
97 | #endif | |
98 | ||
14cf11af PM |
99 | /* |
100 | * Trap & Exception support | |
101 | */ | |
102 | ||
6031d9d9 | 103 | #ifdef CONFIG_PMAC_BACKLIGHT |
104 | static void pmac_backlight_unblank(void) | |
105 | { | |
106 | mutex_lock(&pmac_backlight_mutex); | |
107 | if (pmac_backlight) { | |
108 | struct backlight_properties *props; | |
109 | ||
110 | props = &pmac_backlight->props; | |
111 | props->brightness = props->max_brightness; | |
112 | props->power = FB_BLANK_UNBLANK; | |
113 | backlight_update_status(pmac_backlight); | |
114 | } | |
115 | mutex_unlock(&pmac_backlight_mutex); | |
116 | } | |
117 | #else | |
118 | static inline void pmac_backlight_unblank(void) { } | |
119 | #endif | |
120 | ||
6fcd6baa NP |
121 | /* |
122 | * If oops/die is expected to crash the machine, return true here. | |
123 | * | |
124 | * This should not be expected to be 100% accurate, there may be | |
125 | * notifiers registered or other unexpected conditions that may bring | |
126 | * down the kernel. Or if the current process in the kernel is holding | |
127 | * locks or has other critical state, the kernel may become effectively | |
128 | * unusable anyway. | |
129 | */ | |
130 | bool die_will_crash(void) | |
131 | { | |
132 | if (should_fadump_crash()) | |
133 | return true; | |
134 | if (kexec_should_crash(current)) | |
135 | return true; | |
136 | if (in_interrupt() || panic_on_oops || | |
137 | !current->pid || is_global_init(current)) | |
138 | return true; | |
139 | ||
140 | return false; | |
141 | } | |
142 | ||
760ca4dc AB |
143 | static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED; |
144 | static int die_owner = -1; | |
145 | static unsigned int die_nest_count; | |
146 | static int die_counter; | |
147 | ||
35adacd6 NP |
148 | extern void panic_flush_kmsg_start(void) |
149 | { | |
150 | /* | |
151 | * These are mostly taken from kernel/panic.c, but tries to do | |
152 | * relatively minimal work. Don't use delay functions (TB may | |
153 | * be broken), don't crash dump (need to set a firmware log), | |
154 | * don't run notifiers. We do want to get some information to | |
155 | * Linux console. | |
156 | */ | |
157 | console_verbose(); | |
158 | bust_spinlocks(1); | |
159 | } | |
160 | ||
161 | extern void panic_flush_kmsg_end(void) | |
162 | { | |
163 | printk_safe_flush_on_panic(); | |
164 | kmsg_dump(KMSG_DUMP_PANIC); | |
165 | bust_spinlocks(0); | |
166 | debug_locks_off(); | |
167 | console_flush_on_panic(); | |
168 | } | |
169 | ||
03465f89 | 170 | static unsigned long oops_begin(struct pt_regs *regs) |
14cf11af | 171 | { |
760ca4dc | 172 | int cpu; |
34c2a14f | 173 | unsigned long flags; |
14cf11af | 174 | |
293e4688 | 175 | oops_enter(); |
176 | ||
760ca4dc AB |
177 | /* racy, but better than risking deadlock. */ |
178 | raw_local_irq_save(flags); | |
179 | cpu = smp_processor_id(); | |
180 | if (!arch_spin_trylock(&die_lock)) { | |
181 | if (cpu == die_owner) | |
182 | /* nested oops. should stop eventually */; | |
183 | else | |
184 | arch_spin_lock(&die_lock); | |
34c2a14f | 185 | } |
760ca4dc AB |
186 | die_nest_count++; |
187 | die_owner = cpu; | |
188 | console_verbose(); | |
189 | bust_spinlocks(1); | |
190 | if (machine_is(powermac)) | |
191 | pmac_backlight_unblank(); | |
192 | return flags; | |
193 | } | |
03465f89 | 194 | NOKPROBE_SYMBOL(oops_begin); |
e8222502 | 195 | |
03465f89 | 196 | static void oops_end(unsigned long flags, struct pt_regs *regs, |
760ca4dc AB |
197 | int signr) |
198 | { | |
14cf11af | 199 | bust_spinlocks(0); |
373d4d09 | 200 | add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); |
760ca4dc | 201 | die_nest_count--; |
58154c8c AB |
202 | oops_exit(); |
203 | printk("\n"); | |
7458e8b2 | 204 | if (!die_nest_count) { |
760ca4dc | 205 | /* Nest count reaches zero, release the lock. */ |
7458e8b2 | 206 | die_owner = -1; |
760ca4dc | 207 | arch_spin_unlock(&die_lock); |
7458e8b2 | 208 | } |
760ca4dc | 209 | raw_local_irq_restore(flags); |
cc532915 | 210 | |
ebaeb5ae MS |
211 | crash_fadump(regs, "die oops"); |
212 | ||
4388c9b3 | 213 | if (kexec_should_crash(current)) |
cc532915 | 214 | crash_kexec(regs); |
9b00ac06 | 215 | |
760ca4dc AB |
216 | if (!signr) |
217 | return; | |
218 | ||
58154c8c AB |
219 | /* |
220 | * While our oops output is serialised by a spinlock, output | |
221 | * from panic() called below can race and corrupt it. If we | |
222 | * know we are going to panic, delay for 1 second so we have a | |
223 | * chance to get clean backtraces from all CPUs that are oopsing. | |
224 | */ | |
225 | if (in_interrupt() || panic_on_oops || !current->pid || | |
226 | is_global_init(current)) { | |
227 | mdelay(MSEC_PER_SEC); | |
228 | } | |
229 | ||
14cf11af PM |
230 | if (in_interrupt()) |
231 | panic("Fatal exception in interrupt"); | |
cea6a4ba | 232 | if (panic_on_oops) |
012c437d | 233 | panic("Fatal exception"); |
760ca4dc AB |
234 | do_exit(signr); |
235 | } | |
03465f89 | 236 | NOKPROBE_SYMBOL(oops_end); |
cea6a4ba | 237 | |
03465f89 | 238 | static int __die(const char *str, struct pt_regs *regs, long err) |
760ca4dc AB |
239 | { |
240 | printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter); | |
2e82ca3c ME |
241 | |
242 | if (IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN)) | |
243 | printk("LE "); | |
244 | else | |
245 | printk("BE "); | |
246 | ||
1c56cd8e ME |
247 | if (IS_ENABLED(CONFIG_PREEMPT)) |
248 | pr_cont("PREEMPT "); | |
249 | ||
250 | if (IS_ENABLED(CONFIG_SMP)) | |
251 | pr_cont("SMP NR_CPUS=%d ", NR_CPUS); | |
252 | ||
e7df0d88 | 253 | if (debug_pagealloc_enabled()) |
72c0d9ee | 254 | pr_cont("DEBUG_PAGEALLOC "); |
1c56cd8e ME |
255 | |
256 | if (IS_ENABLED(CONFIG_NUMA)) | |
257 | pr_cont("NUMA "); | |
258 | ||
72c0d9ee | 259 | pr_cont("%s\n", ppc_md.name ? ppc_md.name : ""); |
760ca4dc AB |
260 | |
261 | if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP) | |
262 | return 1; | |
263 | ||
264 | print_modules(); | |
265 | show_regs(regs); | |
14cf11af PM |
266 | |
267 | return 0; | |
268 | } | |
03465f89 | 269 | NOKPROBE_SYMBOL(__die); |
14cf11af | 270 | |
760ca4dc AB |
271 | void die(const char *str, struct pt_regs *regs, long err) |
272 | { | |
6f44b20e NP |
273 | unsigned long flags; |
274 | ||
275 | if (debugger(regs)) | |
276 | return; | |
760ca4dc | 277 | |
6f44b20e | 278 | flags = oops_begin(regs); |
760ca4dc AB |
279 | if (__die(str, regs, err)) |
280 | err = 0; | |
281 | oops_end(flags, regs, err); | |
282 | } | |
15770a13 | 283 | NOKPROBE_SYMBOL(die); |
760ca4dc | 284 | |
25baa35b ON |
285 | void user_single_step_siginfo(struct task_struct *tsk, |
286 | struct pt_regs *regs, siginfo_t *info) | |
287 | { | |
288 | memset(info, 0, sizeof(*info)); | |
289 | info->si_signo = SIGTRAP; | |
290 | info->si_code = TRAP_TRACE; | |
291 | info->si_addr = (void __user *)regs->nip; | |
292 | } | |
293 | ||
99cd1302 RP |
294 | |
295 | void _exception_pkey(int signr, struct pt_regs *regs, int code, | |
296 | unsigned long addr, int key) | |
14cf11af PM |
297 | { |
298 | siginfo_t info; | |
d0c3d534 OJ |
299 | const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \ |
300 | "at %08lx nip %08lx lr %08lx code %x\n"; | |
301 | const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \ | |
302 | "at %016lx nip %016lx lr %016lx code %x\n"; | |
14cf11af PM |
303 | |
304 | if (!user_mode(regs)) { | |
760ca4dc AB |
305 | die("Exception in kernel mode", regs, signr); |
306 | return; | |
307 | } | |
308 | ||
309 | if (show_unhandled_signals && unhandled_signal(current, signr)) { | |
76462232 CD |
310 | printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32, |
311 | current->comm, current->pid, signr, | |
312 | addr, regs->nip, regs->link, code); | |
313 | } | |
14cf11af | 314 | |
a3512b2d | 315 | if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs)) |
9f2f79e3 BH |
316 | local_irq_enable(); |
317 | ||
41ab5266 | 318 | current->thread.trap_nr = code; |
c5cc1f4d TJB |
319 | |
320 | /* | |
321 | * Save all the pkey registers AMR/IAMR/UAMOR. Eg: Core dumps need | |
322 | * to capture the content, if the task gets killed. | |
323 | */ | |
324 | thread_pkey_regs_save(¤t->thread); | |
325 | ||
14cf11af PM |
326 | memset(&info, 0, sizeof(info)); |
327 | info.si_signo = signr; | |
328 | info.si_code = code; | |
329 | info.si_addr = (void __user *) addr; | |
99cd1302 RP |
330 | info.si_pkey = key; |
331 | ||
14cf11af | 332 | force_sig_info(signr, &info, current); |
14cf11af PM |
333 | } |
334 | ||
99cd1302 RP |
335 | void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr) |
336 | { | |
337 | _exception_pkey(signr, regs, code, addr, 0); | |
338 | } | |
339 | ||
14cf11af PM |
340 | void system_reset_exception(struct pt_regs *regs) |
341 | { | |
2b4f3ac5 NP |
342 | /* |
343 | * Avoid crashes in case of nested NMI exceptions. Recoverability | |
344 | * is determined by RI and in_nmi | |
345 | */ | |
346 | bool nested = in_nmi(); | |
347 | if (!nested) | |
348 | nmi_enter(); | |
349 | ||
ca41ad43 NP |
350 | __this_cpu_inc(irq_stat.sreset_irqs); |
351 | ||
14cf11af | 352 | /* See if any machine dependent calls */ |
c902be71 AB |
353 | if (ppc_md.system_reset_exception) { |
354 | if (ppc_md.system_reset_exception(regs)) | |
c4f3b52c | 355 | goto out; |
c902be71 | 356 | } |
14cf11af | 357 | |
4388c9b3 NP |
358 | if (debugger(regs)) |
359 | goto out; | |
360 | ||
361 | /* | |
362 | * A system reset is a request to dump, so we always send | |
363 | * it through the crashdump code (if fadump or kdump are | |
364 | * registered). | |
365 | */ | |
366 | crash_fadump(regs, "System Reset"); | |
367 | ||
368 | crash_kexec(regs); | |
369 | ||
370 | /* | |
371 | * We aren't the primary crash CPU. We need to send it | |
372 | * to a holding pattern to avoid it ending up in the panic | |
373 | * code. | |
374 | */ | |
375 | crash_kexec_secondary(regs); | |
376 | ||
377 | /* | |
378 | * No debugger or crash dump registered, print logs then | |
379 | * panic. | |
380 | */ | |
4552d128 | 381 | die("System Reset", regs, SIGABRT); |
4388c9b3 NP |
382 | |
383 | mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */ | |
384 | add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); | |
385 | nmi_panic(regs, "System Reset"); | |
14cf11af | 386 | |
c4f3b52c NP |
387 | out: |
388 | #ifdef CONFIG_PPC_BOOK3S_64 | |
389 | BUG_ON(get_paca()->in_nmi == 0); | |
390 | if (get_paca()->in_nmi > 1) | |
4388c9b3 | 391 | nmi_panic(regs, "Unrecoverable nested System Reset"); |
c4f3b52c | 392 | #endif |
14cf11af PM |
393 | /* Must die if the interrupt is not recoverable */ |
394 | if (!(regs->msr & MSR_RI)) | |
4388c9b3 | 395 | nmi_panic(regs, "Unrecoverable System Reset"); |
14cf11af | 396 | |
2b4f3ac5 NP |
397 | if (!nested) |
398 | nmi_exit(); | |
399 | ||
14cf11af PM |
400 | /* What should we do here? We could issue a shutdown or hard reset. */ |
401 | } | |
1e9b4507 | 402 | |
14cf11af PM |
403 | /* |
404 | * I/O accesses can cause machine checks on powermacs. | |
405 | * Check if the NIP corresponds to the address of a sync | |
406 | * instruction for which there is an entry in the exception | |
407 | * table. | |
408 | * Note that the 601 only takes a machine check on TEA | |
409 | * (transfer error ack) signal assertion, and does not | |
410 | * set any of the top 16 bits of SRR1. | |
411 | * -- paulus. | |
412 | */ | |
413 | static inline int check_io_access(struct pt_regs *regs) | |
414 | { | |
68a64357 | 415 | #ifdef CONFIG_PPC32 |
14cf11af PM |
416 | unsigned long msr = regs->msr; |
417 | const struct exception_table_entry *entry; | |
418 | unsigned int *nip = (unsigned int *)regs->nip; | |
419 | ||
420 | if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000))) | |
421 | && (entry = search_exception_tables(regs->nip)) != NULL) { | |
422 | /* | |
423 | * Check that it's a sync instruction, or somewhere | |
424 | * in the twi; isync; nop sequence that inb/inw/inl uses. | |
425 | * As the address is in the exception table | |
426 | * we should be able to read the instr there. | |
427 | * For the debug message, we look at the preceding | |
428 | * load or store. | |
429 | */ | |
ddc6cd0d | 430 | if (*nip == PPC_INST_NOP) |
14cf11af | 431 | nip -= 2; |
ddc6cd0d | 432 | else if (*nip == PPC_INST_ISYNC) |
14cf11af | 433 | --nip; |
ddc6cd0d | 434 | if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) { |
14cf11af PM |
435 | unsigned int rb; |
436 | ||
437 | --nip; | |
438 | rb = (*nip >> 11) & 0x1f; | |
439 | printk(KERN_DEBUG "%s bad port %lx at %p\n", | |
440 | (*nip & 0x100)? "OUT to": "IN from", | |
441 | regs->gpr[rb] - _IO_BASE, nip); | |
442 | regs->msr |= MSR_RI; | |
61a92f70 | 443 | regs->nip = extable_fixup(entry); |
14cf11af PM |
444 | return 1; |
445 | } | |
446 | } | |
68a64357 | 447 | #endif /* CONFIG_PPC32 */ |
14cf11af PM |
448 | return 0; |
449 | } | |
450 | ||
172ae2e7 | 451 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
14cf11af PM |
452 | /* On 4xx, the reason for the machine check or program exception |
453 | is in the ESR. */ | |
454 | #define get_reason(regs) ((regs)->dsisr) | |
14cf11af PM |
455 | #define REASON_FP ESR_FP |
456 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) | |
457 | #define REASON_PRIVILEGED ESR_PPR | |
458 | #define REASON_TRAP ESR_PTR | |
459 | ||
460 | /* single-step stuff */ | |
51ae8d4a BB |
461 | #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC) |
462 | #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC) | |
14cf11af PM |
463 | |
464 | #else | |
465 | /* On non-4xx, the reason for the machine check or program | |
466 | exception is in the MSR. */ | |
467 | #define get_reason(regs) ((regs)->msr) | |
d30a5a52 ME |
468 | #define REASON_TM SRR1_PROGTM |
469 | #define REASON_FP SRR1_PROGFPE | |
470 | #define REASON_ILLEGAL SRR1_PROGILL | |
471 | #define REASON_PRIVILEGED SRR1_PROGPRIV | |
472 | #define REASON_TRAP SRR1_PROGTRAP | |
14cf11af PM |
473 | |
474 | #define single_stepping(regs) ((regs)->msr & MSR_SE) | |
475 | #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE) | |
476 | #endif | |
477 | ||
0d0935b3 | 478 | #if defined(CONFIG_E500) |
fe04b112 SW |
479 | int machine_check_e500mc(struct pt_regs *regs) |
480 | { | |
481 | unsigned long mcsr = mfspr(SPRN_MCSR); | |
a4e89ffb | 482 | unsigned long pvr = mfspr(SPRN_PVR); |
fe04b112 SW |
483 | unsigned long reason = mcsr; |
484 | int recoverable = 1; | |
485 | ||
82a9a480 | 486 | if (reason & MCSR_LD) { |
cce1f106 SX |
487 | recoverable = fsl_rio_mcheck_exception(regs); |
488 | if (recoverable == 1) | |
489 | goto silent_out; | |
490 | } | |
491 | ||
fe04b112 SW |
492 | printk("Machine check in kernel mode.\n"); |
493 | printk("Caused by (from MCSR=%lx): ", reason); | |
494 | ||
495 | if (reason & MCSR_MCP) | |
496 | printk("Machine Check Signal\n"); | |
497 | ||
498 | if (reason & MCSR_ICPERR) { | |
499 | printk("Instruction Cache Parity Error\n"); | |
500 | ||
501 | /* | |
502 | * This is recoverable by invalidating the i-cache. | |
503 | */ | |
504 | mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); | |
505 | while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) | |
506 | ; | |
507 | ||
508 | /* | |
509 | * This will generally be accompanied by an instruction | |
510 | * fetch error report -- only treat MCSR_IF as fatal | |
511 | * if it wasn't due to an L1 parity error. | |
512 | */ | |
513 | reason &= ~MCSR_IF; | |
514 | } | |
515 | ||
516 | if (reason & MCSR_DCPERR_MC) { | |
517 | printk("Data Cache Parity Error\n"); | |
37caf9f2 KG |
518 | |
519 | /* | |
520 | * In write shadow mode we auto-recover from the error, but it | |
521 | * may still get logged and cause a machine check. We should | |
522 | * only treat the non-write shadow case as non-recoverable. | |
523 | */ | |
a4e89ffb MW |
524 | /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit |
525 | * is not implemented but L1 data cache always runs in write | |
526 | * shadow mode. Hence on data cache parity errors HW will | |
527 | * automatically invalidate the L1 Data Cache. | |
528 | */ | |
529 | if (PVR_VER(pvr) != PVR_VER_E6500) { | |
530 | if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS)) | |
531 | recoverable = 0; | |
532 | } | |
fe04b112 SW |
533 | } |
534 | ||
535 | if (reason & MCSR_L2MMU_MHIT) { | |
536 | printk("Hit on multiple TLB entries\n"); | |
537 | recoverable = 0; | |
538 | } | |
539 | ||
540 | if (reason & MCSR_NMI) | |
541 | printk("Non-maskable interrupt\n"); | |
542 | ||
543 | if (reason & MCSR_IF) { | |
544 | printk("Instruction Fetch Error Report\n"); | |
545 | recoverable = 0; | |
546 | } | |
547 | ||
548 | if (reason & MCSR_LD) { | |
549 | printk("Load Error Report\n"); | |
550 | recoverable = 0; | |
551 | } | |
552 | ||
553 | if (reason & MCSR_ST) { | |
554 | printk("Store Error Report\n"); | |
555 | recoverable = 0; | |
556 | } | |
557 | ||
558 | if (reason & MCSR_LDG) { | |
559 | printk("Guarded Load Error Report\n"); | |
560 | recoverable = 0; | |
561 | } | |
562 | ||
563 | if (reason & MCSR_TLBSYNC) | |
564 | printk("Simultaneous tlbsync operations\n"); | |
565 | ||
566 | if (reason & MCSR_BSL2_ERR) { | |
567 | printk("Level 2 Cache Error\n"); | |
568 | recoverable = 0; | |
569 | } | |
570 | ||
571 | if (reason & MCSR_MAV) { | |
572 | u64 addr; | |
573 | ||
574 | addr = mfspr(SPRN_MCAR); | |
575 | addr |= (u64)mfspr(SPRN_MCARU) << 32; | |
576 | ||
577 | printk("Machine Check %s Address: %#llx\n", | |
578 | reason & MCSR_MEA ? "Effective" : "Physical", addr); | |
579 | } | |
580 | ||
cce1f106 | 581 | silent_out: |
fe04b112 SW |
582 | mtspr(SPRN_MCSR, mcsr); |
583 | return mfspr(SPRN_MCSR) == 0 && recoverable; | |
584 | } | |
585 | ||
47c0bd1a BH |
586 | int machine_check_e500(struct pt_regs *regs) |
587 | { | |
42bff234 | 588 | unsigned long reason = mfspr(SPRN_MCSR); |
47c0bd1a | 589 | |
cce1f106 SX |
590 | if (reason & MCSR_BUS_RBERR) { |
591 | if (fsl_rio_mcheck_exception(regs)) | |
592 | return 1; | |
4e0e3435 HJ |
593 | if (fsl_pci_mcheck_exception(regs)) |
594 | return 1; | |
cce1f106 SX |
595 | } |
596 | ||
14cf11af PM |
597 | printk("Machine check in kernel mode.\n"); |
598 | printk("Caused by (from MCSR=%lx): ", reason); | |
599 | ||
600 | if (reason & MCSR_MCP) | |
601 | printk("Machine Check Signal\n"); | |
602 | if (reason & MCSR_ICPERR) | |
603 | printk("Instruction Cache Parity Error\n"); | |
604 | if (reason & MCSR_DCP_PERR) | |
605 | printk("Data Cache Push Parity Error\n"); | |
606 | if (reason & MCSR_DCPERR) | |
607 | printk("Data Cache Parity Error\n"); | |
14cf11af PM |
608 | if (reason & MCSR_BUS_IAERR) |
609 | printk("Bus - Instruction Address Error\n"); | |
610 | if (reason & MCSR_BUS_RAERR) | |
611 | printk("Bus - Read Address Error\n"); | |
612 | if (reason & MCSR_BUS_WAERR) | |
613 | printk("Bus - Write Address Error\n"); | |
614 | if (reason & MCSR_BUS_IBERR) | |
615 | printk("Bus - Instruction Data Error\n"); | |
616 | if (reason & MCSR_BUS_RBERR) | |
617 | printk("Bus - Read Data Bus Error\n"); | |
618 | if (reason & MCSR_BUS_WBERR) | |
c1528339 | 619 | printk("Bus - Write Data Bus Error\n"); |
14cf11af PM |
620 | if (reason & MCSR_BUS_IPERR) |
621 | printk("Bus - Instruction Parity Error\n"); | |
622 | if (reason & MCSR_BUS_RPERR) | |
623 | printk("Bus - Read Parity Error\n"); | |
47c0bd1a BH |
624 | |
625 | return 0; | |
626 | } | |
4490c06b KG |
627 | |
628 | int machine_check_generic(struct pt_regs *regs) | |
629 | { | |
630 | return 0; | |
631 | } | |
47c0bd1a BH |
632 | #elif defined(CONFIG_E200) |
633 | int machine_check_e200(struct pt_regs *regs) | |
634 | { | |
42bff234 | 635 | unsigned long reason = mfspr(SPRN_MCSR); |
47c0bd1a | 636 | |
14cf11af PM |
637 | printk("Machine check in kernel mode.\n"); |
638 | printk("Caused by (from MCSR=%lx): ", reason); | |
639 | ||
640 | if (reason & MCSR_MCP) | |
641 | printk("Machine Check Signal\n"); | |
642 | if (reason & MCSR_CP_PERR) | |
643 | printk("Cache Push Parity Error\n"); | |
644 | if (reason & MCSR_CPERR) | |
645 | printk("Cache Parity Error\n"); | |
646 | if (reason & MCSR_EXCP_ERR) | |
647 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | |
648 | if (reason & MCSR_BUS_IRERR) | |
649 | printk("Bus - Read Bus Error on instruction fetch\n"); | |
650 | if (reason & MCSR_BUS_DRERR) | |
651 | printk("Bus - Read Bus Error on data load\n"); | |
652 | if (reason & MCSR_BUS_WRERR) | |
653 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | |
47c0bd1a BH |
654 | |
655 | return 0; | |
656 | } | |
7f3f819e | 657 | #elif defined(CONFIG_PPC32) |
47c0bd1a BH |
658 | int machine_check_generic(struct pt_regs *regs) |
659 | { | |
42bff234 | 660 | unsigned long reason = regs->msr; |
47c0bd1a | 661 | |
14cf11af PM |
662 | printk("Machine check in kernel mode.\n"); |
663 | printk("Caused by (from SRR1=%lx): ", reason); | |
664 | switch (reason & 0x601F0000) { | |
665 | case 0x80000: | |
666 | printk("Machine check signal\n"); | |
667 | break; | |
668 | case 0: /* for 601 */ | |
669 | case 0x40000: | |
670 | case 0x140000: /* 7450 MSS error and TEA */ | |
671 | printk("Transfer error ack signal\n"); | |
672 | break; | |
673 | case 0x20000: | |
674 | printk("Data parity error signal\n"); | |
675 | break; | |
676 | case 0x10000: | |
677 | printk("Address parity error signal\n"); | |
678 | break; | |
679 | case 0x20000000: | |
680 | printk("L1 Data Cache error\n"); | |
681 | break; | |
682 | case 0x40000000: | |
683 | printk("L1 Instruction Cache error\n"); | |
684 | break; | |
685 | case 0x00100000: | |
686 | printk("L2 data cache parity error\n"); | |
687 | break; | |
688 | default: | |
689 | printk("Unknown values in msr\n"); | |
690 | } | |
75918a4b OJ |
691 | return 0; |
692 | } | |
47c0bd1a | 693 | #endif /* everything else */ |
75918a4b OJ |
694 | |
695 | void machine_check_exception(struct pt_regs *regs) | |
696 | { | |
697 | int recover = 0; | |
b96672dd NP |
698 | bool nested = in_nmi(); |
699 | if (!nested) | |
700 | nmi_enter(); | |
75918a4b | 701 | |
f886f0f6 NP |
702 | /* 64s accounts the mce in machine_check_early when in HVMODE */ |
703 | if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64) || !cpu_has_feature(CPU_FTR_HVMODE)) | |
704 | __this_cpu_inc(irq_stat.mce_exceptions); | |
89713ed1 | 705 | |
d93b0ac0 MS |
706 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); |
707 | ||
47c0bd1a BH |
708 | /* See if any machine dependent calls. In theory, we would want |
709 | * to call the CPU first, and call the ppc_md. one if the CPU | |
710 | * one returns a positive number. However there is existing code | |
711 | * that assumes the board gets a first chance, so let's keep it | |
712 | * that way for now and fix things later. --BenH. | |
713 | */ | |
75918a4b OJ |
714 | if (ppc_md.machine_check_exception) |
715 | recover = ppc_md.machine_check_exception(regs); | |
47c0bd1a BH |
716 | else if (cur_cpu_spec->machine_check) |
717 | recover = cur_cpu_spec->machine_check(regs); | |
75918a4b | 718 | |
47c0bd1a | 719 | if (recover > 0) |
ba12eede | 720 | goto bail; |
75918a4b | 721 | |
a443506b | 722 | if (debugger_fault_handler(regs)) |
ba12eede | 723 | goto bail; |
75918a4b OJ |
724 | |
725 | if (check_io_access(regs)) | |
ba12eede | 726 | goto bail; |
75918a4b | 727 | |
8dad3f92 | 728 | die("Machine check", regs, SIGBUS); |
14cf11af PM |
729 | |
730 | /* Must die if the interrupt is not recoverable */ | |
731 | if (!(regs->msr & MSR_RI)) | |
b96672dd | 732 | nmi_panic(regs, "Unrecoverable Machine check"); |
ba12eede LZ |
733 | |
734 | bail: | |
b96672dd NP |
735 | if (!nested) |
736 | nmi_exit(); | |
14cf11af PM |
737 | } |
738 | ||
739 | void SMIException(struct pt_regs *regs) | |
740 | { | |
741 | die("System Management Interrupt", regs, SIGABRT); | |
742 | } | |
743 | ||
5080332c MN |
744 | #ifdef CONFIG_VSX |
745 | static void p9_hmi_special_emu(struct pt_regs *regs) | |
746 | { | |
747 | unsigned int ra, rb, t, i, sel, instr, rc; | |
748 | const void __user *addr; | |
749 | u8 vbuf[16], *vdst; | |
750 | unsigned long ea, msr, msr_mask; | |
751 | bool swap; | |
752 | ||
753 | if (__get_user_inatomic(instr, (unsigned int __user *)regs->nip)) | |
754 | return; | |
755 | ||
756 | /* | |
757 | * lxvb16x opcode: 0x7c0006d8 | |
758 | * lxvd2x opcode: 0x7c000698 | |
759 | * lxvh8x opcode: 0x7c000658 | |
760 | * lxvw4x opcode: 0x7c000618 | |
761 | */ | |
762 | if ((instr & 0xfc00073e) != 0x7c000618) { | |
763 | pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx" | |
764 | " instr=%08x\n", | |
765 | smp_processor_id(), current->comm, current->pid, | |
766 | regs->nip, instr); | |
767 | return; | |
768 | } | |
769 | ||
770 | /* Grab vector registers into the task struct */ | |
771 | msr = regs->msr; /* Grab msr before we flush the bits */ | |
772 | flush_vsx_to_thread(current); | |
773 | enable_kernel_altivec(); | |
774 | ||
775 | /* | |
776 | * Is userspace running with a different endian (this is rare but | |
777 | * not impossible) | |
778 | */ | |
779 | swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE); | |
780 | ||
781 | /* Decode the instruction */ | |
782 | ra = (instr >> 16) & 0x1f; | |
783 | rb = (instr >> 11) & 0x1f; | |
784 | t = (instr >> 21) & 0x1f; | |
785 | if (instr & 1) | |
786 | vdst = (u8 *)¤t->thread.vr_state.vr[t]; | |
787 | else | |
788 | vdst = (u8 *)¤t->thread.fp_state.fpr[t][0]; | |
789 | ||
790 | /* Grab the vector address */ | |
791 | ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0); | |
792 | if (is_32bit_task()) | |
793 | ea &= 0xfffffffful; | |
794 | addr = (__force const void __user *)ea; | |
795 | ||
796 | /* Check it */ | |
797 | if (!access_ok(VERIFY_READ, addr, 16)) { | |
798 | pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx" | |
799 | " instr=%08x addr=%016lx\n", | |
800 | smp_processor_id(), current->comm, current->pid, | |
801 | regs->nip, instr, (unsigned long)addr); | |
802 | return; | |
803 | } | |
804 | ||
805 | /* Read the vector */ | |
806 | rc = 0; | |
807 | if ((unsigned long)addr & 0xfUL) | |
808 | /* unaligned case */ | |
809 | rc = __copy_from_user_inatomic(vbuf, addr, 16); | |
810 | else | |
811 | __get_user_atomic_128_aligned(vbuf, addr, rc); | |
812 | if (rc) { | |
813 | pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx" | |
814 | " instr=%08x addr=%016lx\n", | |
815 | smp_processor_id(), current->comm, current->pid, | |
816 | regs->nip, instr, (unsigned long)addr); | |
817 | return; | |
818 | } | |
819 | ||
820 | pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx" | |
821 | " instr=%08x addr=%016lx\n", | |
822 | smp_processor_id(), current->comm, current->pid, regs->nip, | |
823 | instr, (unsigned long) addr); | |
824 | ||
825 | /* Grab instruction "selector" */ | |
826 | sel = (instr >> 6) & 3; | |
827 | ||
828 | /* | |
829 | * Check to make sure the facility is actually enabled. This | |
830 | * could happen if we get a false positive hit. | |
831 | * | |
832 | * lxvd2x/lxvw4x always check MSR VSX sel = 0,2 | |
833 | * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3 | |
834 | */ | |
835 | msr_mask = MSR_VSX; | |
836 | if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */ | |
837 | msr_mask = MSR_VEC; | |
838 | if (!(msr & msr_mask)) { | |
839 | pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx" | |
840 | " instr=%08x msr:%016lx\n", | |
841 | smp_processor_id(), current->comm, current->pid, | |
842 | regs->nip, instr, msr); | |
843 | return; | |
844 | } | |
845 | ||
846 | /* Do logging here before we modify sel based on endian */ | |
847 | switch (sel) { | |
848 | case 0: /* lxvw4x */ | |
849 | PPC_WARN_EMULATED(lxvw4x, regs); | |
850 | break; | |
851 | case 1: /* lxvh8x */ | |
852 | PPC_WARN_EMULATED(lxvh8x, regs); | |
853 | break; | |
854 | case 2: /* lxvd2x */ | |
855 | PPC_WARN_EMULATED(lxvd2x, regs); | |
856 | break; | |
857 | case 3: /* lxvb16x */ | |
858 | PPC_WARN_EMULATED(lxvb16x, regs); | |
859 | break; | |
860 | } | |
861 | ||
862 | #ifdef __LITTLE_ENDIAN__ | |
863 | /* | |
864 | * An LE kernel stores the vector in the task struct as an LE | |
865 | * byte array (effectively swapping both the components and | |
866 | * the content of the components). Those instructions expect | |
867 | * the components to remain in ascending address order, so we | |
868 | * swap them back. | |
869 | * | |
870 | * If we are running a BE user space, the expectation is that | |
871 | * of a simple memcpy, so forcing the emulation to look like | |
872 | * a lxvb16x should do the trick. | |
873 | */ | |
874 | if (swap) | |
875 | sel = 3; | |
876 | ||
877 | switch (sel) { | |
878 | case 0: /* lxvw4x */ | |
879 | for (i = 0; i < 4; i++) | |
880 | ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i]; | |
881 | break; | |
882 | case 1: /* lxvh8x */ | |
883 | for (i = 0; i < 8; i++) | |
884 | ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i]; | |
885 | break; | |
886 | case 2: /* lxvd2x */ | |
887 | for (i = 0; i < 2; i++) | |
888 | ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i]; | |
889 | break; | |
890 | case 3: /* lxvb16x */ | |
891 | for (i = 0; i < 16; i++) | |
892 | vdst[i] = vbuf[15-i]; | |
893 | break; | |
894 | } | |
895 | #else /* __LITTLE_ENDIAN__ */ | |
896 | /* On a big endian kernel, a BE userspace only needs a memcpy */ | |
897 | if (!swap) | |
898 | sel = 3; | |
899 | ||
900 | /* Otherwise, we need to swap the content of the components */ | |
901 | switch (sel) { | |
902 | case 0: /* lxvw4x */ | |
903 | for (i = 0; i < 4; i++) | |
904 | ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]); | |
905 | break; | |
906 | case 1: /* lxvh8x */ | |
907 | for (i = 0; i < 8; i++) | |
908 | ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]); | |
909 | break; | |
910 | case 2: /* lxvd2x */ | |
911 | for (i = 0; i < 2; i++) | |
912 | ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]); | |
913 | break; | |
914 | case 3: /* lxvb16x */ | |
915 | memcpy(vdst, vbuf, 16); | |
916 | break; | |
917 | } | |
918 | #endif /* !__LITTLE_ENDIAN__ */ | |
919 | ||
920 | /* Go to next instruction */ | |
921 | regs->nip += 4; | |
922 | } | |
923 | #endif /* CONFIG_VSX */ | |
924 | ||
0869b6fd MS |
925 | void handle_hmi_exception(struct pt_regs *regs) |
926 | { | |
927 | struct pt_regs *old_regs; | |
928 | ||
929 | old_regs = set_irq_regs(regs); | |
930 | irq_enter(); | |
931 | ||
5080332c MN |
932 | #ifdef CONFIG_VSX |
933 | /* Real mode flagged P9 special emu is needed */ | |
934 | if (local_paca->hmi_p9_special_emu) { | |
935 | local_paca->hmi_p9_special_emu = 0; | |
936 | ||
937 | /* | |
938 | * We don't want to take page faults while doing the | |
939 | * emulation, we just replay the instruction if necessary. | |
940 | */ | |
941 | pagefault_disable(); | |
942 | p9_hmi_special_emu(regs); | |
943 | pagefault_enable(); | |
944 | } | |
945 | #endif /* CONFIG_VSX */ | |
946 | ||
0869b6fd MS |
947 | if (ppc_md.handle_hmi_exception) |
948 | ppc_md.handle_hmi_exception(regs); | |
949 | ||
950 | irq_exit(); | |
951 | set_irq_regs(old_regs); | |
952 | } | |
953 | ||
dc1c1ca3 | 954 | void unknown_exception(struct pt_regs *regs) |
14cf11af | 955 | { |
ba12eede LZ |
956 | enum ctx_state prev_state = exception_enter(); |
957 | ||
14cf11af PM |
958 | printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", |
959 | regs->nip, regs->msr, regs->trap); | |
960 | ||
cf4674c4 | 961 | _exception(SIGTRAP, regs, TRAP_FIXME, 0); |
ba12eede LZ |
962 | |
963 | exception_exit(prev_state); | |
14cf11af PM |
964 | } |
965 | ||
dc1c1ca3 | 966 | void instruction_breakpoint_exception(struct pt_regs *regs) |
14cf11af | 967 | { |
ba12eede LZ |
968 | enum ctx_state prev_state = exception_enter(); |
969 | ||
14cf11af PM |
970 | if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5, |
971 | 5, SIGTRAP) == NOTIFY_STOP) | |
ba12eede | 972 | goto bail; |
14cf11af | 973 | if (debugger_iabr_match(regs)) |
ba12eede | 974 | goto bail; |
14cf11af | 975 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
ba12eede LZ |
976 | |
977 | bail: | |
978 | exception_exit(prev_state); | |
14cf11af PM |
979 | } |
980 | ||
981 | void RunModeException(struct pt_regs *regs) | |
982 | { | |
cf4674c4 | 983 | _exception(SIGTRAP, regs, TRAP_FIXME, 0); |
14cf11af PM |
984 | } |
985 | ||
03465f89 | 986 | void single_step_exception(struct pt_regs *regs) |
14cf11af | 987 | { |
ba12eede LZ |
988 | enum ctx_state prev_state = exception_enter(); |
989 | ||
2538c2d0 | 990 | clear_single_step(regs); |
14cf11af | 991 | |
6cc89bad NR |
992 | if (kprobe_post_handler(regs)) |
993 | return; | |
994 | ||
14cf11af PM |
995 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, |
996 | 5, SIGTRAP) == NOTIFY_STOP) | |
ba12eede | 997 | goto bail; |
14cf11af | 998 | if (debugger_sstep(regs)) |
ba12eede | 999 | goto bail; |
14cf11af PM |
1000 | |
1001 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
ba12eede LZ |
1002 | |
1003 | bail: | |
1004 | exception_exit(prev_state); | |
14cf11af | 1005 | } |
03465f89 | 1006 | NOKPROBE_SYMBOL(single_step_exception); |
14cf11af PM |
1007 | |
1008 | /* | |
1009 | * After we have successfully emulated an instruction, we have to | |
1010 | * check if the instruction was being single-stepped, and if so, | |
1011 | * pretend we got a single-step exception. This was pointed out | |
1012 | * by Kumar Gala. -- paulus | |
1013 | */ | |
8dad3f92 | 1014 | static void emulate_single_step(struct pt_regs *regs) |
14cf11af | 1015 | { |
2538c2d0 P |
1016 | if (single_stepping(regs)) |
1017 | single_step_exception(regs); | |
14cf11af PM |
1018 | } |
1019 | ||
5fad293b | 1020 | static inline int __parse_fpscr(unsigned long fpscr) |
dc1c1ca3 | 1021 | { |
cf4674c4 | 1022 | int ret = FPE_FIXME; |
dc1c1ca3 SR |
1023 | |
1024 | /* Invalid operation */ | |
1025 | if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX)) | |
5fad293b | 1026 | ret = FPE_FLTINV; |
dc1c1ca3 SR |
1027 | |
1028 | /* Overflow */ | |
1029 | else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX)) | |
5fad293b | 1030 | ret = FPE_FLTOVF; |
dc1c1ca3 SR |
1031 | |
1032 | /* Underflow */ | |
1033 | else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX)) | |
5fad293b | 1034 | ret = FPE_FLTUND; |
dc1c1ca3 SR |
1035 | |
1036 | /* Divide by zero */ | |
1037 | else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX)) | |
5fad293b | 1038 | ret = FPE_FLTDIV; |
dc1c1ca3 SR |
1039 | |
1040 | /* Inexact result */ | |
1041 | else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX)) | |
5fad293b KG |
1042 | ret = FPE_FLTRES; |
1043 | ||
1044 | return ret; | |
1045 | } | |
1046 | ||
1047 | static void parse_fpe(struct pt_regs *regs) | |
1048 | { | |
1049 | int code = 0; | |
1050 | ||
1051 | flush_fp_to_thread(current); | |
1052 | ||
de79f7b9 | 1053 | code = __parse_fpscr(current->thread.fp_state.fpscr); |
dc1c1ca3 SR |
1054 | |
1055 | _exception(SIGFPE, regs, code, regs->nip); | |
1056 | } | |
1057 | ||
1058 | /* | |
1059 | * Illegal instruction emulation support. Originally written to | |
14cf11af PM |
1060 | * provide the PVR to user applications using the mfspr rd, PVR. |
1061 | * Return non-zero if we can't emulate, or -EFAULT if the associated | |
1062 | * memory access caused an access fault. Return zero on success. | |
1063 | * | |
1064 | * There are a couple of ways to do this, either "decode" the instruction | |
1065 | * or directly match lots of bits. In this case, matching lots of | |
1066 | * bits is faster and easier. | |
86417780 | 1067 | * |
14cf11af | 1068 | */ |
14cf11af PM |
1069 | static int emulate_string_inst(struct pt_regs *regs, u32 instword) |
1070 | { | |
1071 | u8 rT = (instword >> 21) & 0x1f; | |
1072 | u8 rA = (instword >> 16) & 0x1f; | |
1073 | u8 NB_RB = (instword >> 11) & 0x1f; | |
1074 | u32 num_bytes; | |
1075 | unsigned long EA; | |
1076 | int pos = 0; | |
1077 | ||
1078 | /* Early out if we are an invalid form of lswx */ | |
16c57b36 | 1079 | if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX) |
14cf11af PM |
1080 | if ((rT == rA) || (rT == NB_RB)) |
1081 | return -EINVAL; | |
1082 | ||
1083 | EA = (rA == 0) ? 0 : regs->gpr[rA]; | |
1084 | ||
16c57b36 KG |
1085 | switch (instword & PPC_INST_STRING_MASK) { |
1086 | case PPC_INST_LSWX: | |
1087 | case PPC_INST_STSWX: | |
14cf11af PM |
1088 | EA += NB_RB; |
1089 | num_bytes = regs->xer & 0x7f; | |
1090 | break; | |
16c57b36 KG |
1091 | case PPC_INST_LSWI: |
1092 | case PPC_INST_STSWI: | |
14cf11af PM |
1093 | num_bytes = (NB_RB == 0) ? 32 : NB_RB; |
1094 | break; | |
1095 | default: | |
1096 | return -EINVAL; | |
1097 | } | |
1098 | ||
1099 | while (num_bytes != 0) | |
1100 | { | |
1101 | u8 val; | |
1102 | u32 shift = 8 * (3 - (pos & 0x3)); | |
1103 | ||
80aa0fb4 JY |
1104 | /* if process is 32-bit, clear upper 32 bits of EA */ |
1105 | if ((regs->msr & MSR_64BIT) == 0) | |
1106 | EA &= 0xFFFFFFFF; | |
1107 | ||
16c57b36 KG |
1108 | switch ((instword & PPC_INST_STRING_MASK)) { |
1109 | case PPC_INST_LSWX: | |
1110 | case PPC_INST_LSWI: | |
14cf11af PM |
1111 | if (get_user(val, (u8 __user *)EA)) |
1112 | return -EFAULT; | |
1113 | /* first time updating this reg, | |
1114 | * zero it out */ | |
1115 | if (pos == 0) | |
1116 | regs->gpr[rT] = 0; | |
1117 | regs->gpr[rT] |= val << shift; | |
1118 | break; | |
16c57b36 KG |
1119 | case PPC_INST_STSWI: |
1120 | case PPC_INST_STSWX: | |
14cf11af PM |
1121 | val = regs->gpr[rT] >> shift; |
1122 | if (put_user(val, (u8 __user *)EA)) | |
1123 | return -EFAULT; | |
1124 | break; | |
1125 | } | |
1126 | /* move EA to next address */ | |
1127 | EA += 1; | |
1128 | num_bytes--; | |
1129 | ||
1130 | /* manage our position within the register */ | |
1131 | if (++pos == 4) { | |
1132 | pos = 0; | |
1133 | if (++rT == 32) | |
1134 | rT = 0; | |
1135 | } | |
1136 | } | |
1137 | ||
1138 | return 0; | |
1139 | } | |
1140 | ||
c3412dcb WS |
1141 | static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword) |
1142 | { | |
1143 | u32 ra,rs; | |
1144 | unsigned long tmp; | |
1145 | ||
1146 | ra = (instword >> 16) & 0x1f; | |
1147 | rs = (instword >> 21) & 0x1f; | |
1148 | ||
1149 | tmp = regs->gpr[rs]; | |
1150 | tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL); | |
1151 | tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL); | |
1152 | tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL; | |
1153 | regs->gpr[ra] = tmp; | |
1154 | ||
1155 | return 0; | |
1156 | } | |
1157 | ||
c1469f13 KG |
1158 | static int emulate_isel(struct pt_regs *regs, u32 instword) |
1159 | { | |
1160 | u8 rT = (instword >> 21) & 0x1f; | |
1161 | u8 rA = (instword >> 16) & 0x1f; | |
1162 | u8 rB = (instword >> 11) & 0x1f; | |
1163 | u8 BC = (instword >> 6) & 0x1f; | |
1164 | u8 bit; | |
1165 | unsigned long tmp; | |
1166 | ||
1167 | tmp = (rA == 0) ? 0 : regs->gpr[rA]; | |
1168 | bit = (regs->ccr >> (31 - BC)) & 0x1; | |
1169 | ||
1170 | regs->gpr[rT] = bit ? tmp : regs->gpr[rB]; | |
1171 | ||
1172 | return 0; | |
1173 | } | |
1174 | ||
6ce6c629 MN |
1175 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1176 | static inline bool tm_abort_check(struct pt_regs *regs, int cause) | |
1177 | { | |
1178 | /* If we're emulating a load/store in an active transaction, we cannot | |
1179 | * emulate it as the kernel operates in transaction suspended context. | |
1180 | * We need to abort the transaction. This creates a persistent TM | |
1181 | * abort so tell the user what caused it with a new code. | |
1182 | */ | |
1183 | if (MSR_TM_TRANSACTIONAL(regs->msr)) { | |
1184 | tm_enable(); | |
1185 | tm_abort(cause); | |
1186 | return true; | |
1187 | } | |
1188 | return false; | |
1189 | } | |
1190 | #else | |
1191 | static inline bool tm_abort_check(struct pt_regs *regs, int reason) | |
1192 | { | |
1193 | return false; | |
1194 | } | |
1195 | #endif | |
1196 | ||
14cf11af PM |
1197 | static int emulate_instruction(struct pt_regs *regs) |
1198 | { | |
1199 | u32 instword; | |
1200 | u32 rd; | |
1201 | ||
4288e343 | 1202 | if (!user_mode(regs)) |
14cf11af PM |
1203 | return -EINVAL; |
1204 | CHECK_FULL_REGS(regs); | |
1205 | ||
1206 | if (get_user(instword, (u32 __user *)(regs->nip))) | |
1207 | return -EFAULT; | |
1208 | ||
1209 | /* Emulate the mfspr rD, PVR. */ | |
16c57b36 | 1210 | if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) { |
eecff81d | 1211 | PPC_WARN_EMULATED(mfpvr, regs); |
14cf11af PM |
1212 | rd = (instword >> 21) & 0x1f; |
1213 | regs->gpr[rd] = mfspr(SPRN_PVR); | |
1214 | return 0; | |
1215 | } | |
1216 | ||
1217 | /* Emulating the dcba insn is just a no-op. */ | |
80947e7c | 1218 | if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) { |
eecff81d | 1219 | PPC_WARN_EMULATED(dcba, regs); |
14cf11af | 1220 | return 0; |
80947e7c | 1221 | } |
14cf11af PM |
1222 | |
1223 | /* Emulate the mcrxr insn. */ | |
16c57b36 | 1224 | if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) { |
86417780 | 1225 | int shift = (instword >> 21) & 0x1c; |
14cf11af PM |
1226 | unsigned long msk = 0xf0000000UL >> shift; |
1227 | ||
eecff81d | 1228 | PPC_WARN_EMULATED(mcrxr, regs); |
14cf11af PM |
1229 | regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk); |
1230 | regs->xer &= ~0xf0000000UL; | |
1231 | return 0; | |
1232 | } | |
1233 | ||
1234 | /* Emulate load/store string insn. */ | |
80947e7c | 1235 | if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) { |
6ce6c629 MN |
1236 | if (tm_abort_check(regs, |
1237 | TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT)) | |
1238 | return -EINVAL; | |
eecff81d | 1239 | PPC_WARN_EMULATED(string, regs); |
14cf11af | 1240 | return emulate_string_inst(regs, instword); |
80947e7c | 1241 | } |
14cf11af | 1242 | |
c3412dcb | 1243 | /* Emulate the popcntb (Population Count Bytes) instruction. */ |
16c57b36 | 1244 | if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) { |
eecff81d | 1245 | PPC_WARN_EMULATED(popcntb, regs); |
c3412dcb WS |
1246 | return emulate_popcntb_inst(regs, instword); |
1247 | } | |
1248 | ||
c1469f13 | 1249 | /* Emulate isel (Integer Select) instruction */ |
16c57b36 | 1250 | if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) { |
eecff81d | 1251 | PPC_WARN_EMULATED(isel, regs); |
c1469f13 KG |
1252 | return emulate_isel(regs, instword); |
1253 | } | |
1254 | ||
9863c28a JY |
1255 | /* Emulate sync instruction variants */ |
1256 | if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) { | |
1257 | PPC_WARN_EMULATED(sync, regs); | |
1258 | asm volatile("sync"); | |
1259 | return 0; | |
1260 | } | |
1261 | ||
efcac658 AK |
1262 | #ifdef CONFIG_PPC64 |
1263 | /* Emulate the mfspr rD, DSCR. */ | |
73d2fb75 AB |
1264 | if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == |
1265 | PPC_INST_MFSPR_DSCR_USER) || | |
1266 | ((instword & PPC_INST_MFSPR_DSCR_MASK) == | |
1267 | PPC_INST_MFSPR_DSCR)) && | |
efcac658 AK |
1268 | cpu_has_feature(CPU_FTR_DSCR)) { |
1269 | PPC_WARN_EMULATED(mfdscr, regs); | |
1270 | rd = (instword >> 21) & 0x1f; | |
1271 | regs->gpr[rd] = mfspr(SPRN_DSCR); | |
1272 | return 0; | |
1273 | } | |
1274 | /* Emulate the mtspr DSCR, rD. */ | |
73d2fb75 AB |
1275 | if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) == |
1276 | PPC_INST_MTSPR_DSCR_USER) || | |
1277 | ((instword & PPC_INST_MTSPR_DSCR_MASK) == | |
1278 | PPC_INST_MTSPR_DSCR)) && | |
efcac658 AK |
1279 | cpu_has_feature(CPU_FTR_DSCR)) { |
1280 | PPC_WARN_EMULATED(mtdscr, regs); | |
1281 | rd = (instword >> 21) & 0x1f; | |
00ca0de0 | 1282 | current->thread.dscr = regs->gpr[rd]; |
efcac658 | 1283 | current->thread.dscr_inherit = 1; |
00ca0de0 | 1284 | mtspr(SPRN_DSCR, current->thread.dscr); |
efcac658 AK |
1285 | return 0; |
1286 | } | |
1287 | #endif | |
1288 | ||
14cf11af PM |
1289 | return -EINVAL; |
1290 | } | |
1291 | ||
73c9ceab | 1292 | int is_valid_bugaddr(unsigned long addr) |
14cf11af | 1293 | { |
73c9ceab | 1294 | return is_kernel_addr(addr); |
14cf11af PM |
1295 | } |
1296 | ||
3a3b5aa6 KH |
1297 | #ifdef CONFIG_MATH_EMULATION |
1298 | static int emulate_math(struct pt_regs *regs) | |
1299 | { | |
1300 | int ret; | |
1301 | extern int do_mathemu(struct pt_regs *regs); | |
1302 | ||
1303 | ret = do_mathemu(regs); | |
1304 | if (ret >= 0) | |
1305 | PPC_WARN_EMULATED(math, regs); | |
1306 | ||
1307 | switch (ret) { | |
1308 | case 0: | |
1309 | emulate_single_step(regs); | |
1310 | return 0; | |
1311 | case 1: { | |
1312 | int code = 0; | |
de79f7b9 | 1313 | code = __parse_fpscr(current->thread.fp_state.fpscr); |
3a3b5aa6 KH |
1314 | _exception(SIGFPE, regs, code, regs->nip); |
1315 | return 0; | |
1316 | } | |
1317 | case -EFAULT: | |
1318 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
1319 | return 0; | |
1320 | } | |
1321 | ||
1322 | return -1; | |
1323 | } | |
1324 | #else | |
1325 | static inline int emulate_math(struct pt_regs *regs) { return -1; } | |
1326 | #endif | |
1327 | ||
03465f89 | 1328 | void program_check_exception(struct pt_regs *regs) |
14cf11af | 1329 | { |
ba12eede | 1330 | enum ctx_state prev_state = exception_enter(); |
14cf11af | 1331 | unsigned int reason = get_reason(regs); |
14cf11af | 1332 | |
aa42c69c | 1333 | /* We can now get here via a FP Unavailable exception if the core |
04903a30 | 1334 | * has no FPU, in that case the reason flags will be 0 */ |
14cf11af | 1335 | |
dc1c1ca3 SR |
1336 | if (reason & REASON_FP) { |
1337 | /* IEEE FP exception */ | |
1338 | parse_fpe(regs); | |
ba12eede | 1339 | goto bail; |
8dad3f92 PM |
1340 | } |
1341 | if (reason & REASON_TRAP) { | |
a4c3f909 | 1342 | unsigned long bugaddr; |
ba797b28 JW |
1343 | /* Debugger is first in line to stop recursive faults in |
1344 | * rcu_lock, notify_die, or atomic_notifier_call_chain */ | |
1345 | if (debugger_bpt(regs)) | |
ba12eede | 1346 | goto bail; |
ba797b28 | 1347 | |
6cc89bad NR |
1348 | if (kprobe_handler(regs)) |
1349 | goto bail; | |
1350 | ||
14cf11af | 1351 | /* trap exception */ |
dc1c1ca3 SR |
1352 | if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP) |
1353 | == NOTIFY_STOP) | |
ba12eede | 1354 | goto bail; |
73c9ceab | 1355 | |
a4c3f909 BS |
1356 | bugaddr = regs->nip; |
1357 | /* | |
1358 | * Fixup bugaddr for BUG_ON() in real mode | |
1359 | */ | |
1360 | if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR)) | |
1361 | bugaddr += PAGE_OFFSET; | |
1362 | ||
73c9ceab | 1363 | if (!(regs->msr & MSR_PR) && /* not user-mode */ |
a4c3f909 | 1364 | report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) { |
14cf11af | 1365 | regs->nip += 4; |
ba12eede | 1366 | goto bail; |
14cf11af | 1367 | } |
8dad3f92 | 1368 | _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip); |
ba12eede | 1369 | goto bail; |
8dad3f92 | 1370 | } |
bc2a9408 MN |
1371 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1372 | if (reason & REASON_TM) { | |
1373 | /* This is a TM "Bad Thing Exception" program check. | |
1374 | * This occurs when: | |
1375 | * - An rfid/hrfid/mtmsrd attempts to cause an illegal | |
1376 | * transition in TM states. | |
1377 | * - A trechkpt is attempted when transactional. | |
1378 | * - A treclaim is attempted when non transactional. | |
1379 | * - A tend is illegally attempted. | |
1380 | * - writing a TM SPR when transactional. | |
632f0574 ME |
1381 | * |
1382 | * If usermode caused this, it's done something illegal and | |
bc2a9408 MN |
1383 | * gets a SIGILL slap on the wrist. We call it an illegal |
1384 | * operand to distinguish from the instruction just being bad | |
1385 | * (e.g. executing a 'tend' on a CPU without TM!); it's an | |
1386 | * illegal /placement/ of a valid instruction. | |
1387 | */ | |
1388 | if (user_mode(regs)) { | |
1389 | _exception(SIGILL, regs, ILL_ILLOPN, regs->nip); | |
ba12eede | 1390 | goto bail; |
bc2a9408 MN |
1391 | } else { |
1392 | printk(KERN_EMERG "Unexpected TM Bad Thing exception " | |
1393 | "at %lx (msr 0x%x)\n", regs->nip, reason); | |
1394 | die("Unrecoverable exception", regs, SIGABRT); | |
1395 | } | |
1396 | } | |
1397 | #endif | |
8dad3f92 | 1398 | |
b3f6a459 ME |
1399 | /* |
1400 | * If we took the program check in the kernel skip down to sending a | |
1401 | * SIGILL. The subsequent cases all relate to emulating instructions | |
1402 | * which we should only do for userspace. We also do not want to enable | |
1403 | * interrupts for kernel faults because that might lead to further | |
1404 | * faults, and loose the context of the original exception. | |
1405 | */ | |
1406 | if (!user_mode(regs)) | |
1407 | goto sigill; | |
1408 | ||
a3512b2d BH |
1409 | /* We restore the interrupt state now */ |
1410 | if (!arch_irq_disabled_regs(regs)) | |
1411 | local_irq_enable(); | |
cd8a5673 | 1412 | |
04903a30 KG |
1413 | /* (reason & REASON_ILLEGAL) would be the obvious thing here, |
1414 | * but there seems to be a hardware bug on the 405GP (RevD) | |
1415 | * that means ESR is sometimes set incorrectly - either to | |
1416 | * ESR_DST (!?) or 0. In the process of chasing this with the | |
1417 | * hardware people - not sure if it can happen on any illegal | |
1418 | * instruction or only on FP instructions, whether there is a | |
4e63f8ed BH |
1419 | * pattern to occurrences etc. -dgibson 31/Mar/2003 |
1420 | */ | |
3a3b5aa6 | 1421 | if (!emulate_math(regs)) |
ba12eede | 1422 | goto bail; |
04903a30 | 1423 | |
8dad3f92 PM |
1424 | /* Try to emulate it if we should. */ |
1425 | if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) { | |
14cf11af PM |
1426 | switch (emulate_instruction(regs)) { |
1427 | case 0: | |
1428 | regs->nip += 4; | |
1429 | emulate_single_step(regs); | |
ba12eede | 1430 | goto bail; |
14cf11af PM |
1431 | case -EFAULT: |
1432 | _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip); | |
ba12eede | 1433 | goto bail; |
14cf11af PM |
1434 | } |
1435 | } | |
8dad3f92 | 1436 | |
b3f6a459 | 1437 | sigill: |
8dad3f92 PM |
1438 | if (reason & REASON_PRIVILEGED) |
1439 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1440 | else | |
1441 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
ba12eede LZ |
1442 | |
1443 | bail: | |
1444 | exception_exit(prev_state); | |
14cf11af | 1445 | } |
03465f89 | 1446 | NOKPROBE_SYMBOL(program_check_exception); |
14cf11af | 1447 | |
bf593907 PM |
1448 | /* |
1449 | * This occurs when running in hypervisor mode on POWER6 or later | |
1450 | * and an illegal instruction is encountered. | |
1451 | */ | |
03465f89 | 1452 | void emulation_assist_interrupt(struct pt_regs *regs) |
bf593907 PM |
1453 | { |
1454 | regs->msr |= REASON_ILLEGAL; | |
1455 | program_check_exception(regs); | |
1456 | } | |
03465f89 | 1457 | NOKPROBE_SYMBOL(emulation_assist_interrupt); |
bf593907 | 1458 | |
dc1c1ca3 | 1459 | void alignment_exception(struct pt_regs *regs) |
14cf11af | 1460 | { |
ba12eede | 1461 | enum ctx_state prev_state = exception_enter(); |
4393c4f6 | 1462 | int sig, code, fixed = 0; |
14cf11af | 1463 | |
a3512b2d BH |
1464 | /* We restore the interrupt state now */ |
1465 | if (!arch_irq_disabled_regs(regs)) | |
1466 | local_irq_enable(); | |
1467 | ||
6ce6c629 MN |
1468 | if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT)) |
1469 | goto bail; | |
1470 | ||
e9370ae1 PM |
1471 | /* we don't implement logging of alignment exceptions */ |
1472 | if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS)) | |
1473 | fixed = fix_alignment(regs); | |
14cf11af PM |
1474 | |
1475 | if (fixed == 1) { | |
1476 | regs->nip += 4; /* skip over emulated instruction */ | |
1477 | emulate_single_step(regs); | |
ba12eede | 1478 | goto bail; |
14cf11af PM |
1479 | } |
1480 | ||
dc1c1ca3 | 1481 | /* Operand address was bad */ |
14cf11af | 1482 | if (fixed == -EFAULT) { |
4393c4f6 BH |
1483 | sig = SIGSEGV; |
1484 | code = SEGV_ACCERR; | |
1485 | } else { | |
1486 | sig = SIGBUS; | |
1487 | code = BUS_ADRALN; | |
14cf11af | 1488 | } |
4393c4f6 BH |
1489 | if (user_mode(regs)) |
1490 | _exception(sig, regs, code, regs->dar); | |
1491 | else | |
1492 | bad_page_fault(regs, regs->dar, sig); | |
ba12eede LZ |
1493 | |
1494 | bail: | |
1495 | exception_exit(prev_state); | |
14cf11af PM |
1496 | } |
1497 | ||
f0f558b1 PM |
1498 | void slb_miss_bad_addr(struct pt_regs *regs) |
1499 | { | |
1500 | enum ctx_state prev_state = exception_enter(); | |
1501 | ||
1502 | if (user_mode(regs)) | |
1503 | _exception(SIGSEGV, regs, SEGV_BNDERR, regs->dar); | |
1504 | else | |
1505 | bad_page_fault(regs, regs->dar, SIGSEGV); | |
1506 | ||
1507 | exception_exit(prev_state); | |
1508 | } | |
1509 | ||
14cf11af PM |
1510 | void StackOverflow(struct pt_regs *regs) |
1511 | { | |
1512 | printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n", | |
1513 | current, regs->gpr[1]); | |
1514 | debugger(regs); | |
1515 | show_regs(regs); | |
1516 | panic("kernel stack overflow"); | |
1517 | } | |
1518 | ||
1519 | void nonrecoverable_exception(struct pt_regs *regs) | |
1520 | { | |
1521 | printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n", | |
1522 | regs->nip, regs->msr); | |
1523 | debugger(regs); | |
1524 | die("nonrecoverable exception", regs, SIGKILL); | |
1525 | } | |
1526 | ||
dc1c1ca3 SR |
1527 | void kernel_fp_unavailable_exception(struct pt_regs *regs) |
1528 | { | |
ba12eede LZ |
1529 | enum ctx_state prev_state = exception_enter(); |
1530 | ||
dc1c1ca3 SR |
1531 | printk(KERN_EMERG "Unrecoverable FP Unavailable Exception " |
1532 | "%lx at %lx\n", regs->trap, regs->nip); | |
1533 | die("Unrecoverable FP Unavailable Exception", regs, SIGABRT); | |
ba12eede LZ |
1534 | |
1535 | exception_exit(prev_state); | |
dc1c1ca3 | 1536 | } |
dc1c1ca3 SR |
1537 | |
1538 | void altivec_unavailable_exception(struct pt_regs *regs) | |
1539 | { | |
ba12eede LZ |
1540 | enum ctx_state prev_state = exception_enter(); |
1541 | ||
dc1c1ca3 SR |
1542 | if (user_mode(regs)) { |
1543 | /* A user program has executed an altivec instruction, | |
1544 | but this kernel doesn't support altivec. */ | |
1545 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
ba12eede | 1546 | goto bail; |
dc1c1ca3 | 1547 | } |
6c4841c2 | 1548 | |
dc1c1ca3 SR |
1549 | printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception " |
1550 | "%lx at %lx\n", regs->trap, regs->nip); | |
1551 | die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT); | |
ba12eede LZ |
1552 | |
1553 | bail: | |
1554 | exception_exit(prev_state); | |
dc1c1ca3 SR |
1555 | } |
1556 | ||
ce48b210 MN |
1557 | void vsx_unavailable_exception(struct pt_regs *regs) |
1558 | { | |
1559 | if (user_mode(regs)) { | |
1560 | /* A user program has executed an vsx instruction, | |
1561 | but this kernel doesn't support vsx. */ | |
1562 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1563 | return; | |
1564 | } | |
1565 | ||
1566 | printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception " | |
1567 | "%lx at %lx\n", regs->trap, regs->nip); | |
1568 | die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT); | |
1569 | } | |
1570 | ||
2517617e | 1571 | #ifdef CONFIG_PPC64 |
172f7aaa CB |
1572 | static void tm_unavailable(struct pt_regs *regs) |
1573 | { | |
5d176f75 CB |
1574 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1575 | if (user_mode(regs)) { | |
1576 | current->thread.load_tm++; | |
1577 | regs->msr |= MSR_TM; | |
1578 | tm_enable(); | |
1579 | tm_restore_sprs(¤t->thread); | |
1580 | return; | |
1581 | } | |
1582 | #endif | |
172f7aaa CB |
1583 | pr_emerg("Unrecoverable TM Unavailable Exception " |
1584 | "%lx at %lx\n", regs->trap, regs->nip); | |
1585 | die("Unrecoverable TM Unavailable Exception", regs, SIGABRT); | |
1586 | } | |
1587 | ||
021424a1 | 1588 | void facility_unavailable_exception(struct pt_regs *regs) |
d0c0c9a1 | 1589 | { |
021424a1 | 1590 | static char *facility_strings[] = { |
2517617e MN |
1591 | [FSCR_FP_LG] = "FPU", |
1592 | [FSCR_VECVSX_LG] = "VMX/VSX", | |
1593 | [FSCR_DSCR_LG] = "DSCR", | |
1594 | [FSCR_PM_LG] = "PMU SPRs", | |
1595 | [FSCR_BHRB_LG] = "BHRB", | |
1596 | [FSCR_TM_LG] = "TM", | |
1597 | [FSCR_EBB_LG] = "EBB", | |
1598 | [FSCR_TAR_LG] = "TAR", | |
794464f4 | 1599 | [FSCR_MSGP_LG] = "MSGP", |
9b7ff0c6 | 1600 | [FSCR_SCV_LG] = "SCV", |
021424a1 | 1601 | }; |
2517617e | 1602 | char *facility = "unknown"; |
021424a1 | 1603 | u64 value; |
c952c1c4 | 1604 | u32 instword, rd; |
2517617e MN |
1605 | u8 status; |
1606 | bool hv; | |
021424a1 | 1607 | |
2271db20 | 1608 | hv = (TRAP(regs) == 0xf80); |
2517617e | 1609 | if (hv) |
b14b6260 | 1610 | value = mfspr(SPRN_HFSCR); |
2517617e MN |
1611 | else |
1612 | value = mfspr(SPRN_FSCR); | |
1613 | ||
1614 | status = value >> 56; | |
1615 | if (status == FSCR_DSCR_LG) { | |
c952c1c4 AK |
1616 | /* |
1617 | * User is accessing the DSCR register using the problem | |
1618 | * state only SPR number (0x03) either through a mfspr or | |
1619 | * a mtspr instruction. If it is a write attempt through | |
1620 | * a mtspr, then we set the inherit bit. This also allows | |
1621 | * the user to write or read the register directly in the | |
1622 | * future by setting via the FSCR DSCR bit. But in case it | |
1623 | * is a read DSCR attempt through a mfspr instruction, we | |
1624 | * just emulate the instruction instead. This code path will | |
1625 | * always emulate all the mfspr instructions till the user | |
446957ba | 1626 | * has attempted at least one mtspr instruction. This way it |
c952c1c4 AK |
1627 | * preserves the same behaviour when the user is accessing |
1628 | * the DSCR through privilege level only SPR number (0x11) | |
1629 | * which is emulated through illegal instruction exception. | |
1630 | * We always leave HFSCR DSCR set. | |
2517617e | 1631 | */ |
c952c1c4 AK |
1632 | if (get_user(instword, (u32 __user *)(regs->nip))) { |
1633 | pr_err("Failed to fetch the user instruction\n"); | |
1634 | return; | |
1635 | } | |
1636 | ||
1637 | /* Write into DSCR (mtspr 0x03, RS) */ | |
1638 | if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK) | |
1639 | == PPC_INST_MTSPR_DSCR_USER) { | |
1640 | rd = (instword >> 21) & 0x1f; | |
1641 | current->thread.dscr = regs->gpr[rd]; | |
1642 | current->thread.dscr_inherit = 1; | |
b57bd2de MN |
1643 | current->thread.fscr |= FSCR_DSCR; |
1644 | mtspr(SPRN_FSCR, current->thread.fscr); | |
c952c1c4 AK |
1645 | } |
1646 | ||
1647 | /* Read from DSCR (mfspr RT, 0x03) */ | |
1648 | if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK) | |
1649 | == PPC_INST_MFSPR_DSCR_USER) { | |
1650 | if (emulate_instruction(regs)) { | |
1651 | pr_err("DSCR based mfspr emulation failed\n"); | |
1652 | return; | |
1653 | } | |
1654 | regs->nip += 4; | |
1655 | emulate_single_step(regs); | |
1656 | } | |
2517617e | 1657 | return; |
b14b6260 ME |
1658 | } |
1659 | ||
172f7aaa CB |
1660 | if (status == FSCR_TM_LG) { |
1661 | /* | |
1662 | * If we're here then the hardware is TM aware because it | |
1663 | * generated an exception with FSRM_TM set. | |
1664 | * | |
1665 | * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware | |
1666 | * told us not to do TM, or the kernel is not built with TM | |
1667 | * support. | |
1668 | * | |
1669 | * If both of those things are true, then userspace can spam the | |
1670 | * console by triggering the printk() below just by continually | |
1671 | * doing tbegin (or any TM instruction). So in that case just | |
1672 | * send the process a SIGILL immediately. | |
1673 | */ | |
1674 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1675 | goto out; | |
1676 | ||
1677 | tm_unavailable(regs); | |
1678 | return; | |
1679 | } | |
1680 | ||
93c2ec0f BS |
1681 | if ((hv || status >= 2) && |
1682 | (status < ARRAY_SIZE(facility_strings)) && | |
2517617e MN |
1683 | facility_strings[status]) |
1684 | facility = facility_strings[status]; | |
021424a1 | 1685 | |
d0c0c9a1 MN |
1686 | /* We restore the interrupt state now */ |
1687 | if (!arch_irq_disabled_regs(regs)) | |
1688 | local_irq_enable(); | |
1689 | ||
93c2ec0f BS |
1690 | pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n", |
1691 | hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr); | |
d0c0c9a1 | 1692 | |
172f7aaa | 1693 | out: |
d0c0c9a1 MN |
1694 | if (user_mode(regs)) { |
1695 | _exception(SIGILL, regs, ILL_ILLOPC, regs->nip); | |
1696 | return; | |
1697 | } | |
1698 | ||
021424a1 | 1699 | die("Unexpected facility unavailable exception", regs, SIGABRT); |
d0c0c9a1 | 1700 | } |
2517617e | 1701 | #endif |
d0c0c9a1 | 1702 | |
f54db641 MN |
1703 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1704 | ||
f54db641 MN |
1705 | void fp_unavailable_tm(struct pt_regs *regs) |
1706 | { | |
1707 | /* Note: This does not handle any kind of FP laziness. */ | |
1708 | ||
1709 | TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n", | |
1710 | regs->nip, regs->msr); | |
f54db641 MN |
1711 | |
1712 | /* We can only have got here if the task started using FP after | |
1713 | * beginning the transaction. So, the transactional regs are just a | |
1714 | * copy of the checkpointed ones. But, we still need to recheckpoint | |
1715 | * as we're enabling FP for the process; it will return, abort the | |
1716 | * transaction, and probably retry but now with FP enabled. So the | |
1717 | * checkpointed FP registers need to be loaded. | |
1718 | */ | |
d31626f7 | 1719 | tm_reclaim_current(TM_CAUSE_FAC_UNAV); |
f54db641 MN |
1720 | /* Reclaim didn't save out any FPRs to transact_fprs. */ |
1721 | ||
1722 | /* Enable FP for the task: */ | |
a7771176 | 1723 | current->thread.load_fp = 1; |
f54db641 MN |
1724 | |
1725 | /* This loads and recheckpoints the FP registers from | |
1726 | * thread.fpr[]. They will remain in registers after the | |
1727 | * checkpoint so we don't need to reload them after. | |
3ac8ff1c PM |
1728 | * If VMX is in use, the VRs now hold checkpointed values, |
1729 | * so we don't want to load the VRs from the thread_struct. | |
f54db641 | 1730 | */ |
eb5c3f1c | 1731 | tm_recheckpoint(¤t->thread); |
f54db641 MN |
1732 | } |
1733 | ||
f54db641 MN |
1734 | void altivec_unavailable_tm(struct pt_regs *regs) |
1735 | { | |
1736 | /* See the comments in fp_unavailable_tm(). This function operates | |
1737 | * the same way. | |
1738 | */ | |
1739 | ||
1740 | TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx," | |
1741 | "MSR=%lx\n", | |
1742 | regs->nip, regs->msr); | |
d31626f7 | 1743 | tm_reclaim_current(TM_CAUSE_FAC_UNAV); |
a7771176 | 1744 | current->thread.load_vec = 1; |
eb5c3f1c | 1745 | tm_recheckpoint(¤t->thread); |
f54db641 MN |
1746 | current->thread.used_vr = 1; |
1747 | } | |
f54db641 | 1748 | |
f54db641 MN |
1749 | void vsx_unavailable_tm(struct pt_regs *regs) |
1750 | { | |
1751 | /* See the comments in fp_unavailable_tm(). This works similarly, | |
1752 | * though we're loading both FP and VEC registers in here. | |
1753 | * | |
1754 | * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC | |
1755 | * regs. Either way, set MSR_VSX. | |
1756 | */ | |
1757 | ||
1758 | TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx," | |
1759 | "MSR=%lx\n", | |
1760 | regs->nip, regs->msr); | |
1761 | ||
3ac8ff1c PM |
1762 | current->thread.used_vsr = 1; |
1763 | ||
f54db641 | 1764 | /* This reclaims FP and/or VR regs if they're already enabled */ |
d31626f7 | 1765 | tm_reclaim_current(TM_CAUSE_FAC_UNAV); |
f54db641 | 1766 | |
a7771176 CB |
1767 | current->thread.load_vec = 1; |
1768 | current->thread.load_fp = 1; | |
3ac8ff1c | 1769 | |
eb5c3f1c | 1770 | tm_recheckpoint(¤t->thread); |
f54db641 | 1771 | } |
f54db641 MN |
1772 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
1773 | ||
dc1c1ca3 SR |
1774 | void performance_monitor_exception(struct pt_regs *regs) |
1775 | { | |
69111bac | 1776 | __this_cpu_inc(irq_stat.pmu_irqs); |
89713ed1 | 1777 | |
dc1c1ca3 SR |
1778 | perf_irq(regs); |
1779 | } | |
dc1c1ca3 | 1780 | |
172ae2e7 | 1781 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3bffb652 DK |
1782 | static void handle_debug(struct pt_regs *regs, unsigned long debug_status) |
1783 | { | |
1784 | int changed = 0; | |
1785 | /* | |
1786 | * Determine the cause of the debug event, clear the | |
1787 | * event flags and send a trap to the handler. Torez | |
1788 | */ | |
1789 | if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { | |
1790 | dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); | |
1791 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a | 1792 | current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; |
3bffb652 | 1793 | #endif |
47355040 | 1794 | do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, |
3bffb652 DK |
1795 | 5); |
1796 | changed |= 0x01; | |
1797 | } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) { | |
1798 | dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W); | |
47355040 | 1799 | do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, |
3bffb652 DK |
1800 | 6); |
1801 | changed |= 0x01; | |
1802 | } else if (debug_status & DBSR_IAC1) { | |
51ae8d4a | 1803 | current->thread.debug.dbcr0 &= ~DBCR0_IAC1; |
3bffb652 | 1804 | dbcr_iac_range(current) &= ~DBCR_IAC12MODE; |
47355040 | 1805 | do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, |
3bffb652 DK |
1806 | 1); |
1807 | changed |= 0x01; | |
1808 | } else if (debug_status & DBSR_IAC2) { | |
51ae8d4a | 1809 | current->thread.debug.dbcr0 &= ~DBCR0_IAC2; |
47355040 | 1810 | do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, |
3bffb652 DK |
1811 | 2); |
1812 | changed |= 0x01; | |
1813 | } else if (debug_status & DBSR_IAC3) { | |
51ae8d4a | 1814 | current->thread.debug.dbcr0 &= ~DBCR0_IAC3; |
3bffb652 | 1815 | dbcr_iac_range(current) &= ~DBCR_IAC34MODE; |
47355040 | 1816 | do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, |
3bffb652 DK |
1817 | 3); |
1818 | changed |= 0x01; | |
1819 | } else if (debug_status & DBSR_IAC4) { | |
51ae8d4a | 1820 | current->thread.debug.dbcr0 &= ~DBCR0_IAC4; |
47355040 | 1821 | do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, |
3bffb652 DK |
1822 | 4); |
1823 | changed |= 0x01; | |
1824 | } | |
1825 | /* | |
1826 | * At the point this routine was called, the MSR(DE) was turned off. | |
1827 | * Check all other debug flags and see if that bit needs to be turned | |
1828 | * back on or not. | |
1829 | */ | |
51ae8d4a | 1830 | if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, |
95791988 | 1831 | current->thread.debug.dbcr1)) |
3bffb652 DK |
1832 | regs->msr |= MSR_DE; |
1833 | else | |
1834 | /* Make sure the IDM flag is off */ | |
51ae8d4a | 1835 | current->thread.debug.dbcr0 &= ~DBCR0_IDM; |
3bffb652 DK |
1836 | |
1837 | if (changed & 0x01) | |
51ae8d4a | 1838 | mtspr(SPRN_DBCR0, current->thread.debug.dbcr0); |
3bffb652 | 1839 | } |
14cf11af | 1840 | |
03465f89 | 1841 | void DebugException(struct pt_regs *regs, unsigned long debug_status) |
14cf11af | 1842 | { |
51ae8d4a | 1843 | current->thread.debug.dbsr = debug_status; |
3bffb652 | 1844 | |
ec097c84 RM |
1845 | /* Hack alert: On BookE, Branch Taken stops on the branch itself, while |
1846 | * on server, it stops on the target of the branch. In order to simulate | |
1847 | * the server behaviour, we thus restart right away with a single step | |
1848 | * instead of stopping here when hitting a BT | |
1849 | */ | |
1850 | if (debug_status & DBSR_BT) { | |
1851 | regs->msr &= ~MSR_DE; | |
1852 | ||
1853 | /* Disable BT */ | |
1854 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT); | |
1855 | /* Clear the BT event */ | |
1856 | mtspr(SPRN_DBSR, DBSR_BT); | |
1857 | ||
1858 | /* Do the single step trick only when coming from userspace */ | |
1859 | if (user_mode(regs)) { | |
51ae8d4a BB |
1860 | current->thread.debug.dbcr0 &= ~DBCR0_BT; |
1861 | current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
ec097c84 RM |
1862 | regs->msr |= MSR_DE; |
1863 | return; | |
1864 | } | |
1865 | ||
6cc89bad NR |
1866 | if (kprobe_post_handler(regs)) |
1867 | return; | |
1868 | ||
ec097c84 RM |
1869 | if (notify_die(DIE_SSTEP, "block_step", regs, 5, |
1870 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1871 | return; | |
1872 | } | |
1873 | if (debugger_sstep(regs)) | |
1874 | return; | |
1875 | } else if (debug_status & DBSR_IC) { /* Instruction complete */ | |
14cf11af | 1876 | regs->msr &= ~MSR_DE; |
f8279621 KG |
1877 | |
1878 | /* Disable instruction completion */ | |
1879 | mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC); | |
1880 | /* Clear the instruction completion event */ | |
1881 | mtspr(SPRN_DBSR, DBSR_IC); | |
1882 | ||
6cc89bad NR |
1883 | if (kprobe_post_handler(regs)) |
1884 | return; | |
1885 | ||
f8279621 KG |
1886 | if (notify_die(DIE_SSTEP, "single_step", regs, 5, |
1887 | 5, SIGTRAP) == NOTIFY_STOP) { | |
1888 | return; | |
1889 | } | |
1890 | ||
1891 | if (debugger_sstep(regs)) | |
1892 | return; | |
1893 | ||
d6a61bfc | 1894 | if (user_mode(regs)) { |
51ae8d4a BB |
1895 | current->thread.debug.dbcr0 &= ~DBCR0_IC; |
1896 | if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0, | |
1897 | current->thread.debug.dbcr1)) | |
3bffb652 DK |
1898 | regs->msr |= MSR_DE; |
1899 | else | |
1900 | /* Make sure the IDM bit is off */ | |
51ae8d4a | 1901 | current->thread.debug.dbcr0 &= ~DBCR0_IDM; |
d6a61bfc | 1902 | } |
3bffb652 DK |
1903 | |
1904 | _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); | |
1905 | } else | |
1906 | handle_debug(regs, debug_status); | |
14cf11af | 1907 | } |
03465f89 | 1908 | NOKPROBE_SYMBOL(DebugException); |
172ae2e7 | 1909 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
14cf11af PM |
1910 | |
1911 | #if !defined(CONFIG_TAU_INT) | |
1912 | void TAUException(struct pt_regs *regs) | |
1913 | { | |
1914 | printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n", | |
1915 | regs->nip, regs->msr, regs->trap, print_tainted()); | |
1916 | } | |
1917 | #endif /* CONFIG_INT_TAU */ | |
14cf11af PM |
1918 | |
1919 | #ifdef CONFIG_ALTIVEC | |
dc1c1ca3 | 1920 | void altivec_assist_exception(struct pt_regs *regs) |
14cf11af PM |
1921 | { |
1922 | int err; | |
1923 | ||
14cf11af PM |
1924 | if (!user_mode(regs)) { |
1925 | printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode" | |
1926 | " at %lx\n", regs->nip); | |
8dad3f92 | 1927 | die("Kernel VMX/Altivec assist exception", regs, SIGILL); |
14cf11af PM |
1928 | } |
1929 | ||
dc1c1ca3 | 1930 | flush_altivec_to_thread(current); |
dc1c1ca3 | 1931 | |
eecff81d | 1932 | PPC_WARN_EMULATED(altivec, regs); |
14cf11af PM |
1933 | err = emulate_altivec(regs); |
1934 | if (err == 0) { | |
1935 | regs->nip += 4; /* skip emulated instruction */ | |
1936 | emulate_single_step(regs); | |
1937 | return; | |
1938 | } | |
1939 | ||
1940 | if (err == -EFAULT) { | |
1941 | /* got an error reading the instruction */ | |
1942 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
1943 | } else { | |
1944 | /* didn't recognize the instruction */ | |
1945 | /* XXX quick hack for now: set the non-Java bit in the VSCR */ | |
76462232 CD |
1946 | printk_ratelimited(KERN_ERR "Unrecognized altivec instruction " |
1947 | "in %s at %lx\n", current->comm, regs->nip); | |
de79f7b9 | 1948 | current->thread.vr_state.vscr.u[3] |= 0x10000; |
14cf11af PM |
1949 | } |
1950 | } | |
1951 | #endif /* CONFIG_ALTIVEC */ | |
1952 | ||
14cf11af PM |
1953 | #ifdef CONFIG_FSL_BOOKE |
1954 | void CacheLockingException(struct pt_regs *regs, unsigned long address, | |
1955 | unsigned long error_code) | |
1956 | { | |
1957 | /* We treat cache locking instructions from the user | |
1958 | * as priv ops, in the future we could try to do | |
1959 | * something smarter | |
1960 | */ | |
1961 | if (error_code & (ESR_DLK|ESR_ILK)) | |
1962 | _exception(SIGILL, regs, ILL_PRVOPC, regs->nip); | |
1963 | return; | |
1964 | } | |
1965 | #endif /* CONFIG_FSL_BOOKE */ | |
1966 | ||
1967 | #ifdef CONFIG_SPE | |
1968 | void SPEFloatingPointException(struct pt_regs *regs) | |
1969 | { | |
6a800f36 | 1970 | extern int do_spe_mathemu(struct pt_regs *regs); |
14cf11af PM |
1971 | unsigned long spefscr; |
1972 | int fpexc_mode; | |
cf4674c4 | 1973 | int code = FPE_FIXME; |
6a800f36 LY |
1974 | int err; |
1975 | ||
685659ee | 1976 | flush_spe_to_thread(current); |
14cf11af PM |
1977 | |
1978 | spefscr = current->thread.spefscr; | |
1979 | fpexc_mode = current->thread.fpexc_mode; | |
1980 | ||
14cf11af PM |
1981 | if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) { |
1982 | code = FPE_FLTOVF; | |
14cf11af PM |
1983 | } |
1984 | else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) { | |
1985 | code = FPE_FLTUND; | |
14cf11af PM |
1986 | } |
1987 | else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV)) | |
1988 | code = FPE_FLTDIV; | |
1989 | else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) { | |
1990 | code = FPE_FLTINV; | |
14cf11af PM |
1991 | } |
1992 | else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES)) | |
1993 | code = FPE_FLTRES; | |
1994 | ||
6a800f36 LY |
1995 | err = do_spe_mathemu(regs); |
1996 | if (err == 0) { | |
1997 | regs->nip += 4; /* skip emulated instruction */ | |
1998 | emulate_single_step(regs); | |
1999 | return; | |
2000 | } | |
2001 | ||
2002 | if (err == -EFAULT) { | |
2003 | /* got an error reading the instruction */ | |
2004 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
2005 | } else if (err == -EINVAL) { | |
2006 | /* didn't recognize the instruction */ | |
2007 | printk(KERN_ERR "unrecognized spe instruction " | |
2008 | "in %s at %lx\n", current->comm, regs->nip); | |
2009 | } else { | |
2010 | _exception(SIGFPE, regs, code, regs->nip); | |
2011 | } | |
14cf11af | 2012 | |
14cf11af PM |
2013 | return; |
2014 | } | |
6a800f36 LY |
2015 | |
2016 | void SPEFloatingPointRoundException(struct pt_regs *regs) | |
2017 | { | |
2018 | extern int speround_handler(struct pt_regs *regs); | |
2019 | int err; | |
2020 | ||
2021 | preempt_disable(); | |
2022 | if (regs->msr & MSR_SPE) | |
2023 | giveup_spe(current); | |
2024 | preempt_enable(); | |
2025 | ||
2026 | regs->nip -= 4; | |
2027 | err = speround_handler(regs); | |
2028 | if (err == 0) { | |
2029 | regs->nip += 4; /* skip emulated instruction */ | |
2030 | emulate_single_step(regs); | |
2031 | return; | |
2032 | } | |
2033 | ||
2034 | if (err == -EFAULT) { | |
2035 | /* got an error reading the instruction */ | |
2036 | _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip); | |
2037 | } else if (err == -EINVAL) { | |
2038 | /* didn't recognize the instruction */ | |
2039 | printk(KERN_ERR "unrecognized spe instruction " | |
2040 | "in %s at %lx\n", current->comm, regs->nip); | |
2041 | } else { | |
cf4674c4 | 2042 | _exception(SIGFPE, regs, FPE_FIXME, regs->nip); |
6a800f36 LY |
2043 | return; |
2044 | } | |
2045 | } | |
14cf11af PM |
2046 | #endif |
2047 | ||
dc1c1ca3 SR |
2048 | /* |
2049 | * We enter here if we get an unrecoverable exception, that is, one | |
2050 | * that happened at a point where the RI (recoverable interrupt) bit | |
2051 | * in the MSR is 0. This indicates that SRR0/1 are live, and that | |
2052 | * we therefore lost state by taking this exception. | |
2053 | */ | |
2054 | void unrecoverable_exception(struct pt_regs *regs) | |
2055 | { | |
2056 | printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n", | |
2057 | regs->trap, regs->nip); | |
2058 | die("Unrecoverable exception", regs, SIGABRT); | |
2059 | } | |
15770a13 | 2060 | NOKPROBE_SYMBOL(unrecoverable_exception); |
dc1c1ca3 | 2061 | |
1e18c17a | 2062 | #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x) |
14cf11af PM |
2063 | /* |
2064 | * Default handler for a Watchdog exception, | |
2065 | * spins until a reboot occurs | |
2066 | */ | |
2067 | void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs) | |
2068 | { | |
2069 | /* Generic WatchdogHandler, implement your own */ | |
2070 | mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE)); | |
2071 | return; | |
2072 | } | |
2073 | ||
2074 | void WatchdogException(struct pt_regs *regs) | |
2075 | { | |
2076 | printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n"); | |
2077 | WatchdogHandler(regs); | |
2078 | } | |
2079 | #endif | |
dc1c1ca3 | 2080 | |
dc1c1ca3 SR |
2081 | /* |
2082 | * We enter here if we discover during exception entry that we are | |
2083 | * running in supervisor mode with a userspace value in the stack pointer. | |
2084 | */ | |
2085 | void kernel_bad_stack(struct pt_regs *regs) | |
2086 | { | |
2087 | printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n", | |
2088 | regs->gpr[1], regs->nip); | |
2089 | die("Bad kernel stack pointer", regs, SIGABRT); | |
2090 | } | |
15770a13 | 2091 | NOKPROBE_SYMBOL(kernel_bad_stack); |
14cf11af PM |
2092 | |
2093 | void __init trap_init(void) | |
2094 | { | |
2095 | } | |
80947e7c GU |
2096 | |
2097 | ||
2098 | #ifdef CONFIG_PPC_EMULATED_STATS | |
2099 | ||
2100 | #define WARN_EMULATED_SETUP(type) .type = { .name = #type } | |
2101 | ||
2102 | struct ppc_emulated ppc_emulated = { | |
2103 | #ifdef CONFIG_ALTIVEC | |
2104 | WARN_EMULATED_SETUP(altivec), | |
2105 | #endif | |
2106 | WARN_EMULATED_SETUP(dcba), | |
2107 | WARN_EMULATED_SETUP(dcbz), | |
2108 | WARN_EMULATED_SETUP(fp_pair), | |
2109 | WARN_EMULATED_SETUP(isel), | |
2110 | WARN_EMULATED_SETUP(mcrxr), | |
2111 | WARN_EMULATED_SETUP(mfpvr), | |
2112 | WARN_EMULATED_SETUP(multiple), | |
2113 | WARN_EMULATED_SETUP(popcntb), | |
2114 | WARN_EMULATED_SETUP(spe), | |
2115 | WARN_EMULATED_SETUP(string), | |
a3821b2a | 2116 | WARN_EMULATED_SETUP(sync), |
80947e7c GU |
2117 | WARN_EMULATED_SETUP(unaligned), |
2118 | #ifdef CONFIG_MATH_EMULATION | |
2119 | WARN_EMULATED_SETUP(math), | |
80947e7c GU |
2120 | #endif |
2121 | #ifdef CONFIG_VSX | |
2122 | WARN_EMULATED_SETUP(vsx), | |
2123 | #endif | |
efcac658 AK |
2124 | #ifdef CONFIG_PPC64 |
2125 | WARN_EMULATED_SETUP(mfdscr), | |
2126 | WARN_EMULATED_SETUP(mtdscr), | |
f83319d7 | 2127 | WARN_EMULATED_SETUP(lq_stq), |
5080332c MN |
2128 | WARN_EMULATED_SETUP(lxvw4x), |
2129 | WARN_EMULATED_SETUP(lxvh8x), | |
2130 | WARN_EMULATED_SETUP(lxvd2x), | |
2131 | WARN_EMULATED_SETUP(lxvb16x), | |
efcac658 | 2132 | #endif |
80947e7c GU |
2133 | }; |
2134 | ||
2135 | u32 ppc_warn_emulated; | |
2136 | ||
2137 | void ppc_warn_emulated_print(const char *type) | |
2138 | { | |
76462232 CD |
2139 | pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm, |
2140 | type); | |
80947e7c GU |
2141 | } |
2142 | ||
2143 | static int __init ppc_warn_emulated_init(void) | |
2144 | { | |
2145 | struct dentry *dir, *d; | |
2146 | unsigned int i; | |
2147 | struct ppc_emulated_entry *entries = (void *)&ppc_emulated; | |
2148 | ||
2149 | if (!powerpc_debugfs_root) | |
2150 | return -ENODEV; | |
2151 | ||
2152 | dir = debugfs_create_dir("emulated_instructions", | |
2153 | powerpc_debugfs_root); | |
2154 | if (!dir) | |
2155 | return -ENOMEM; | |
2156 | ||
57ad583f | 2157 | d = debugfs_create_u32("do_warn", 0644, dir, |
80947e7c GU |
2158 | &ppc_warn_emulated); |
2159 | if (!d) | |
2160 | goto fail; | |
2161 | ||
2162 | for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) { | |
57ad583f | 2163 | d = debugfs_create_u32(entries[i].name, 0644, dir, |
80947e7c GU |
2164 | (u32 *)&entries[i].val.counter); |
2165 | if (!d) | |
2166 | goto fail; | |
2167 | } | |
2168 | ||
2169 | return 0; | |
2170 | ||
2171 | fail: | |
2172 | debugfs_remove_recursive(dir); | |
2173 | return -ENOMEM; | |
2174 | } | |
2175 | ||
2176 | device_initcall(ppc_warn_emulated_init); | |
2177 | ||
2178 | #endif /* CONFIG_PPC_EMULATED_STATS */ |