Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * SMP support for ppc. | |
3 | * | |
4 | * Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great | |
5 | * deal of code from the sparc and intel versions. | |
6 | * | |
7 | * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> | |
8 | * | |
9 | * PowerPC-64 Support added by Dave Engebretsen, Peter Bergner, and | |
10 | * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License | |
14 | * as published by the Free Software Foundation; either version | |
15 | * 2 of the License, or (at your option) any later version. | |
16 | */ | |
17 | ||
18 | #undef DEBUG | |
19 | ||
1da177e4 | 20 | #include <linux/kernel.h> |
4b16f8e2 | 21 | #include <linux/export.h> |
68e21be2 | 22 | #include <linux/sched/mm.h> |
105ab3d8 | 23 | #include <linux/sched/topology.h> |
1da177e4 LT |
24 | #include <linux/smp.h> |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/spinlock.h> | |
29 | #include <linux/cache.h> | |
30 | #include <linux/err.h> | |
8a25a2fd | 31 | #include <linux/device.h> |
1da177e4 LT |
32 | #include <linux/cpu.h> |
33 | #include <linux/notifier.h> | |
4b703a23 | 34 | #include <linux/topology.h> |
665e87ff | 35 | #include <linux/profile.h> |
1da177e4 LT |
36 | |
37 | #include <asm/ptrace.h> | |
60063497 | 38 | #include <linux/atomic.h> |
1da177e4 | 39 | #include <asm/irq.h> |
1b67bee1 | 40 | #include <asm/hw_irq.h> |
441c19c8 | 41 | #include <asm/kvm_ppc.h> |
b866cc21 | 42 | #include <asm/dbell.h> |
1da177e4 LT |
43 | #include <asm/page.h> |
44 | #include <asm/pgtable.h> | |
45 | #include <asm/prom.h> | |
46 | #include <asm/smp.h> | |
1da177e4 LT |
47 | #include <asm/time.h> |
48 | #include <asm/machdep.h> | |
e2075f79 | 49 | #include <asm/cputhreads.h> |
1da177e4 | 50 | #include <asm/cputable.h> |
bbeb3f4c | 51 | #include <asm/mpic.h> |
a7f290da | 52 | #include <asm/vdso_datapage.h> |
5ad57078 PM |
53 | #ifdef CONFIG_PPC64 |
54 | #include <asm/paca.h> | |
55 | #endif | |
18ad51dd | 56 | #include <asm/vdso.h> |
ae3a197e | 57 | #include <asm/debug.h> |
1217d34b | 58 | #include <asm/kexec.h> |
42f5b4ca | 59 | #include <asm/asm-prototypes.h> |
b92a226e | 60 | #include <asm/cpu_has_feature.h> |
5ad57078 | 61 | |
1da177e4 | 62 | #ifdef DEBUG |
f9e4ec57 | 63 | #include <asm/udbg.h> |
1da177e4 LT |
64 | #define DBG(fmt...) udbg_printf(fmt) |
65 | #else | |
66 | #define DBG(fmt...) | |
67 | #endif | |
68 | ||
c56e5853 | 69 | #ifdef CONFIG_HOTPLUG_CPU |
fb82b839 BH |
70 | /* State of each CPU during hotplug phases */ |
71 | static DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
c56e5853 BH |
72 | #endif |
73 | ||
f9e4ec57 ME |
74 | struct thread_info *secondary_ti; |
75 | ||
cc1ba8ea AB |
76 | DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
77 | DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); | |
1da177e4 | 78 | |
d5a7430d | 79 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
440a0857 | 80 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
1da177e4 | 81 | |
5ad57078 | 82 | /* SMP operations for this machine */ |
1da177e4 LT |
83 | struct smp_ops_t *smp_ops; |
84 | ||
7ccbe504 BH |
85 | /* Can't be static due to PowerMac hackery */ |
86 | volatile unsigned int cpu_callin_map[NR_CPUS]; | |
1da177e4 | 87 | |
1da177e4 LT |
88 | int smt_enabled_at_boot = 1; |
89 | ||
3cd85250 AF |
90 | /* |
91 | * Returns 1 if the specified cpu should be brought up during boot. | |
92 | * Used to inhibit booting threads if they've been disabled or | |
93 | * limited on the command line | |
94 | */ | |
95 | int smp_generic_cpu_bootable(unsigned int nr) | |
96 | { | |
97 | /* Special case - we inhibit secondary thread startup | |
98 | * during boot if the user requests it. | |
99 | */ | |
100 | if (system_state == SYSTEM_BOOTING && cpu_has_feature(CPU_FTR_SMT)) { | |
101 | if (!smt_enabled_at_boot && cpu_thread_in_core(nr) != 0) | |
102 | return 0; | |
103 | if (smt_enabled_at_boot | |
104 | && cpu_thread_in_core(nr) >= smt_enabled_at_boot) | |
105 | return 0; | |
106 | } | |
107 | ||
108 | return 1; | |
109 | } | |
110 | ||
111 | ||
5ad57078 | 112 | #ifdef CONFIG_PPC64 |
cad5cef6 | 113 | int smp_generic_kick_cpu(int nr) |
1da177e4 | 114 | { |
f8d0d5dc SS |
115 | if (nr < 0 || nr >= NR_CPUS) |
116 | return -EINVAL; | |
1da177e4 LT |
117 | |
118 | /* | |
119 | * The processor is currently spinning, waiting for the | |
120 | * cpu_start field to become non-zero After we set cpu_start, | |
121 | * the processor will continue on to secondary_start | |
122 | */ | |
fb82b839 BH |
123 | if (!paca[nr].cpu_start) { |
124 | paca[nr].cpu_start = 1; | |
125 | smp_mb(); | |
126 | return 0; | |
127 | } | |
128 | ||
129 | #ifdef CONFIG_HOTPLUG_CPU | |
130 | /* | |
131 | * Ok it's not there, so it might be soft-unplugged, let's | |
132 | * try to bring it back | |
133 | */ | |
ae5cab47 | 134 | generic_set_cpu_up(nr); |
fb82b839 BH |
135 | smp_wmb(); |
136 | smp_send_reschedule(nr); | |
137 | #endif /* CONFIG_HOTPLUG_CPU */ | |
de300974 ME |
138 | |
139 | return 0; | |
1da177e4 | 140 | } |
fb82b839 | 141 | #endif /* CONFIG_PPC64 */ |
1da177e4 | 142 | |
25ddd738 MM |
143 | static irqreturn_t call_function_action(int irq, void *data) |
144 | { | |
145 | generic_smp_call_function_interrupt(); | |
146 | return IRQ_HANDLED; | |
147 | } | |
148 | ||
149 | static irqreturn_t reschedule_action(int irq, void *data) | |
150 | { | |
184748cc | 151 | scheduler_ipi(); |
25ddd738 MM |
152 | return IRQ_HANDLED; |
153 | } | |
154 | ||
1b67bee1 | 155 | static irqreturn_t tick_broadcast_ipi_action(int irq, void *data) |
25ddd738 | 156 | { |
1b67bee1 | 157 | tick_broadcast_ipi_handler(); |
25ddd738 MM |
158 | return IRQ_HANDLED; |
159 | } | |
160 | ||
ddd703ca NP |
161 | #ifdef CONFIG_NMI_IPI |
162 | static irqreturn_t nmi_ipi_action(int irq, void *data) | |
25ddd738 | 163 | { |
ddd703ca | 164 | smp_handle_nmi_ipi(get_irq_regs()); |
25ddd738 MM |
165 | return IRQ_HANDLED; |
166 | } | |
ddd703ca | 167 | #endif |
25ddd738 MM |
168 | |
169 | static irq_handler_t smp_ipi_action[] = { | |
170 | [PPC_MSG_CALL_FUNCTION] = call_function_action, | |
171 | [PPC_MSG_RESCHEDULE] = reschedule_action, | |
1b67bee1 | 172 | [PPC_MSG_TICK_BROADCAST] = tick_broadcast_ipi_action, |
ddd703ca NP |
173 | #ifdef CONFIG_NMI_IPI |
174 | [PPC_MSG_NMI_IPI] = nmi_ipi_action, | |
175 | #endif | |
25ddd738 MM |
176 | }; |
177 | ||
ddd703ca NP |
178 | /* |
179 | * The NMI IPI is a fallback and not truly non-maskable. It is simpler | |
180 | * than going through the call function infrastructure, and strongly | |
181 | * serialized, so it is more appropriate for debugging. | |
182 | */ | |
25ddd738 MM |
183 | const char *smp_ipi_name[] = { |
184 | [PPC_MSG_CALL_FUNCTION] = "ipi call function", | |
185 | [PPC_MSG_RESCHEDULE] = "ipi reschedule", | |
1b67bee1 | 186 | [PPC_MSG_TICK_BROADCAST] = "ipi tick-broadcast", |
ddd703ca | 187 | [PPC_MSG_NMI_IPI] = "nmi ipi", |
25ddd738 MM |
188 | }; |
189 | ||
190 | /* optional function to request ipi, for controllers with >= 4 ipis */ | |
191 | int smp_request_message_ipi(int virq, int msg) | |
192 | { | |
193 | int err; | |
194 | ||
ddd703ca | 195 | if (msg < 0 || msg > PPC_MSG_NMI_IPI) |
25ddd738 | 196 | return -EINVAL; |
ddd703ca NP |
197 | #ifndef CONFIG_NMI_IPI |
198 | if (msg == PPC_MSG_NMI_IPI) | |
25ddd738 | 199 | return 1; |
25ddd738 | 200 | #endif |
ddd703ca | 201 | |
3b5e16d7 | 202 | err = request_irq(virq, smp_ipi_action[msg], |
e6651de9 | 203 | IRQF_PERCPU | IRQF_NO_THREAD | IRQF_NO_SUSPEND, |
b0d436c7 | 204 | smp_ipi_name[msg], NULL); |
25ddd738 MM |
205 | WARN(err < 0, "unable to request_irq %d for %s (rc %d)\n", |
206 | virq, smp_ipi_name[msg], err); | |
207 | ||
208 | return err; | |
209 | } | |
210 | ||
1ece355b | 211 | #ifdef CONFIG_PPC_SMP_MUXED_IPI |
23d72bfd | 212 | struct cpu_messages { |
bd7f561f | 213 | long messages; /* current messages */ |
23d72bfd MM |
214 | }; |
215 | static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_messages, ipi_message); | |
216 | ||
31639c77 | 217 | void smp_muxed_ipi_set_message(int cpu, int msg) |
23d72bfd MM |
218 | { |
219 | struct cpu_messages *info = &per_cpu(ipi_message, cpu); | |
71454272 | 220 | char *message = (char *)&info->messages; |
23d72bfd | 221 | |
9fb1b36c PM |
222 | /* |
223 | * Order previous accesses before accesses in the IPI handler. | |
224 | */ | |
225 | smp_mb(); | |
71454272 | 226 | message[msg] = 1; |
31639c77 SW |
227 | } |
228 | ||
229 | void smp_muxed_ipi_message_pass(int cpu, int msg) | |
230 | { | |
31639c77 | 231 | smp_muxed_ipi_set_message(cpu, msg); |
b866cc21 | 232 | |
9fb1b36c PM |
233 | /* |
234 | * cause_ipi functions are required to include a full barrier | |
235 | * before doing whatever causes the IPI. | |
236 | */ | |
b866cc21 | 237 | smp_ops->cause_ipi(cpu); |
23d72bfd MM |
238 | } |
239 | ||
0654de1c | 240 | #ifdef __BIG_ENDIAN__ |
bd7f561f | 241 | #define IPI_MESSAGE(A) (1uL << ((BITS_PER_LONG - 8) - 8 * (A))) |
0654de1c | 242 | #else |
bd7f561f | 243 | #define IPI_MESSAGE(A) (1uL << (8 * (A))) |
0654de1c AB |
244 | #endif |
245 | ||
23d72bfd MM |
246 | irqreturn_t smp_ipi_demux(void) |
247 | { | |
23d72bfd | 248 | mb(); /* order any irq clear */ |
71454272 | 249 | |
b87ac021 NP |
250 | return smp_ipi_demux_relaxed(); |
251 | } | |
252 | ||
253 | /* sync-free variant. Callers should ensure synchronization */ | |
254 | irqreturn_t smp_ipi_demux_relaxed(void) | |
23d72bfd | 255 | { |
b866cc21 | 256 | struct cpu_messages *info; |
bd7f561f | 257 | unsigned long all; |
23d72bfd | 258 | |
b866cc21 | 259 | info = this_cpu_ptr(&ipi_message); |
71454272 | 260 | do { |
9fb1b36c | 261 | all = xchg(&info->messages, 0); |
e17769eb SW |
262 | #if defined(CONFIG_KVM_XICS) && defined(CONFIG_KVM_BOOK3S_HV_POSSIBLE) |
263 | /* | |
264 | * Must check for PPC_MSG_RM_HOST_ACTION messages | |
265 | * before PPC_MSG_CALL_FUNCTION messages because when | |
266 | * a VM is destroyed, we call kick_all_cpus_sync() | |
267 | * to ensure that any pending PPC_MSG_RM_HOST_ACTION | |
268 | * messages have completed before we free any VCPUs. | |
269 | */ | |
270 | if (all & IPI_MESSAGE(PPC_MSG_RM_HOST_ACTION)) | |
271 | kvmppc_xics_ipi_action(); | |
272 | #endif | |
0654de1c | 273 | if (all & IPI_MESSAGE(PPC_MSG_CALL_FUNCTION)) |
23d72bfd | 274 | generic_smp_call_function_interrupt(); |
0654de1c | 275 | if (all & IPI_MESSAGE(PPC_MSG_RESCHEDULE)) |
880102e7 | 276 | scheduler_ipi(); |
1b67bee1 SB |
277 | if (all & IPI_MESSAGE(PPC_MSG_TICK_BROADCAST)) |
278 | tick_broadcast_ipi_handler(); | |
ddd703ca NP |
279 | #ifdef CONFIG_NMI_IPI |
280 | if (all & IPI_MESSAGE(PPC_MSG_NMI_IPI)) | |
281 | nmi_ipi_action(0, NULL); | |
282 | #endif | |
71454272 MM |
283 | } while (info->messages); |
284 | ||
23d72bfd MM |
285 | return IRQ_HANDLED; |
286 | } | |
1ece355b | 287 | #endif /* CONFIG_PPC_SMP_MUXED_IPI */ |
23d72bfd | 288 | |
9ca980dc PM |
289 | static inline void do_message_pass(int cpu, int msg) |
290 | { | |
291 | if (smp_ops->message_pass) | |
292 | smp_ops->message_pass(cpu, msg); | |
293 | #ifdef CONFIG_PPC_SMP_MUXED_IPI | |
294 | else | |
295 | smp_muxed_ipi_message_pass(cpu, msg); | |
296 | #endif | |
297 | } | |
298 | ||
1da177e4 LT |
299 | void smp_send_reschedule(int cpu) |
300 | { | |
8cffc6ac | 301 | if (likely(smp_ops)) |
9ca980dc | 302 | do_message_pass(cpu, PPC_MSG_RESCHEDULE); |
1da177e4 | 303 | } |
de56a948 | 304 | EXPORT_SYMBOL_GPL(smp_send_reschedule); |
1da177e4 | 305 | |
b7d7a240 JA |
306 | void arch_send_call_function_single_ipi(int cpu) |
307 | { | |
402d9a1e | 308 | do_message_pass(cpu, PPC_MSG_CALL_FUNCTION); |
b7d7a240 JA |
309 | } |
310 | ||
f063ea02 | 311 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
b7d7a240 JA |
312 | { |
313 | unsigned int cpu; | |
314 | ||
f063ea02 | 315 | for_each_cpu(cpu, mask) |
9ca980dc | 316 | do_message_pass(cpu, PPC_MSG_CALL_FUNCTION); |
b7d7a240 JA |
317 | } |
318 | ||
ddd703ca NP |
319 | #ifdef CONFIG_NMI_IPI |
320 | ||
321 | /* | |
322 | * "NMI IPI" system. | |
323 | * | |
324 | * NMI IPIs may not be recoverable, so should not be used as ongoing part of | |
325 | * a running system. They can be used for crash, debug, halt/reboot, etc. | |
326 | * | |
327 | * NMI IPIs are globally single threaded. No more than one in progress at | |
328 | * any time. | |
329 | * | |
330 | * The IPI call waits with interrupts disabled until all targets enter the | |
331 | * NMI handler, then the call returns. | |
332 | * | |
333 | * No new NMI can be initiated until targets exit the handler. | |
334 | * | |
335 | * The IPI call may time out without all targets entering the NMI handler. | |
336 | * In that case, there is some logic to recover (and ignore subsequent | |
337 | * NMI interrupts that may eventually be raised), but the platform interrupt | |
338 | * handler may not be able to distinguish this from other exception causes, | |
339 | * which may cause a crash. | |
340 | */ | |
341 | ||
342 | static atomic_t __nmi_ipi_lock = ATOMIC_INIT(0); | |
343 | static struct cpumask nmi_ipi_pending_mask; | |
344 | static int nmi_ipi_busy_count = 0; | |
345 | static void (*nmi_ipi_function)(struct pt_regs *) = NULL; | |
346 | ||
347 | static void nmi_ipi_lock_start(unsigned long *flags) | |
348 | { | |
349 | raw_local_irq_save(*flags); | |
350 | hard_irq_disable(); | |
351 | while (atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1) { | |
352 | raw_local_irq_restore(*flags); | |
353 | cpu_relax(); | |
354 | raw_local_irq_save(*flags); | |
355 | hard_irq_disable(); | |
356 | } | |
357 | } | |
358 | ||
359 | static void nmi_ipi_lock(void) | |
360 | { | |
361 | while (atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1) | |
362 | cpu_relax(); | |
363 | } | |
364 | ||
365 | static void nmi_ipi_unlock(void) | |
366 | { | |
367 | smp_mb(); | |
368 | WARN_ON(atomic_read(&__nmi_ipi_lock) != 1); | |
369 | atomic_set(&__nmi_ipi_lock, 0); | |
370 | } | |
371 | ||
372 | static void nmi_ipi_unlock_end(unsigned long *flags) | |
373 | { | |
374 | nmi_ipi_unlock(); | |
375 | raw_local_irq_restore(*flags); | |
376 | } | |
377 | ||
378 | /* | |
379 | * Platform NMI handler calls this to ack | |
380 | */ | |
381 | int smp_handle_nmi_ipi(struct pt_regs *regs) | |
382 | { | |
383 | void (*fn)(struct pt_regs *); | |
384 | unsigned long flags; | |
385 | int me = raw_smp_processor_id(); | |
386 | int ret = 0; | |
387 | ||
388 | /* | |
389 | * Unexpected NMIs are possible here because the interrupt may not | |
390 | * be able to distinguish NMI IPIs from other types of NMIs, or | |
391 | * because the caller may have timed out. | |
392 | */ | |
393 | nmi_ipi_lock_start(&flags); | |
394 | if (!nmi_ipi_busy_count) | |
395 | goto out; | |
396 | if (!cpumask_test_cpu(me, &nmi_ipi_pending_mask)) | |
397 | goto out; | |
398 | ||
399 | fn = nmi_ipi_function; | |
400 | if (!fn) | |
401 | goto out; | |
402 | ||
403 | cpumask_clear_cpu(me, &nmi_ipi_pending_mask); | |
404 | nmi_ipi_busy_count++; | |
405 | nmi_ipi_unlock(); | |
406 | ||
407 | ret = 1; | |
408 | ||
409 | fn(regs); | |
410 | ||
411 | nmi_ipi_lock(); | |
412 | nmi_ipi_busy_count--; | |
413 | out: | |
414 | nmi_ipi_unlock_end(&flags); | |
415 | ||
416 | return ret; | |
417 | } | |
418 | ||
419 | static void do_smp_send_nmi_ipi(int cpu) | |
420 | { | |
c64af645 NP |
421 | if (smp_ops->cause_nmi_ipi && smp_ops->cause_nmi_ipi(cpu)) |
422 | return; | |
423 | ||
ddd703ca NP |
424 | if (cpu >= 0) { |
425 | do_message_pass(cpu, PPC_MSG_NMI_IPI); | |
426 | } else { | |
427 | int c; | |
428 | ||
429 | for_each_online_cpu(c) { | |
430 | if (c == raw_smp_processor_id()) | |
431 | continue; | |
432 | do_message_pass(c, PPC_MSG_NMI_IPI); | |
433 | } | |
434 | } | |
435 | } | |
436 | ||
437 | /* | |
438 | * - cpu is the target CPU (must not be this CPU), or NMI_IPI_ALL_OTHERS. | |
439 | * - fn is the target callback function. | |
440 | * - delay_us > 0 is the delay before giving up waiting for targets to | |
441 | * enter the handler, == 0 specifies indefinite delay. | |
442 | */ | |
443 | static int smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us) | |
444 | { | |
445 | unsigned long flags; | |
446 | int me = raw_smp_processor_id(); | |
447 | int ret = 1; | |
448 | ||
449 | BUG_ON(cpu == me); | |
450 | BUG_ON(cpu < 0 && cpu != NMI_IPI_ALL_OTHERS); | |
451 | ||
452 | if (unlikely(!smp_ops)) | |
453 | return 0; | |
454 | ||
455 | /* Take the nmi_ipi_busy count/lock with interrupts hard disabled */ | |
456 | nmi_ipi_lock_start(&flags); | |
457 | while (nmi_ipi_busy_count) { | |
458 | nmi_ipi_unlock_end(&flags); | |
459 | cpu_relax(); | |
460 | nmi_ipi_lock_start(&flags); | |
461 | } | |
462 | ||
463 | nmi_ipi_function = fn; | |
464 | ||
465 | if (cpu < 0) { | |
466 | /* ALL_OTHERS */ | |
467 | cpumask_copy(&nmi_ipi_pending_mask, cpu_online_mask); | |
468 | cpumask_clear_cpu(me, &nmi_ipi_pending_mask); | |
469 | } else { | |
470 | /* cpumask starts clear */ | |
471 | cpumask_set_cpu(cpu, &nmi_ipi_pending_mask); | |
472 | } | |
473 | nmi_ipi_busy_count++; | |
474 | nmi_ipi_unlock(); | |
475 | ||
476 | do_smp_send_nmi_ipi(cpu); | |
477 | ||
478 | while (!cpumask_empty(&nmi_ipi_pending_mask)) { | |
479 | udelay(1); | |
480 | if (delay_us) { | |
481 | delay_us--; | |
482 | if (!delay_us) | |
483 | break; | |
484 | } | |
485 | } | |
486 | ||
487 | nmi_ipi_lock(); | |
488 | if (!cpumask_empty(&nmi_ipi_pending_mask)) { | |
489 | /* Could not gather all CPUs */ | |
490 | ret = 0; | |
491 | cpumask_clear(&nmi_ipi_pending_mask); | |
492 | } | |
493 | nmi_ipi_busy_count--; | |
494 | nmi_ipi_unlock_end(&flags); | |
495 | ||
496 | return ret; | |
497 | } | |
498 | #endif /* CONFIG_NMI_IPI */ | |
499 | ||
1b67bee1 SB |
500 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
501 | void tick_broadcast(const struct cpumask *mask) | |
502 | { | |
503 | unsigned int cpu; | |
504 | ||
505 | for_each_cpu(cpu, mask) | |
506 | do_message_pass(cpu, PPC_MSG_TICK_BROADCAST); | |
507 | } | |
508 | #endif | |
509 | ||
ddd703ca NP |
510 | #ifdef CONFIG_DEBUGGER |
511 | void debugger_ipi_callback(struct pt_regs *regs) | |
1da177e4 | 512 | { |
ddd703ca NP |
513 | debugger_ipi(regs); |
514 | } | |
e0476371 | 515 | |
ddd703ca NP |
516 | void smp_send_debugger_break(void) |
517 | { | |
518 | smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, debugger_ipi_callback, 1000000); | |
1da177e4 LT |
519 | } |
520 | #endif | |
521 | ||
da665885 | 522 | #ifdef CONFIG_KEXEC_CORE |
cc532915 ME |
523 | void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *)) |
524 | { | |
ddd703ca | 525 | smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, crash_ipi_callback, 1000000); |
cc532915 ME |
526 | } |
527 | #endif | |
528 | ||
1da177e4 LT |
529 | static void stop_this_cpu(void *dummy) |
530 | { | |
8389b37d VB |
531 | /* Remove this CPU */ |
532 | set_cpu_online(smp_processor_id(), false); | |
533 | ||
1da177e4 LT |
534 | local_irq_disable(); |
535 | while (1) | |
536 | ; | |
537 | } | |
538 | ||
8fd7675c SS |
539 | void smp_send_stop(void) |
540 | { | |
8691e5a8 | 541 | smp_call_function(stop_this_cpu, NULL, 0); |
1da177e4 LT |
542 | } |
543 | ||
1da177e4 LT |
544 | struct thread_info *current_set[NR_CPUS]; |
545 | ||
cad5cef6 | 546 | static void smp_store_cpu_info(int id) |
1da177e4 | 547 | { |
6b7487fc | 548 | per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR); |
3160b097 BB |
549 | #ifdef CONFIG_PPC_FSL_BOOK3E |
550 | per_cpu(next_tlbcam_idx, id) | |
551 | = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1; | |
552 | #endif | |
1da177e4 LT |
553 | } |
554 | ||
1da177e4 LT |
555 | void __init smp_prepare_cpus(unsigned int max_cpus) |
556 | { | |
557 | unsigned int cpu; | |
558 | ||
559 | DBG("smp_prepare_cpus\n"); | |
560 | ||
561 | /* | |
562 | * setup_cpu may need to be called on the boot cpu. We havent | |
563 | * spun any cpus up but lets be paranoid. | |
564 | */ | |
565 | BUG_ON(boot_cpuid != smp_processor_id()); | |
566 | ||
567 | /* Fixup boot cpu */ | |
568 | smp_store_cpu_info(boot_cpuid); | |
569 | cpu_callin_map[boot_cpuid] = 1; | |
570 | ||
cc1ba8ea AB |
571 | for_each_possible_cpu(cpu) { |
572 | zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu), | |
573 | GFP_KERNEL, cpu_to_node(cpu)); | |
574 | zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu), | |
575 | GFP_KERNEL, cpu_to_node(cpu)); | |
2fabf084 NA |
576 | /* |
577 | * numa_node_id() works after this. | |
578 | */ | |
bc3c4327 LZ |
579 | if (cpu_present(cpu)) { |
580 | set_cpu_numa_node(cpu, numa_cpu_lookup_table[cpu]); | |
581 | set_cpu_numa_mem(cpu, | |
582 | local_memory_node(numa_cpu_lookup_table[cpu])); | |
583 | } | |
cc1ba8ea AB |
584 | } |
585 | ||
586 | cpumask_set_cpu(boot_cpuid, cpu_sibling_mask(boot_cpuid)); | |
587 | cpumask_set_cpu(boot_cpuid, cpu_core_mask(boot_cpuid)); | |
588 | ||
dfee0efe CG |
589 | if (smp_ops && smp_ops->probe) |
590 | smp_ops->probe(); | |
1da177e4 LT |
591 | } |
592 | ||
cad5cef6 | 593 | void smp_prepare_boot_cpu(void) |
1da177e4 LT |
594 | { |
595 | BUG_ON(smp_processor_id() != boot_cpuid); | |
5ad57078 | 596 | #ifdef CONFIG_PPC64 |
1da177e4 | 597 | paca[boot_cpuid].__current = current; |
5ad57078 | 598 | #endif |
8c272261 | 599 | set_numa_node(numa_cpu_lookup_table[boot_cpuid]); |
b5e2fc1c | 600 | current_set[boot_cpuid] = task_thread_info(current); |
1da177e4 LT |
601 | } |
602 | ||
603 | #ifdef CONFIG_HOTPLUG_CPU | |
1da177e4 LT |
604 | |
605 | int generic_cpu_disable(void) | |
606 | { | |
607 | unsigned int cpu = smp_processor_id(); | |
608 | ||
609 | if (cpu == boot_cpuid) | |
610 | return -EBUSY; | |
611 | ||
ea0f1cab | 612 | set_cpu_online(cpu, false); |
799d6046 | 613 | #ifdef CONFIG_PPC64 |
a7f290da | 614 | vdso_data->processorCount--; |
094fe2e7 | 615 | #endif |
a978e139 BH |
616 | /* Update affinity of all IRQs previously aimed at this CPU */ |
617 | irq_migrate_all_off_this_cpu(); | |
618 | ||
687b8f24 ME |
619 | /* |
620 | * Depending on the details of the interrupt controller, it's possible | |
621 | * that one of the interrupts we just migrated away from this CPU is | |
622 | * actually already pending on this CPU. If we leave it in that state | |
623 | * the interrupt will never be EOI'ed, and will never fire again. So | |
624 | * temporarily enable interrupts here, to allow any pending interrupt to | |
625 | * be received (and EOI'ed), before we take this CPU offline. | |
626 | */ | |
a978e139 BH |
627 | local_irq_enable(); |
628 | mdelay(1); | |
629 | local_irq_disable(); | |
630 | ||
1da177e4 LT |
631 | return 0; |
632 | } | |
633 | ||
1da177e4 LT |
634 | void generic_cpu_die(unsigned int cpu) |
635 | { | |
636 | int i; | |
637 | ||
638 | for (i = 0; i < 100; i++) { | |
0d8d4d42 | 639 | smp_rmb(); |
2f4f1f81 | 640 | if (is_cpu_dead(cpu)) |
1da177e4 LT |
641 | return; |
642 | msleep(100); | |
643 | } | |
644 | printk(KERN_ERR "CPU%d didn't die...\n", cpu); | |
645 | } | |
646 | ||
105765f4 BH |
647 | void generic_set_cpu_dead(unsigned int cpu) |
648 | { | |
649 | per_cpu(cpu_state, cpu) = CPU_DEAD; | |
650 | } | |
fb82b839 | 651 | |
ae5cab47 ZC |
652 | /* |
653 | * The cpu_state should be set to CPU_UP_PREPARE in kick_cpu(), otherwise | |
654 | * the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(), | |
655 | * which makes the delay in generic_cpu_die() not happen. | |
656 | */ | |
657 | void generic_set_cpu_up(unsigned int cpu) | |
658 | { | |
659 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
660 | } | |
661 | ||
fb82b839 BH |
662 | int generic_check_cpu_restart(unsigned int cpu) |
663 | { | |
664 | return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE; | |
665 | } | |
512691d4 | 666 | |
2f4f1f81 | 667 | int is_cpu_dead(unsigned int cpu) |
668 | { | |
669 | return per_cpu(cpu_state, cpu) == CPU_DEAD; | |
670 | } | |
671 | ||
441c19c8 | 672 | static bool secondaries_inhibited(void) |
512691d4 | 673 | { |
441c19c8 | 674 | return kvm_hv_mode_active(); |
512691d4 PM |
675 | } |
676 | ||
677 | #else /* HOTPLUG_CPU */ | |
678 | ||
679 | #define secondaries_inhibited() 0 | |
680 | ||
1da177e4 LT |
681 | #endif |
682 | ||
17e32eac | 683 | static void cpu_idle_thread_init(unsigned int cpu, struct task_struct *idle) |
c56e5853 | 684 | { |
17e32eac | 685 | struct thread_info *ti = task_thread_info(idle); |
c56e5853 BH |
686 | |
687 | #ifdef CONFIG_PPC64 | |
17e32eac | 688 | paca[cpu].__current = idle; |
c56e5853 BH |
689 | paca[cpu].kstack = (unsigned long)ti + THREAD_SIZE - STACK_FRAME_OVERHEAD; |
690 | #endif | |
691 | ti->cpu = cpu; | |
17e32eac | 692 | secondary_ti = current_set[cpu] = ti; |
c56e5853 BH |
693 | } |
694 | ||
061d19f2 | 695 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 696 | { |
c56e5853 | 697 | int rc, c; |
1da177e4 | 698 | |
512691d4 PM |
699 | /* |
700 | * Don't allow secondary threads to come online if inhibited | |
701 | */ | |
702 | if (threads_per_core > 1 && secondaries_inhibited() && | |
6f5e40a3 | 703 | cpu_thread_in_subcore(cpu)) |
512691d4 PM |
704 | return -EBUSY; |
705 | ||
8cffc6ac BH |
706 | if (smp_ops == NULL || |
707 | (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu))) | |
1da177e4 LT |
708 | return -EINVAL; |
709 | ||
17e32eac | 710 | cpu_idle_thread_init(cpu, tidle); |
c560bbce | 711 | |
14d4ae5c BH |
712 | /* |
713 | * The platform might need to allocate resources prior to bringing | |
714 | * up the CPU | |
715 | */ | |
716 | if (smp_ops->prepare_cpu) { | |
717 | rc = smp_ops->prepare_cpu(cpu); | |
718 | if (rc) | |
719 | return rc; | |
720 | } | |
721 | ||
1da177e4 LT |
722 | /* Make sure callin-map entry is 0 (can be leftover a CPU |
723 | * hotplug | |
724 | */ | |
725 | cpu_callin_map[cpu] = 0; | |
726 | ||
727 | /* The information for processor bringup must | |
728 | * be written out to main store before we release | |
729 | * the processor. | |
730 | */ | |
0d8d4d42 | 731 | smp_mb(); |
1da177e4 LT |
732 | |
733 | /* wake up cpus */ | |
734 | DBG("smp: kicking cpu %d\n", cpu); | |
de300974 ME |
735 | rc = smp_ops->kick_cpu(cpu); |
736 | if (rc) { | |
737 | pr_err("smp: failed starting cpu %d (rc %d)\n", cpu, rc); | |
738 | return rc; | |
739 | } | |
1da177e4 LT |
740 | |
741 | /* | |
742 | * wait to see if the cpu made a callin (is actually up). | |
743 | * use this value that I found through experimentation. | |
744 | * -- Cort | |
745 | */ | |
746 | if (system_state < SYSTEM_RUNNING) | |
ee0339f2 | 747 | for (c = 50000; c && !cpu_callin_map[cpu]; c--) |
1da177e4 LT |
748 | udelay(100); |
749 | #ifdef CONFIG_HOTPLUG_CPU | |
750 | else | |
751 | /* | |
752 | * CPUs can take much longer to come up in the | |
753 | * hotplug case. Wait five seconds. | |
754 | */ | |
67764263 GS |
755 | for (c = 5000; c && !cpu_callin_map[cpu]; c--) |
756 | msleep(1); | |
1da177e4 LT |
757 | #endif |
758 | ||
759 | if (!cpu_callin_map[cpu]) { | |
6685a477 | 760 | printk(KERN_ERR "Processor %u is stuck.\n", cpu); |
1da177e4 LT |
761 | return -ENOENT; |
762 | } | |
763 | ||
6685a477 | 764 | DBG("Processor %u found.\n", cpu); |
1da177e4 LT |
765 | |
766 | if (smp_ops->give_timebase) | |
767 | smp_ops->give_timebase(); | |
768 | ||
875ebe94 | 769 | /* Wait until cpu puts itself in the online & active maps */ |
e9d867a6 | 770 | while (!cpu_online(cpu)) |
1da177e4 LT |
771 | cpu_relax(); |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
e9efed3b NL |
776 | /* Return the value of the reg property corresponding to the given |
777 | * logical cpu. | |
778 | */ | |
779 | int cpu_to_core_id(int cpu) | |
780 | { | |
781 | struct device_node *np; | |
f8a1883a | 782 | const __be32 *reg; |
e9efed3b NL |
783 | int id = -1; |
784 | ||
785 | np = of_get_cpu_node(cpu, NULL); | |
786 | if (!np) | |
787 | goto out; | |
788 | ||
789 | reg = of_get_property(np, "reg", NULL); | |
790 | if (!reg) | |
791 | goto out; | |
792 | ||
f8a1883a | 793 | id = be32_to_cpup(reg); |
e9efed3b NL |
794 | out: |
795 | of_node_put(np); | |
796 | return id; | |
797 | } | |
f8ab4810 | 798 | EXPORT_SYMBOL_GPL(cpu_to_core_id); |
e9efed3b | 799 | |
99d86705 VS |
800 | /* Helper routines for cpu to core mapping */ |
801 | int cpu_core_index_of_thread(int cpu) | |
802 | { | |
803 | return cpu >> threads_shift; | |
804 | } | |
805 | EXPORT_SYMBOL_GPL(cpu_core_index_of_thread); | |
806 | ||
807 | int cpu_first_thread_of_core(int core) | |
808 | { | |
809 | return core << threads_shift; | |
810 | } | |
811 | EXPORT_SYMBOL_GPL(cpu_first_thread_of_core); | |
812 | ||
256f2d4b PM |
813 | static void traverse_siblings_chip_id(int cpu, bool add, int chipid) |
814 | { | |
815 | const struct cpumask *mask; | |
816 | struct device_node *np; | |
817 | int i, plen; | |
818 | const __be32 *prop; | |
819 | ||
820 | mask = add ? cpu_online_mask : cpu_present_mask; | |
821 | for_each_cpu(i, mask) { | |
822 | np = of_get_cpu_node(i, NULL); | |
823 | if (!np) | |
824 | continue; | |
825 | prop = of_get_property(np, "ibm,chip-id", &plen); | |
826 | if (prop && plen == sizeof(int) && | |
827 | of_read_number(prop, 1) == chipid) { | |
828 | if (add) { | |
829 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
830 | cpumask_set_cpu(i, cpu_core_mask(cpu)); | |
831 | } else { | |
832 | cpumask_clear_cpu(cpu, cpu_core_mask(i)); | |
833 | cpumask_clear_cpu(i, cpu_core_mask(cpu)); | |
834 | } | |
835 | } | |
836 | of_node_put(np); | |
837 | } | |
838 | } | |
839 | ||
104699c0 | 840 | /* Must be called when no change can occur to cpu_present_mask, |
440a0857 NL |
841 | * i.e. during cpu online or offline. |
842 | */ | |
843 | static struct device_node *cpu_to_l2cache(int cpu) | |
844 | { | |
845 | struct device_node *np; | |
b2ea25b9 | 846 | struct device_node *cache; |
440a0857 NL |
847 | |
848 | if (!cpu_present(cpu)) | |
849 | return NULL; | |
850 | ||
851 | np = of_get_cpu_node(cpu, NULL); | |
852 | if (np == NULL) | |
853 | return NULL; | |
854 | ||
b2ea25b9 NL |
855 | cache = of_find_next_cache_node(np); |
856 | ||
440a0857 NL |
857 | of_node_put(np); |
858 | ||
b2ea25b9 | 859 | return cache; |
440a0857 | 860 | } |
1da177e4 | 861 | |
a8a5356c PM |
862 | static void traverse_core_siblings(int cpu, bool add) |
863 | { | |
256f2d4b | 864 | struct device_node *l2_cache, *np; |
a8a5356c | 865 | const struct cpumask *mask; |
256f2d4b PM |
866 | int i, chip, plen; |
867 | const __be32 *prop; | |
868 | ||
869 | /* First see if we have ibm,chip-id properties in cpu nodes */ | |
870 | np = of_get_cpu_node(cpu, NULL); | |
871 | if (np) { | |
872 | chip = -1; | |
873 | prop = of_get_property(np, "ibm,chip-id", &plen); | |
874 | if (prop && plen == sizeof(int)) | |
875 | chip = of_read_number(prop, 1); | |
876 | of_node_put(np); | |
877 | if (chip >= 0) { | |
878 | traverse_siblings_chip_id(cpu, add, chip); | |
879 | return; | |
880 | } | |
881 | } | |
a8a5356c PM |
882 | |
883 | l2_cache = cpu_to_l2cache(cpu); | |
884 | mask = add ? cpu_online_mask : cpu_present_mask; | |
885 | for_each_cpu(i, mask) { | |
256f2d4b | 886 | np = cpu_to_l2cache(i); |
a8a5356c PM |
887 | if (!np) |
888 | continue; | |
889 | if (np == l2_cache) { | |
890 | if (add) { | |
891 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
892 | cpumask_set_cpu(i, cpu_core_mask(cpu)); | |
893 | } else { | |
894 | cpumask_clear_cpu(cpu, cpu_core_mask(i)); | |
895 | cpumask_clear_cpu(i, cpu_core_mask(cpu)); | |
896 | } | |
897 | } | |
898 | of_node_put(np); | |
899 | } | |
900 | of_node_put(l2_cache); | |
901 | } | |
902 | ||
1da177e4 | 903 | /* Activate a secondary processor. */ |
061d19f2 | 904 | void start_secondary(void *unused) |
1da177e4 LT |
905 | { |
906 | unsigned int cpu = smp_processor_id(); | |
e2075f79 | 907 | int i, base; |
1da177e4 | 908 | |
f1f10076 | 909 | mmgrab(&init_mm); |
1da177e4 LT |
910 | current->active_mm = &init_mm; |
911 | ||
912 | smp_store_cpu_info(cpu); | |
5ad57078 | 913 | set_dec(tb_ticks_per_jiffy); |
e4d76e1c | 914 | preempt_disable(); |
1be6f10f | 915 | cpu_callin_map[cpu] = 1; |
1da177e4 | 916 | |
757cbd46 KG |
917 | if (smp_ops->setup_cpu) |
918 | smp_ops->setup_cpu(cpu); | |
1da177e4 LT |
919 | if (smp_ops->take_timebase) |
920 | smp_ops->take_timebase(); | |
921 | ||
d831d0b8 TB |
922 | secondary_cpu_time_init(); |
923 | ||
aeeafbfa BH |
924 | #ifdef CONFIG_PPC64 |
925 | if (system_state == SYSTEM_RUNNING) | |
926 | vdso_data->processorCount++; | |
18ad51dd AB |
927 | |
928 | vdso_getcpu_init(); | |
aeeafbfa | 929 | #endif |
e2075f79 | 930 | /* Update sibling maps */ |
99d86705 | 931 | base = cpu_first_thread_sibling(cpu); |
e2075f79 | 932 | for (i = 0; i < threads_per_core; i++) { |
cce606fe | 933 | if (cpu_is_offline(base + i) && (cpu != base + i)) |
e2075f79 | 934 | continue; |
cc1ba8ea AB |
935 | cpumask_set_cpu(cpu, cpu_sibling_mask(base + i)); |
936 | cpumask_set_cpu(base + i, cpu_sibling_mask(cpu)); | |
440a0857 NL |
937 | |
938 | /* cpu_core_map should be a superset of | |
939 | * cpu_sibling_map even if we don't have cache | |
940 | * information, so update the former here, too. | |
941 | */ | |
cc1ba8ea AB |
942 | cpumask_set_cpu(cpu, cpu_core_mask(base + i)); |
943 | cpumask_set_cpu(base + i, cpu_core_mask(cpu)); | |
e2075f79 | 944 | } |
a8a5356c | 945 | traverse_core_siblings(cpu, true); |
1da177e4 | 946 | |
bc3c4327 LZ |
947 | set_numa_node(numa_cpu_lookup_table[cpu]); |
948 | set_numa_mem(local_memory_node(numa_cpu_lookup_table[cpu])); | |
949 | ||
cce606fe LZ |
950 | smp_wmb(); |
951 | notify_cpu_starting(cpu); | |
952 | set_cpu_online(cpu, true); | |
953 | ||
1da177e4 LT |
954 | local_irq_enable(); |
955 | ||
fc6d73d6 | 956 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
fa3f82c8 BH |
957 | |
958 | BUG(); | |
1da177e4 LT |
959 | } |
960 | ||
961 | int setup_profiling_timer(unsigned int multiplier) | |
962 | { | |
963 | return 0; | |
964 | } | |
965 | ||
607b45e9 VG |
966 | #ifdef CONFIG_SCHED_SMT |
967 | /* cpumask of CPUs with asymetric SMT dependancy */ | |
b6220ad6 | 968 | static int powerpc_smt_flags(void) |
607b45e9 | 969 | { |
5d4dfddd | 970 | int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES; |
607b45e9 VG |
971 | |
972 | if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { | |
973 | printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n"); | |
974 | flags |= SD_ASYM_PACKING; | |
975 | } | |
976 | return flags; | |
977 | } | |
978 | #endif | |
979 | ||
980 | static struct sched_domain_topology_level powerpc_topology[] = { | |
981 | #ifdef CONFIG_SCHED_SMT | |
982 | { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, | |
983 | #endif | |
984 | { cpu_cpu_mask, SD_INIT_NAME(DIE) }, | |
985 | { NULL, }, | |
986 | }; | |
987 | ||
6d11b87d | 988 | static __init long smp_setup_cpu_workfn(void *data __always_unused) |
1da177e4 | 989 | { |
6d11b87d TG |
990 | smp_ops->setup_cpu(boot_cpuid); |
991 | return 0; | |
992 | } | |
1da177e4 | 993 | |
6d11b87d TG |
994 | void __init smp_cpus_done(unsigned int max_cpus) |
995 | { | |
996 | /* | |
997 | * We want the setup_cpu() here to be called on the boot CPU, but | |
998 | * init might run on any CPU, so make sure it's invoked on the boot | |
999 | * CPU. | |
1da177e4 | 1000 | */ |
757cbd46 | 1001 | if (smp_ops && smp_ops->setup_cpu) |
6d11b87d | 1002 | work_on_cpu_safe(boot_cpuid, smp_setup_cpu_workfn, NULL); |
4b703a23 | 1003 | |
d7294445 BH |
1004 | if (smp_ops && smp_ops->bringup_done) |
1005 | smp_ops->bringup_done(); | |
1006 | ||
4b703a23 | 1007 | dump_numa_cpu_topology(); |
d7294445 | 1008 | |
607b45e9 | 1009 | set_sched_topology(powerpc_topology); |
e1f0ece1 MN |
1010 | } |
1011 | ||
1da177e4 LT |
1012 | #ifdef CONFIG_HOTPLUG_CPU |
1013 | int __cpu_disable(void) | |
1014 | { | |
e2075f79 NL |
1015 | int cpu = smp_processor_id(); |
1016 | int base, i; | |
1017 | int err; | |
1da177e4 | 1018 | |
e2075f79 NL |
1019 | if (!smp_ops->cpu_disable) |
1020 | return -ENOSYS; | |
1021 | ||
1022 | err = smp_ops->cpu_disable(); | |
1023 | if (err) | |
1024 | return err; | |
1025 | ||
1026 | /* Update sibling maps */ | |
99d86705 | 1027 | base = cpu_first_thread_sibling(cpu); |
19ab58d1 | 1028 | for (i = 0; i < threads_per_core && base + i < nr_cpu_ids; i++) { |
cc1ba8ea AB |
1029 | cpumask_clear_cpu(cpu, cpu_sibling_mask(base + i)); |
1030 | cpumask_clear_cpu(base + i, cpu_sibling_mask(cpu)); | |
1031 | cpumask_clear_cpu(cpu, cpu_core_mask(base + i)); | |
1032 | cpumask_clear_cpu(base + i, cpu_core_mask(cpu)); | |
440a0857 | 1033 | } |
a8a5356c | 1034 | traverse_core_siblings(cpu, false); |
e2075f79 NL |
1035 | |
1036 | return 0; | |
1da177e4 LT |
1037 | } |
1038 | ||
1039 | void __cpu_die(unsigned int cpu) | |
1040 | { | |
1041 | if (smp_ops->cpu_die) | |
1042 | smp_ops->cpu_die(cpu); | |
1043 | } | |
d0174c72 | 1044 | |
abb17f9c MM |
1045 | void cpu_die(void) |
1046 | { | |
1047 | if (ppc_md.cpu_die) | |
1048 | ppc_md.cpu_die(); | |
fa3f82c8 BH |
1049 | |
1050 | /* If we return, we re-enter start_secondary */ | |
1051 | start_secondary_resume(); | |
abb17f9c | 1052 | } |
fa3f82c8 | 1053 | |
1da177e4 | 1054 | #endif |