Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * SMP support for ppc. | |
3 | * | |
4 | * Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great | |
5 | * deal of code from the sparc and intel versions. | |
6 | * | |
7 | * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> | |
8 | * | |
9 | * PowerPC-64 Support added by Dave Engebretsen, Peter Bergner, and | |
10 | * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License | |
14 | * as published by the Free Software Foundation; either version | |
15 | * 2 of the License, or (at your option) any later version. | |
16 | */ | |
17 | ||
18 | #undef DEBUG | |
19 | ||
1da177e4 | 20 | #include <linux/kernel.h> |
4b16f8e2 | 21 | #include <linux/export.h> |
68e21be2 | 22 | #include <linux/sched/mm.h> |
105ab3d8 | 23 | #include <linux/sched/topology.h> |
1da177e4 LT |
24 | #include <linux/smp.h> |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/spinlock.h> | |
29 | #include <linux/cache.h> | |
30 | #include <linux/err.h> | |
8a25a2fd | 31 | #include <linux/device.h> |
1da177e4 LT |
32 | #include <linux/cpu.h> |
33 | #include <linux/notifier.h> | |
4b703a23 | 34 | #include <linux/topology.h> |
665e87ff | 35 | #include <linux/profile.h> |
4e287e65 | 36 | #include <linux/processor.h> |
1da177e4 LT |
37 | |
38 | #include <asm/ptrace.h> | |
60063497 | 39 | #include <linux/atomic.h> |
1da177e4 | 40 | #include <asm/irq.h> |
1b67bee1 | 41 | #include <asm/hw_irq.h> |
441c19c8 | 42 | #include <asm/kvm_ppc.h> |
b866cc21 | 43 | #include <asm/dbell.h> |
1da177e4 LT |
44 | #include <asm/page.h> |
45 | #include <asm/pgtable.h> | |
46 | #include <asm/prom.h> | |
47 | #include <asm/smp.h> | |
1da177e4 LT |
48 | #include <asm/time.h> |
49 | #include <asm/machdep.h> | |
e2075f79 | 50 | #include <asm/cputhreads.h> |
1da177e4 | 51 | #include <asm/cputable.h> |
bbeb3f4c | 52 | #include <asm/mpic.h> |
a7f290da | 53 | #include <asm/vdso_datapage.h> |
5ad57078 PM |
54 | #ifdef CONFIG_PPC64 |
55 | #include <asm/paca.h> | |
56 | #endif | |
18ad51dd | 57 | #include <asm/vdso.h> |
ae3a197e | 58 | #include <asm/debug.h> |
1217d34b | 59 | #include <asm/kexec.h> |
42f5b4ca | 60 | #include <asm/asm-prototypes.h> |
b92a226e | 61 | #include <asm/cpu_has_feature.h> |
d1039786 | 62 | #include <asm/ftrace.h> |
5ad57078 | 63 | |
1da177e4 | 64 | #ifdef DEBUG |
f9e4ec57 | 65 | #include <asm/udbg.h> |
1da177e4 LT |
66 | #define DBG(fmt...) udbg_printf(fmt) |
67 | #else | |
68 | #define DBG(fmt...) | |
69 | #endif | |
70 | ||
c56e5853 | 71 | #ifdef CONFIG_HOTPLUG_CPU |
fb82b839 BH |
72 | /* State of each CPU during hotplug phases */ |
73 | static DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
c56e5853 BH |
74 | #endif |
75 | ||
f9e4ec57 ME |
76 | struct thread_info *secondary_ti; |
77 | ||
cc1ba8ea | 78 | DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
2a636a56 | 79 | DEFINE_PER_CPU(cpumask_var_t, cpu_l2_cache_map); |
cc1ba8ea | 80 | DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); |
1da177e4 | 81 | |
d5a7430d | 82 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
2a636a56 | 83 | EXPORT_PER_CPU_SYMBOL(cpu_l2_cache_map); |
440a0857 | 84 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
1da177e4 | 85 | |
5ad57078 | 86 | /* SMP operations for this machine */ |
1da177e4 LT |
87 | struct smp_ops_t *smp_ops; |
88 | ||
7ccbe504 BH |
89 | /* Can't be static due to PowerMac hackery */ |
90 | volatile unsigned int cpu_callin_map[NR_CPUS]; | |
1da177e4 | 91 | |
1da177e4 LT |
92 | int smt_enabled_at_boot = 1; |
93 | ||
3cd85250 AF |
94 | /* |
95 | * Returns 1 if the specified cpu should be brought up during boot. | |
96 | * Used to inhibit booting threads if they've been disabled or | |
97 | * limited on the command line | |
98 | */ | |
99 | int smp_generic_cpu_bootable(unsigned int nr) | |
100 | { | |
101 | /* Special case - we inhibit secondary thread startup | |
102 | * during boot if the user requests it. | |
103 | */ | |
a8fcfc19 | 104 | if (system_state < SYSTEM_RUNNING && cpu_has_feature(CPU_FTR_SMT)) { |
3cd85250 AF |
105 | if (!smt_enabled_at_boot && cpu_thread_in_core(nr) != 0) |
106 | return 0; | |
107 | if (smt_enabled_at_boot | |
108 | && cpu_thread_in_core(nr) >= smt_enabled_at_boot) | |
109 | return 0; | |
110 | } | |
111 | ||
112 | return 1; | |
113 | } | |
114 | ||
115 | ||
5ad57078 | 116 | #ifdef CONFIG_PPC64 |
cad5cef6 | 117 | int smp_generic_kick_cpu(int nr) |
1da177e4 | 118 | { |
c642af9c | 119 | if (nr < 0 || nr >= nr_cpu_ids) |
f8d0d5dc | 120 | return -EINVAL; |
1da177e4 LT |
121 | |
122 | /* | |
123 | * The processor is currently spinning, waiting for the | |
124 | * cpu_start field to become non-zero After we set cpu_start, | |
125 | * the processor will continue on to secondary_start | |
126 | */ | |
d2e60075 NP |
127 | if (!paca_ptrs[nr]->cpu_start) { |
128 | paca_ptrs[nr]->cpu_start = 1; | |
fb82b839 BH |
129 | smp_mb(); |
130 | return 0; | |
131 | } | |
132 | ||
133 | #ifdef CONFIG_HOTPLUG_CPU | |
134 | /* | |
135 | * Ok it's not there, so it might be soft-unplugged, let's | |
136 | * try to bring it back | |
137 | */ | |
ae5cab47 | 138 | generic_set_cpu_up(nr); |
fb82b839 BH |
139 | smp_wmb(); |
140 | smp_send_reschedule(nr); | |
141 | #endif /* CONFIG_HOTPLUG_CPU */ | |
de300974 ME |
142 | |
143 | return 0; | |
1da177e4 | 144 | } |
fb82b839 | 145 | #endif /* CONFIG_PPC64 */ |
1da177e4 | 146 | |
25ddd738 MM |
147 | static irqreturn_t call_function_action(int irq, void *data) |
148 | { | |
149 | generic_smp_call_function_interrupt(); | |
150 | return IRQ_HANDLED; | |
151 | } | |
152 | ||
153 | static irqreturn_t reschedule_action(int irq, void *data) | |
154 | { | |
184748cc | 155 | scheduler_ipi(); |
25ddd738 MM |
156 | return IRQ_HANDLED; |
157 | } | |
158 | ||
bc907113 | 159 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
1b67bee1 | 160 | static irqreturn_t tick_broadcast_ipi_action(int irq, void *data) |
25ddd738 | 161 | { |
3f984620 | 162 | timer_broadcast_interrupt(); |
25ddd738 MM |
163 | return IRQ_HANDLED; |
164 | } | |
bc907113 | 165 | #endif |
25ddd738 | 166 | |
ddd703ca NP |
167 | #ifdef CONFIG_NMI_IPI |
168 | static irqreturn_t nmi_ipi_action(int irq, void *data) | |
25ddd738 | 169 | { |
ddd703ca | 170 | smp_handle_nmi_ipi(get_irq_regs()); |
25ddd738 MM |
171 | return IRQ_HANDLED; |
172 | } | |
ddd703ca | 173 | #endif |
25ddd738 MM |
174 | |
175 | static irq_handler_t smp_ipi_action[] = { | |
176 | [PPC_MSG_CALL_FUNCTION] = call_function_action, | |
177 | [PPC_MSG_RESCHEDULE] = reschedule_action, | |
bc907113 | 178 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
1b67bee1 | 179 | [PPC_MSG_TICK_BROADCAST] = tick_broadcast_ipi_action, |
bc907113 | 180 | #endif |
ddd703ca NP |
181 | #ifdef CONFIG_NMI_IPI |
182 | [PPC_MSG_NMI_IPI] = nmi_ipi_action, | |
183 | #endif | |
25ddd738 MM |
184 | }; |
185 | ||
ddd703ca NP |
186 | /* |
187 | * The NMI IPI is a fallback and not truly non-maskable. It is simpler | |
188 | * than going through the call function infrastructure, and strongly | |
189 | * serialized, so it is more appropriate for debugging. | |
190 | */ | |
25ddd738 MM |
191 | const char *smp_ipi_name[] = { |
192 | [PPC_MSG_CALL_FUNCTION] = "ipi call function", | |
193 | [PPC_MSG_RESCHEDULE] = "ipi reschedule", | |
bc907113 | 194 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
1b67bee1 | 195 | [PPC_MSG_TICK_BROADCAST] = "ipi tick-broadcast", |
bc907113 | 196 | #endif |
21bfd6a8 | 197 | #ifdef CONFIG_NMI_IPI |
ddd703ca | 198 | [PPC_MSG_NMI_IPI] = "nmi ipi", |
21bfd6a8 | 199 | #endif |
25ddd738 MM |
200 | }; |
201 | ||
202 | /* optional function to request ipi, for controllers with >= 4 ipis */ | |
203 | int smp_request_message_ipi(int virq, int msg) | |
204 | { | |
205 | int err; | |
206 | ||
ddd703ca | 207 | if (msg < 0 || msg > PPC_MSG_NMI_IPI) |
25ddd738 | 208 | return -EINVAL; |
ddd703ca NP |
209 | #ifndef CONFIG_NMI_IPI |
210 | if (msg == PPC_MSG_NMI_IPI) | |
25ddd738 | 211 | return 1; |
25ddd738 | 212 | #endif |
ddd703ca | 213 | |
3b5e16d7 | 214 | err = request_irq(virq, smp_ipi_action[msg], |
e6651de9 | 215 | IRQF_PERCPU | IRQF_NO_THREAD | IRQF_NO_SUSPEND, |
b0d436c7 | 216 | smp_ipi_name[msg], NULL); |
25ddd738 MM |
217 | WARN(err < 0, "unable to request_irq %d for %s (rc %d)\n", |
218 | virq, smp_ipi_name[msg], err); | |
219 | ||
220 | return err; | |
221 | } | |
222 | ||
1ece355b | 223 | #ifdef CONFIG_PPC_SMP_MUXED_IPI |
23d72bfd | 224 | struct cpu_messages { |
bd7f561f | 225 | long messages; /* current messages */ |
23d72bfd MM |
226 | }; |
227 | static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_messages, ipi_message); | |
228 | ||
31639c77 | 229 | void smp_muxed_ipi_set_message(int cpu, int msg) |
23d72bfd MM |
230 | { |
231 | struct cpu_messages *info = &per_cpu(ipi_message, cpu); | |
71454272 | 232 | char *message = (char *)&info->messages; |
23d72bfd | 233 | |
9fb1b36c PM |
234 | /* |
235 | * Order previous accesses before accesses in the IPI handler. | |
236 | */ | |
237 | smp_mb(); | |
71454272 | 238 | message[msg] = 1; |
31639c77 SW |
239 | } |
240 | ||
241 | void smp_muxed_ipi_message_pass(int cpu, int msg) | |
242 | { | |
31639c77 | 243 | smp_muxed_ipi_set_message(cpu, msg); |
b866cc21 | 244 | |
9fb1b36c PM |
245 | /* |
246 | * cause_ipi functions are required to include a full barrier | |
247 | * before doing whatever causes the IPI. | |
248 | */ | |
b866cc21 | 249 | smp_ops->cause_ipi(cpu); |
23d72bfd MM |
250 | } |
251 | ||
0654de1c | 252 | #ifdef __BIG_ENDIAN__ |
bd7f561f | 253 | #define IPI_MESSAGE(A) (1uL << ((BITS_PER_LONG - 8) - 8 * (A))) |
0654de1c | 254 | #else |
bd7f561f | 255 | #define IPI_MESSAGE(A) (1uL << (8 * (A))) |
0654de1c AB |
256 | #endif |
257 | ||
23d72bfd MM |
258 | irqreturn_t smp_ipi_demux(void) |
259 | { | |
23d72bfd | 260 | mb(); /* order any irq clear */ |
71454272 | 261 | |
b87ac021 NP |
262 | return smp_ipi_demux_relaxed(); |
263 | } | |
264 | ||
265 | /* sync-free variant. Callers should ensure synchronization */ | |
266 | irqreturn_t smp_ipi_demux_relaxed(void) | |
23d72bfd | 267 | { |
b866cc21 | 268 | struct cpu_messages *info; |
bd7f561f | 269 | unsigned long all; |
23d72bfd | 270 | |
b866cc21 | 271 | info = this_cpu_ptr(&ipi_message); |
71454272 | 272 | do { |
9fb1b36c | 273 | all = xchg(&info->messages, 0); |
e17769eb SW |
274 | #if defined(CONFIG_KVM_XICS) && defined(CONFIG_KVM_BOOK3S_HV_POSSIBLE) |
275 | /* | |
276 | * Must check for PPC_MSG_RM_HOST_ACTION messages | |
277 | * before PPC_MSG_CALL_FUNCTION messages because when | |
278 | * a VM is destroyed, we call kick_all_cpus_sync() | |
279 | * to ensure that any pending PPC_MSG_RM_HOST_ACTION | |
280 | * messages have completed before we free any VCPUs. | |
281 | */ | |
282 | if (all & IPI_MESSAGE(PPC_MSG_RM_HOST_ACTION)) | |
283 | kvmppc_xics_ipi_action(); | |
284 | #endif | |
0654de1c | 285 | if (all & IPI_MESSAGE(PPC_MSG_CALL_FUNCTION)) |
23d72bfd | 286 | generic_smp_call_function_interrupt(); |
0654de1c | 287 | if (all & IPI_MESSAGE(PPC_MSG_RESCHEDULE)) |
880102e7 | 288 | scheduler_ipi(); |
bc907113 | 289 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
1b67bee1 | 290 | if (all & IPI_MESSAGE(PPC_MSG_TICK_BROADCAST)) |
3f984620 | 291 | timer_broadcast_interrupt(); |
bc907113 | 292 | #endif |
ddd703ca NP |
293 | #ifdef CONFIG_NMI_IPI |
294 | if (all & IPI_MESSAGE(PPC_MSG_NMI_IPI)) | |
295 | nmi_ipi_action(0, NULL); | |
296 | #endif | |
71454272 MM |
297 | } while (info->messages); |
298 | ||
23d72bfd MM |
299 | return IRQ_HANDLED; |
300 | } | |
1ece355b | 301 | #endif /* CONFIG_PPC_SMP_MUXED_IPI */ |
23d72bfd | 302 | |
9ca980dc PM |
303 | static inline void do_message_pass(int cpu, int msg) |
304 | { | |
305 | if (smp_ops->message_pass) | |
306 | smp_ops->message_pass(cpu, msg); | |
307 | #ifdef CONFIG_PPC_SMP_MUXED_IPI | |
308 | else | |
309 | smp_muxed_ipi_message_pass(cpu, msg); | |
310 | #endif | |
311 | } | |
312 | ||
1da177e4 LT |
313 | void smp_send_reschedule(int cpu) |
314 | { | |
8cffc6ac | 315 | if (likely(smp_ops)) |
9ca980dc | 316 | do_message_pass(cpu, PPC_MSG_RESCHEDULE); |
1da177e4 | 317 | } |
de56a948 | 318 | EXPORT_SYMBOL_GPL(smp_send_reschedule); |
1da177e4 | 319 | |
b7d7a240 JA |
320 | void arch_send_call_function_single_ipi(int cpu) |
321 | { | |
402d9a1e | 322 | do_message_pass(cpu, PPC_MSG_CALL_FUNCTION); |
b7d7a240 JA |
323 | } |
324 | ||
f063ea02 | 325 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
b7d7a240 JA |
326 | { |
327 | unsigned int cpu; | |
328 | ||
f063ea02 | 329 | for_each_cpu(cpu, mask) |
9ca980dc | 330 | do_message_pass(cpu, PPC_MSG_CALL_FUNCTION); |
b7d7a240 JA |
331 | } |
332 | ||
ddd703ca NP |
333 | #ifdef CONFIG_NMI_IPI |
334 | ||
335 | /* | |
336 | * "NMI IPI" system. | |
337 | * | |
338 | * NMI IPIs may not be recoverable, so should not be used as ongoing part of | |
339 | * a running system. They can be used for crash, debug, halt/reboot, etc. | |
340 | * | |
341 | * NMI IPIs are globally single threaded. No more than one in progress at | |
342 | * any time. | |
343 | * | |
344 | * The IPI call waits with interrupts disabled until all targets enter the | |
345 | * NMI handler, then the call returns. | |
346 | * | |
347 | * No new NMI can be initiated until targets exit the handler. | |
348 | * | |
349 | * The IPI call may time out without all targets entering the NMI handler. | |
350 | * In that case, there is some logic to recover (and ignore subsequent | |
351 | * NMI interrupts that may eventually be raised), but the platform interrupt | |
352 | * handler may not be able to distinguish this from other exception causes, | |
353 | * which may cause a crash. | |
354 | */ | |
355 | ||
356 | static atomic_t __nmi_ipi_lock = ATOMIC_INIT(0); | |
357 | static struct cpumask nmi_ipi_pending_mask; | |
358 | static int nmi_ipi_busy_count = 0; | |
359 | static void (*nmi_ipi_function)(struct pt_regs *) = NULL; | |
360 | ||
361 | static void nmi_ipi_lock_start(unsigned long *flags) | |
362 | { | |
363 | raw_local_irq_save(*flags); | |
364 | hard_irq_disable(); | |
365 | while (atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1) { | |
366 | raw_local_irq_restore(*flags); | |
0459ddfd | 367 | spin_until_cond(atomic_read(&__nmi_ipi_lock) == 0); |
ddd703ca NP |
368 | raw_local_irq_save(*flags); |
369 | hard_irq_disable(); | |
370 | } | |
371 | } | |
372 | ||
373 | static void nmi_ipi_lock(void) | |
374 | { | |
375 | while (atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1) | |
0459ddfd | 376 | spin_until_cond(atomic_read(&__nmi_ipi_lock) == 0); |
ddd703ca NP |
377 | } |
378 | ||
379 | static void nmi_ipi_unlock(void) | |
380 | { | |
381 | smp_mb(); | |
382 | WARN_ON(atomic_read(&__nmi_ipi_lock) != 1); | |
383 | atomic_set(&__nmi_ipi_lock, 0); | |
384 | } | |
385 | ||
386 | static void nmi_ipi_unlock_end(unsigned long *flags) | |
387 | { | |
388 | nmi_ipi_unlock(); | |
389 | raw_local_irq_restore(*flags); | |
390 | } | |
391 | ||
392 | /* | |
393 | * Platform NMI handler calls this to ack | |
394 | */ | |
395 | int smp_handle_nmi_ipi(struct pt_regs *regs) | |
396 | { | |
397 | void (*fn)(struct pt_regs *); | |
398 | unsigned long flags; | |
399 | int me = raw_smp_processor_id(); | |
400 | int ret = 0; | |
401 | ||
402 | /* | |
403 | * Unexpected NMIs are possible here because the interrupt may not | |
404 | * be able to distinguish NMI IPIs from other types of NMIs, or | |
405 | * because the caller may have timed out. | |
406 | */ | |
407 | nmi_ipi_lock_start(&flags); | |
408 | if (!nmi_ipi_busy_count) | |
409 | goto out; | |
410 | if (!cpumask_test_cpu(me, &nmi_ipi_pending_mask)) | |
411 | goto out; | |
412 | ||
413 | fn = nmi_ipi_function; | |
414 | if (!fn) | |
415 | goto out; | |
416 | ||
417 | cpumask_clear_cpu(me, &nmi_ipi_pending_mask); | |
418 | nmi_ipi_busy_count++; | |
419 | nmi_ipi_unlock(); | |
420 | ||
421 | ret = 1; | |
422 | ||
423 | fn(regs); | |
424 | ||
425 | nmi_ipi_lock(); | |
426 | nmi_ipi_busy_count--; | |
427 | out: | |
428 | nmi_ipi_unlock_end(&flags); | |
429 | ||
430 | return ret; | |
431 | } | |
432 | ||
6ba55716 | 433 | static void do_smp_send_nmi_ipi(int cpu, bool safe) |
ddd703ca | 434 | { |
6ba55716 | 435 | if (!safe && smp_ops->cause_nmi_ipi && smp_ops->cause_nmi_ipi(cpu)) |
c64af645 NP |
436 | return; |
437 | ||
ddd703ca NP |
438 | if (cpu >= 0) { |
439 | do_message_pass(cpu, PPC_MSG_NMI_IPI); | |
440 | } else { | |
441 | int c; | |
442 | ||
443 | for_each_online_cpu(c) { | |
444 | if (c == raw_smp_processor_id()) | |
445 | continue; | |
446 | do_message_pass(c, PPC_MSG_NMI_IPI); | |
447 | } | |
448 | } | |
449 | } | |
450 | ||
2104180a NP |
451 | void smp_flush_nmi_ipi(u64 delay_us) |
452 | { | |
453 | unsigned long flags; | |
454 | ||
455 | nmi_ipi_lock_start(&flags); | |
456 | while (nmi_ipi_busy_count) { | |
457 | nmi_ipi_unlock_end(&flags); | |
458 | udelay(1); | |
459 | if (delay_us) { | |
460 | delay_us--; | |
461 | if (!delay_us) | |
462 | return; | |
463 | } | |
464 | nmi_ipi_lock_start(&flags); | |
465 | } | |
466 | nmi_ipi_unlock_end(&flags); | |
467 | } | |
468 | ||
ddd703ca NP |
469 | /* |
470 | * - cpu is the target CPU (must not be this CPU), or NMI_IPI_ALL_OTHERS. | |
471 | * - fn is the target callback function. | |
472 | * - delay_us > 0 is the delay before giving up waiting for targets to | |
473 | * enter the handler, == 0 specifies indefinite delay. | |
474 | */ | |
6ba55716 | 475 | int __smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us, bool safe) |
ddd703ca NP |
476 | { |
477 | unsigned long flags; | |
478 | int me = raw_smp_processor_id(); | |
479 | int ret = 1; | |
480 | ||
481 | BUG_ON(cpu == me); | |
482 | BUG_ON(cpu < 0 && cpu != NMI_IPI_ALL_OTHERS); | |
483 | ||
484 | if (unlikely(!smp_ops)) | |
485 | return 0; | |
486 | ||
487 | /* Take the nmi_ipi_busy count/lock with interrupts hard disabled */ | |
488 | nmi_ipi_lock_start(&flags); | |
489 | while (nmi_ipi_busy_count) { | |
490 | nmi_ipi_unlock_end(&flags); | |
0459ddfd | 491 | spin_until_cond(nmi_ipi_busy_count == 0); |
ddd703ca NP |
492 | nmi_ipi_lock_start(&flags); |
493 | } | |
494 | ||
495 | nmi_ipi_function = fn; | |
496 | ||
497 | if (cpu < 0) { | |
498 | /* ALL_OTHERS */ | |
499 | cpumask_copy(&nmi_ipi_pending_mask, cpu_online_mask); | |
500 | cpumask_clear_cpu(me, &nmi_ipi_pending_mask); | |
501 | } else { | |
502 | /* cpumask starts clear */ | |
503 | cpumask_set_cpu(cpu, &nmi_ipi_pending_mask); | |
504 | } | |
505 | nmi_ipi_busy_count++; | |
506 | nmi_ipi_unlock(); | |
507 | ||
6ba55716 | 508 | do_smp_send_nmi_ipi(cpu, safe); |
ddd703ca NP |
509 | |
510 | while (!cpumask_empty(&nmi_ipi_pending_mask)) { | |
511 | udelay(1); | |
512 | if (delay_us) { | |
513 | delay_us--; | |
514 | if (!delay_us) | |
515 | break; | |
516 | } | |
517 | } | |
518 | ||
519 | nmi_ipi_lock(); | |
520 | if (!cpumask_empty(&nmi_ipi_pending_mask)) { | |
521 | /* Could not gather all CPUs */ | |
522 | ret = 0; | |
523 | cpumask_clear(&nmi_ipi_pending_mask); | |
524 | } | |
525 | nmi_ipi_busy_count--; | |
526 | nmi_ipi_unlock_end(&flags); | |
527 | ||
528 | return ret; | |
529 | } | |
6ba55716 ME |
530 | |
531 | int smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us) | |
532 | { | |
533 | return __smp_send_nmi_ipi(cpu, fn, delay_us, false); | |
534 | } | |
535 | ||
536 | int smp_send_safe_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us) | |
537 | { | |
538 | return __smp_send_nmi_ipi(cpu, fn, delay_us, true); | |
539 | } | |
ddd703ca NP |
540 | #endif /* CONFIG_NMI_IPI */ |
541 | ||
1b67bee1 SB |
542 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
543 | void tick_broadcast(const struct cpumask *mask) | |
544 | { | |
545 | unsigned int cpu; | |
546 | ||
547 | for_each_cpu(cpu, mask) | |
548 | do_message_pass(cpu, PPC_MSG_TICK_BROADCAST); | |
549 | } | |
550 | #endif | |
551 | ||
ddd703ca NP |
552 | #ifdef CONFIG_DEBUGGER |
553 | void debugger_ipi_callback(struct pt_regs *regs) | |
1da177e4 | 554 | { |
ddd703ca NP |
555 | debugger_ipi(regs); |
556 | } | |
e0476371 | 557 | |
ddd703ca NP |
558 | void smp_send_debugger_break(void) |
559 | { | |
560 | smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, debugger_ipi_callback, 1000000); | |
1da177e4 LT |
561 | } |
562 | #endif | |
563 | ||
da665885 | 564 | #ifdef CONFIG_KEXEC_CORE |
cc532915 ME |
565 | void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *)) |
566 | { | |
4145f358 BS |
567 | int cpu; |
568 | ||
ddd703ca | 569 | smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, crash_ipi_callback, 1000000); |
4145f358 BS |
570 | if (kdump_in_progress() && crash_wake_offline) { |
571 | for_each_present_cpu(cpu) { | |
572 | if (cpu_online(cpu)) | |
573 | continue; | |
574 | /* | |
575 | * crash_ipi_callback will wait for | |
576 | * all cpus, including offline CPUs. | |
577 | * We don't care about nmi_ipi_function. | |
578 | * Offline cpus will jump straight into | |
579 | * crash_ipi_callback, we can skip the | |
580 | * entire NMI dance and waiting for | |
581 | * cpus to clear pending mask, etc. | |
582 | */ | |
6ba55716 | 583 | do_smp_send_nmi_ipi(cpu, false); |
4145f358 BS |
584 | } |
585 | } | |
cc532915 ME |
586 | } |
587 | #endif | |
588 | ||
ac61c115 NP |
589 | #ifdef CONFIG_NMI_IPI |
590 | static void nmi_stop_this_cpu(struct pt_regs *regs) | |
591 | { | |
592 | /* | |
593 | * This is a special case because it never returns, so the NMI IPI | |
594 | * handling would never mark it as done, which makes any later | |
595 | * smp_send_nmi_ipi() call spin forever. Mark it done now. | |
6029755e NP |
596 | * |
597 | * IRQs are already hard disabled by the smp_handle_nmi_ipi. | |
ac61c115 NP |
598 | */ |
599 | nmi_ipi_lock(); | |
600 | nmi_ipi_busy_count--; | |
601 | nmi_ipi_unlock(); | |
602 | ||
6029755e NP |
603 | spin_begin(); |
604 | while (1) | |
605 | spin_cpu_relax(); | |
ac61c115 | 606 | } |
ac61c115 | 607 | |
8fd7675c SS |
608 | void smp_send_stop(void) |
609 | { | |
ac61c115 | 610 | smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, nmi_stop_this_cpu, 1000000); |
6029755e NP |
611 | } |
612 | ||
613 | #else /* CONFIG_NMI_IPI */ | |
614 | ||
615 | static void stop_this_cpu(void *dummy) | |
616 | { | |
6029755e NP |
617 | hard_irq_disable(); |
618 | spin_begin(); | |
619 | while (1) | |
620 | spin_cpu_relax(); | |
621 | } | |
622 | ||
623 | void smp_send_stop(void) | |
624 | { | |
625 | static bool stopped = false; | |
626 | ||
627 | /* | |
628 | * Prevent waiting on csd lock from a previous smp_send_stop. | |
629 | * This is racy, but in general callers try to do the right | |
630 | * thing and only fire off one smp_send_stop (e.g., see | |
631 | * kernel/panic.c) | |
632 | */ | |
633 | if (stopped) | |
634 | return; | |
635 | ||
636 | stopped = true; | |
637 | ||
8691e5a8 | 638 | smp_call_function(stop_this_cpu, NULL, 0); |
1da177e4 | 639 | } |
6029755e | 640 | #endif /* CONFIG_NMI_IPI */ |
1da177e4 | 641 | |
1da177e4 LT |
642 | struct thread_info *current_set[NR_CPUS]; |
643 | ||
cad5cef6 | 644 | static void smp_store_cpu_info(int id) |
1da177e4 | 645 | { |
6b7487fc | 646 | per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR); |
3160b097 BB |
647 | #ifdef CONFIG_PPC_FSL_BOOK3E |
648 | per_cpu(next_tlbcam_idx, id) | |
649 | = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1; | |
650 | #endif | |
1da177e4 LT |
651 | } |
652 | ||
df52f671 OH |
653 | /* |
654 | * Relationships between CPUs are maintained in a set of per-cpu cpumasks so | |
655 | * rather than just passing around the cpumask we pass around a function that | |
656 | * returns the that cpumask for the given CPU. | |
657 | */ | |
658 | static void set_cpus_related(int i, int j, struct cpumask *(*get_cpumask)(int)) | |
659 | { | |
660 | cpumask_set_cpu(i, get_cpumask(j)); | |
661 | cpumask_set_cpu(j, get_cpumask(i)); | |
662 | } | |
663 | ||
664 | #ifdef CONFIG_HOTPLUG_CPU | |
665 | static void set_cpus_unrelated(int i, int j, | |
666 | struct cpumask *(*get_cpumask)(int)) | |
667 | { | |
668 | cpumask_clear_cpu(i, get_cpumask(j)); | |
669 | cpumask_clear_cpu(j, get_cpumask(i)); | |
670 | } | |
671 | #endif | |
672 | ||
1da177e4 LT |
673 | void __init smp_prepare_cpus(unsigned int max_cpus) |
674 | { | |
675 | unsigned int cpu; | |
676 | ||
677 | DBG("smp_prepare_cpus\n"); | |
678 | ||
679 | /* | |
680 | * setup_cpu may need to be called on the boot cpu. We havent | |
681 | * spun any cpus up but lets be paranoid. | |
682 | */ | |
683 | BUG_ON(boot_cpuid != smp_processor_id()); | |
684 | ||
685 | /* Fixup boot cpu */ | |
686 | smp_store_cpu_info(boot_cpuid); | |
687 | cpu_callin_map[boot_cpuid] = 1; | |
688 | ||
cc1ba8ea AB |
689 | for_each_possible_cpu(cpu) { |
690 | zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu), | |
691 | GFP_KERNEL, cpu_to_node(cpu)); | |
2a636a56 OH |
692 | zalloc_cpumask_var_node(&per_cpu(cpu_l2_cache_map, cpu), |
693 | GFP_KERNEL, cpu_to_node(cpu)); | |
cc1ba8ea AB |
694 | zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu), |
695 | GFP_KERNEL, cpu_to_node(cpu)); | |
2fabf084 NA |
696 | /* |
697 | * numa_node_id() works after this. | |
698 | */ | |
bc3c4327 LZ |
699 | if (cpu_present(cpu)) { |
700 | set_cpu_numa_node(cpu, numa_cpu_lookup_table[cpu]); | |
701 | set_cpu_numa_mem(cpu, | |
702 | local_memory_node(numa_cpu_lookup_table[cpu])); | |
703 | } | |
cc1ba8ea AB |
704 | } |
705 | ||
df52f671 | 706 | /* Init the cpumasks so the boot CPU is related to itself */ |
cc1ba8ea | 707 | cpumask_set_cpu(boot_cpuid, cpu_sibling_mask(boot_cpuid)); |
2a636a56 | 708 | cpumask_set_cpu(boot_cpuid, cpu_l2_cache_mask(boot_cpuid)); |
cc1ba8ea AB |
709 | cpumask_set_cpu(boot_cpuid, cpu_core_mask(boot_cpuid)); |
710 | ||
dfee0efe CG |
711 | if (smp_ops && smp_ops->probe) |
712 | smp_ops->probe(); | |
1da177e4 LT |
713 | } |
714 | ||
cad5cef6 | 715 | void smp_prepare_boot_cpu(void) |
1da177e4 LT |
716 | { |
717 | BUG_ON(smp_processor_id() != boot_cpuid); | |
5ad57078 | 718 | #ifdef CONFIG_PPC64 |
d2e60075 | 719 | paca_ptrs[boot_cpuid]->__current = current; |
5ad57078 | 720 | #endif |
8c272261 | 721 | set_numa_node(numa_cpu_lookup_table[boot_cpuid]); |
b5e2fc1c | 722 | current_set[boot_cpuid] = task_thread_info(current); |
1da177e4 LT |
723 | } |
724 | ||
725 | #ifdef CONFIG_HOTPLUG_CPU | |
1da177e4 LT |
726 | |
727 | int generic_cpu_disable(void) | |
728 | { | |
729 | unsigned int cpu = smp_processor_id(); | |
730 | ||
731 | if (cpu == boot_cpuid) | |
732 | return -EBUSY; | |
733 | ||
ea0f1cab | 734 | set_cpu_online(cpu, false); |
799d6046 | 735 | #ifdef CONFIG_PPC64 |
a7f290da | 736 | vdso_data->processorCount--; |
094fe2e7 | 737 | #endif |
a978e139 BH |
738 | /* Update affinity of all IRQs previously aimed at this CPU */ |
739 | irq_migrate_all_off_this_cpu(); | |
740 | ||
687b8f24 ME |
741 | /* |
742 | * Depending on the details of the interrupt controller, it's possible | |
743 | * that one of the interrupts we just migrated away from this CPU is | |
744 | * actually already pending on this CPU. If we leave it in that state | |
745 | * the interrupt will never be EOI'ed, and will never fire again. So | |
746 | * temporarily enable interrupts here, to allow any pending interrupt to | |
747 | * be received (and EOI'ed), before we take this CPU offline. | |
748 | */ | |
a978e139 BH |
749 | local_irq_enable(); |
750 | mdelay(1); | |
751 | local_irq_disable(); | |
752 | ||
1da177e4 LT |
753 | return 0; |
754 | } | |
755 | ||
1da177e4 LT |
756 | void generic_cpu_die(unsigned int cpu) |
757 | { | |
758 | int i; | |
759 | ||
760 | for (i = 0; i < 100; i++) { | |
0d8d4d42 | 761 | smp_rmb(); |
2f4f1f81 | 762 | if (is_cpu_dead(cpu)) |
1da177e4 LT |
763 | return; |
764 | msleep(100); | |
765 | } | |
766 | printk(KERN_ERR "CPU%d didn't die...\n", cpu); | |
767 | } | |
768 | ||
105765f4 BH |
769 | void generic_set_cpu_dead(unsigned int cpu) |
770 | { | |
771 | per_cpu(cpu_state, cpu) = CPU_DEAD; | |
772 | } | |
fb82b839 | 773 | |
ae5cab47 ZC |
774 | /* |
775 | * The cpu_state should be set to CPU_UP_PREPARE in kick_cpu(), otherwise | |
776 | * the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(), | |
777 | * which makes the delay in generic_cpu_die() not happen. | |
778 | */ | |
779 | void generic_set_cpu_up(unsigned int cpu) | |
780 | { | |
781 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
782 | } | |
783 | ||
fb82b839 BH |
784 | int generic_check_cpu_restart(unsigned int cpu) |
785 | { | |
786 | return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE; | |
787 | } | |
512691d4 | 788 | |
2f4f1f81 | 789 | int is_cpu_dead(unsigned int cpu) |
790 | { | |
791 | return per_cpu(cpu_state, cpu) == CPU_DEAD; | |
792 | } | |
793 | ||
441c19c8 | 794 | static bool secondaries_inhibited(void) |
512691d4 | 795 | { |
441c19c8 | 796 | return kvm_hv_mode_active(); |
512691d4 PM |
797 | } |
798 | ||
799 | #else /* HOTPLUG_CPU */ | |
800 | ||
801 | #define secondaries_inhibited() 0 | |
802 | ||
1da177e4 LT |
803 | #endif |
804 | ||
17e32eac | 805 | static void cpu_idle_thread_init(unsigned int cpu, struct task_struct *idle) |
c56e5853 | 806 | { |
17e32eac | 807 | struct thread_info *ti = task_thread_info(idle); |
c56e5853 BH |
808 | |
809 | #ifdef CONFIG_PPC64 | |
d2e60075 NP |
810 | paca_ptrs[cpu]->__current = idle; |
811 | paca_ptrs[cpu]->kstack = (unsigned long)ti + THREAD_SIZE - STACK_FRAME_OVERHEAD; | |
c56e5853 BH |
812 | #endif |
813 | ti->cpu = cpu; | |
17e32eac | 814 | secondary_ti = current_set[cpu] = ti; |
c56e5853 BH |
815 | } |
816 | ||
061d19f2 | 817 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 818 | { |
c56e5853 | 819 | int rc, c; |
1da177e4 | 820 | |
512691d4 PM |
821 | /* |
822 | * Don't allow secondary threads to come online if inhibited | |
823 | */ | |
824 | if (threads_per_core > 1 && secondaries_inhibited() && | |
6f5e40a3 | 825 | cpu_thread_in_subcore(cpu)) |
512691d4 PM |
826 | return -EBUSY; |
827 | ||
8cffc6ac BH |
828 | if (smp_ops == NULL || |
829 | (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu))) | |
1da177e4 LT |
830 | return -EINVAL; |
831 | ||
17e32eac | 832 | cpu_idle_thread_init(cpu, tidle); |
c560bbce | 833 | |
14d4ae5c BH |
834 | /* |
835 | * The platform might need to allocate resources prior to bringing | |
836 | * up the CPU | |
837 | */ | |
838 | if (smp_ops->prepare_cpu) { | |
839 | rc = smp_ops->prepare_cpu(cpu); | |
840 | if (rc) | |
841 | return rc; | |
842 | } | |
843 | ||
1da177e4 LT |
844 | /* Make sure callin-map entry is 0 (can be leftover a CPU |
845 | * hotplug | |
846 | */ | |
847 | cpu_callin_map[cpu] = 0; | |
848 | ||
849 | /* The information for processor bringup must | |
850 | * be written out to main store before we release | |
851 | * the processor. | |
852 | */ | |
0d8d4d42 | 853 | smp_mb(); |
1da177e4 LT |
854 | |
855 | /* wake up cpus */ | |
856 | DBG("smp: kicking cpu %d\n", cpu); | |
de300974 ME |
857 | rc = smp_ops->kick_cpu(cpu); |
858 | if (rc) { | |
859 | pr_err("smp: failed starting cpu %d (rc %d)\n", cpu, rc); | |
860 | return rc; | |
861 | } | |
1da177e4 LT |
862 | |
863 | /* | |
864 | * wait to see if the cpu made a callin (is actually up). | |
865 | * use this value that I found through experimentation. | |
866 | * -- Cort | |
867 | */ | |
868 | if (system_state < SYSTEM_RUNNING) | |
ee0339f2 | 869 | for (c = 50000; c && !cpu_callin_map[cpu]; c--) |
1da177e4 LT |
870 | udelay(100); |
871 | #ifdef CONFIG_HOTPLUG_CPU | |
872 | else | |
873 | /* | |
874 | * CPUs can take much longer to come up in the | |
875 | * hotplug case. Wait five seconds. | |
876 | */ | |
67764263 GS |
877 | for (c = 5000; c && !cpu_callin_map[cpu]; c--) |
878 | msleep(1); | |
1da177e4 LT |
879 | #endif |
880 | ||
881 | if (!cpu_callin_map[cpu]) { | |
6685a477 | 882 | printk(KERN_ERR "Processor %u is stuck.\n", cpu); |
1da177e4 LT |
883 | return -ENOENT; |
884 | } | |
885 | ||
6685a477 | 886 | DBG("Processor %u found.\n", cpu); |
1da177e4 LT |
887 | |
888 | if (smp_ops->give_timebase) | |
889 | smp_ops->give_timebase(); | |
890 | ||
875ebe94 | 891 | /* Wait until cpu puts itself in the online & active maps */ |
4e287e65 | 892 | spin_until_cond(cpu_online(cpu)); |
1da177e4 LT |
893 | |
894 | return 0; | |
895 | } | |
896 | ||
e9efed3b NL |
897 | /* Return the value of the reg property corresponding to the given |
898 | * logical cpu. | |
899 | */ | |
900 | int cpu_to_core_id(int cpu) | |
901 | { | |
902 | struct device_node *np; | |
f8a1883a | 903 | const __be32 *reg; |
e9efed3b NL |
904 | int id = -1; |
905 | ||
906 | np = of_get_cpu_node(cpu, NULL); | |
907 | if (!np) | |
908 | goto out; | |
909 | ||
910 | reg = of_get_property(np, "reg", NULL); | |
911 | if (!reg) | |
912 | goto out; | |
913 | ||
f8a1883a | 914 | id = be32_to_cpup(reg); |
e9efed3b NL |
915 | out: |
916 | of_node_put(np); | |
917 | return id; | |
918 | } | |
f8ab4810 | 919 | EXPORT_SYMBOL_GPL(cpu_to_core_id); |
e9efed3b | 920 | |
99d86705 VS |
921 | /* Helper routines for cpu to core mapping */ |
922 | int cpu_core_index_of_thread(int cpu) | |
923 | { | |
924 | return cpu >> threads_shift; | |
925 | } | |
926 | EXPORT_SYMBOL_GPL(cpu_core_index_of_thread); | |
927 | ||
928 | int cpu_first_thread_of_core(int core) | |
929 | { | |
930 | return core << threads_shift; | |
931 | } | |
932 | EXPORT_SYMBOL_GPL(cpu_first_thread_of_core); | |
933 | ||
104699c0 | 934 | /* Must be called when no change can occur to cpu_present_mask, |
440a0857 NL |
935 | * i.e. during cpu online or offline. |
936 | */ | |
937 | static struct device_node *cpu_to_l2cache(int cpu) | |
938 | { | |
939 | struct device_node *np; | |
b2ea25b9 | 940 | struct device_node *cache; |
440a0857 NL |
941 | |
942 | if (!cpu_present(cpu)) | |
943 | return NULL; | |
944 | ||
945 | np = of_get_cpu_node(cpu, NULL); | |
946 | if (np == NULL) | |
947 | return NULL; | |
948 | ||
b2ea25b9 NL |
949 | cache = of_find_next_cache_node(np); |
950 | ||
440a0857 NL |
951 | of_node_put(np); |
952 | ||
b2ea25b9 | 953 | return cache; |
440a0857 | 954 | } |
1da177e4 | 955 | |
df52f671 | 956 | static bool update_mask_by_l2(int cpu, struct cpumask *(*mask_fn)(int)) |
a8a5356c | 957 | { |
256f2d4b | 958 | struct device_node *l2_cache, *np; |
e3d8b67e | 959 | int i; |
256f2d4b | 960 | |
a8a5356c | 961 | l2_cache = cpu_to_l2cache(cpu); |
df52f671 OH |
962 | if (!l2_cache) |
963 | return false; | |
964 | ||
965 | for_each_cpu(i, cpu_online_mask) { | |
966 | /* | |
967 | * when updating the marks the current CPU has not been marked | |
968 | * online, but we need to update the cache masks | |
969 | */ | |
256f2d4b | 970 | np = cpu_to_l2cache(i); |
a8a5356c PM |
971 | if (!np) |
972 | continue; | |
df52f671 OH |
973 | |
974 | if (np == l2_cache) | |
975 | set_cpus_related(cpu, i, mask_fn); | |
976 | ||
a8a5356c PM |
977 | of_node_put(np); |
978 | } | |
979 | of_node_put(l2_cache); | |
df52f671 OH |
980 | |
981 | return true; | |
982 | } | |
983 | ||
984 | #ifdef CONFIG_HOTPLUG_CPU | |
985 | static void remove_cpu_from_masks(int cpu) | |
986 | { | |
987 | int i; | |
988 | ||
989 | /* NB: cpu_core_mask is a superset of the others */ | |
990 | for_each_cpu(i, cpu_core_mask(cpu)) { | |
991 | set_cpus_unrelated(cpu, i, cpu_core_mask); | |
2a636a56 | 992 | set_cpus_unrelated(cpu, i, cpu_l2_cache_mask); |
df52f671 OH |
993 | set_cpus_unrelated(cpu, i, cpu_sibling_mask); |
994 | } | |
995 | } | |
996 | #endif | |
997 | ||
998 | static void add_cpu_to_masks(int cpu) | |
999 | { | |
1000 | int first_thread = cpu_first_thread_sibling(cpu); | |
1001 | int chipid = cpu_to_chip_id(cpu); | |
1002 | int i; | |
1003 | ||
1004 | /* | |
1005 | * This CPU will not be in the online mask yet so we need to manually | |
1006 | * add it to it's own thread sibling mask. | |
1007 | */ | |
1008 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); | |
1009 | ||
1010 | for (i = first_thread; i < first_thread + threads_per_core; i++) | |
1011 | if (cpu_online(i)) | |
1012 | set_cpus_related(i, cpu, cpu_sibling_mask); | |
1013 | ||
1014 | /* | |
2a636a56 OH |
1015 | * Copy the thread sibling mask into the cache sibling mask |
1016 | * and mark any CPUs that share an L2 with this CPU. | |
df52f671 OH |
1017 | */ |
1018 | for_each_cpu(i, cpu_sibling_mask(cpu)) | |
2a636a56 OH |
1019 | set_cpus_related(cpu, i, cpu_l2_cache_mask); |
1020 | update_mask_by_l2(cpu, cpu_l2_cache_mask); | |
1021 | ||
1022 | /* | |
1023 | * Copy the cache sibling mask into core sibling mask and mark | |
1024 | * any CPUs on the same chip as this CPU. | |
1025 | */ | |
1026 | for_each_cpu(i, cpu_l2_cache_mask(cpu)) | |
df52f671 OH |
1027 | set_cpus_related(cpu, i, cpu_core_mask); |
1028 | ||
2a636a56 | 1029 | if (chipid == -1) |
df52f671 | 1030 | return; |
df52f671 OH |
1031 | |
1032 | for_each_cpu(i, cpu_online_mask) | |
1033 | if (cpu_to_chip_id(i) == chipid) | |
1034 | set_cpus_related(cpu, i, cpu_core_mask); | |
a8a5356c PM |
1035 | } |
1036 | ||
96d91431 OH |
1037 | static bool shared_caches; |
1038 | ||
1da177e4 | 1039 | /* Activate a secondary processor. */ |
061d19f2 | 1040 | void start_secondary(void *unused) |
1da177e4 LT |
1041 | { |
1042 | unsigned int cpu = smp_processor_id(); | |
1043 | ||
f1f10076 | 1044 | mmgrab(&init_mm); |
1da177e4 LT |
1045 | current->active_mm = &init_mm; |
1046 | ||
1047 | smp_store_cpu_info(cpu); | |
5ad57078 | 1048 | set_dec(tb_ticks_per_jiffy); |
e4d76e1c | 1049 | preempt_disable(); |
1be6f10f | 1050 | cpu_callin_map[cpu] = 1; |
1da177e4 | 1051 | |
757cbd46 KG |
1052 | if (smp_ops->setup_cpu) |
1053 | smp_ops->setup_cpu(cpu); | |
1da177e4 LT |
1054 | if (smp_ops->take_timebase) |
1055 | smp_ops->take_timebase(); | |
1056 | ||
d831d0b8 TB |
1057 | secondary_cpu_time_init(); |
1058 | ||
aeeafbfa BH |
1059 | #ifdef CONFIG_PPC64 |
1060 | if (system_state == SYSTEM_RUNNING) | |
1061 | vdso_data->processorCount++; | |
18ad51dd AB |
1062 | |
1063 | vdso_getcpu_init(); | |
aeeafbfa | 1064 | #endif |
df52f671 OH |
1065 | /* Update topology CPU masks */ |
1066 | add_cpu_to_masks(cpu); | |
1da177e4 | 1067 | |
96d91431 OH |
1068 | /* |
1069 | * Check for any shared caches. Note that this must be done on a | |
1070 | * per-core basis because one core in the pair might be disabled. | |
1071 | */ | |
1072 | if (!cpumask_equal(cpu_l2_cache_mask(cpu), cpu_sibling_mask(cpu))) | |
1073 | shared_caches = true; | |
1074 | ||
bc3c4327 LZ |
1075 | set_numa_node(numa_cpu_lookup_table[cpu]); |
1076 | set_numa_mem(local_memory_node(numa_cpu_lookup_table[cpu])); | |
1077 | ||
cce606fe LZ |
1078 | smp_wmb(); |
1079 | notify_cpu_starting(cpu); | |
1080 | set_cpu_online(cpu, true); | |
1081 | ||
1da177e4 LT |
1082 | local_irq_enable(); |
1083 | ||
d1039786 NR |
1084 | /* We can enable ftrace for secondary cpus now */ |
1085 | this_cpu_enable_ftrace(); | |
1086 | ||
fc6d73d6 | 1087 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
fa3f82c8 BH |
1088 | |
1089 | BUG(); | |
1da177e4 LT |
1090 | } |
1091 | ||
1092 | int setup_profiling_timer(unsigned int multiplier) | |
1093 | { | |
1094 | return 0; | |
1095 | } | |
1096 | ||
607b45e9 VG |
1097 | #ifdef CONFIG_SCHED_SMT |
1098 | /* cpumask of CPUs with asymetric SMT dependancy */ | |
b6220ad6 | 1099 | static int powerpc_smt_flags(void) |
607b45e9 | 1100 | { |
5d4dfddd | 1101 | int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES; |
607b45e9 VG |
1102 | |
1103 | if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { | |
1104 | printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n"); | |
1105 | flags |= SD_ASYM_PACKING; | |
1106 | } | |
1107 | return flags; | |
1108 | } | |
1109 | #endif | |
1110 | ||
1111 | static struct sched_domain_topology_level powerpc_topology[] = { | |
1112 | #ifdef CONFIG_SCHED_SMT | |
1113 | { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, | |
1114 | #endif | |
1115 | { cpu_cpu_mask, SD_INIT_NAME(DIE) }, | |
1116 | { NULL, }, | |
1117 | }; | |
1118 | ||
96d91431 OH |
1119 | /* |
1120 | * P9 has a slightly odd architecture where pairs of cores share an L2 cache. | |
1121 | * This topology makes it *much* cheaper to migrate tasks between adjacent cores | |
1122 | * since the migrated task remains cache hot. We want to take advantage of this | |
1123 | * at the scheduler level so an extra topology level is required. | |
1124 | */ | |
1125 | static int powerpc_shared_cache_flags(void) | |
1126 | { | |
1127 | return SD_SHARE_PKG_RESOURCES; | |
1128 | } | |
1129 | ||
1130 | /* | |
1131 | * We can't just pass cpu_l2_cache_mask() directly because | |
1132 | * returns a non-const pointer and the compiler barfs on that. | |
1133 | */ | |
1134 | static const struct cpumask *shared_cache_mask(int cpu) | |
1135 | { | |
1136 | return cpu_l2_cache_mask(cpu); | |
1137 | } | |
1138 | ||
1139 | static struct sched_domain_topology_level power9_topology[] = { | |
1140 | #ifdef CONFIG_SCHED_SMT | |
1141 | { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, | |
1142 | #endif | |
1143 | { shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) }, | |
1144 | { cpu_cpu_mask, SD_INIT_NAME(DIE) }, | |
1145 | { NULL, }, | |
1146 | }; | |
1147 | ||
6d11b87d TG |
1148 | void __init smp_cpus_done(unsigned int max_cpus) |
1149 | { | |
1150 | /* | |
7b7622bb | 1151 | * We are running pinned to the boot CPU, see rest_init(). |
1da177e4 | 1152 | */ |
757cbd46 | 1153 | if (smp_ops && smp_ops->setup_cpu) |
7b7622bb | 1154 | smp_ops->setup_cpu(boot_cpuid); |
4b703a23 | 1155 | |
d7294445 BH |
1156 | if (smp_ops && smp_ops->bringup_done) |
1157 | smp_ops->bringup_done(); | |
1158 | ||
4b703a23 | 1159 | dump_numa_cpu_topology(); |
d7294445 | 1160 | |
96d91431 OH |
1161 | /* |
1162 | * If any CPU detects that it's sharing a cache with another CPU then | |
1163 | * use the deeper topology that is aware of this sharing. | |
1164 | */ | |
1165 | if (shared_caches) { | |
1166 | pr_info("Using shared cache scheduler topology\n"); | |
1167 | set_sched_topology(power9_topology); | |
1168 | } else { | |
1169 | pr_info("Using standard scheduler topology\n"); | |
1170 | set_sched_topology(powerpc_topology); | |
1171 | } | |
e1f0ece1 MN |
1172 | } |
1173 | ||
1da177e4 LT |
1174 | #ifdef CONFIG_HOTPLUG_CPU |
1175 | int __cpu_disable(void) | |
1176 | { | |
e2075f79 | 1177 | int cpu = smp_processor_id(); |
e2075f79 | 1178 | int err; |
1da177e4 | 1179 | |
e2075f79 NL |
1180 | if (!smp_ops->cpu_disable) |
1181 | return -ENOSYS; | |
1182 | ||
424ef016 NR |
1183 | this_cpu_disable_ftrace(); |
1184 | ||
e2075f79 NL |
1185 | err = smp_ops->cpu_disable(); |
1186 | if (err) | |
1187 | return err; | |
1188 | ||
1189 | /* Update sibling maps */ | |
df52f671 | 1190 | remove_cpu_from_masks(cpu); |
e2075f79 NL |
1191 | |
1192 | return 0; | |
1da177e4 LT |
1193 | } |
1194 | ||
1195 | void __cpu_die(unsigned int cpu) | |
1196 | { | |
1197 | if (smp_ops->cpu_die) | |
1198 | smp_ops->cpu_die(cpu); | |
1199 | } | |
d0174c72 | 1200 | |
abb17f9c MM |
1201 | void cpu_die(void) |
1202 | { | |
424ef016 NR |
1203 | /* |
1204 | * Disable on the down path. This will be re-enabled by | |
1205 | * start_secondary() via start_secondary_resume() below | |
1206 | */ | |
1207 | this_cpu_disable_ftrace(); | |
1208 | ||
abb17f9c MM |
1209 | if (ppc_md.cpu_die) |
1210 | ppc_md.cpu_die(); | |
fa3f82c8 BH |
1211 | |
1212 | /* If we return, we re-enter start_secondary */ | |
1213 | start_secondary_resume(); | |
abb17f9c | 1214 | } |
fa3f82c8 | 1215 | |
1da177e4 | 1216 | #endif |