Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 LT |
2 | /* |
3 | * SMP support for ppc. | |
4 | * | |
5 | * Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great | |
6 | * deal of code from the sparc and intel versions. | |
7 | * | |
8 | * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> | |
9 | * | |
10 | * PowerPC-64 Support added by Dave Engebretsen, Peter Bergner, and | |
11 | * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com | |
1da177e4 LT |
12 | */ |
13 | ||
14 | #undef DEBUG | |
15 | ||
1da177e4 | 16 | #include <linux/kernel.h> |
4b16f8e2 | 17 | #include <linux/export.h> |
68e21be2 | 18 | #include <linux/sched/mm.h> |
678c668a | 19 | #include <linux/sched/task_stack.h> |
105ab3d8 | 20 | #include <linux/sched/topology.h> |
1da177e4 LT |
21 | #include <linux/smp.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/err.h> | |
8a25a2fd | 28 | #include <linux/device.h> |
1da177e4 LT |
29 | #include <linux/cpu.h> |
30 | #include <linux/notifier.h> | |
4b703a23 | 31 | #include <linux/topology.h> |
665e87ff | 32 | #include <linux/profile.h> |
4e287e65 | 33 | #include <linux/processor.h> |
7241d26e | 34 | #include <linux/random.h> |
b6aeddea | 35 | #include <linux/stackprotector.h> |
65fddcfc | 36 | #include <linux/pgtable.h> |
1da177e4 LT |
37 | |
38 | #include <asm/ptrace.h> | |
60063497 | 39 | #include <linux/atomic.h> |
1da177e4 | 40 | #include <asm/irq.h> |
1b67bee1 | 41 | #include <asm/hw_irq.h> |
441c19c8 | 42 | #include <asm/kvm_ppc.h> |
b866cc21 | 43 | #include <asm/dbell.h> |
1da177e4 | 44 | #include <asm/page.h> |
1da177e4 LT |
45 | #include <asm/prom.h> |
46 | #include <asm/smp.h> | |
1da177e4 LT |
47 | #include <asm/time.h> |
48 | #include <asm/machdep.h> | |
e2075f79 | 49 | #include <asm/cputhreads.h> |
1da177e4 | 50 | #include <asm/cputable.h> |
bbeb3f4c | 51 | #include <asm/mpic.h> |
a7f290da | 52 | #include <asm/vdso_datapage.h> |
5ad57078 PM |
53 | #ifdef CONFIG_PPC64 |
54 | #include <asm/paca.h> | |
55 | #endif | |
18ad51dd | 56 | #include <asm/vdso.h> |
ae3a197e | 57 | #include <asm/debug.h> |
1217d34b | 58 | #include <asm/kexec.h> |
42f5b4ca | 59 | #include <asm/asm-prototypes.h> |
b92a226e | 60 | #include <asm/cpu_has_feature.h> |
d1039786 | 61 | #include <asm/ftrace.h> |
e0d8e991 | 62 | #include <asm/kup.h> |
5ad57078 | 63 | |
1da177e4 | 64 | #ifdef DEBUG |
f9e4ec57 | 65 | #include <asm/udbg.h> |
1da177e4 LT |
66 | #define DBG(fmt...) udbg_printf(fmt) |
67 | #else | |
68 | #define DBG(fmt...) | |
69 | #endif | |
70 | ||
c56e5853 | 71 | #ifdef CONFIG_HOTPLUG_CPU |
fb82b839 BH |
72 | /* State of each CPU during hotplug phases */ |
73 | static DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
c56e5853 BH |
74 | #endif |
75 | ||
7c19c2e5 | 76 | struct task_struct *secondary_current; |
425752c6 | 77 | bool has_big_cores; |
f9e4ec57 | 78 | |
cc1ba8ea | 79 | DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
425752c6 | 80 | DEFINE_PER_CPU(cpumask_var_t, cpu_smallcore_map); |
2a636a56 | 81 | DEFINE_PER_CPU(cpumask_var_t, cpu_l2_cache_map); |
cc1ba8ea | 82 | DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); |
1da177e4 | 83 | |
d5a7430d | 84 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
2a636a56 | 85 | EXPORT_PER_CPU_SYMBOL(cpu_l2_cache_map); |
440a0857 | 86 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
425752c6 GS |
87 | EXPORT_SYMBOL_GPL(has_big_cores); |
88 | ||
89 | #define MAX_THREAD_LIST_SIZE 8 | |
90 | #define THREAD_GROUP_SHARE_L1 1 | |
91 | struct thread_groups { | |
92 | unsigned int property; | |
93 | unsigned int nr_groups; | |
94 | unsigned int threads_per_group; | |
95 | unsigned int thread_list[MAX_THREAD_LIST_SIZE]; | |
96 | }; | |
97 | ||
98 | /* | |
99 | * On big-cores system, cpu_l1_cache_map for each CPU corresponds to | |
100 | * the set its siblings that share the L1-cache. | |
101 | */ | |
102 | DEFINE_PER_CPU(cpumask_var_t, cpu_l1_cache_map); | |
1da177e4 | 103 | |
5ad57078 | 104 | /* SMP operations for this machine */ |
1da177e4 LT |
105 | struct smp_ops_t *smp_ops; |
106 | ||
7ccbe504 BH |
107 | /* Can't be static due to PowerMac hackery */ |
108 | volatile unsigned int cpu_callin_map[NR_CPUS]; | |
1da177e4 | 109 | |
1da177e4 LT |
110 | int smt_enabled_at_boot = 1; |
111 | ||
3cd85250 AF |
112 | /* |
113 | * Returns 1 if the specified cpu should be brought up during boot. | |
114 | * Used to inhibit booting threads if they've been disabled or | |
115 | * limited on the command line | |
116 | */ | |
117 | int smp_generic_cpu_bootable(unsigned int nr) | |
118 | { | |
119 | /* Special case - we inhibit secondary thread startup | |
120 | * during boot if the user requests it. | |
121 | */ | |
a8fcfc19 | 122 | if (system_state < SYSTEM_RUNNING && cpu_has_feature(CPU_FTR_SMT)) { |
3cd85250 AF |
123 | if (!smt_enabled_at_boot && cpu_thread_in_core(nr) != 0) |
124 | return 0; | |
125 | if (smt_enabled_at_boot | |
126 | && cpu_thread_in_core(nr) >= smt_enabled_at_boot) | |
127 | return 0; | |
128 | } | |
129 | ||
130 | return 1; | |
131 | } | |
132 | ||
133 | ||
5ad57078 | 134 | #ifdef CONFIG_PPC64 |
cad5cef6 | 135 | int smp_generic_kick_cpu(int nr) |
1da177e4 | 136 | { |
c642af9c | 137 | if (nr < 0 || nr >= nr_cpu_ids) |
f8d0d5dc | 138 | return -EINVAL; |
1da177e4 LT |
139 | |
140 | /* | |
141 | * The processor is currently spinning, waiting for the | |
142 | * cpu_start field to become non-zero After we set cpu_start, | |
143 | * the processor will continue on to secondary_start | |
144 | */ | |
d2e60075 NP |
145 | if (!paca_ptrs[nr]->cpu_start) { |
146 | paca_ptrs[nr]->cpu_start = 1; | |
fb82b839 BH |
147 | smp_mb(); |
148 | return 0; | |
149 | } | |
150 | ||
151 | #ifdef CONFIG_HOTPLUG_CPU | |
152 | /* | |
153 | * Ok it's not there, so it might be soft-unplugged, let's | |
154 | * try to bring it back | |
155 | */ | |
ae5cab47 | 156 | generic_set_cpu_up(nr); |
fb82b839 BH |
157 | smp_wmb(); |
158 | smp_send_reschedule(nr); | |
159 | #endif /* CONFIG_HOTPLUG_CPU */ | |
de300974 ME |
160 | |
161 | return 0; | |
1da177e4 | 162 | } |
fb82b839 | 163 | #endif /* CONFIG_PPC64 */ |
1da177e4 | 164 | |
25ddd738 MM |
165 | static irqreturn_t call_function_action(int irq, void *data) |
166 | { | |
167 | generic_smp_call_function_interrupt(); | |
168 | return IRQ_HANDLED; | |
169 | } | |
170 | ||
171 | static irqreturn_t reschedule_action(int irq, void *data) | |
172 | { | |
184748cc | 173 | scheduler_ipi(); |
25ddd738 MM |
174 | return IRQ_HANDLED; |
175 | } | |
176 | ||
bc907113 | 177 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
1b67bee1 | 178 | static irqreturn_t tick_broadcast_ipi_action(int irq, void *data) |
25ddd738 | 179 | { |
3f984620 | 180 | timer_broadcast_interrupt(); |
25ddd738 MM |
181 | return IRQ_HANDLED; |
182 | } | |
bc907113 | 183 | #endif |
25ddd738 | 184 | |
ddd703ca NP |
185 | #ifdef CONFIG_NMI_IPI |
186 | static irqreturn_t nmi_ipi_action(int irq, void *data) | |
25ddd738 | 187 | { |
ddd703ca | 188 | smp_handle_nmi_ipi(get_irq_regs()); |
25ddd738 MM |
189 | return IRQ_HANDLED; |
190 | } | |
ddd703ca | 191 | #endif |
25ddd738 MM |
192 | |
193 | static irq_handler_t smp_ipi_action[] = { | |
194 | [PPC_MSG_CALL_FUNCTION] = call_function_action, | |
195 | [PPC_MSG_RESCHEDULE] = reschedule_action, | |
bc907113 | 196 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
1b67bee1 | 197 | [PPC_MSG_TICK_BROADCAST] = tick_broadcast_ipi_action, |
bc907113 | 198 | #endif |
ddd703ca NP |
199 | #ifdef CONFIG_NMI_IPI |
200 | [PPC_MSG_NMI_IPI] = nmi_ipi_action, | |
201 | #endif | |
25ddd738 MM |
202 | }; |
203 | ||
ddd703ca NP |
204 | /* |
205 | * The NMI IPI is a fallback and not truly non-maskable. It is simpler | |
206 | * than going through the call function infrastructure, and strongly | |
207 | * serialized, so it is more appropriate for debugging. | |
208 | */ | |
25ddd738 MM |
209 | const char *smp_ipi_name[] = { |
210 | [PPC_MSG_CALL_FUNCTION] = "ipi call function", | |
211 | [PPC_MSG_RESCHEDULE] = "ipi reschedule", | |
bc907113 | 212 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
1b67bee1 | 213 | [PPC_MSG_TICK_BROADCAST] = "ipi tick-broadcast", |
bc907113 | 214 | #endif |
21bfd6a8 | 215 | #ifdef CONFIG_NMI_IPI |
ddd703ca | 216 | [PPC_MSG_NMI_IPI] = "nmi ipi", |
21bfd6a8 | 217 | #endif |
25ddd738 MM |
218 | }; |
219 | ||
220 | /* optional function to request ipi, for controllers with >= 4 ipis */ | |
221 | int smp_request_message_ipi(int virq, int msg) | |
222 | { | |
223 | int err; | |
224 | ||
ddd703ca | 225 | if (msg < 0 || msg > PPC_MSG_NMI_IPI) |
25ddd738 | 226 | return -EINVAL; |
ddd703ca NP |
227 | #ifndef CONFIG_NMI_IPI |
228 | if (msg == PPC_MSG_NMI_IPI) | |
25ddd738 | 229 | return 1; |
25ddd738 | 230 | #endif |
ddd703ca | 231 | |
3b5e16d7 | 232 | err = request_irq(virq, smp_ipi_action[msg], |
e6651de9 | 233 | IRQF_PERCPU | IRQF_NO_THREAD | IRQF_NO_SUSPEND, |
b0d436c7 | 234 | smp_ipi_name[msg], NULL); |
25ddd738 MM |
235 | WARN(err < 0, "unable to request_irq %d for %s (rc %d)\n", |
236 | virq, smp_ipi_name[msg], err); | |
237 | ||
238 | return err; | |
239 | } | |
240 | ||
1ece355b | 241 | #ifdef CONFIG_PPC_SMP_MUXED_IPI |
23d72bfd | 242 | struct cpu_messages { |
bd7f561f | 243 | long messages; /* current messages */ |
23d72bfd MM |
244 | }; |
245 | static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_messages, ipi_message); | |
246 | ||
31639c77 | 247 | void smp_muxed_ipi_set_message(int cpu, int msg) |
23d72bfd MM |
248 | { |
249 | struct cpu_messages *info = &per_cpu(ipi_message, cpu); | |
71454272 | 250 | char *message = (char *)&info->messages; |
23d72bfd | 251 | |
9fb1b36c PM |
252 | /* |
253 | * Order previous accesses before accesses in the IPI handler. | |
254 | */ | |
255 | smp_mb(); | |
71454272 | 256 | message[msg] = 1; |
31639c77 SW |
257 | } |
258 | ||
259 | void smp_muxed_ipi_message_pass(int cpu, int msg) | |
260 | { | |
31639c77 | 261 | smp_muxed_ipi_set_message(cpu, msg); |
b866cc21 | 262 | |
9fb1b36c PM |
263 | /* |
264 | * cause_ipi functions are required to include a full barrier | |
265 | * before doing whatever causes the IPI. | |
266 | */ | |
b866cc21 | 267 | smp_ops->cause_ipi(cpu); |
23d72bfd MM |
268 | } |
269 | ||
0654de1c | 270 | #ifdef __BIG_ENDIAN__ |
bd7f561f | 271 | #define IPI_MESSAGE(A) (1uL << ((BITS_PER_LONG - 8) - 8 * (A))) |
0654de1c | 272 | #else |
bd7f561f | 273 | #define IPI_MESSAGE(A) (1uL << (8 * (A))) |
0654de1c AB |
274 | #endif |
275 | ||
23d72bfd MM |
276 | irqreturn_t smp_ipi_demux(void) |
277 | { | |
23d72bfd | 278 | mb(); /* order any irq clear */ |
71454272 | 279 | |
b87ac021 NP |
280 | return smp_ipi_demux_relaxed(); |
281 | } | |
282 | ||
283 | /* sync-free variant. Callers should ensure synchronization */ | |
284 | irqreturn_t smp_ipi_demux_relaxed(void) | |
23d72bfd | 285 | { |
b866cc21 | 286 | struct cpu_messages *info; |
bd7f561f | 287 | unsigned long all; |
23d72bfd | 288 | |
b866cc21 | 289 | info = this_cpu_ptr(&ipi_message); |
71454272 | 290 | do { |
9fb1b36c | 291 | all = xchg(&info->messages, 0); |
e17769eb SW |
292 | #if defined(CONFIG_KVM_XICS) && defined(CONFIG_KVM_BOOK3S_HV_POSSIBLE) |
293 | /* | |
294 | * Must check for PPC_MSG_RM_HOST_ACTION messages | |
295 | * before PPC_MSG_CALL_FUNCTION messages because when | |
296 | * a VM is destroyed, we call kick_all_cpus_sync() | |
297 | * to ensure that any pending PPC_MSG_RM_HOST_ACTION | |
298 | * messages have completed before we free any VCPUs. | |
299 | */ | |
300 | if (all & IPI_MESSAGE(PPC_MSG_RM_HOST_ACTION)) | |
301 | kvmppc_xics_ipi_action(); | |
302 | #endif | |
0654de1c | 303 | if (all & IPI_MESSAGE(PPC_MSG_CALL_FUNCTION)) |
23d72bfd | 304 | generic_smp_call_function_interrupt(); |
0654de1c | 305 | if (all & IPI_MESSAGE(PPC_MSG_RESCHEDULE)) |
880102e7 | 306 | scheduler_ipi(); |
bc907113 | 307 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
1b67bee1 | 308 | if (all & IPI_MESSAGE(PPC_MSG_TICK_BROADCAST)) |
3f984620 | 309 | timer_broadcast_interrupt(); |
bc907113 | 310 | #endif |
ddd703ca NP |
311 | #ifdef CONFIG_NMI_IPI |
312 | if (all & IPI_MESSAGE(PPC_MSG_NMI_IPI)) | |
313 | nmi_ipi_action(0, NULL); | |
314 | #endif | |
71454272 MM |
315 | } while (info->messages); |
316 | ||
23d72bfd MM |
317 | return IRQ_HANDLED; |
318 | } | |
1ece355b | 319 | #endif /* CONFIG_PPC_SMP_MUXED_IPI */ |
23d72bfd | 320 | |
9ca980dc PM |
321 | static inline void do_message_pass(int cpu, int msg) |
322 | { | |
323 | if (smp_ops->message_pass) | |
324 | smp_ops->message_pass(cpu, msg); | |
325 | #ifdef CONFIG_PPC_SMP_MUXED_IPI | |
326 | else | |
327 | smp_muxed_ipi_message_pass(cpu, msg); | |
328 | #endif | |
329 | } | |
330 | ||
1da177e4 LT |
331 | void smp_send_reschedule(int cpu) |
332 | { | |
8cffc6ac | 333 | if (likely(smp_ops)) |
9ca980dc | 334 | do_message_pass(cpu, PPC_MSG_RESCHEDULE); |
1da177e4 | 335 | } |
de56a948 | 336 | EXPORT_SYMBOL_GPL(smp_send_reschedule); |
1da177e4 | 337 | |
b7d7a240 JA |
338 | void arch_send_call_function_single_ipi(int cpu) |
339 | { | |
402d9a1e | 340 | do_message_pass(cpu, PPC_MSG_CALL_FUNCTION); |
b7d7a240 JA |
341 | } |
342 | ||
f063ea02 | 343 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
b7d7a240 JA |
344 | { |
345 | unsigned int cpu; | |
346 | ||
f063ea02 | 347 | for_each_cpu(cpu, mask) |
9ca980dc | 348 | do_message_pass(cpu, PPC_MSG_CALL_FUNCTION); |
b7d7a240 JA |
349 | } |
350 | ||
ddd703ca NP |
351 | #ifdef CONFIG_NMI_IPI |
352 | ||
353 | /* | |
354 | * "NMI IPI" system. | |
355 | * | |
356 | * NMI IPIs may not be recoverable, so should not be used as ongoing part of | |
357 | * a running system. They can be used for crash, debug, halt/reboot, etc. | |
358 | * | |
ddd703ca | 359 | * The IPI call waits with interrupts disabled until all targets enter the |
88b9a3d1 NP |
360 | * NMI handler, then returns. Subsequent IPIs can be issued before targets |
361 | * have returned from their handlers, so there is no guarantee about | |
362 | * concurrency or re-entrancy. | |
ddd703ca | 363 | * |
88b9a3d1 | 364 | * A new NMI can be issued before all targets exit the handler. |
ddd703ca NP |
365 | * |
366 | * The IPI call may time out without all targets entering the NMI handler. | |
367 | * In that case, there is some logic to recover (and ignore subsequent | |
368 | * NMI interrupts that may eventually be raised), but the platform interrupt | |
369 | * handler may not be able to distinguish this from other exception causes, | |
370 | * which may cause a crash. | |
371 | */ | |
372 | ||
373 | static atomic_t __nmi_ipi_lock = ATOMIC_INIT(0); | |
374 | static struct cpumask nmi_ipi_pending_mask; | |
88b9a3d1 | 375 | static bool nmi_ipi_busy = false; |
ddd703ca NP |
376 | static void (*nmi_ipi_function)(struct pt_regs *) = NULL; |
377 | ||
378 | static void nmi_ipi_lock_start(unsigned long *flags) | |
379 | { | |
380 | raw_local_irq_save(*flags); | |
381 | hard_irq_disable(); | |
382 | while (atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1) { | |
383 | raw_local_irq_restore(*flags); | |
0459ddfd | 384 | spin_until_cond(atomic_read(&__nmi_ipi_lock) == 0); |
ddd703ca NP |
385 | raw_local_irq_save(*flags); |
386 | hard_irq_disable(); | |
387 | } | |
388 | } | |
389 | ||
390 | static void nmi_ipi_lock(void) | |
391 | { | |
392 | while (atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1) | |
0459ddfd | 393 | spin_until_cond(atomic_read(&__nmi_ipi_lock) == 0); |
ddd703ca NP |
394 | } |
395 | ||
396 | static void nmi_ipi_unlock(void) | |
397 | { | |
398 | smp_mb(); | |
399 | WARN_ON(atomic_read(&__nmi_ipi_lock) != 1); | |
400 | atomic_set(&__nmi_ipi_lock, 0); | |
401 | } | |
402 | ||
403 | static void nmi_ipi_unlock_end(unsigned long *flags) | |
404 | { | |
405 | nmi_ipi_unlock(); | |
406 | raw_local_irq_restore(*flags); | |
407 | } | |
408 | ||
409 | /* | |
410 | * Platform NMI handler calls this to ack | |
411 | */ | |
412 | int smp_handle_nmi_ipi(struct pt_regs *regs) | |
413 | { | |
88b9a3d1 | 414 | void (*fn)(struct pt_regs *) = NULL; |
ddd703ca NP |
415 | unsigned long flags; |
416 | int me = raw_smp_processor_id(); | |
417 | int ret = 0; | |
418 | ||
419 | /* | |
420 | * Unexpected NMIs are possible here because the interrupt may not | |
421 | * be able to distinguish NMI IPIs from other types of NMIs, or | |
422 | * because the caller may have timed out. | |
423 | */ | |
424 | nmi_ipi_lock_start(&flags); | |
88b9a3d1 NP |
425 | if (cpumask_test_cpu(me, &nmi_ipi_pending_mask)) { |
426 | cpumask_clear_cpu(me, &nmi_ipi_pending_mask); | |
427 | fn = READ_ONCE(nmi_ipi_function); | |
428 | WARN_ON_ONCE(!fn); | |
429 | ret = 1; | |
430 | } | |
ddd703ca NP |
431 | nmi_ipi_unlock_end(&flags); |
432 | ||
88b9a3d1 NP |
433 | if (fn) |
434 | fn(regs); | |
435 | ||
ddd703ca NP |
436 | return ret; |
437 | } | |
438 | ||
6ba55716 | 439 | static void do_smp_send_nmi_ipi(int cpu, bool safe) |
ddd703ca | 440 | { |
6ba55716 | 441 | if (!safe && smp_ops->cause_nmi_ipi && smp_ops->cause_nmi_ipi(cpu)) |
c64af645 NP |
442 | return; |
443 | ||
ddd703ca NP |
444 | if (cpu >= 0) { |
445 | do_message_pass(cpu, PPC_MSG_NMI_IPI); | |
446 | } else { | |
447 | int c; | |
448 | ||
449 | for_each_online_cpu(c) { | |
450 | if (c == raw_smp_processor_id()) | |
451 | continue; | |
452 | do_message_pass(c, PPC_MSG_NMI_IPI); | |
453 | } | |
454 | } | |
455 | } | |
456 | ||
457 | /* | |
458 | * - cpu is the target CPU (must not be this CPU), or NMI_IPI_ALL_OTHERS. | |
459 | * - fn is the target callback function. | |
460 | * - delay_us > 0 is the delay before giving up waiting for targets to | |
88b9a3d1 | 461 | * begin executing the handler, == 0 specifies indefinite delay. |
ddd703ca | 462 | */ |
6fe243fe NP |
463 | static int __smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), |
464 | u64 delay_us, bool safe) | |
ddd703ca NP |
465 | { |
466 | unsigned long flags; | |
467 | int me = raw_smp_processor_id(); | |
468 | int ret = 1; | |
469 | ||
470 | BUG_ON(cpu == me); | |
471 | BUG_ON(cpu < 0 && cpu != NMI_IPI_ALL_OTHERS); | |
472 | ||
473 | if (unlikely(!smp_ops)) | |
474 | return 0; | |
475 | ||
ddd703ca | 476 | nmi_ipi_lock_start(&flags); |
88b9a3d1 | 477 | while (nmi_ipi_busy) { |
ddd703ca | 478 | nmi_ipi_unlock_end(&flags); |
88b9a3d1 | 479 | spin_until_cond(!nmi_ipi_busy); |
ddd703ca NP |
480 | nmi_ipi_lock_start(&flags); |
481 | } | |
88b9a3d1 | 482 | nmi_ipi_busy = true; |
ddd703ca NP |
483 | nmi_ipi_function = fn; |
484 | ||
88b9a3d1 NP |
485 | WARN_ON_ONCE(!cpumask_empty(&nmi_ipi_pending_mask)); |
486 | ||
ddd703ca NP |
487 | if (cpu < 0) { |
488 | /* ALL_OTHERS */ | |
489 | cpumask_copy(&nmi_ipi_pending_mask, cpu_online_mask); | |
490 | cpumask_clear_cpu(me, &nmi_ipi_pending_mask); | |
491 | } else { | |
ddd703ca NP |
492 | cpumask_set_cpu(cpu, &nmi_ipi_pending_mask); |
493 | } | |
88b9a3d1 | 494 | |
ddd703ca NP |
495 | nmi_ipi_unlock(); |
496 | ||
88b9a3d1 NP |
497 | /* Interrupts remain hard disabled */ |
498 | ||
6ba55716 | 499 | do_smp_send_nmi_ipi(cpu, safe); |
ddd703ca | 500 | |
5b73151f | 501 | nmi_ipi_lock(); |
88b9a3d1 | 502 | /* nmi_ipi_busy is set here, so unlock/lock is okay */ |
ddd703ca | 503 | while (!cpumask_empty(&nmi_ipi_pending_mask)) { |
5b73151f | 504 | nmi_ipi_unlock(); |
ddd703ca | 505 | udelay(1); |
5b73151f NP |
506 | nmi_ipi_lock(); |
507 | if (delay_us) { | |
508 | delay_us--; | |
509 | if (!delay_us) | |
88b9a3d1 | 510 | break; |
5b73151f NP |
511 | } |
512 | } | |
513 | ||
ddd703ca | 514 | if (!cpumask_empty(&nmi_ipi_pending_mask)) { |
5b73151f | 515 | /* Timeout waiting for CPUs to call smp_handle_nmi_ipi */ |
ddd703ca NP |
516 | ret = 0; |
517 | cpumask_clear(&nmi_ipi_pending_mask); | |
518 | } | |
5b73151f | 519 | |
88b9a3d1 NP |
520 | nmi_ipi_function = NULL; |
521 | nmi_ipi_busy = false; | |
522 | ||
ddd703ca NP |
523 | nmi_ipi_unlock_end(&flags); |
524 | ||
525 | return ret; | |
526 | } | |
6ba55716 ME |
527 | |
528 | int smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us) | |
529 | { | |
530 | return __smp_send_nmi_ipi(cpu, fn, delay_us, false); | |
531 | } | |
532 | ||
533 | int smp_send_safe_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us) | |
534 | { | |
535 | return __smp_send_nmi_ipi(cpu, fn, delay_us, true); | |
536 | } | |
ddd703ca NP |
537 | #endif /* CONFIG_NMI_IPI */ |
538 | ||
1b67bee1 SB |
539 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
540 | void tick_broadcast(const struct cpumask *mask) | |
541 | { | |
542 | unsigned int cpu; | |
543 | ||
544 | for_each_cpu(cpu, mask) | |
545 | do_message_pass(cpu, PPC_MSG_TICK_BROADCAST); | |
546 | } | |
547 | #endif | |
548 | ||
ddd703ca NP |
549 | #ifdef CONFIG_DEBUGGER |
550 | void debugger_ipi_callback(struct pt_regs *regs) | |
1da177e4 | 551 | { |
ddd703ca NP |
552 | debugger_ipi(regs); |
553 | } | |
e0476371 | 554 | |
ddd703ca NP |
555 | void smp_send_debugger_break(void) |
556 | { | |
557 | smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, debugger_ipi_callback, 1000000); | |
1da177e4 LT |
558 | } |
559 | #endif | |
560 | ||
da665885 | 561 | #ifdef CONFIG_KEXEC_CORE |
cc532915 ME |
562 | void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *)) |
563 | { | |
4145f358 BS |
564 | int cpu; |
565 | ||
ddd703ca | 566 | smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, crash_ipi_callback, 1000000); |
4145f358 BS |
567 | if (kdump_in_progress() && crash_wake_offline) { |
568 | for_each_present_cpu(cpu) { | |
569 | if (cpu_online(cpu)) | |
570 | continue; | |
571 | /* | |
572 | * crash_ipi_callback will wait for | |
573 | * all cpus, including offline CPUs. | |
574 | * We don't care about nmi_ipi_function. | |
575 | * Offline cpus will jump straight into | |
576 | * crash_ipi_callback, we can skip the | |
577 | * entire NMI dance and waiting for | |
578 | * cpus to clear pending mask, etc. | |
579 | */ | |
6ba55716 | 580 | do_smp_send_nmi_ipi(cpu, false); |
4145f358 BS |
581 | } |
582 | } | |
cc532915 ME |
583 | } |
584 | #endif | |
585 | ||
ac61c115 NP |
586 | #ifdef CONFIG_NMI_IPI |
587 | static void nmi_stop_this_cpu(struct pt_regs *regs) | |
588 | { | |
589 | /* | |
6029755e | 590 | * IRQs are already hard disabled by the smp_handle_nmi_ipi. |
ac61c115 | 591 | */ |
6029755e NP |
592 | spin_begin(); |
593 | while (1) | |
594 | spin_cpu_relax(); | |
ac61c115 | 595 | } |
ac61c115 | 596 | |
8fd7675c SS |
597 | void smp_send_stop(void) |
598 | { | |
ac61c115 | 599 | smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, nmi_stop_this_cpu, 1000000); |
6029755e NP |
600 | } |
601 | ||
602 | #else /* CONFIG_NMI_IPI */ | |
603 | ||
604 | static void stop_this_cpu(void *dummy) | |
605 | { | |
6029755e NP |
606 | hard_irq_disable(); |
607 | spin_begin(); | |
608 | while (1) | |
609 | spin_cpu_relax(); | |
610 | } | |
611 | ||
612 | void smp_send_stop(void) | |
613 | { | |
614 | static bool stopped = false; | |
615 | ||
616 | /* | |
617 | * Prevent waiting on csd lock from a previous smp_send_stop. | |
618 | * This is racy, but in general callers try to do the right | |
619 | * thing and only fire off one smp_send_stop (e.g., see | |
620 | * kernel/panic.c) | |
621 | */ | |
622 | if (stopped) | |
623 | return; | |
624 | ||
625 | stopped = true; | |
626 | ||
8691e5a8 | 627 | smp_call_function(stop_this_cpu, NULL, 0); |
1da177e4 | 628 | } |
6029755e | 629 | #endif /* CONFIG_NMI_IPI */ |
1da177e4 | 630 | |
7c19c2e5 | 631 | struct task_struct *current_set[NR_CPUS]; |
1da177e4 | 632 | |
cad5cef6 | 633 | static void smp_store_cpu_info(int id) |
1da177e4 | 634 | { |
6b7487fc | 635 | per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR); |
3160b097 BB |
636 | #ifdef CONFIG_PPC_FSL_BOOK3E |
637 | per_cpu(next_tlbcam_idx, id) | |
638 | = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1; | |
639 | #endif | |
1da177e4 LT |
640 | } |
641 | ||
df52f671 OH |
642 | /* |
643 | * Relationships between CPUs are maintained in a set of per-cpu cpumasks so | |
644 | * rather than just passing around the cpumask we pass around a function that | |
645 | * returns the that cpumask for the given CPU. | |
646 | */ | |
647 | static void set_cpus_related(int i, int j, struct cpumask *(*get_cpumask)(int)) | |
648 | { | |
649 | cpumask_set_cpu(i, get_cpumask(j)); | |
650 | cpumask_set_cpu(j, get_cpumask(i)); | |
651 | } | |
652 | ||
653 | #ifdef CONFIG_HOTPLUG_CPU | |
654 | static void set_cpus_unrelated(int i, int j, | |
655 | struct cpumask *(*get_cpumask)(int)) | |
656 | { | |
657 | cpumask_clear_cpu(i, get_cpumask(j)); | |
658 | cpumask_clear_cpu(j, get_cpumask(i)); | |
659 | } | |
660 | #endif | |
661 | ||
425752c6 GS |
662 | /* |
663 | * parse_thread_groups: Parses the "ibm,thread-groups" device tree | |
664 | * property for the CPU device node @dn and stores | |
665 | * the parsed output in the thread_groups | |
666 | * structure @tg if the ibm,thread-groups[0] | |
667 | * matches @property. | |
668 | * | |
669 | * @dn: The device node of the CPU device. | |
670 | * @tg: Pointer to a thread group structure into which the parsed | |
671 | * output of "ibm,thread-groups" is stored. | |
672 | * @property: The property of the thread-group that the caller is | |
673 | * interested in. | |
674 | * | |
675 | * ibm,thread-groups[0..N-1] array defines which group of threads in | |
676 | * the CPU-device node can be grouped together based on the property. | |
677 | * | |
678 | * ibm,thread-groups[0] tells us the property based on which the | |
679 | * threads are being grouped together. If this value is 1, it implies | |
680 | * that the threads in the same group share L1, translation cache. | |
681 | * | |
682 | * ibm,thread-groups[1] tells us how many such thread groups exist. | |
683 | * | |
684 | * ibm,thread-groups[2] tells us the number of threads in each such | |
685 | * group. | |
686 | * | |
687 | * ibm,thread-groups[3..N-1] is the list of threads identified by | |
688 | * "ibm,ppc-interrupt-server#s" arranged as per their membership in | |
689 | * the grouping. | |
690 | * | |
691 | * Example: If ibm,thread-groups = [1,2,4,5,6,7,8,9,10,11,12] it | |
692 | * implies that there are 2 groups of 4 threads each, where each group | |
693 | * of threads share L1, translation cache. | |
694 | * | |
695 | * The "ibm,ppc-interrupt-server#s" of the first group is {5,6,7,8} | |
696 | * and the "ibm,ppc-interrupt-server#s" of the second group is {9, 10, | |
697 | * 11, 12} structure | |
698 | * | |
699 | * Returns 0 on success, -EINVAL if the property does not exist, | |
700 | * -ENODATA if property does not have a value, and -EOVERFLOW if the | |
701 | * property data isn't large enough. | |
702 | */ | |
703 | static int parse_thread_groups(struct device_node *dn, | |
704 | struct thread_groups *tg, | |
705 | unsigned int property) | |
706 | { | |
707 | int i; | |
708 | u32 thread_group_array[3 + MAX_THREAD_LIST_SIZE]; | |
709 | u32 *thread_list; | |
710 | size_t total_threads; | |
711 | int ret; | |
712 | ||
713 | ret = of_property_read_u32_array(dn, "ibm,thread-groups", | |
714 | thread_group_array, 3); | |
715 | if (ret) | |
716 | return ret; | |
717 | ||
718 | tg->property = thread_group_array[0]; | |
719 | tg->nr_groups = thread_group_array[1]; | |
720 | tg->threads_per_group = thread_group_array[2]; | |
721 | if (tg->property != property || | |
722 | tg->nr_groups < 1 || | |
723 | tg->threads_per_group < 1) | |
724 | return -ENODATA; | |
725 | ||
726 | total_threads = tg->nr_groups * tg->threads_per_group; | |
727 | ||
728 | ret = of_property_read_u32_array(dn, "ibm,thread-groups", | |
729 | thread_group_array, | |
730 | 3 + total_threads); | |
731 | if (ret) | |
732 | return ret; | |
733 | ||
734 | thread_list = &thread_group_array[3]; | |
735 | ||
736 | for (i = 0 ; i < total_threads; i++) | |
737 | tg->thread_list[i] = thread_list[i]; | |
738 | ||
739 | return 0; | |
740 | } | |
741 | ||
742 | /* | |
743 | * get_cpu_thread_group_start : Searches the thread group in tg->thread_list | |
744 | * that @cpu belongs to. | |
745 | * | |
746 | * @cpu : The logical CPU whose thread group is being searched. | |
747 | * @tg : The thread-group structure of the CPU node which @cpu belongs | |
748 | * to. | |
749 | * | |
750 | * Returns the index to tg->thread_list that points to the the start | |
751 | * of the thread_group that @cpu belongs to. | |
752 | * | |
753 | * Returns -1 if cpu doesn't belong to any of the groups pointed to by | |
754 | * tg->thread_list. | |
755 | */ | |
756 | static int get_cpu_thread_group_start(int cpu, struct thread_groups *tg) | |
757 | { | |
758 | int hw_cpu_id = get_hard_smp_processor_id(cpu); | |
759 | int i, j; | |
760 | ||
761 | for (i = 0; i < tg->nr_groups; i++) { | |
762 | int group_start = i * tg->threads_per_group; | |
763 | ||
764 | for (j = 0; j < tg->threads_per_group; j++) { | |
765 | int idx = group_start + j; | |
766 | ||
767 | if (tg->thread_list[idx] == hw_cpu_id) | |
768 | return group_start; | |
769 | } | |
770 | } | |
771 | ||
772 | return -1; | |
773 | } | |
774 | ||
775 | static int init_cpu_l1_cache_map(int cpu) | |
776 | ||
777 | { | |
778 | struct device_node *dn = of_get_cpu_node(cpu, NULL); | |
779 | struct thread_groups tg = {.property = 0, | |
780 | .nr_groups = 0, | |
781 | .threads_per_group = 0}; | |
782 | int first_thread = cpu_first_thread_sibling(cpu); | |
783 | int i, cpu_group_start = -1, err = 0; | |
784 | ||
785 | if (!dn) | |
786 | return -ENODATA; | |
787 | ||
788 | err = parse_thread_groups(dn, &tg, THREAD_GROUP_SHARE_L1); | |
789 | if (err) | |
790 | goto out; | |
791 | ||
792 | zalloc_cpumask_var_node(&per_cpu(cpu_l1_cache_map, cpu), | |
793 | GFP_KERNEL, | |
794 | cpu_to_node(cpu)); | |
795 | ||
796 | cpu_group_start = get_cpu_thread_group_start(cpu, &tg); | |
797 | ||
798 | if (unlikely(cpu_group_start == -1)) { | |
799 | WARN_ON_ONCE(1); | |
800 | err = -ENODATA; | |
801 | goto out; | |
802 | } | |
803 | ||
804 | for (i = first_thread; i < first_thread + threads_per_core; i++) { | |
805 | int i_group_start = get_cpu_thread_group_start(i, &tg); | |
806 | ||
807 | if (unlikely(i_group_start == -1)) { | |
808 | WARN_ON_ONCE(1); | |
809 | err = -ENODATA; | |
810 | goto out; | |
811 | } | |
812 | ||
813 | if (i_group_start == cpu_group_start) | |
814 | cpumask_set_cpu(i, per_cpu(cpu_l1_cache_map, cpu)); | |
815 | } | |
816 | ||
817 | out: | |
818 | of_node_put(dn); | |
819 | return err; | |
820 | } | |
821 | ||
5e93f16a SD |
822 | static bool shared_caches; |
823 | ||
824 | #ifdef CONFIG_SCHED_SMT | |
825 | /* cpumask of CPUs with asymmetric SMT dependency */ | |
826 | static int powerpc_smt_flags(void) | |
827 | { | |
828 | int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES; | |
829 | ||
830 | if (cpu_has_feature(CPU_FTR_ASYM_SMT)) { | |
831 | printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n"); | |
832 | flags |= SD_ASYM_PACKING; | |
833 | } | |
834 | return flags; | |
835 | } | |
836 | #endif | |
837 | ||
838 | /* | |
839 | * P9 has a slightly odd architecture where pairs of cores share an L2 cache. | |
840 | * This topology makes it *much* cheaper to migrate tasks between adjacent cores | |
841 | * since the migrated task remains cache hot. We want to take advantage of this | |
842 | * at the scheduler level so an extra topology level is required. | |
843 | */ | |
844 | static int powerpc_shared_cache_flags(void) | |
845 | { | |
846 | return SD_SHARE_PKG_RESOURCES; | |
847 | } | |
848 | ||
849 | /* | |
850 | * We can't just pass cpu_l2_cache_mask() directly because | |
851 | * returns a non-const pointer and the compiler barfs on that. | |
852 | */ | |
853 | static const struct cpumask *shared_cache_mask(int cpu) | |
854 | { | |
855 | return cpu_l2_cache_mask(cpu); | |
856 | } | |
857 | ||
858 | #ifdef CONFIG_SCHED_SMT | |
859 | static const struct cpumask *smallcore_smt_mask(int cpu) | |
860 | { | |
861 | return cpu_smallcore_mask(cpu); | |
862 | } | |
863 | #endif | |
864 | ||
865 | static struct sched_domain_topology_level powerpc_topology[] = { | |
866 | #ifdef CONFIG_SCHED_SMT | |
867 | { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) }, | |
868 | #endif | |
869 | { shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) }, | |
870 | { cpu_cpu_mask, SD_INIT_NAME(DIE) }, | |
871 | { NULL, }, | |
872 | }; | |
873 | ||
425752c6 GS |
874 | static int init_big_cores(void) |
875 | { | |
876 | int cpu; | |
877 | ||
878 | for_each_possible_cpu(cpu) { | |
879 | int err = init_cpu_l1_cache_map(cpu); | |
880 | ||
881 | if (err) | |
882 | return err; | |
883 | ||
884 | zalloc_cpumask_var_node(&per_cpu(cpu_smallcore_map, cpu), | |
885 | GFP_KERNEL, | |
886 | cpu_to_node(cpu)); | |
887 | } | |
888 | ||
889 | has_big_cores = true; | |
890 | return 0; | |
891 | } | |
892 | ||
1da177e4 LT |
893 | void __init smp_prepare_cpus(unsigned int max_cpus) |
894 | { | |
895 | unsigned int cpu; | |
896 | ||
897 | DBG("smp_prepare_cpus\n"); | |
898 | ||
899 | /* | |
900 | * setup_cpu may need to be called on the boot cpu. We havent | |
901 | * spun any cpus up but lets be paranoid. | |
902 | */ | |
903 | BUG_ON(boot_cpuid != smp_processor_id()); | |
904 | ||
905 | /* Fixup boot cpu */ | |
906 | smp_store_cpu_info(boot_cpuid); | |
907 | cpu_callin_map[boot_cpuid] = 1; | |
908 | ||
cc1ba8ea AB |
909 | for_each_possible_cpu(cpu) { |
910 | zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu), | |
911 | GFP_KERNEL, cpu_to_node(cpu)); | |
2a636a56 OH |
912 | zalloc_cpumask_var_node(&per_cpu(cpu_l2_cache_map, cpu), |
913 | GFP_KERNEL, cpu_to_node(cpu)); | |
cc1ba8ea AB |
914 | zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu), |
915 | GFP_KERNEL, cpu_to_node(cpu)); | |
d0fd24bb | 916 | #ifdef CONFIG_NEED_MULTIPLE_NODES |
2fabf084 NA |
917 | /* |
918 | * numa_node_id() works after this. | |
919 | */ | |
bc3c4327 LZ |
920 | if (cpu_present(cpu)) { |
921 | set_cpu_numa_node(cpu, numa_cpu_lookup_table[cpu]); | |
922 | set_cpu_numa_mem(cpu, | |
923 | local_memory_node(numa_cpu_lookup_table[cpu])); | |
924 | } | |
d0fd24bb | 925 | #endif |
cc1ba8ea AB |
926 | } |
927 | ||
df52f671 | 928 | /* Init the cpumasks so the boot CPU is related to itself */ |
cc1ba8ea | 929 | cpumask_set_cpu(boot_cpuid, cpu_sibling_mask(boot_cpuid)); |
2a636a56 | 930 | cpumask_set_cpu(boot_cpuid, cpu_l2_cache_mask(boot_cpuid)); |
cc1ba8ea AB |
931 | cpumask_set_cpu(boot_cpuid, cpu_core_mask(boot_cpuid)); |
932 | ||
425752c6 GS |
933 | init_big_cores(); |
934 | if (has_big_cores) { | |
935 | cpumask_set_cpu(boot_cpuid, | |
936 | cpu_smallcore_mask(boot_cpuid)); | |
937 | } | |
938 | ||
dfee0efe CG |
939 | if (smp_ops && smp_ops->probe) |
940 | smp_ops->probe(); | |
1da177e4 LT |
941 | } |
942 | ||
cad5cef6 | 943 | void smp_prepare_boot_cpu(void) |
1da177e4 LT |
944 | { |
945 | BUG_ON(smp_processor_id() != boot_cpuid); | |
5ad57078 | 946 | #ifdef CONFIG_PPC64 |
d2e60075 | 947 | paca_ptrs[boot_cpuid]->__current = current; |
5ad57078 | 948 | #endif |
8c272261 | 949 | set_numa_node(numa_cpu_lookup_table[boot_cpuid]); |
7c19c2e5 | 950 | current_set[boot_cpuid] = current; |
1da177e4 LT |
951 | } |
952 | ||
953 | #ifdef CONFIG_HOTPLUG_CPU | |
1da177e4 LT |
954 | |
955 | int generic_cpu_disable(void) | |
956 | { | |
957 | unsigned int cpu = smp_processor_id(); | |
958 | ||
959 | if (cpu == boot_cpuid) | |
960 | return -EBUSY; | |
961 | ||
ea0f1cab | 962 | set_cpu_online(cpu, false); |
799d6046 | 963 | #ifdef CONFIG_PPC64 |
a7f290da | 964 | vdso_data->processorCount--; |
094fe2e7 | 965 | #endif |
a978e139 BH |
966 | /* Update affinity of all IRQs previously aimed at this CPU */ |
967 | irq_migrate_all_off_this_cpu(); | |
968 | ||
687b8f24 ME |
969 | /* |
970 | * Depending on the details of the interrupt controller, it's possible | |
971 | * that one of the interrupts we just migrated away from this CPU is | |
972 | * actually already pending on this CPU. If we leave it in that state | |
973 | * the interrupt will never be EOI'ed, and will never fire again. So | |
974 | * temporarily enable interrupts here, to allow any pending interrupt to | |
975 | * be received (and EOI'ed), before we take this CPU offline. | |
976 | */ | |
a978e139 BH |
977 | local_irq_enable(); |
978 | mdelay(1); | |
979 | local_irq_disable(); | |
980 | ||
1da177e4 LT |
981 | return 0; |
982 | } | |
983 | ||
1da177e4 LT |
984 | void generic_cpu_die(unsigned int cpu) |
985 | { | |
986 | int i; | |
987 | ||
988 | for (i = 0; i < 100; i++) { | |
0d8d4d42 | 989 | smp_rmb(); |
2f4f1f81 | 990 | if (is_cpu_dead(cpu)) |
1da177e4 LT |
991 | return; |
992 | msleep(100); | |
993 | } | |
994 | printk(KERN_ERR "CPU%d didn't die...\n", cpu); | |
995 | } | |
996 | ||
105765f4 BH |
997 | void generic_set_cpu_dead(unsigned int cpu) |
998 | { | |
999 | per_cpu(cpu_state, cpu) = CPU_DEAD; | |
1000 | } | |
fb82b839 | 1001 | |
ae5cab47 ZC |
1002 | /* |
1003 | * The cpu_state should be set to CPU_UP_PREPARE in kick_cpu(), otherwise | |
1004 | * the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(), | |
1005 | * which makes the delay in generic_cpu_die() not happen. | |
1006 | */ | |
1007 | void generic_set_cpu_up(unsigned int cpu) | |
1008 | { | |
1009 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
1010 | } | |
1011 | ||
fb82b839 BH |
1012 | int generic_check_cpu_restart(unsigned int cpu) |
1013 | { | |
1014 | return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE; | |
1015 | } | |
512691d4 | 1016 | |
2f4f1f81 | 1017 | int is_cpu_dead(unsigned int cpu) |
1018 | { | |
1019 | return per_cpu(cpu_state, cpu) == CPU_DEAD; | |
1020 | } | |
1021 | ||
441c19c8 | 1022 | static bool secondaries_inhibited(void) |
512691d4 | 1023 | { |
441c19c8 | 1024 | return kvm_hv_mode_active(); |
512691d4 PM |
1025 | } |
1026 | ||
1027 | #else /* HOTPLUG_CPU */ | |
1028 | ||
1029 | #define secondaries_inhibited() 0 | |
1030 | ||
1da177e4 LT |
1031 | #endif |
1032 | ||
17e32eac | 1033 | static void cpu_idle_thread_init(unsigned int cpu, struct task_struct *idle) |
c56e5853 | 1034 | { |
c56e5853 | 1035 | #ifdef CONFIG_PPC64 |
d2e60075 | 1036 | paca_ptrs[cpu]->__current = idle; |
678c668a CL |
1037 | paca_ptrs[cpu]->kstack = (unsigned long)task_stack_page(idle) + |
1038 | THREAD_SIZE - STACK_FRAME_OVERHEAD; | |
c56e5853 | 1039 | #endif |
ed1cd6de | 1040 | idle->cpu = cpu; |
7c19c2e5 | 1041 | secondary_current = current_set[cpu] = idle; |
c56e5853 BH |
1042 | } |
1043 | ||
061d19f2 | 1044 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 1045 | { |
c56e5853 | 1046 | int rc, c; |
1da177e4 | 1047 | |
512691d4 PM |
1048 | /* |
1049 | * Don't allow secondary threads to come online if inhibited | |
1050 | */ | |
1051 | if (threads_per_core > 1 && secondaries_inhibited() && | |
6f5e40a3 | 1052 | cpu_thread_in_subcore(cpu)) |
512691d4 PM |
1053 | return -EBUSY; |
1054 | ||
8cffc6ac BH |
1055 | if (smp_ops == NULL || |
1056 | (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu))) | |
1da177e4 LT |
1057 | return -EINVAL; |
1058 | ||
17e32eac | 1059 | cpu_idle_thread_init(cpu, tidle); |
c560bbce | 1060 | |
14d4ae5c BH |
1061 | /* |
1062 | * The platform might need to allocate resources prior to bringing | |
1063 | * up the CPU | |
1064 | */ | |
1065 | if (smp_ops->prepare_cpu) { | |
1066 | rc = smp_ops->prepare_cpu(cpu); | |
1067 | if (rc) | |
1068 | return rc; | |
1069 | } | |
1070 | ||
1da177e4 LT |
1071 | /* Make sure callin-map entry is 0 (can be leftover a CPU |
1072 | * hotplug | |
1073 | */ | |
1074 | cpu_callin_map[cpu] = 0; | |
1075 | ||
1076 | /* The information for processor bringup must | |
1077 | * be written out to main store before we release | |
1078 | * the processor. | |
1079 | */ | |
0d8d4d42 | 1080 | smp_mb(); |
1da177e4 LT |
1081 | |
1082 | /* wake up cpus */ | |
1083 | DBG("smp: kicking cpu %d\n", cpu); | |
de300974 ME |
1084 | rc = smp_ops->kick_cpu(cpu); |
1085 | if (rc) { | |
1086 | pr_err("smp: failed starting cpu %d (rc %d)\n", cpu, rc); | |
1087 | return rc; | |
1088 | } | |
1da177e4 LT |
1089 | |
1090 | /* | |
1091 | * wait to see if the cpu made a callin (is actually up). | |
1092 | * use this value that I found through experimentation. | |
1093 | * -- Cort | |
1094 | */ | |
1095 | if (system_state < SYSTEM_RUNNING) | |
ee0339f2 | 1096 | for (c = 50000; c && !cpu_callin_map[cpu]; c--) |
1da177e4 LT |
1097 | udelay(100); |
1098 | #ifdef CONFIG_HOTPLUG_CPU | |
1099 | else | |
1100 | /* | |
1101 | * CPUs can take much longer to come up in the | |
1102 | * hotplug case. Wait five seconds. | |
1103 | */ | |
67764263 GS |
1104 | for (c = 5000; c && !cpu_callin_map[cpu]; c--) |
1105 | msleep(1); | |
1da177e4 LT |
1106 | #endif |
1107 | ||
1108 | if (!cpu_callin_map[cpu]) { | |
6685a477 | 1109 | printk(KERN_ERR "Processor %u is stuck.\n", cpu); |
1da177e4 LT |
1110 | return -ENOENT; |
1111 | } | |
1112 | ||
6685a477 | 1113 | DBG("Processor %u found.\n", cpu); |
1da177e4 LT |
1114 | |
1115 | if (smp_ops->give_timebase) | |
1116 | smp_ops->give_timebase(); | |
1117 | ||
875ebe94 | 1118 | /* Wait until cpu puts itself in the online & active maps */ |
4e287e65 | 1119 | spin_until_cond(cpu_online(cpu)); |
1da177e4 LT |
1120 | |
1121 | return 0; | |
1122 | } | |
1123 | ||
e9efed3b NL |
1124 | /* Return the value of the reg property corresponding to the given |
1125 | * logical cpu. | |
1126 | */ | |
1127 | int cpu_to_core_id(int cpu) | |
1128 | { | |
1129 | struct device_node *np; | |
f8a1883a | 1130 | const __be32 *reg; |
e9efed3b NL |
1131 | int id = -1; |
1132 | ||
1133 | np = of_get_cpu_node(cpu, NULL); | |
1134 | if (!np) | |
1135 | goto out; | |
1136 | ||
1137 | reg = of_get_property(np, "reg", NULL); | |
1138 | if (!reg) | |
1139 | goto out; | |
1140 | ||
f8a1883a | 1141 | id = be32_to_cpup(reg); |
e9efed3b NL |
1142 | out: |
1143 | of_node_put(np); | |
1144 | return id; | |
1145 | } | |
f8ab4810 | 1146 | EXPORT_SYMBOL_GPL(cpu_to_core_id); |
e9efed3b | 1147 | |
99d86705 VS |
1148 | /* Helper routines for cpu to core mapping */ |
1149 | int cpu_core_index_of_thread(int cpu) | |
1150 | { | |
1151 | return cpu >> threads_shift; | |
1152 | } | |
1153 | EXPORT_SYMBOL_GPL(cpu_core_index_of_thread); | |
1154 | ||
1155 | int cpu_first_thread_of_core(int core) | |
1156 | { | |
1157 | return core << threads_shift; | |
1158 | } | |
1159 | EXPORT_SYMBOL_GPL(cpu_first_thread_of_core); | |
1160 | ||
104699c0 | 1161 | /* Must be called when no change can occur to cpu_present_mask, |
440a0857 NL |
1162 | * i.e. during cpu online or offline. |
1163 | */ | |
1164 | static struct device_node *cpu_to_l2cache(int cpu) | |
1165 | { | |
1166 | struct device_node *np; | |
b2ea25b9 | 1167 | struct device_node *cache; |
440a0857 NL |
1168 | |
1169 | if (!cpu_present(cpu)) | |
1170 | return NULL; | |
1171 | ||
1172 | np = of_get_cpu_node(cpu, NULL); | |
1173 | if (np == NULL) | |
1174 | return NULL; | |
1175 | ||
b2ea25b9 NL |
1176 | cache = of_find_next_cache_node(np); |
1177 | ||
440a0857 NL |
1178 | of_node_put(np); |
1179 | ||
b2ea25b9 | 1180 | return cache; |
440a0857 | 1181 | } |
1da177e4 | 1182 | |
df52f671 | 1183 | static bool update_mask_by_l2(int cpu, struct cpumask *(*mask_fn)(int)) |
a8a5356c | 1184 | { |
256f2d4b | 1185 | struct device_node *l2_cache, *np; |
e3d8b67e | 1186 | int i; |
256f2d4b | 1187 | |
a8a5356c | 1188 | l2_cache = cpu_to_l2cache(cpu); |
df52f671 OH |
1189 | if (!l2_cache) |
1190 | return false; | |
1191 | ||
1192 | for_each_cpu(i, cpu_online_mask) { | |
1193 | /* | |
1194 | * when updating the marks the current CPU has not been marked | |
1195 | * online, but we need to update the cache masks | |
1196 | */ | |
256f2d4b | 1197 | np = cpu_to_l2cache(i); |
a8a5356c PM |
1198 | if (!np) |
1199 | continue; | |
df52f671 OH |
1200 | |
1201 | if (np == l2_cache) | |
1202 | set_cpus_related(cpu, i, mask_fn); | |
1203 | ||
a8a5356c PM |
1204 | of_node_put(np); |
1205 | } | |
1206 | of_node_put(l2_cache); | |
df52f671 OH |
1207 | |
1208 | return true; | |
1209 | } | |
1210 | ||
1211 | #ifdef CONFIG_HOTPLUG_CPU | |
1212 | static void remove_cpu_from_masks(int cpu) | |
1213 | { | |
1214 | int i; | |
1215 | ||
1216 | /* NB: cpu_core_mask is a superset of the others */ | |
1217 | for_each_cpu(i, cpu_core_mask(cpu)) { | |
1218 | set_cpus_unrelated(cpu, i, cpu_core_mask); | |
2a636a56 | 1219 | set_cpus_unrelated(cpu, i, cpu_l2_cache_mask); |
df52f671 | 1220 | set_cpus_unrelated(cpu, i, cpu_sibling_mask); |
425752c6 GS |
1221 | if (has_big_cores) |
1222 | set_cpus_unrelated(cpu, i, cpu_smallcore_mask); | |
df52f671 OH |
1223 | } |
1224 | } | |
1225 | #endif | |
1226 | ||
425752c6 GS |
1227 | static inline void add_cpu_to_smallcore_masks(int cpu) |
1228 | { | |
1229 | struct cpumask *this_l1_cache_map = per_cpu(cpu_l1_cache_map, cpu); | |
1230 | int i, first_thread = cpu_first_thread_sibling(cpu); | |
1231 | ||
1232 | if (!has_big_cores) | |
1233 | return; | |
1234 | ||
1235 | cpumask_set_cpu(cpu, cpu_smallcore_mask(cpu)); | |
1236 | ||
1237 | for (i = first_thread; i < first_thread + threads_per_core; i++) { | |
1238 | if (cpu_online(i) && cpumask_test_cpu(i, this_l1_cache_map)) | |
1239 | set_cpus_related(i, cpu, cpu_smallcore_mask); | |
1240 | } | |
1241 | } | |
1242 | ||
a05f0e5b SD |
1243 | int get_physical_package_id(int cpu) |
1244 | { | |
1245 | int pkg_id = cpu_to_chip_id(cpu); | |
1246 | ||
a05f0e5b SD |
1247 | /* |
1248 | * If the platform is PowerNV or Guest on KVM, ibm,chip-id is | |
1249 | * defined. Hence we would return the chip-id as the result of | |
1250 | * get_physical_package_id. | |
1251 | */ | |
c72e8da0 ME |
1252 | if (pkg_id == -1 && firmware_has_feature(FW_FEATURE_LPAR) && |
1253 | IS_ENABLED(CONFIG_PPC_SPLPAR)) { | |
a05f0e5b | 1254 | struct device_node *np = of_get_cpu_node(cpu, NULL); |
4b4d181d ME |
1255 | pkg_id = of_node_to_nid(np); |
1256 | of_node_put(np); | |
a05f0e5b | 1257 | } |
a05f0e5b SD |
1258 | |
1259 | return pkg_id; | |
1260 | } | |
1261 | EXPORT_SYMBOL_GPL(get_physical_package_id); | |
1262 | ||
df52f671 OH |
1263 | static void add_cpu_to_masks(int cpu) |
1264 | { | |
1265 | int first_thread = cpu_first_thread_sibling(cpu); | |
a05f0e5b | 1266 | int pkg_id = get_physical_package_id(cpu); |
df52f671 OH |
1267 | int i; |
1268 | ||
1269 | /* | |
1270 | * This CPU will not be in the online mask yet so we need to manually | |
1271 | * add it to it's own thread sibling mask. | |
1272 | */ | |
1273 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); | |
1274 | ||
1275 | for (i = first_thread; i < first_thread + threads_per_core; i++) | |
1276 | if (cpu_online(i)) | |
1277 | set_cpus_related(i, cpu, cpu_sibling_mask); | |
1278 | ||
425752c6 | 1279 | add_cpu_to_smallcore_masks(cpu); |
df52f671 | 1280 | /* |
2a636a56 OH |
1281 | * Copy the thread sibling mask into the cache sibling mask |
1282 | * and mark any CPUs that share an L2 with this CPU. | |
df52f671 OH |
1283 | */ |
1284 | for_each_cpu(i, cpu_sibling_mask(cpu)) | |
2a636a56 OH |
1285 | set_cpus_related(cpu, i, cpu_l2_cache_mask); |
1286 | update_mask_by_l2(cpu, cpu_l2_cache_mask); | |
1287 | ||
1288 | /* | |
1289 | * Copy the cache sibling mask into core sibling mask and mark | |
1290 | * any CPUs on the same chip as this CPU. | |
1291 | */ | |
1292 | for_each_cpu(i, cpu_l2_cache_mask(cpu)) | |
df52f671 OH |
1293 | set_cpus_related(cpu, i, cpu_core_mask); |
1294 | ||
a05f0e5b | 1295 | if (pkg_id == -1) |
df52f671 | 1296 | return; |
df52f671 OH |
1297 | |
1298 | for_each_cpu(i, cpu_online_mask) | |
a05f0e5b | 1299 | if (get_physical_package_id(i) == pkg_id) |
df52f671 | 1300 | set_cpus_related(cpu, i, cpu_core_mask); |
a8a5356c PM |
1301 | } |
1302 | ||
1da177e4 | 1303 | /* Activate a secondary processor. */ |
061d19f2 | 1304 | void start_secondary(void *unused) |
1da177e4 LT |
1305 | { |
1306 | unsigned int cpu = smp_processor_id(); | |
8e8a31d7 | 1307 | struct cpumask *(*sibling_mask)(int) = cpu_sibling_mask; |
1da177e4 | 1308 | |
f1f10076 | 1309 | mmgrab(&init_mm); |
1da177e4 LT |
1310 | current->active_mm = &init_mm; |
1311 | ||
1312 | smp_store_cpu_info(cpu); | |
5ad57078 | 1313 | set_dec(tb_ticks_per_jiffy); |
e4d76e1c | 1314 | preempt_disable(); |
1be6f10f | 1315 | cpu_callin_map[cpu] = 1; |
1da177e4 | 1316 | |
757cbd46 KG |
1317 | if (smp_ops->setup_cpu) |
1318 | smp_ops->setup_cpu(cpu); | |
1da177e4 LT |
1319 | if (smp_ops->take_timebase) |
1320 | smp_ops->take_timebase(); | |
1321 | ||
d831d0b8 TB |
1322 | secondary_cpu_time_init(); |
1323 | ||
aeeafbfa BH |
1324 | #ifdef CONFIG_PPC64 |
1325 | if (system_state == SYSTEM_RUNNING) | |
1326 | vdso_data->processorCount++; | |
18ad51dd AB |
1327 | |
1328 | vdso_getcpu_init(); | |
aeeafbfa | 1329 | #endif |
df52f671 OH |
1330 | /* Update topology CPU masks */ |
1331 | add_cpu_to_masks(cpu); | |
1da177e4 | 1332 | |
8e8a31d7 GS |
1333 | if (has_big_cores) |
1334 | sibling_mask = cpu_smallcore_mask; | |
96d91431 OH |
1335 | /* |
1336 | * Check for any shared caches. Note that this must be done on a | |
1337 | * per-core basis because one core in the pair might be disabled. | |
1338 | */ | |
8e8a31d7 | 1339 | if (!cpumask_equal(cpu_l2_cache_mask(cpu), sibling_mask(cpu))) |
96d91431 OH |
1340 | shared_caches = true; |
1341 | ||
bc3c4327 LZ |
1342 | set_numa_node(numa_cpu_lookup_table[cpu]); |
1343 | set_numa_mem(local_memory_node(numa_cpu_lookup_table[cpu])); | |
1344 | ||
cce606fe LZ |
1345 | smp_wmb(); |
1346 | notify_cpu_starting(cpu); | |
1347 | set_cpu_online(cpu, true); | |
1348 | ||
b6aeddea ME |
1349 | boot_init_stack_canary(); |
1350 | ||
1da177e4 LT |
1351 | local_irq_enable(); |
1352 | ||
d1039786 NR |
1353 | /* We can enable ftrace for secondary cpus now */ |
1354 | this_cpu_enable_ftrace(); | |
1355 | ||
fc6d73d6 | 1356 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
fa3f82c8 BH |
1357 | |
1358 | BUG(); | |
1da177e4 LT |
1359 | } |
1360 | ||
1361 | int setup_profiling_timer(unsigned int multiplier) | |
1362 | { | |
1363 | return 0; | |
1364 | } | |
1365 | ||
6d11b87d TG |
1366 | void __init smp_cpus_done(unsigned int max_cpus) |
1367 | { | |
1368 | /* | |
7b7622bb | 1369 | * We are running pinned to the boot CPU, see rest_init(). |
1da177e4 | 1370 | */ |
757cbd46 | 1371 | if (smp_ops && smp_ops->setup_cpu) |
7b7622bb | 1372 | smp_ops->setup_cpu(boot_cpuid); |
4b703a23 | 1373 | |
d7294445 BH |
1374 | if (smp_ops && smp_ops->bringup_done) |
1375 | smp_ops->bringup_done(); | |
1376 | ||
4b703a23 | 1377 | dump_numa_cpu_topology(); |
d7294445 | 1378 | |
8e8a31d7 GS |
1379 | #ifdef CONFIG_SCHED_SMT |
1380 | if (has_big_cores) { | |
82a7cebd | 1381 | pr_info("Big cores detected but using small core scheduling\n"); |
8e8a31d7 GS |
1382 | powerpc_topology[0].mask = smallcore_smt_mask; |
1383 | } | |
1384 | #endif | |
2ef0ca54 | 1385 | set_sched_topology(powerpc_topology); |
e1f0ece1 MN |
1386 | } |
1387 | ||
1da177e4 LT |
1388 | #ifdef CONFIG_HOTPLUG_CPU |
1389 | int __cpu_disable(void) | |
1390 | { | |
e2075f79 | 1391 | int cpu = smp_processor_id(); |
e2075f79 | 1392 | int err; |
1da177e4 | 1393 | |
e2075f79 NL |
1394 | if (!smp_ops->cpu_disable) |
1395 | return -ENOSYS; | |
1396 | ||
424ef016 NR |
1397 | this_cpu_disable_ftrace(); |
1398 | ||
e2075f79 NL |
1399 | err = smp_ops->cpu_disable(); |
1400 | if (err) | |
1401 | return err; | |
1402 | ||
1403 | /* Update sibling maps */ | |
df52f671 | 1404 | remove_cpu_from_masks(cpu); |
e2075f79 NL |
1405 | |
1406 | return 0; | |
1da177e4 LT |
1407 | } |
1408 | ||
1409 | void __cpu_die(unsigned int cpu) | |
1410 | { | |
1411 | if (smp_ops->cpu_die) | |
1412 | smp_ops->cpu_die(cpu); | |
1413 | } | |
d0174c72 | 1414 | |
abb17f9c MM |
1415 | void cpu_die(void) |
1416 | { | |
424ef016 NR |
1417 | /* |
1418 | * Disable on the down path. This will be re-enabled by | |
1419 | * start_secondary() via start_secondary_resume() below | |
1420 | */ | |
1421 | this_cpu_disable_ftrace(); | |
1422 | ||
abb17f9c MM |
1423 | if (ppc_md.cpu_die) |
1424 | ppc_md.cpu_die(); | |
fa3f82c8 BH |
1425 | |
1426 | /* If we return, we re-enter start_secondary */ | |
1427 | start_secondary_resume(); | |
abb17f9c | 1428 | } |
fa3f82c8 | 1429 | |
1da177e4 | 1430 | #endif |