Commit | Line | Data |
---|---|---|
40ef8cbc PM |
1 | /* |
2 | * | |
3 | * Common boot and setup code. | |
4 | * | |
5 | * Copyright (C) 2001 PPC64 Team, IBM Corp | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
7191b615 | 13 | #define DEBUG |
40ef8cbc | 14 | |
4b16f8e2 | 15 | #include <linux/export.h> |
40ef8cbc PM |
16 | #include <linux/string.h> |
17 | #include <linux/sched.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/reboot.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/initrd.h> | |
40ef8cbc PM |
23 | #include <linux/seq_file.h> |
24 | #include <linux/ioport.h> | |
25 | #include <linux/console.h> | |
26 | #include <linux/utsname.h> | |
27 | #include <linux/tty.h> | |
28 | #include <linux/root_dev.h> | |
29 | #include <linux/notifier.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/unistd.h> | |
32 | #include <linux/serial.h> | |
33 | #include <linux/serial_8250.h> | |
7a0268fa | 34 | #include <linux/bootmem.h> |
12d04eef | 35 | #include <linux/pci.h> |
945feb17 | 36 | #include <linux/lockdep.h> |
95f72d1e | 37 | #include <linux/memblock.h> |
a6146888 | 38 | #include <linux/hugetlb.h> |
a5d86257 | 39 | #include <linux/memory.h> |
a6146888 | 40 | |
40ef8cbc | 41 | #include <asm/io.h> |
0cc4746c | 42 | #include <asm/kdump.h> |
40ef8cbc PM |
43 | #include <asm/prom.h> |
44 | #include <asm/processor.h> | |
45 | #include <asm/pgtable.h> | |
40ef8cbc PM |
46 | #include <asm/smp.h> |
47 | #include <asm/elf.h> | |
48 | #include <asm/machdep.h> | |
49 | #include <asm/paca.h> | |
40ef8cbc PM |
50 | #include <asm/time.h> |
51 | #include <asm/cputable.h> | |
52 | #include <asm/sections.h> | |
53 | #include <asm/btext.h> | |
54 | #include <asm/nvram.h> | |
55 | #include <asm/setup.h> | |
40ef8cbc PM |
56 | #include <asm/rtas.h> |
57 | #include <asm/iommu.h> | |
58 | #include <asm/serial.h> | |
59 | #include <asm/cache.h> | |
60 | #include <asm/page.h> | |
61 | #include <asm/mmu.h> | |
40ef8cbc | 62 | #include <asm/firmware.h> |
f78541dc | 63 | #include <asm/xmon.h> |
dcad47fc | 64 | #include <asm/udbg.h> |
593e537b | 65 | #include <asm/kexec.h> |
25d21ad6 | 66 | #include <asm/mmu_context.h> |
d36b4c4f | 67 | #include <asm/code-patching.h> |
aa04b4cc | 68 | #include <asm/kvm_ppc.h> |
a6146888 | 69 | #include <asm/hugetlb.h> |
4e21b94c | 70 | #include <asm/epapr_hcalls.h> |
40ef8cbc PM |
71 | |
72 | #ifdef DEBUG | |
73 | #define DBG(fmt...) udbg_printf(fmt) | |
74 | #else | |
75 | #define DBG(fmt...) | |
76 | #endif | |
77 | ||
8246aca7 | 78 | int spinning_secondaries; |
40ef8cbc PM |
79 | u64 ppc64_pft_size; |
80 | ||
dabcafd3 OJ |
81 | /* Pick defaults since we might want to patch instructions |
82 | * before we've read this from the device tree. | |
83 | */ | |
84 | struct ppc64_caches ppc64_caches = { | |
5a2fe38d OJ |
85 | .dline_size = 0x40, |
86 | .log_dline_size = 6, | |
87 | .iline_size = 0x40, | |
88 | .log_iline_size = 6 | |
dabcafd3 | 89 | }; |
40ef8cbc PM |
90 | EXPORT_SYMBOL_GPL(ppc64_caches); |
91 | ||
92 | /* | |
93 | * These are used in binfmt_elf.c to put aux entries on the stack | |
94 | * for each elf executable being started. | |
95 | */ | |
96 | int dcache_bsize; | |
97 | int icache_bsize; | |
98 | int ucache_bsize; | |
99 | ||
28efc35f SW |
100 | #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) |
101 | static void setup_tlb_core_data(void) | |
102 | { | |
103 | int cpu; | |
104 | ||
82d86de2 SW |
105 | BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); |
106 | ||
28efc35f SW |
107 | for_each_possible_cpu(cpu) { |
108 | int first = cpu_first_thread_sibling(cpu); | |
109 | ||
110 | paca[cpu].tcd_ptr = &paca[first].tcd; | |
111 | ||
112 | /* | |
113 | * If we have threads, we need either tlbsrx. | |
114 | * or e6500 tablewalk mode, or else TLB handlers | |
115 | * will be racy and could produce duplicate entries. | |
116 | */ | |
117 | if (smt_enabled_at_boot >= 2 && | |
118 | !mmu_has_feature(MMU_FTR_USE_TLBRSRV) && | |
119 | book3e_htw_mode != PPC_HTW_E6500) { | |
120 | /* Should we panic instead? */ | |
121 | WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n", | |
122 | __func__); | |
123 | } | |
124 | } | |
125 | } | |
126 | #else | |
127 | static void setup_tlb_core_data(void) | |
128 | { | |
129 | } | |
130 | #endif | |
131 | ||
40ef8cbc PM |
132 | #ifdef CONFIG_SMP |
133 | ||
954e6da5 | 134 | static char *smt_enabled_cmdline; |
40ef8cbc PM |
135 | |
136 | /* Look for ibm,smt-enabled OF option */ | |
137 | static void check_smt_enabled(void) | |
138 | { | |
139 | struct device_node *dn; | |
a7f67bdf | 140 | const char *smt_option; |
40ef8cbc | 141 | |
954e6da5 NF |
142 | /* Default to enabling all threads */ |
143 | smt_enabled_at_boot = threads_per_core; | |
40ef8cbc | 144 | |
954e6da5 NF |
145 | /* Allow the command line to overrule the OF option */ |
146 | if (smt_enabled_cmdline) { | |
147 | if (!strcmp(smt_enabled_cmdline, "on")) | |
148 | smt_enabled_at_boot = threads_per_core; | |
149 | else if (!strcmp(smt_enabled_cmdline, "off")) | |
150 | smt_enabled_at_boot = 0; | |
151 | else { | |
152 | long smt; | |
153 | int rc; | |
154 | ||
155 | rc = strict_strtol(smt_enabled_cmdline, 10, &smt); | |
156 | if (!rc) | |
157 | smt_enabled_at_boot = | |
158 | min(threads_per_core, (int)smt); | |
159 | } | |
160 | } else { | |
161 | dn = of_find_node_by_path("/options"); | |
162 | if (dn) { | |
163 | smt_option = of_get_property(dn, "ibm,smt-enabled", | |
164 | NULL); | |
165 | ||
166 | if (smt_option) { | |
167 | if (!strcmp(smt_option, "on")) | |
168 | smt_enabled_at_boot = threads_per_core; | |
169 | else if (!strcmp(smt_option, "off")) | |
170 | smt_enabled_at_boot = 0; | |
171 | } | |
172 | ||
173 | of_node_put(dn); | |
174 | } | |
175 | } | |
40ef8cbc PM |
176 | } |
177 | ||
178 | /* Look for smt-enabled= cmdline option */ | |
179 | static int __init early_smt_enabled(char *p) | |
180 | { | |
954e6da5 | 181 | smt_enabled_cmdline = p; |
40ef8cbc PM |
182 | return 0; |
183 | } | |
184 | early_param("smt-enabled", early_smt_enabled); | |
185 | ||
5ad57078 PM |
186 | #else |
187 | #define check_smt_enabled() | |
40ef8cbc PM |
188 | #endif /* CONFIG_SMP */ |
189 | ||
25e13814 ME |
190 | /** Fix up paca fields required for the boot cpu */ |
191 | static void fixup_boot_paca(void) | |
192 | { | |
193 | /* The boot cpu is started */ | |
194 | get_paca()->cpu_start = 1; | |
195 | /* Allow percpu accesses to work until we setup percpu data */ | |
196 | get_paca()->data_offset = 0; | |
197 | } | |
198 | ||
8f619b54 BH |
199 | static void cpu_ready_for_interrupts(void) |
200 | { | |
201 | /* Set IR and DR in PACA MSR */ | |
202 | get_paca()->kernel_msr = MSR_KERNEL; | |
203 | ||
204 | /* Enable AIL if supported */ | |
18aa0da3 PM |
205 | if (cpu_has_feature(CPU_FTR_HVMODE) && |
206 | cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
8f619b54 BH |
207 | unsigned long lpcr = mfspr(SPRN_LPCR); |
208 | mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3); | |
209 | } | |
210 | } | |
211 | ||
40ef8cbc PM |
212 | /* |
213 | * Early initialization entry point. This is called by head.S | |
214 | * with MMU translation disabled. We rely on the "feature" of | |
215 | * the CPU that ignores the top 2 bits of the address in real | |
216 | * mode so we can access kernel globals normally provided we | |
217 | * only toy with things in the RMO region. From here, we do | |
95f72d1e | 218 | * some early parsing of the device-tree to setup out MEMBLOCK |
40ef8cbc PM |
219 | * data structures, and allocate & initialize the hash table |
220 | * and segment tables so we can start running with translation | |
221 | * enabled. | |
222 | * | |
223 | * It is this function which will call the probe() callback of | |
224 | * the various platform types and copy the matching one to the | |
225 | * global ppc_md structure. Your platform can eventually do | |
226 | * some very early initializations from the probe() routine, but | |
227 | * this is not recommended, be very careful as, for example, the | |
228 | * device-tree is not accessible via normal means at this point. | |
229 | */ | |
230 | ||
231 | void __init early_setup(unsigned long dt_ptr) | |
232 | { | |
6a7e4064 GL |
233 | static __initdata struct paca_struct boot_paca; |
234 | ||
24d96495 BH |
235 | /* -------- printk is _NOT_ safe to use here ! ------- */ |
236 | ||
42c4aaad | 237 | /* Identify CPU type */ |
974a76f5 | 238 | identify_cpu(0, mfspr(SPRN_PVR)); |
42c4aaad | 239 | |
33dbcf72 | 240 | /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ |
1426d5a3 ME |
241 | initialise_paca(&boot_paca, 0); |
242 | setup_paca(&boot_paca); | |
25e13814 | 243 | fixup_boot_paca(); |
33dbcf72 | 244 | |
945feb17 BH |
245 | /* Initialize lockdep early or else spinlocks will blow */ |
246 | lockdep_init(); | |
247 | ||
24d96495 BH |
248 | /* -------- printk is now safe to use ------- */ |
249 | ||
f2fd2513 BH |
250 | /* Enable early debugging if any specified (see udbg.h) */ |
251 | udbg_early_init(); | |
252 | ||
e8222502 | 253 | DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); |
40ef8cbc | 254 | |
40ef8cbc | 255 | /* |
3c607ce2 LV |
256 | * Do early initialization using the flattened device |
257 | * tree, such as retrieving the physical memory map or | |
258 | * calculating/retrieving the hash table size. | |
40ef8cbc PM |
259 | */ |
260 | early_init_devtree(__va(dt_ptr)); | |
261 | ||
4e21b94c LT |
262 | epapr_paravirt_early_init(); |
263 | ||
4df20460 | 264 | /* Now we know the logical id of our boot cpu, setup the paca. */ |
1426d5a3 | 265 | setup_paca(&paca[boot_cpuid]); |
25e13814 | 266 | fixup_boot_paca(); |
4df20460 | 267 | |
e8222502 BH |
268 | /* Probe the machine type */ |
269 | probe_machine(); | |
40ef8cbc | 270 | |
47310413 | 271 | setup_kdump_trampoline(); |
0cc4746c | 272 | |
40ef8cbc PM |
273 | DBG("Found, Initializing memory management...\n"); |
274 | ||
757c74d2 BH |
275 | /* Initialize the hash table or TLB handling */ |
276 | early_init_mmu(); | |
40ef8cbc | 277 | |
a944a9c4 BH |
278 | /* |
279 | * At this point, we can let interrupts switch to virtual mode | |
280 | * (the MMU has been setup), so adjust the MSR in the PACA to | |
8f619b54 | 281 | * have IR and DR set and enable AIL if it exists |
a944a9c4 | 282 | */ |
8f619b54 | 283 | cpu_ready_for_interrupts(); |
a944a9c4 BH |
284 | |
285 | /* Reserve large chunks of memory for use by CMA for KVM */ | |
fa61a4e3 AK |
286 | kvm_cma_reserve(); |
287 | ||
a6146888 BB |
288 | /* |
289 | * Reserve any gigantic pages requested on the command line. | |
290 | * memblock needs to have been initialized by the time this is | |
291 | * called since this will reserve memory. | |
292 | */ | |
293 | reserve_hugetlb_gpages(); | |
294 | ||
40ef8cbc | 295 | DBG(" <- early_setup()\n"); |
7191b615 BH |
296 | |
297 | #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX | |
298 | /* | |
299 | * This needs to be done *last* (after the above DBG() even) | |
300 | * | |
301 | * Right after we return from this function, we turn on the MMU | |
302 | * which means the real-mode access trick that btext does will | |
303 | * no longer work, it needs to switch to using a real MMU | |
304 | * mapping. This call will ensure that it does | |
305 | */ | |
306 | btext_map(); | |
307 | #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ | |
40ef8cbc PM |
308 | } |
309 | ||
799d6046 PM |
310 | #ifdef CONFIG_SMP |
311 | void early_setup_secondary(void) | |
312 | { | |
d04c56f7 | 313 | /* Mark interrupts enabled in PACA */ |
757c74d2 | 314 | get_paca()->soft_enabled = 0; |
799d6046 | 315 | |
757c74d2 BH |
316 | /* Initialize the hash table or TLB handling */ |
317 | early_init_mmu_secondary(); | |
a944a9c4 BH |
318 | |
319 | /* | |
320 | * At this point, we can let interrupts switch to virtual mode | |
321 | * (the MMU has been setup), so adjust the MSR in the PACA to | |
322 | * have IR and DR set. | |
323 | */ | |
8f619b54 | 324 | cpu_ready_for_interrupts(); |
799d6046 PM |
325 | } |
326 | ||
327 | #endif /* CONFIG_SMP */ | |
40ef8cbc | 328 | |
b8f51021 ME |
329 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) |
330 | void smp_release_cpus(void) | |
331 | { | |
758438a7 | 332 | unsigned long *ptr; |
9d07bc84 | 333 | int i; |
b8f51021 ME |
334 | |
335 | DBG(" -> smp_release_cpus()\n"); | |
336 | ||
337 | /* All secondary cpus are spinning on a common spinloop, release them | |
338 | * all now so they can start to spin on their individual paca | |
339 | * spinloops. For non SMP kernels, the secondary cpus never get out | |
340 | * of the common spinloop. | |
1f6a93e4 | 341 | */ |
b8f51021 | 342 | |
758438a7 ME |
343 | ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop |
344 | - PHYSICAL_START); | |
2751b628 | 345 | *ptr = ppc_function_entry(generic_secondary_smp_init); |
9d07bc84 BH |
346 | |
347 | /* And wait a bit for them to catch up */ | |
348 | for (i = 0; i < 100000; i++) { | |
349 | mb(); | |
350 | HMT_low(); | |
7ac87abb | 351 | if (spinning_secondaries == 0) |
9d07bc84 BH |
352 | break; |
353 | udelay(1); | |
354 | } | |
7ac87abb | 355 | DBG("spinning_secondaries = %d\n", spinning_secondaries); |
b8f51021 ME |
356 | |
357 | DBG(" <- smp_release_cpus()\n"); | |
358 | } | |
359 | #endif /* CONFIG_SMP || CONFIG_KEXEC */ | |
360 | ||
40ef8cbc | 361 | /* |
799d6046 PM |
362 | * Initialize some remaining members of the ppc64_caches and systemcfg |
363 | * structures | |
40ef8cbc PM |
364 | * (at least until we get rid of them completely). This is mostly some |
365 | * cache informations about the CPU that will be used by cache flush | |
366 | * routines and/or provided to userland | |
367 | */ | |
368 | static void __init initialize_cache_info(void) | |
369 | { | |
370 | struct device_node *np; | |
371 | unsigned long num_cpus = 0; | |
372 | ||
373 | DBG(" -> initialize_cache_info()\n"); | |
374 | ||
94db7c5e | 375 | for_each_node_by_type(np, "cpu") { |
40ef8cbc PM |
376 | num_cpus += 1; |
377 | ||
dfbe93a2 AB |
378 | /* |
379 | * We're assuming *all* of the CPUs have the same | |
40ef8cbc PM |
380 | * d-cache and i-cache sizes... -Peter |
381 | */ | |
dfbe93a2 | 382 | if (num_cpus == 1) { |
7946d5a5 | 383 | const __be32 *sizep, *lsizep; |
40ef8cbc | 384 | u32 size, lsize; |
40ef8cbc PM |
385 | |
386 | size = 0; | |
387 | lsize = cur_cpu_spec->dcache_bsize; | |
e2eb6392 | 388 | sizep = of_get_property(np, "d-cache-size", NULL); |
40ef8cbc | 389 | if (sizep != NULL) |
7946d5a5 | 390 | size = be32_to_cpu(*sizep); |
dfbe93a2 AB |
391 | lsizep = of_get_property(np, "d-cache-block-size", |
392 | NULL); | |
20474abd BH |
393 | /* fallback if block size missing */ |
394 | if (lsizep == NULL) | |
dfbe93a2 AB |
395 | lsizep = of_get_property(np, |
396 | "d-cache-line-size", | |
397 | NULL); | |
40ef8cbc | 398 | if (lsizep != NULL) |
7946d5a5 | 399 | lsize = be32_to_cpu(*lsizep); |
b0d436c7 | 400 | if (sizep == NULL || lsizep == NULL) |
40ef8cbc PM |
401 | DBG("Argh, can't find dcache properties ! " |
402 | "sizep: %p, lsizep: %p\n", sizep, lsizep); | |
403 | ||
a7f290da BH |
404 | ppc64_caches.dsize = size; |
405 | ppc64_caches.dline_size = lsize; | |
40ef8cbc PM |
406 | ppc64_caches.log_dline_size = __ilog2(lsize); |
407 | ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; | |
408 | ||
409 | size = 0; | |
410 | lsize = cur_cpu_spec->icache_bsize; | |
e2eb6392 | 411 | sizep = of_get_property(np, "i-cache-size", NULL); |
40ef8cbc | 412 | if (sizep != NULL) |
7946d5a5 | 413 | size = be32_to_cpu(*sizep); |
dfbe93a2 AB |
414 | lsizep = of_get_property(np, "i-cache-block-size", |
415 | NULL); | |
20474abd | 416 | if (lsizep == NULL) |
dfbe93a2 AB |
417 | lsizep = of_get_property(np, |
418 | "i-cache-line-size", | |
419 | NULL); | |
40ef8cbc | 420 | if (lsizep != NULL) |
7946d5a5 | 421 | lsize = be32_to_cpu(*lsizep); |
b0d436c7 | 422 | if (sizep == NULL || lsizep == NULL) |
40ef8cbc PM |
423 | DBG("Argh, can't find icache properties ! " |
424 | "sizep: %p, lsizep: %p\n", sizep, lsizep); | |
425 | ||
a7f290da BH |
426 | ppc64_caches.isize = size; |
427 | ppc64_caches.iline_size = lsize; | |
40ef8cbc PM |
428 | ppc64_caches.log_iline_size = __ilog2(lsize); |
429 | ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; | |
430 | } | |
431 | } | |
432 | ||
40ef8cbc PM |
433 | DBG(" <- initialize_cache_info()\n"); |
434 | } | |
435 | ||
40ef8cbc PM |
436 | |
437 | /* | |
438 | * Do some initial setup of the system. The parameters are those which | |
439 | * were passed in from the bootloader. | |
440 | */ | |
441 | void __init setup_system(void) | |
442 | { | |
443 | DBG(" -> setup_system()\n"); | |
444 | ||
826ea8f2 TB |
445 | /* Apply the CPUs-specific and firmware specific fixups to kernel |
446 | * text (nop out sections not relevant to this CPU or this firmware) | |
42c4aaad | 447 | */ |
0909c8c2 | 448 | do_feature_fixups(cur_cpu_spec->cpu_features, |
42c4aaad | 449 | &__start___ftr_fixup, &__stop___ftr_fixup); |
7c03d653 BH |
450 | do_feature_fixups(cur_cpu_spec->mmu_features, |
451 | &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); | |
826ea8f2 TB |
452 | do_feature_fixups(powerpc_firmware_features, |
453 | &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); | |
2d1b2027 KG |
454 | do_lwsync_fixups(cur_cpu_spec->cpu_features, |
455 | &__start___lwsync_fixup, &__stop___lwsync_fixup); | |
d715e433 | 456 | do_final_fixups(); |
42c4aaad | 457 | |
40ef8cbc PM |
458 | /* |
459 | * Unflatten the device-tree passed by prom_init or kexec | |
460 | */ | |
461 | unflatten_device_tree(); | |
462 | ||
463 | /* | |
464 | * Fill the ppc64_caches & systemcfg structures with informations | |
0ebfff14 | 465 | * retrieved from the device-tree. |
40ef8cbc PM |
466 | */ |
467 | initialize_cache_info(); | |
468 | ||
469 | #ifdef CONFIG_PPC_RTAS | |
470 | /* | |
471 | * Initialize RTAS if available | |
472 | */ | |
473 | rtas_initialize(); | |
474 | #endif /* CONFIG_PPC_RTAS */ | |
40ef8cbc PM |
475 | |
476 | /* | |
477 | * Check if we have an initrd provided via the device-tree | |
478 | */ | |
479 | check_for_initrd(); | |
40ef8cbc PM |
480 | |
481 | /* | |
482 | * Do some platform specific early initializations, that includes | |
483 | * setting up the hash table pointers. It also sets up some interrupt-mapping | |
484 | * related options that will be used by finish_device_tree() | |
485 | */ | |
57744ea9 GL |
486 | if (ppc_md.init_early) |
487 | ppc_md.init_early(); | |
40ef8cbc | 488 | |
463ce0e1 BH |
489 | /* |
490 | * We can discover serial ports now since the above did setup the | |
491 | * hash table management for us, thus ioremap works. We do that early | |
492 | * so that further code can be debugged | |
493 | */ | |
463ce0e1 | 494 | find_legacy_serial_ports(); |
463ce0e1 | 495 | |
40ef8cbc PM |
496 | /* |
497 | * Register early console | |
498 | */ | |
499 | register_early_udbg_console(); | |
40ef8cbc | 500 | |
47679283 ME |
501 | /* |
502 | * Initialize xmon | |
503 | */ | |
504 | xmon_setup(); | |
480f6f35 | 505 | |
5ad57078 | 506 | smp_setup_cpu_maps(); |
954e6da5 | 507 | check_smt_enabled(); |
28efc35f | 508 | setup_tlb_core_data(); |
40ef8cbc | 509 | |
f018b36f | 510 | #ifdef CONFIG_SMP |
40ef8cbc PM |
511 | /* Release secondary cpus out of their spinloops at 0x60 now that |
512 | * we can map physical -> logical CPU ids | |
513 | */ | |
514 | smp_release_cpus(); | |
f018b36f | 515 | #endif |
40ef8cbc | 516 | |
96b644bd | 517 | printk("Starting Linux PPC64 %s\n", init_utsname()->version); |
40ef8cbc PM |
518 | |
519 | printk("-----------------------------------------------------\n"); | |
fe333321 | 520 | printk("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); |
95f72d1e | 521 | printk("physicalMemorySize = 0x%llx\n", memblock_phys_mem_size()); |
9697add0 AB |
522 | if (ppc64_caches.dline_size != 0x80) |
523 | printk("ppc64_caches.dcache_line_size = 0x%x\n", | |
524 | ppc64_caches.dline_size); | |
525 | if (ppc64_caches.iline_size != 0x80) | |
526 | printk("ppc64_caches.icache_line_size = 0x%x\n", | |
527 | ppc64_caches.iline_size); | |
94491685 | 528 | #ifdef CONFIG_PPC_STD_MMU_64 |
9697add0 AB |
529 | if (htab_address) |
530 | printk("htab_address = 0x%p\n", htab_address); | |
40ef8cbc | 531 | printk("htab_hash_mask = 0x%lx\n", htab_hash_mask); |
94491685 | 532 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
b160544c | 533 | if (PHYSICAL_START > 0) |
e468455e ME |
534 | printk("physical_start = 0x%llx\n", |
535 | (unsigned long long)PHYSICAL_START); | |
40ef8cbc | 536 | printk("-----------------------------------------------------\n"); |
40ef8cbc | 537 | |
40ef8cbc PM |
538 | DBG(" <- setup_system()\n"); |
539 | } | |
540 | ||
40bd587a BH |
541 | /* This returns the limit below which memory accesses to the linear |
542 | * mapping are guarnateed not to cause a TLB or SLB miss. This is | |
543 | * used to allocate interrupt or emergency stacks for which our | |
544 | * exception entry path doesn't deal with being interrupted. | |
545 | */ | |
546 | static u64 safe_stack_limit(void) | |
095c7965 | 547 | { |
40bd587a BH |
548 | #ifdef CONFIG_PPC_BOOK3E |
549 | /* Freescale BookE bolts the entire linear mapping */ | |
550 | if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) | |
551 | return linear_map_top; | |
552 | /* Other BookE, we assume the first GB is bolted */ | |
553 | return 1ul << 30; | |
554 | #else | |
555 | /* BookS, the first segment is bolted */ | |
556 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) | |
095c7965 | 557 | return 1UL << SID_SHIFT_1T; |
095c7965 | 558 | return 1UL << SID_SHIFT; |
40bd587a | 559 | #endif |
095c7965 AB |
560 | } |
561 | ||
40ef8cbc PM |
562 | static void __init irqstack_early_init(void) |
563 | { | |
40bd587a | 564 | u64 limit = safe_stack_limit(); |
40ef8cbc PM |
565 | unsigned int i; |
566 | ||
567 | /* | |
8f4da26e AB |
568 | * Interrupt stacks must be in the first segment since we |
569 | * cannot afford to take SLB misses on them. | |
40ef8cbc | 570 | */ |
0e551954 | 571 | for_each_possible_cpu(i) { |
3c726f8d | 572 | softirq_ctx[i] = (struct thread_info *) |
95f72d1e | 573 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 574 | THREAD_SIZE, limit)); |
3c726f8d | 575 | hardirq_ctx[i] = (struct thread_info *) |
95f72d1e | 576 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 577 | THREAD_SIZE, limit)); |
40ef8cbc PM |
578 | } |
579 | } | |
40ef8cbc | 580 | |
2d27cfd3 BH |
581 | #ifdef CONFIG_PPC_BOOK3E |
582 | static void __init exc_lvl_early_init(void) | |
583 | { | |
584 | unsigned int i; | |
160c7324 | 585 | unsigned long sp; |
2d27cfd3 BH |
586 | |
587 | for_each_possible_cpu(i) { | |
160c7324 TC |
588 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); |
589 | critirq_ctx[i] = (struct thread_info *)__va(sp); | |
590 | paca[i].crit_kstack = __va(sp + THREAD_SIZE); | |
591 | ||
592 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); | |
593 | dbgirq_ctx[i] = (struct thread_info *)__va(sp); | |
594 | paca[i].dbg_kstack = __va(sp + THREAD_SIZE); | |
595 | ||
596 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); | |
597 | mcheckirq_ctx[i] = (struct thread_info *)__va(sp); | |
598 | paca[i].mc_kstack = __va(sp + THREAD_SIZE); | |
2d27cfd3 | 599 | } |
d36b4c4f KG |
600 | |
601 | if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) | |
565c2f24 | 602 | patch_exception(0x040, exc_debug_debug_book3e); |
2d27cfd3 BH |
603 | } |
604 | #else | |
605 | #define exc_lvl_early_init() | |
606 | #endif | |
607 | ||
40ef8cbc PM |
608 | /* |
609 | * Stack space used when we detect a bad kernel stack pointer, and | |
729b0f71 MS |
610 | * early in SMP boots before relocation is enabled. Exclusive emergency |
611 | * stack for machine checks. | |
40ef8cbc PM |
612 | */ |
613 | static void __init emergency_stack_init(void) | |
614 | { | |
095c7965 | 615 | u64 limit; |
40ef8cbc PM |
616 | unsigned int i; |
617 | ||
618 | /* | |
619 | * Emergency stacks must be under 256MB, we cannot afford to take | |
620 | * SLB misses on them. The ABI also requires them to be 128-byte | |
621 | * aligned. | |
622 | * | |
623 | * Since we use these as temporary stacks during secondary CPU | |
624 | * bringup, we need to get at them in real mode. This means they | |
625 | * must also be within the RMO region. | |
626 | */ | |
40bd587a | 627 | limit = min(safe_stack_limit(), ppc64_rma_size); |
40ef8cbc | 628 | |
3243d874 ME |
629 | for_each_possible_cpu(i) { |
630 | unsigned long sp; | |
95f72d1e | 631 | sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); |
3243d874 ME |
632 | sp += THREAD_SIZE; |
633 | paca[i].emergency_sp = __va(sp); | |
729b0f71 MS |
634 | |
635 | #ifdef CONFIG_PPC_BOOK3S_64 | |
636 | /* emergency stack for machine check exception handling. */ | |
637 | sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); | |
638 | sp += THREAD_SIZE; | |
639 | paca[i].mc_emergency_sp = __va(sp); | |
640 | #endif | |
3243d874 | 641 | } |
40ef8cbc PM |
642 | } |
643 | ||
40ef8cbc | 644 | /* |
0f6b77ca AIB |
645 | * Called into from start_kernel this initializes bootmem, which is used |
646 | * to manage page allocation until mem_init is called. | |
40ef8cbc PM |
647 | */ |
648 | void __init setup_arch(char **cmdline_p) | |
649 | { | |
40ef8cbc PM |
650 | ppc64_boot_msg(0x12, "Setup Arch"); |
651 | ||
652 | *cmdline_p = cmd_line; | |
653 | ||
654 | /* | |
655 | * Set cache line size based on type of cpu as a default. | |
656 | * Systems with OF can look in the properties on the cpu node(s) | |
657 | * for a possibly more accurate value. | |
658 | */ | |
659 | dcache_bsize = ppc64_caches.dline_size; | |
660 | icache_bsize = ppc64_caches.iline_size; | |
661 | ||
40ef8cbc | 662 | if (ppc_md.panic) |
7e990266 | 663 | setup_panic(); |
40ef8cbc | 664 | |
4846c5de | 665 | init_mm.start_code = (unsigned long)_stext; |
40ef8cbc PM |
666 | init_mm.end_code = (unsigned long) _etext; |
667 | init_mm.end_data = (unsigned long) _edata; | |
668 | init_mm.brk = klimit; | |
5c1f6ee9 AK |
669 | #ifdef CONFIG_PPC_64K_PAGES |
670 | init_mm.context.pte_frag = NULL; | |
671 | #endif | |
40ef8cbc | 672 | irqstack_early_init(); |
2d27cfd3 | 673 | exc_lvl_early_init(); |
40ef8cbc PM |
674 | emergency_stack_init(); |
675 | ||
94491685 | 676 | #ifdef CONFIG_PPC_STD_MMU_64 |
40ef8cbc | 677 | stabs_alloc(); |
94491685 | 678 | #endif |
40ef8cbc PM |
679 | /* set up the bootmem stuff with available memory */ |
680 | do_init_bootmem(); | |
681 | sparse_init(); | |
682 | ||
0458060c PM |
683 | #ifdef CONFIG_DUMMY_CONSOLE |
684 | conswitchp = &dummy_con; | |
685 | #endif | |
686 | ||
38db7e74 GL |
687 | if (ppc_md.setup_arch) |
688 | ppc_md.setup_arch(); | |
40ef8cbc | 689 | |
40ef8cbc | 690 | paging_init(); |
6f0ef0f5 BH |
691 | |
692 | /* Initialize the MMU context management stuff */ | |
693 | mmu_context_init(); | |
694 | ||
61e2390e MN |
695 | /* Interrupt code needs to be 64K-aligned */ |
696 | if ((unsigned long)_stext & 0xffff) | |
697 | panic("Kernelbase not 64K-aligned (0x%lx)!\n", | |
698 | (unsigned long)_stext); | |
699 | ||
40ef8cbc PM |
700 | ppc64_boot_msg(0x15, "Setup Done"); |
701 | } | |
702 | ||
703 | ||
704 | /* ToDo: do something useful if ppc_md is not yet setup. */ | |
705 | #define PPC64_LINUX_FUNCTION 0x0f000000 | |
706 | #define PPC64_IPL_MESSAGE 0xc0000000 | |
707 | #define PPC64_TERM_MESSAGE 0xb0000000 | |
708 | ||
709 | static void ppc64_do_msg(unsigned int src, const char *msg) | |
710 | { | |
711 | if (ppc_md.progress) { | |
712 | char buf[128]; | |
713 | ||
714 | sprintf(buf, "%08X\n", src); | |
715 | ppc_md.progress(buf, 0); | |
716 | snprintf(buf, 128, "%s", msg); | |
717 | ppc_md.progress(buf, 0); | |
718 | } | |
719 | } | |
720 | ||
721 | /* Print a boot progress message. */ | |
722 | void ppc64_boot_msg(unsigned int src, const char *msg) | |
723 | { | |
724 | ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_IPL_MESSAGE|src, msg); | |
725 | printk("[boot]%04x %s\n", src, msg); | |
726 | } | |
727 | ||
7a0268fa | 728 | #ifdef CONFIG_SMP |
c2a7e818 TH |
729 | #define PCPU_DYN_SIZE () |
730 | ||
731 | static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) | |
7a0268fa | 732 | { |
c2a7e818 TH |
733 | return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, |
734 | __pa(MAX_DMA_ADDRESS)); | |
735 | } | |
7a0268fa | 736 | |
c2a7e818 TH |
737 | static void __init pcpu_fc_free(void *ptr, size_t size) |
738 | { | |
739 | free_bootmem(__pa(ptr), size); | |
740 | } | |
7a0268fa | 741 | |
c2a7e818 TH |
742 | static int pcpu_cpu_distance(unsigned int from, unsigned int to) |
743 | { | |
744 | if (cpu_to_node(from) == cpu_to_node(to)) | |
745 | return LOCAL_DISTANCE; | |
746 | else | |
747 | return REMOTE_DISTANCE; | |
748 | } | |
749 | ||
ae01f84b AB |
750 | unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; |
751 | EXPORT_SYMBOL(__per_cpu_offset); | |
752 | ||
c2a7e818 TH |
753 | void __init setup_per_cpu_areas(void) |
754 | { | |
755 | const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; | |
756 | size_t atom_size; | |
757 | unsigned long delta; | |
758 | unsigned int cpu; | |
759 | int rc; | |
760 | ||
761 | /* | |
762 | * Linear mapping is one of 4K, 1M and 16M. For 4K, no need | |
763 | * to group units. For larger mappings, use 1M atom which | |
764 | * should be large enough to contain a number of units. | |
765 | */ | |
766 | if (mmu_linear_psize == MMU_PAGE_4K) | |
767 | atom_size = PAGE_SIZE; | |
768 | else | |
769 | atom_size = 1 << 20; | |
770 | ||
771 | rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, | |
772 | pcpu_fc_alloc, pcpu_fc_free); | |
773 | if (rc < 0) | |
774 | panic("cannot initialize percpu area (err=%d)", rc); | |
775 | ||
776 | delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; | |
ae01f84b AB |
777 | for_each_possible_cpu(cpu) { |
778 | __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; | |
779 | paca[cpu].data_offset = __per_cpu_offset[cpu]; | |
780 | } | |
7a0268fa AB |
781 | } |
782 | #endif | |
4cb3cee0 | 783 | |
a5d86257 AB |
784 | #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE |
785 | unsigned long memory_block_size_bytes(void) | |
786 | { | |
787 | if (ppc_md.memory_block_size) | |
788 | return ppc_md.memory_block_size(); | |
789 | ||
790 | return MIN_MEMORY_BLOCK_SIZE; | |
791 | } | |
792 | #endif | |
4cb3cee0 | 793 | |
ecd73cc5 | 794 | #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) |
4cb3cee0 BH |
795 | struct ppc_pci_io ppc_pci_io; |
796 | EXPORT_SYMBOL(ppc_pci_io); | |
ecd73cc5 | 797 | #endif |