powerpc: panic if we can't instantiate RTAS
[linux-2.6-block.git] / arch / powerpc / kernel / setup_64.c
CommitLineData
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1/*
2 *
3 * Common boot and setup code.
4 *
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#undef DEBUG
14
4b16f8e2 15#include <linux/export.h>
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16#include <linux/string.h>
17#include <linux/sched.h>
18#include <linux/init.h>
19#include <linux/kernel.h>
20#include <linux/reboot.h>
21#include <linux/delay.h>
22#include <linux/initrd.h>
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23#include <linux/seq_file.h>
24#include <linux/ioport.h>
25#include <linux/console.h>
26#include <linux/utsname.h>
27#include <linux/tty.h>
28#include <linux/root_dev.h>
29#include <linux/notifier.h>
30#include <linux/cpu.h>
31#include <linux/unistd.h>
32#include <linux/serial.h>
33#include <linux/serial_8250.h>
7a0268fa 34#include <linux/bootmem.h>
12d04eef 35#include <linux/pci.h>
945feb17 36#include <linux/lockdep.h>
95f72d1e 37#include <linux/memblock.h>
40ef8cbc 38#include <asm/io.h>
0cc4746c 39#include <asm/kdump.h>
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40#include <asm/prom.h>
41#include <asm/processor.h>
42#include <asm/pgtable.h>
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43#include <asm/smp.h>
44#include <asm/elf.h>
45#include <asm/machdep.h>
46#include <asm/paca.h>
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47#include <asm/time.h>
48#include <asm/cputable.h>
49#include <asm/sections.h>
50#include <asm/btext.h>
51#include <asm/nvram.h>
52#include <asm/setup.h>
53#include <asm/system.h>
54#include <asm/rtas.h>
55#include <asm/iommu.h>
56#include <asm/serial.h>
57#include <asm/cache.h>
58#include <asm/page.h>
59#include <asm/mmu.h>
40ef8cbc 60#include <asm/firmware.h>
f78541dc 61#include <asm/xmon.h>
dcad47fc 62#include <asm/udbg.h>
593e537b 63#include <asm/kexec.h>
25d21ad6 64#include <asm/mmu_context.h>
d36b4c4f 65#include <asm/code-patching.h>
aa04b4cc 66#include <asm/kvm_ppc.h>
40ef8cbc 67
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68#include "setup.h"
69
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70#ifdef DEBUG
71#define DBG(fmt...) udbg_printf(fmt)
72#else
73#define DBG(fmt...)
74#endif
75
40ef8cbc 76int boot_cpuid = 0;
7ac87abb 77int __initdata spinning_secondaries;
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78u64 ppc64_pft_size;
79
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80/* Pick defaults since we might want to patch instructions
81 * before we've read this from the device tree.
82 */
83struct ppc64_caches ppc64_caches = {
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84 .dline_size = 0x40,
85 .log_dline_size = 6,
86 .iline_size = 0x40,
87 .log_iline_size = 6
dabcafd3 88};
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89EXPORT_SYMBOL_GPL(ppc64_caches);
90
91/*
92 * These are used in binfmt_elf.c to put aux entries on the stack
93 * for each elf executable being started.
94 */
95int dcache_bsize;
96int icache_bsize;
97int ucache_bsize;
98
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99#ifdef CONFIG_SMP
100
954e6da5 101static char *smt_enabled_cmdline;
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102
103/* Look for ibm,smt-enabled OF option */
104static void check_smt_enabled(void)
105{
106 struct device_node *dn;
a7f67bdf 107 const char *smt_option;
40ef8cbc 108
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109 /* Default to enabling all threads */
110 smt_enabled_at_boot = threads_per_core;
40ef8cbc 111
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112 /* Allow the command line to overrule the OF option */
113 if (smt_enabled_cmdline) {
114 if (!strcmp(smt_enabled_cmdline, "on"))
115 smt_enabled_at_boot = threads_per_core;
116 else if (!strcmp(smt_enabled_cmdline, "off"))
117 smt_enabled_at_boot = 0;
118 else {
119 long smt;
120 int rc;
121
122 rc = strict_strtol(smt_enabled_cmdline, 10, &smt);
123 if (!rc)
124 smt_enabled_at_boot =
125 min(threads_per_core, (int)smt);
126 }
127 } else {
128 dn = of_find_node_by_path("/options");
129 if (dn) {
130 smt_option = of_get_property(dn, "ibm,smt-enabled",
131 NULL);
132
133 if (smt_option) {
134 if (!strcmp(smt_option, "on"))
135 smt_enabled_at_boot = threads_per_core;
136 else if (!strcmp(smt_option, "off"))
137 smt_enabled_at_boot = 0;
138 }
139
140 of_node_put(dn);
141 }
142 }
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143}
144
145/* Look for smt-enabled= cmdline option */
146static int __init early_smt_enabled(char *p)
147{
954e6da5 148 smt_enabled_cmdline = p;
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149 return 0;
150}
151early_param("smt-enabled", early_smt_enabled);
152
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153#else
154#define check_smt_enabled()
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155#endif /* CONFIG_SMP */
156
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157/*
158 * Early initialization entry point. This is called by head.S
159 * with MMU translation disabled. We rely on the "feature" of
160 * the CPU that ignores the top 2 bits of the address in real
161 * mode so we can access kernel globals normally provided we
162 * only toy with things in the RMO region. From here, we do
95f72d1e 163 * some early parsing of the device-tree to setup out MEMBLOCK
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164 * data structures, and allocate & initialize the hash table
165 * and segment tables so we can start running with translation
166 * enabled.
167 *
168 * It is this function which will call the probe() callback of
169 * the various platform types and copy the matching one to the
170 * global ppc_md structure. Your platform can eventually do
171 * some very early initializations from the probe() routine, but
172 * this is not recommended, be very careful as, for example, the
173 * device-tree is not accessible via normal means at this point.
174 */
175
176void __init early_setup(unsigned long dt_ptr)
177{
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178 /* -------- printk is _NOT_ safe to use here ! ------- */
179
42c4aaad 180 /* Identify CPU type */
974a76f5 181 identify_cpu(0, mfspr(SPRN_PVR));
42c4aaad 182
33dbcf72 183 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
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184 initialise_paca(&boot_paca, 0);
185 setup_paca(&boot_paca);
33dbcf72 186
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187 /* Initialize lockdep early or else spinlocks will blow */
188 lockdep_init();
189
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190 /* -------- printk is now safe to use ------- */
191
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192 /* Enable early debugging if any specified (see udbg.h) */
193 udbg_early_init();
194
e8222502 195 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
40ef8cbc 196
40ef8cbc 197 /*
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198 * Do early initialization using the flattened device
199 * tree, such as retrieving the physical memory map or
200 * calculating/retrieving the hash table size.
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201 */
202 early_init_devtree(__va(dt_ptr));
203
4df20460 204 /* Now we know the logical id of our boot cpu, setup the paca. */
1426d5a3 205 setup_paca(&paca[boot_cpuid]);
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206
207 /* Fix up paca fields required for the boot cpu */
208 get_paca()->cpu_start = 1;
4df20460 209
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210 /* Probe the machine type */
211 probe_machine();
40ef8cbc 212
47310413 213 setup_kdump_trampoline();
0cc4746c 214
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215 DBG("Found, Initializing memory management...\n");
216
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217 /* Initialize the hash table or TLB handling */
218 early_init_mmu();
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219
220 DBG(" <- early_setup()\n");
221}
222
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223#ifdef CONFIG_SMP
224void early_setup_secondary(void)
225{
d04c56f7 226 /* Mark interrupts enabled in PACA */
757c74d2 227 get_paca()->soft_enabled = 0;
799d6046 228
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229 /* Initialize the hash table or TLB handling */
230 early_init_mmu_secondary();
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231}
232
233#endif /* CONFIG_SMP */
40ef8cbc 234
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235#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
236void smp_release_cpus(void)
237{
758438a7 238 unsigned long *ptr;
9d07bc84 239 int i;
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240
241 DBG(" -> smp_release_cpus()\n");
242
243 /* All secondary cpus are spinning on a common spinloop, release them
244 * all now so they can start to spin on their individual paca
245 * spinloops. For non SMP kernels, the secondary cpus never get out
246 * of the common spinloop.
1f6a93e4 247 */
b8f51021 248
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249 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
250 - PHYSICAL_START);
1f6a93e4 251 *ptr = __pa(generic_secondary_smp_init);
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252
253 /* And wait a bit for them to catch up */
254 for (i = 0; i < 100000; i++) {
255 mb();
256 HMT_low();
7ac87abb 257 if (spinning_secondaries == 0)
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258 break;
259 udelay(1);
260 }
7ac87abb 261 DBG("spinning_secondaries = %d\n", spinning_secondaries);
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262
263 DBG(" <- smp_release_cpus()\n");
264}
265#endif /* CONFIG_SMP || CONFIG_KEXEC */
266
40ef8cbc 267/*
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268 * Initialize some remaining members of the ppc64_caches and systemcfg
269 * structures
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270 * (at least until we get rid of them completely). This is mostly some
271 * cache informations about the CPU that will be used by cache flush
272 * routines and/or provided to userland
273 */
274static void __init initialize_cache_info(void)
275{
276 struct device_node *np;
277 unsigned long num_cpus = 0;
278
279 DBG(" -> initialize_cache_info()\n");
280
94db7c5e 281 for_each_node_by_type(np, "cpu") {
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282 num_cpus += 1;
283
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284 /*
285 * We're assuming *all* of the CPUs have the same
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286 * d-cache and i-cache sizes... -Peter
287 */
dfbe93a2 288 if (num_cpus == 1) {
a7f67bdf 289 const u32 *sizep, *lsizep;
40ef8cbc 290 u32 size, lsize;
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291
292 size = 0;
293 lsize = cur_cpu_spec->dcache_bsize;
e2eb6392 294 sizep = of_get_property(np, "d-cache-size", NULL);
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295 if (sizep != NULL)
296 size = *sizep;
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297 lsizep = of_get_property(np, "d-cache-block-size",
298 NULL);
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299 /* fallback if block size missing */
300 if (lsizep == NULL)
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301 lsizep = of_get_property(np,
302 "d-cache-line-size",
303 NULL);
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304 if (lsizep != NULL)
305 lsize = *lsizep;
306 if (sizep == 0 || lsizep == 0)
307 DBG("Argh, can't find dcache properties ! "
308 "sizep: %p, lsizep: %p\n", sizep, lsizep);
309
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310 ppc64_caches.dsize = size;
311 ppc64_caches.dline_size = lsize;
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312 ppc64_caches.log_dline_size = __ilog2(lsize);
313 ppc64_caches.dlines_per_page = PAGE_SIZE / lsize;
314
315 size = 0;
316 lsize = cur_cpu_spec->icache_bsize;
e2eb6392 317 sizep = of_get_property(np, "i-cache-size", NULL);
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318 if (sizep != NULL)
319 size = *sizep;
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320 lsizep = of_get_property(np, "i-cache-block-size",
321 NULL);
20474abd 322 if (lsizep == NULL)
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323 lsizep = of_get_property(np,
324 "i-cache-line-size",
325 NULL);
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326 if (lsizep != NULL)
327 lsize = *lsizep;
328 if (sizep == 0 || lsizep == 0)
329 DBG("Argh, can't find icache properties ! "
330 "sizep: %p, lsizep: %p\n", sizep, lsizep);
331
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332 ppc64_caches.isize = size;
333 ppc64_caches.iline_size = lsize;
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334 ppc64_caches.log_iline_size = __ilog2(lsize);
335 ppc64_caches.ilines_per_page = PAGE_SIZE / lsize;
336 }
337 }
338
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339 DBG(" <- initialize_cache_info()\n");
340}
341
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342
343/*
344 * Do some initial setup of the system. The parameters are those which
345 * were passed in from the bootloader.
346 */
347void __init setup_system(void)
348{
349 DBG(" -> setup_system()\n");
350
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351 /* Apply the CPUs-specific and firmware specific fixups to kernel
352 * text (nop out sections not relevant to this CPU or this firmware)
42c4aaad 353 */
0909c8c2 354 do_feature_fixups(cur_cpu_spec->cpu_features,
42c4aaad 355 &__start___ftr_fixup, &__stop___ftr_fixup);
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356 do_feature_fixups(cur_cpu_spec->mmu_features,
357 &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup);
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358 do_feature_fixups(powerpc_firmware_features,
359 &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup);
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360 do_lwsync_fixups(cur_cpu_spec->cpu_features,
361 &__start___lwsync_fixup, &__stop___lwsync_fixup);
42c4aaad 362
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363 /*
364 * Unflatten the device-tree passed by prom_init or kexec
365 */
366 unflatten_device_tree();
367
368 /*
369 * Fill the ppc64_caches & systemcfg structures with informations
0ebfff14 370 * retrieved from the device-tree.
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371 */
372 initialize_cache_info();
373
374#ifdef CONFIG_PPC_RTAS
375 /*
376 * Initialize RTAS if available
377 */
378 rtas_initialize();
379#endif /* CONFIG_PPC_RTAS */
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380
381 /*
382 * Check if we have an initrd provided via the device-tree
383 */
384 check_for_initrd();
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385
386 /*
387 * Do some platform specific early initializations, that includes
388 * setting up the hash table pointers. It also sets up some interrupt-mapping
389 * related options that will be used by finish_device_tree()
390 */
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391 if (ppc_md.init_early)
392 ppc_md.init_early();
40ef8cbc 393
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394 /*
395 * We can discover serial ports now since the above did setup the
396 * hash table management for us, thus ioremap works. We do that early
397 * so that further code can be debugged
398 */
463ce0e1 399 find_legacy_serial_ports();
463ce0e1 400
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401 /*
402 * Register early console
403 */
404 register_early_udbg_console();
40ef8cbc 405
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406 /*
407 * Initialize xmon
408 */
409 xmon_setup();
480f6f35 410
5ad57078 411 smp_setup_cpu_maps();
954e6da5 412 check_smt_enabled();
40ef8cbc 413
f018b36f 414#ifdef CONFIG_SMP
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415 /* Release secondary cpus out of their spinloops at 0x60 now that
416 * we can map physical -> logical CPU ids
417 */
418 smp_release_cpus();
f018b36f 419#endif
40ef8cbc 420
96b644bd 421 printk("Starting Linux PPC64 %s\n", init_utsname()->version);
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422
423 printk("-----------------------------------------------------\n");
fe333321 424 printk("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
95f72d1e 425 printk("physicalMemorySize = 0x%llx\n", memblock_phys_mem_size());
9697add0
AB
426 if (ppc64_caches.dline_size != 0x80)
427 printk("ppc64_caches.dcache_line_size = 0x%x\n",
428 ppc64_caches.dline_size);
429 if (ppc64_caches.iline_size != 0x80)
430 printk("ppc64_caches.icache_line_size = 0x%x\n",
431 ppc64_caches.iline_size);
94491685 432#ifdef CONFIG_PPC_STD_MMU_64
9697add0
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433 if (htab_address)
434 printk("htab_address = 0x%p\n", htab_address);
40ef8cbc 435 printk("htab_hash_mask = 0x%lx\n", htab_hash_mask);
94491685 436#endif /* CONFIG_PPC_STD_MMU_64 */
b160544c 437 if (PHYSICAL_START > 0)
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438 printk("physical_start = 0x%llx\n",
439 (unsigned long long)PHYSICAL_START);
40ef8cbc 440 printk("-----------------------------------------------------\n");
40ef8cbc 441
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442 DBG(" <- setup_system()\n");
443}
444
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445/* This returns the limit below which memory accesses to the linear
446 * mapping are guarnateed not to cause a TLB or SLB miss. This is
447 * used to allocate interrupt or emergency stacks for which our
448 * exception entry path doesn't deal with being interrupted.
449 */
450static u64 safe_stack_limit(void)
095c7965 451{
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BH
452#ifdef CONFIG_PPC_BOOK3E
453 /* Freescale BookE bolts the entire linear mapping */
454 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
455 return linear_map_top;
456 /* Other BookE, we assume the first GB is bolted */
457 return 1ul << 30;
458#else
459 /* BookS, the first segment is bolted */
460 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
095c7965 461 return 1UL << SID_SHIFT_1T;
095c7965 462 return 1UL << SID_SHIFT;
40bd587a 463#endif
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464}
465
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466static void __init irqstack_early_init(void)
467{
40bd587a 468 u64 limit = safe_stack_limit();
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469 unsigned int i;
470
471 /*
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472 * Interrupt stacks must be in the first segment since we
473 * cannot afford to take SLB misses on them.
40ef8cbc 474 */
0e551954 475 for_each_possible_cpu(i) {
3c726f8d 476 softirq_ctx[i] = (struct thread_info *)
95f72d1e 477 __va(memblock_alloc_base(THREAD_SIZE,
095c7965 478 THREAD_SIZE, limit));
3c726f8d 479 hardirq_ctx[i] = (struct thread_info *)
95f72d1e 480 __va(memblock_alloc_base(THREAD_SIZE,
095c7965 481 THREAD_SIZE, limit));
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482 }
483}
40ef8cbc 484
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485#ifdef CONFIG_PPC_BOOK3E
486static void __init exc_lvl_early_init(void)
487{
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488 extern unsigned int interrupt_base_book3e;
489 extern unsigned int exc_debug_debug_book3e;
490
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491 unsigned int i;
492
493 for_each_possible_cpu(i) {
494 critirq_ctx[i] = (struct thread_info *)
95f72d1e 495 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
2d27cfd3 496 dbgirq_ctx[i] = (struct thread_info *)
95f72d1e 497 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
2d27cfd3 498 mcheckirq_ctx[i] = (struct thread_info *)
95f72d1e 499 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
2d27cfd3 500 }
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501
502 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
503 patch_branch(&interrupt_base_book3e + (0x040 / 4) + 1,
504 (unsigned long)&exc_debug_debug_book3e, 0);
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505}
506#else
507#define exc_lvl_early_init()
508#endif
509
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510/*
511 * Stack space used when we detect a bad kernel stack pointer, and
512 * early in SMP boots before relocation is enabled.
513 */
514static void __init emergency_stack_init(void)
515{
095c7965 516 u64 limit;
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517 unsigned int i;
518
519 /*
520 * Emergency stacks must be under 256MB, we cannot afford to take
521 * SLB misses on them. The ABI also requires them to be 128-byte
522 * aligned.
523 *
524 * Since we use these as temporary stacks during secondary CPU
525 * bringup, we need to get at them in real mode. This means they
526 * must also be within the RMO region.
527 */
40bd587a 528 limit = min(safe_stack_limit(), ppc64_rma_size);
40ef8cbc 529
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530 for_each_possible_cpu(i) {
531 unsigned long sp;
95f72d1e 532 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
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533 sp += THREAD_SIZE;
534 paca[i].emergency_sp = __va(sp);
535 }
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536}
537
40ef8cbc 538/*
0f6b77ca
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539 * Called into from start_kernel this initializes bootmem, which is used
540 * to manage page allocation until mem_init is called.
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541 */
542void __init setup_arch(char **cmdline_p)
543{
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544 ppc64_boot_msg(0x12, "Setup Arch");
545
546 *cmdline_p = cmd_line;
547
548 /*
549 * Set cache line size based on type of cpu as a default.
550 * Systems with OF can look in the properties on the cpu node(s)
551 * for a possibly more accurate value.
552 */
553 dcache_bsize = ppc64_caches.dline_size;
554 icache_bsize = ppc64_caches.iline_size;
555
556 /* reboot on panic */
557 panic_timeout = 180;
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558
559 if (ppc_md.panic)
7e990266 560 setup_panic();
40ef8cbc 561
4846c5de 562 init_mm.start_code = (unsigned long)_stext;
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563 init_mm.end_code = (unsigned long) _etext;
564 init_mm.end_data = (unsigned long) _edata;
565 init_mm.brk = klimit;
566
567 irqstack_early_init();
2d27cfd3 568 exc_lvl_early_init();
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569 emergency_stack_init();
570
94491685 571#ifdef CONFIG_PPC_STD_MMU_64
40ef8cbc 572 stabs_alloc();
94491685 573#endif
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574 /* set up the bootmem stuff with available memory */
575 do_init_bootmem();
576 sparse_init();
577
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578#ifdef CONFIG_DUMMY_CONSOLE
579 conswitchp = &dummy_con;
580#endif
581
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582 if (ppc_md.setup_arch)
583 ppc_md.setup_arch();
40ef8cbc 584
40ef8cbc 585 paging_init();
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586
587 /* Initialize the MMU context management stuff */
588 mmu_context_init();
589
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590 kvm_rma_init();
591
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592 ppc64_boot_msg(0x15, "Setup Done");
593}
594
595
596/* ToDo: do something useful if ppc_md is not yet setup. */
597#define PPC64_LINUX_FUNCTION 0x0f000000
598#define PPC64_IPL_MESSAGE 0xc0000000
599#define PPC64_TERM_MESSAGE 0xb0000000
600
601static void ppc64_do_msg(unsigned int src, const char *msg)
602{
603 if (ppc_md.progress) {
604 char buf[128];
605
606 sprintf(buf, "%08X\n", src);
607 ppc_md.progress(buf, 0);
608 snprintf(buf, 128, "%s", msg);
609 ppc_md.progress(buf, 0);
610 }
611}
612
613/* Print a boot progress message. */
614void ppc64_boot_msg(unsigned int src, const char *msg)
615{
616 ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_IPL_MESSAGE|src, msg);
617 printk("[boot]%04x %s\n", src, msg);
618}
619
7a0268fa 620#ifdef CONFIG_SMP
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621#define PCPU_DYN_SIZE ()
622
623static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
7a0268fa 624{
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625 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align,
626 __pa(MAX_DMA_ADDRESS));
627}
7a0268fa 628
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629static void __init pcpu_fc_free(void *ptr, size_t size)
630{
631 free_bootmem(__pa(ptr), size);
632}
7a0268fa 633
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634static int pcpu_cpu_distance(unsigned int from, unsigned int to)
635{
636 if (cpu_to_node(from) == cpu_to_node(to))
637 return LOCAL_DISTANCE;
638 else
639 return REMOTE_DISTANCE;
640}
641
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642unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
643EXPORT_SYMBOL(__per_cpu_offset);
644
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645void __init setup_per_cpu_areas(void)
646{
647 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
648 size_t atom_size;
649 unsigned long delta;
650 unsigned int cpu;
651 int rc;
652
653 /*
654 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
655 * to group units. For larger mappings, use 1M atom which
656 * should be large enough to contain a number of units.
657 */
658 if (mmu_linear_psize == MMU_PAGE_4K)
659 atom_size = PAGE_SIZE;
660 else
661 atom_size = 1 << 20;
662
663 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
664 pcpu_fc_alloc, pcpu_fc_free);
665 if (rc < 0)
666 panic("cannot initialize percpu area (err=%d)", rc);
667
668 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
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669 for_each_possible_cpu(cpu) {
670 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
671 paca[cpu].data_offset = __per_cpu_offset[cpu];
672 }
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673}
674#endif
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675
676
677#ifdef CONFIG_PPC_INDIRECT_IO
678struct ppc_pci_io ppc_pci_io;
679EXPORT_SYMBOL(ppc_pci_io);
680#endif /* CONFIG_PPC_INDIRECT_IO */
681