Commit | Line | Data |
---|---|---|
40ef8cbc PM |
1 | /* |
2 | * | |
3 | * Common boot and setup code. | |
4 | * | |
5 | * Copyright (C) 2001 PPC64 Team, IBM Corp | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
7191b615 | 13 | #define DEBUG |
40ef8cbc | 14 | |
4b16f8e2 | 15 | #include <linux/export.h> |
40ef8cbc PM |
16 | #include <linux/string.h> |
17 | #include <linux/sched.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/reboot.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/initrd.h> | |
40ef8cbc PM |
23 | #include <linux/seq_file.h> |
24 | #include <linux/ioport.h> | |
25 | #include <linux/console.h> | |
26 | #include <linux/utsname.h> | |
27 | #include <linux/tty.h> | |
28 | #include <linux/root_dev.h> | |
29 | #include <linux/notifier.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/unistd.h> | |
32 | #include <linux/serial.h> | |
33 | #include <linux/serial_8250.h> | |
7a0268fa | 34 | #include <linux/bootmem.h> |
12d04eef | 35 | #include <linux/pci.h> |
945feb17 | 36 | #include <linux/lockdep.h> |
95f72d1e | 37 | #include <linux/memblock.h> |
a6146888 | 38 | #include <linux/hugetlb.h> |
a5d86257 | 39 | #include <linux/memory.h> |
c54b2bf1 | 40 | #include <linux/nmi.h> |
a6146888 | 41 | |
40ef8cbc | 42 | #include <asm/io.h> |
0cc4746c | 43 | #include <asm/kdump.h> |
40ef8cbc PM |
44 | #include <asm/prom.h> |
45 | #include <asm/processor.h> | |
46 | #include <asm/pgtable.h> | |
40ef8cbc PM |
47 | #include <asm/smp.h> |
48 | #include <asm/elf.h> | |
49 | #include <asm/machdep.h> | |
50 | #include <asm/paca.h> | |
40ef8cbc PM |
51 | #include <asm/time.h> |
52 | #include <asm/cputable.h> | |
53 | #include <asm/sections.h> | |
54 | #include <asm/btext.h> | |
55 | #include <asm/nvram.h> | |
56 | #include <asm/setup.h> | |
40ef8cbc PM |
57 | #include <asm/rtas.h> |
58 | #include <asm/iommu.h> | |
59 | #include <asm/serial.h> | |
60 | #include <asm/cache.h> | |
61 | #include <asm/page.h> | |
62 | #include <asm/mmu.h> | |
40ef8cbc | 63 | #include <asm/firmware.h> |
f78541dc | 64 | #include <asm/xmon.h> |
dcad47fc | 65 | #include <asm/udbg.h> |
593e537b | 66 | #include <asm/kexec.h> |
25d21ad6 | 67 | #include <asm/mmu_context.h> |
d36b4c4f | 68 | #include <asm/code-patching.h> |
aa04b4cc | 69 | #include <asm/kvm_ppc.h> |
a6146888 | 70 | #include <asm/hugetlb.h> |
4e21b94c | 71 | #include <asm/epapr_hcalls.h> |
40ef8cbc PM |
72 | |
73 | #ifdef DEBUG | |
74 | #define DBG(fmt...) udbg_printf(fmt) | |
75 | #else | |
76 | #define DBG(fmt...) | |
77 | #endif | |
78 | ||
8246aca7 | 79 | int spinning_secondaries; |
40ef8cbc PM |
80 | u64 ppc64_pft_size; |
81 | ||
dabcafd3 OJ |
82 | /* Pick defaults since we might want to patch instructions |
83 | * before we've read this from the device tree. | |
84 | */ | |
85 | struct ppc64_caches ppc64_caches = { | |
5a2fe38d OJ |
86 | .dline_size = 0x40, |
87 | .log_dline_size = 6, | |
88 | .iline_size = 0x40, | |
89 | .log_iline_size = 6 | |
dabcafd3 | 90 | }; |
40ef8cbc PM |
91 | EXPORT_SYMBOL_GPL(ppc64_caches); |
92 | ||
93 | /* | |
94 | * These are used in binfmt_elf.c to put aux entries on the stack | |
95 | * for each elf executable being started. | |
96 | */ | |
97 | int dcache_bsize; | |
98 | int icache_bsize; | |
99 | int ucache_bsize; | |
100 | ||
28efc35f SW |
101 | #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) |
102 | static void setup_tlb_core_data(void) | |
103 | { | |
104 | int cpu; | |
105 | ||
82d86de2 SW |
106 | BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); |
107 | ||
28efc35f SW |
108 | for_each_possible_cpu(cpu) { |
109 | int first = cpu_first_thread_sibling(cpu); | |
110 | ||
111 | paca[cpu].tcd_ptr = &paca[first].tcd; | |
112 | ||
113 | /* | |
114 | * If we have threads, we need either tlbsrx. | |
115 | * or e6500 tablewalk mode, or else TLB handlers | |
116 | * will be racy and could produce duplicate entries. | |
117 | */ | |
118 | if (smt_enabled_at_boot >= 2 && | |
119 | !mmu_has_feature(MMU_FTR_USE_TLBRSRV) && | |
120 | book3e_htw_mode != PPC_HTW_E6500) { | |
121 | /* Should we panic instead? */ | |
122 | WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n", | |
123 | __func__); | |
124 | } | |
125 | } | |
126 | } | |
127 | #else | |
128 | static void setup_tlb_core_data(void) | |
129 | { | |
130 | } | |
131 | #endif | |
132 | ||
40ef8cbc PM |
133 | #ifdef CONFIG_SMP |
134 | ||
954e6da5 | 135 | static char *smt_enabled_cmdline; |
40ef8cbc PM |
136 | |
137 | /* Look for ibm,smt-enabled OF option */ | |
138 | static void check_smt_enabled(void) | |
139 | { | |
140 | struct device_node *dn; | |
a7f67bdf | 141 | const char *smt_option; |
40ef8cbc | 142 | |
954e6da5 NF |
143 | /* Default to enabling all threads */ |
144 | smt_enabled_at_boot = threads_per_core; | |
40ef8cbc | 145 | |
954e6da5 NF |
146 | /* Allow the command line to overrule the OF option */ |
147 | if (smt_enabled_cmdline) { | |
148 | if (!strcmp(smt_enabled_cmdline, "on")) | |
149 | smt_enabled_at_boot = threads_per_core; | |
150 | else if (!strcmp(smt_enabled_cmdline, "off")) | |
151 | smt_enabled_at_boot = 0; | |
152 | else { | |
1618bd53 | 153 | int smt; |
954e6da5 NF |
154 | int rc; |
155 | ||
1618bd53 | 156 | rc = kstrtoint(smt_enabled_cmdline, 10, &smt); |
954e6da5 NF |
157 | if (!rc) |
158 | smt_enabled_at_boot = | |
1618bd53 | 159 | min(threads_per_core, smt); |
954e6da5 NF |
160 | } |
161 | } else { | |
162 | dn = of_find_node_by_path("/options"); | |
163 | if (dn) { | |
164 | smt_option = of_get_property(dn, "ibm,smt-enabled", | |
165 | NULL); | |
166 | ||
167 | if (smt_option) { | |
168 | if (!strcmp(smt_option, "on")) | |
169 | smt_enabled_at_boot = threads_per_core; | |
170 | else if (!strcmp(smt_option, "off")) | |
171 | smt_enabled_at_boot = 0; | |
172 | } | |
173 | ||
174 | of_node_put(dn); | |
175 | } | |
176 | } | |
40ef8cbc PM |
177 | } |
178 | ||
179 | /* Look for smt-enabled= cmdline option */ | |
180 | static int __init early_smt_enabled(char *p) | |
181 | { | |
954e6da5 | 182 | smt_enabled_cmdline = p; |
40ef8cbc PM |
183 | return 0; |
184 | } | |
185 | early_param("smt-enabled", early_smt_enabled); | |
186 | ||
5ad57078 PM |
187 | #else |
188 | #define check_smt_enabled() | |
40ef8cbc PM |
189 | #endif /* CONFIG_SMP */ |
190 | ||
25e13814 ME |
191 | /** Fix up paca fields required for the boot cpu */ |
192 | static void fixup_boot_paca(void) | |
193 | { | |
194 | /* The boot cpu is started */ | |
195 | get_paca()->cpu_start = 1; | |
196 | /* Allow percpu accesses to work until we setup percpu data */ | |
197 | get_paca()->data_offset = 0; | |
198 | } | |
199 | ||
8f619b54 BH |
200 | static void cpu_ready_for_interrupts(void) |
201 | { | |
202 | /* Set IR and DR in PACA MSR */ | |
203 | get_paca()->kernel_msr = MSR_KERNEL; | |
204 | ||
633440f1 ME |
205 | /* |
206 | * Enable AIL if supported, and we are in hypervisor mode. If we are | |
207 | * not in hypervisor mode, we enable relocation-on interrupts later | |
208 | * in pSeries_setup_arch() using the H_SET_MODE hcall. | |
209 | */ | |
18aa0da3 PM |
210 | if (cpu_has_feature(CPU_FTR_HVMODE) && |
211 | cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
8f619b54 BH |
212 | unsigned long lpcr = mfspr(SPRN_LPCR); |
213 | mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3); | |
214 | } | |
215 | } | |
216 | ||
40ef8cbc PM |
217 | /* |
218 | * Early initialization entry point. This is called by head.S | |
219 | * with MMU translation disabled. We rely on the "feature" of | |
220 | * the CPU that ignores the top 2 bits of the address in real | |
221 | * mode so we can access kernel globals normally provided we | |
222 | * only toy with things in the RMO region. From here, we do | |
95f72d1e | 223 | * some early parsing of the device-tree to setup out MEMBLOCK |
40ef8cbc PM |
224 | * data structures, and allocate & initialize the hash table |
225 | * and segment tables so we can start running with translation | |
226 | * enabled. | |
227 | * | |
228 | * It is this function which will call the probe() callback of | |
229 | * the various platform types and copy the matching one to the | |
230 | * global ppc_md structure. Your platform can eventually do | |
231 | * some very early initializations from the probe() routine, but | |
232 | * this is not recommended, be very careful as, for example, the | |
233 | * device-tree is not accessible via normal means at this point. | |
234 | */ | |
235 | ||
236 | void __init early_setup(unsigned long dt_ptr) | |
237 | { | |
6a7e4064 GL |
238 | static __initdata struct paca_struct boot_paca; |
239 | ||
24d96495 BH |
240 | /* -------- printk is _NOT_ safe to use here ! ------- */ |
241 | ||
42c4aaad | 242 | /* Identify CPU type */ |
974a76f5 | 243 | identify_cpu(0, mfspr(SPRN_PVR)); |
42c4aaad | 244 | |
33dbcf72 | 245 | /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ |
1426d5a3 ME |
246 | initialise_paca(&boot_paca, 0); |
247 | setup_paca(&boot_paca); | |
25e13814 | 248 | fixup_boot_paca(); |
33dbcf72 | 249 | |
945feb17 BH |
250 | /* Initialize lockdep early or else spinlocks will blow */ |
251 | lockdep_init(); | |
252 | ||
24d96495 BH |
253 | /* -------- printk is now safe to use ------- */ |
254 | ||
f2fd2513 BH |
255 | /* Enable early debugging if any specified (see udbg.h) */ |
256 | udbg_early_init(); | |
257 | ||
e8222502 | 258 | DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); |
40ef8cbc | 259 | |
40ef8cbc | 260 | /* |
3c607ce2 LV |
261 | * Do early initialization using the flattened device |
262 | * tree, such as retrieving the physical memory map or | |
263 | * calculating/retrieving the hash table size. | |
40ef8cbc PM |
264 | */ |
265 | early_init_devtree(__va(dt_ptr)); | |
266 | ||
4e21b94c LT |
267 | epapr_paravirt_early_init(); |
268 | ||
4df20460 | 269 | /* Now we know the logical id of our boot cpu, setup the paca. */ |
1426d5a3 | 270 | setup_paca(&paca[boot_cpuid]); |
25e13814 | 271 | fixup_boot_paca(); |
4df20460 | 272 | |
e8222502 BH |
273 | /* Probe the machine type */ |
274 | probe_machine(); | |
40ef8cbc | 275 | |
47310413 | 276 | setup_kdump_trampoline(); |
0cc4746c | 277 | |
40ef8cbc PM |
278 | DBG("Found, Initializing memory management...\n"); |
279 | ||
757c74d2 BH |
280 | /* Initialize the hash table or TLB handling */ |
281 | early_init_mmu(); | |
40ef8cbc | 282 | |
a944a9c4 BH |
283 | /* |
284 | * At this point, we can let interrupts switch to virtual mode | |
285 | * (the MMU has been setup), so adjust the MSR in the PACA to | |
8f619b54 | 286 | * have IR and DR set and enable AIL if it exists |
a944a9c4 | 287 | */ |
8f619b54 | 288 | cpu_ready_for_interrupts(); |
a944a9c4 BH |
289 | |
290 | /* Reserve large chunks of memory for use by CMA for KVM */ | |
fa61a4e3 AK |
291 | kvm_cma_reserve(); |
292 | ||
a6146888 BB |
293 | /* |
294 | * Reserve any gigantic pages requested on the command line. | |
295 | * memblock needs to have been initialized by the time this is | |
296 | * called since this will reserve memory. | |
297 | */ | |
298 | reserve_hugetlb_gpages(); | |
299 | ||
40ef8cbc | 300 | DBG(" <- early_setup()\n"); |
7191b615 BH |
301 | |
302 | #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX | |
303 | /* | |
304 | * This needs to be done *last* (after the above DBG() even) | |
305 | * | |
306 | * Right after we return from this function, we turn on the MMU | |
307 | * which means the real-mode access trick that btext does will | |
308 | * no longer work, it needs to switch to using a real MMU | |
309 | * mapping. This call will ensure that it does | |
310 | */ | |
311 | btext_map(); | |
312 | #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ | |
40ef8cbc PM |
313 | } |
314 | ||
799d6046 PM |
315 | #ifdef CONFIG_SMP |
316 | void early_setup_secondary(void) | |
317 | { | |
d04c56f7 | 318 | /* Mark interrupts enabled in PACA */ |
757c74d2 | 319 | get_paca()->soft_enabled = 0; |
799d6046 | 320 | |
757c74d2 BH |
321 | /* Initialize the hash table or TLB handling */ |
322 | early_init_mmu_secondary(); | |
a944a9c4 BH |
323 | |
324 | /* | |
325 | * At this point, we can let interrupts switch to virtual mode | |
326 | * (the MMU has been setup), so adjust the MSR in the PACA to | |
327 | * have IR and DR set. | |
328 | */ | |
8f619b54 | 329 | cpu_ready_for_interrupts(); |
799d6046 PM |
330 | } |
331 | ||
332 | #endif /* CONFIG_SMP */ | |
40ef8cbc | 333 | |
b8f51021 ME |
334 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) |
335 | void smp_release_cpus(void) | |
336 | { | |
758438a7 | 337 | unsigned long *ptr; |
9d07bc84 | 338 | int i; |
b8f51021 ME |
339 | |
340 | DBG(" -> smp_release_cpus()\n"); | |
341 | ||
342 | /* All secondary cpus are spinning on a common spinloop, release them | |
343 | * all now so they can start to spin on their individual paca | |
344 | * spinloops. For non SMP kernels, the secondary cpus never get out | |
345 | * of the common spinloop. | |
1f6a93e4 | 346 | */ |
b8f51021 | 347 | |
758438a7 ME |
348 | ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop |
349 | - PHYSICAL_START); | |
2751b628 | 350 | *ptr = ppc_function_entry(generic_secondary_smp_init); |
9d07bc84 BH |
351 | |
352 | /* And wait a bit for them to catch up */ | |
353 | for (i = 0; i < 100000; i++) { | |
354 | mb(); | |
355 | HMT_low(); | |
7ac87abb | 356 | if (spinning_secondaries == 0) |
9d07bc84 BH |
357 | break; |
358 | udelay(1); | |
359 | } | |
7ac87abb | 360 | DBG("spinning_secondaries = %d\n", spinning_secondaries); |
b8f51021 ME |
361 | |
362 | DBG(" <- smp_release_cpus()\n"); | |
363 | } | |
364 | #endif /* CONFIG_SMP || CONFIG_KEXEC */ | |
365 | ||
40ef8cbc | 366 | /* |
799d6046 PM |
367 | * Initialize some remaining members of the ppc64_caches and systemcfg |
368 | * structures | |
40ef8cbc PM |
369 | * (at least until we get rid of them completely). This is mostly some |
370 | * cache informations about the CPU that will be used by cache flush | |
371 | * routines and/or provided to userland | |
372 | */ | |
373 | static void __init initialize_cache_info(void) | |
374 | { | |
375 | struct device_node *np; | |
376 | unsigned long num_cpus = 0; | |
377 | ||
378 | DBG(" -> initialize_cache_info()\n"); | |
379 | ||
94db7c5e | 380 | for_each_node_by_type(np, "cpu") { |
40ef8cbc PM |
381 | num_cpus += 1; |
382 | ||
dfbe93a2 AB |
383 | /* |
384 | * We're assuming *all* of the CPUs have the same | |
40ef8cbc PM |
385 | * d-cache and i-cache sizes... -Peter |
386 | */ | |
dfbe93a2 | 387 | if (num_cpus == 1) { |
7946d5a5 | 388 | const __be32 *sizep, *lsizep; |
40ef8cbc | 389 | u32 size, lsize; |
40ef8cbc PM |
390 | |
391 | size = 0; | |
392 | lsize = cur_cpu_spec->dcache_bsize; | |
e2eb6392 | 393 | sizep = of_get_property(np, "d-cache-size", NULL); |
40ef8cbc | 394 | if (sizep != NULL) |
7946d5a5 | 395 | size = be32_to_cpu(*sizep); |
dfbe93a2 AB |
396 | lsizep = of_get_property(np, "d-cache-block-size", |
397 | NULL); | |
20474abd BH |
398 | /* fallback if block size missing */ |
399 | if (lsizep == NULL) | |
dfbe93a2 AB |
400 | lsizep = of_get_property(np, |
401 | "d-cache-line-size", | |
402 | NULL); | |
40ef8cbc | 403 | if (lsizep != NULL) |
7946d5a5 | 404 | lsize = be32_to_cpu(*lsizep); |
b0d436c7 | 405 | if (sizep == NULL || lsizep == NULL) |
40ef8cbc PM |
406 | DBG("Argh, can't find dcache properties ! " |
407 | "sizep: %p, lsizep: %p\n", sizep, lsizep); | |
408 | ||
a7f290da BH |
409 | ppc64_caches.dsize = size; |
410 | ppc64_caches.dline_size = lsize; | |
40ef8cbc PM |
411 | ppc64_caches.log_dline_size = __ilog2(lsize); |
412 | ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; | |
413 | ||
414 | size = 0; | |
415 | lsize = cur_cpu_spec->icache_bsize; | |
e2eb6392 | 416 | sizep = of_get_property(np, "i-cache-size", NULL); |
40ef8cbc | 417 | if (sizep != NULL) |
7946d5a5 | 418 | size = be32_to_cpu(*sizep); |
dfbe93a2 AB |
419 | lsizep = of_get_property(np, "i-cache-block-size", |
420 | NULL); | |
20474abd | 421 | if (lsizep == NULL) |
dfbe93a2 AB |
422 | lsizep = of_get_property(np, |
423 | "i-cache-line-size", | |
424 | NULL); | |
40ef8cbc | 425 | if (lsizep != NULL) |
7946d5a5 | 426 | lsize = be32_to_cpu(*lsizep); |
b0d436c7 | 427 | if (sizep == NULL || lsizep == NULL) |
40ef8cbc PM |
428 | DBG("Argh, can't find icache properties ! " |
429 | "sizep: %p, lsizep: %p\n", sizep, lsizep); | |
430 | ||
a7f290da BH |
431 | ppc64_caches.isize = size; |
432 | ppc64_caches.iline_size = lsize; | |
40ef8cbc PM |
433 | ppc64_caches.log_iline_size = __ilog2(lsize); |
434 | ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; | |
435 | } | |
436 | } | |
437 | ||
40ef8cbc PM |
438 | DBG(" <- initialize_cache_info()\n"); |
439 | } | |
440 | ||
40ef8cbc PM |
441 | |
442 | /* | |
443 | * Do some initial setup of the system. The parameters are those which | |
444 | * were passed in from the bootloader. | |
445 | */ | |
446 | void __init setup_system(void) | |
447 | { | |
448 | DBG(" -> setup_system()\n"); | |
449 | ||
826ea8f2 TB |
450 | /* Apply the CPUs-specific and firmware specific fixups to kernel |
451 | * text (nop out sections not relevant to this CPU or this firmware) | |
42c4aaad | 452 | */ |
0909c8c2 | 453 | do_feature_fixups(cur_cpu_spec->cpu_features, |
42c4aaad | 454 | &__start___ftr_fixup, &__stop___ftr_fixup); |
7c03d653 BH |
455 | do_feature_fixups(cur_cpu_spec->mmu_features, |
456 | &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); | |
826ea8f2 TB |
457 | do_feature_fixups(powerpc_firmware_features, |
458 | &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); | |
2d1b2027 KG |
459 | do_lwsync_fixups(cur_cpu_spec->cpu_features, |
460 | &__start___lwsync_fixup, &__stop___lwsync_fixup); | |
d715e433 | 461 | do_final_fixups(); |
42c4aaad | 462 | |
40ef8cbc PM |
463 | /* |
464 | * Unflatten the device-tree passed by prom_init or kexec | |
465 | */ | |
466 | unflatten_device_tree(); | |
467 | ||
468 | /* | |
469 | * Fill the ppc64_caches & systemcfg structures with informations | |
0ebfff14 | 470 | * retrieved from the device-tree. |
40ef8cbc PM |
471 | */ |
472 | initialize_cache_info(); | |
473 | ||
474 | #ifdef CONFIG_PPC_RTAS | |
475 | /* | |
476 | * Initialize RTAS if available | |
477 | */ | |
478 | rtas_initialize(); | |
479 | #endif /* CONFIG_PPC_RTAS */ | |
40ef8cbc PM |
480 | |
481 | /* | |
482 | * Check if we have an initrd provided via the device-tree | |
483 | */ | |
484 | check_for_initrd(); | |
40ef8cbc PM |
485 | |
486 | /* | |
487 | * Do some platform specific early initializations, that includes | |
488 | * setting up the hash table pointers. It also sets up some interrupt-mapping | |
489 | * related options that will be used by finish_device_tree() | |
490 | */ | |
57744ea9 GL |
491 | if (ppc_md.init_early) |
492 | ppc_md.init_early(); | |
40ef8cbc | 493 | |
463ce0e1 BH |
494 | /* |
495 | * We can discover serial ports now since the above did setup the | |
496 | * hash table management for us, thus ioremap works. We do that early | |
497 | * so that further code can be debugged | |
498 | */ | |
463ce0e1 | 499 | find_legacy_serial_ports(); |
463ce0e1 | 500 | |
40ef8cbc PM |
501 | /* |
502 | * Register early console | |
503 | */ | |
504 | register_early_udbg_console(); | |
40ef8cbc | 505 | |
47679283 ME |
506 | /* |
507 | * Initialize xmon | |
508 | */ | |
509 | xmon_setup(); | |
480f6f35 | 510 | |
5ad57078 | 511 | smp_setup_cpu_maps(); |
954e6da5 | 512 | check_smt_enabled(); |
28efc35f | 513 | setup_tlb_core_data(); |
40ef8cbc | 514 | |
e16c8765 AF |
515 | /* |
516 | * Freescale Book3e parts spin in a loop provided by firmware, | |
517 | * so smp_release_cpus() does nothing for them | |
518 | */ | |
519 | #if defined(CONFIG_SMP) && !defined(CONFIG_PPC_FSL_BOOK3E) | |
40ef8cbc PM |
520 | /* Release secondary cpus out of their spinloops at 0x60 now that |
521 | * we can map physical -> logical CPU ids | |
522 | */ | |
523 | smp_release_cpus(); | |
f018b36f | 524 | #endif |
40ef8cbc | 525 | |
5c0aebf6 ME |
526 | pr_info("Starting Linux %s %s\n", init_utsname()->machine, |
527 | init_utsname()->version); | |
40ef8cbc | 528 | |
2c186e05 AB |
529 | pr_info("-----------------------------------------------------\n"); |
530 | pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); | |
531 | pr_info("phys_mem_size = 0x%llx\n", memblock_phys_mem_size()); | |
bdce97e9 | 532 | |
9697add0 | 533 | if (ppc64_caches.dline_size != 0x80) |
2c186e05 | 534 | pr_info("dcache_line_size = 0x%x\n", ppc64_caches.dline_size); |
9697add0 | 535 | if (ppc64_caches.iline_size != 0x80) |
2c186e05 | 536 | pr_info("icache_line_size = 0x%x\n", ppc64_caches.iline_size); |
bdce97e9 | 537 | |
2c186e05 AB |
538 | pr_info("cpu_features = 0x%016lx\n", cur_cpu_spec->cpu_features); |
539 | pr_info(" possible = 0x%016lx\n", CPU_FTRS_POSSIBLE); | |
540 | pr_info(" always = 0x%016lx\n", CPU_FTRS_ALWAYS); | |
541 | pr_info("cpu_user_features = 0x%08x 0x%08x\n", cur_cpu_spec->cpu_user_features, | |
87d99c0e | 542 | cur_cpu_spec->cpu_user_features2); |
2c186e05 AB |
543 | pr_info("mmu_features = 0x%08x\n", cur_cpu_spec->mmu_features); |
544 | pr_info("firmware_features = 0x%016lx\n", powerpc_firmware_features); | |
87d99c0e | 545 | |
94491685 | 546 | #ifdef CONFIG_PPC_STD_MMU_64 |
9697add0 | 547 | if (htab_address) |
2c186e05 | 548 | pr_info("htab_address = 0x%p\n", htab_address); |
bdce97e9 | 549 | |
2c186e05 | 550 | pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask); |
bdce97e9 ME |
551 | #endif |
552 | ||
b160544c | 553 | if (PHYSICAL_START > 0) |
2c186e05 | 554 | pr_info("physical_start = 0x%llx\n", |
e468455e | 555 | (unsigned long long)PHYSICAL_START); |
2c186e05 | 556 | pr_info("-----------------------------------------------------\n"); |
40ef8cbc | 557 | |
40ef8cbc PM |
558 | DBG(" <- setup_system()\n"); |
559 | } | |
560 | ||
40bd587a BH |
561 | /* This returns the limit below which memory accesses to the linear |
562 | * mapping are guarnateed not to cause a TLB or SLB miss. This is | |
563 | * used to allocate interrupt or emergency stacks for which our | |
564 | * exception entry path doesn't deal with being interrupted. | |
565 | */ | |
566 | static u64 safe_stack_limit(void) | |
095c7965 | 567 | { |
40bd587a BH |
568 | #ifdef CONFIG_PPC_BOOK3E |
569 | /* Freescale BookE bolts the entire linear mapping */ | |
570 | if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) | |
571 | return linear_map_top; | |
572 | /* Other BookE, we assume the first GB is bolted */ | |
573 | return 1ul << 30; | |
574 | #else | |
575 | /* BookS, the first segment is bolted */ | |
576 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) | |
095c7965 | 577 | return 1UL << SID_SHIFT_1T; |
095c7965 | 578 | return 1UL << SID_SHIFT; |
40bd587a | 579 | #endif |
095c7965 AB |
580 | } |
581 | ||
40ef8cbc PM |
582 | static void __init irqstack_early_init(void) |
583 | { | |
40bd587a | 584 | u64 limit = safe_stack_limit(); |
40ef8cbc PM |
585 | unsigned int i; |
586 | ||
587 | /* | |
8f4da26e AB |
588 | * Interrupt stacks must be in the first segment since we |
589 | * cannot afford to take SLB misses on them. | |
40ef8cbc | 590 | */ |
0e551954 | 591 | for_each_possible_cpu(i) { |
3c726f8d | 592 | softirq_ctx[i] = (struct thread_info *) |
95f72d1e | 593 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 594 | THREAD_SIZE, limit)); |
3c726f8d | 595 | hardirq_ctx[i] = (struct thread_info *) |
95f72d1e | 596 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 597 | THREAD_SIZE, limit)); |
40ef8cbc PM |
598 | } |
599 | } | |
40ef8cbc | 600 | |
2d27cfd3 BH |
601 | #ifdef CONFIG_PPC_BOOK3E |
602 | static void __init exc_lvl_early_init(void) | |
603 | { | |
604 | unsigned int i; | |
160c7324 | 605 | unsigned long sp; |
2d27cfd3 BH |
606 | |
607 | for_each_possible_cpu(i) { | |
160c7324 TC |
608 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); |
609 | critirq_ctx[i] = (struct thread_info *)__va(sp); | |
610 | paca[i].crit_kstack = __va(sp + THREAD_SIZE); | |
611 | ||
612 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); | |
613 | dbgirq_ctx[i] = (struct thread_info *)__va(sp); | |
614 | paca[i].dbg_kstack = __va(sp + THREAD_SIZE); | |
615 | ||
616 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); | |
617 | mcheckirq_ctx[i] = (struct thread_info *)__va(sp); | |
618 | paca[i].mc_kstack = __va(sp + THREAD_SIZE); | |
2d27cfd3 | 619 | } |
d36b4c4f KG |
620 | |
621 | if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) | |
565c2f24 | 622 | patch_exception(0x040, exc_debug_debug_book3e); |
2d27cfd3 BH |
623 | } |
624 | #else | |
625 | #define exc_lvl_early_init() | |
626 | #endif | |
627 | ||
40ef8cbc PM |
628 | /* |
629 | * Stack space used when we detect a bad kernel stack pointer, and | |
729b0f71 MS |
630 | * early in SMP boots before relocation is enabled. Exclusive emergency |
631 | * stack for machine checks. | |
40ef8cbc PM |
632 | */ |
633 | static void __init emergency_stack_init(void) | |
634 | { | |
095c7965 | 635 | u64 limit; |
40ef8cbc PM |
636 | unsigned int i; |
637 | ||
638 | /* | |
639 | * Emergency stacks must be under 256MB, we cannot afford to take | |
640 | * SLB misses on them. The ABI also requires them to be 128-byte | |
641 | * aligned. | |
642 | * | |
643 | * Since we use these as temporary stacks during secondary CPU | |
644 | * bringup, we need to get at them in real mode. This means they | |
645 | * must also be within the RMO region. | |
646 | */ | |
40bd587a | 647 | limit = min(safe_stack_limit(), ppc64_rma_size); |
40ef8cbc | 648 | |
3243d874 ME |
649 | for_each_possible_cpu(i) { |
650 | unsigned long sp; | |
95f72d1e | 651 | sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); |
3243d874 ME |
652 | sp += THREAD_SIZE; |
653 | paca[i].emergency_sp = __va(sp); | |
729b0f71 MS |
654 | |
655 | #ifdef CONFIG_PPC_BOOK3S_64 | |
656 | /* emergency stack for machine check exception handling. */ | |
657 | sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); | |
658 | sp += THREAD_SIZE; | |
659 | paca[i].mc_emergency_sp = __va(sp); | |
660 | #endif | |
3243d874 | 661 | } |
40ef8cbc PM |
662 | } |
663 | ||
40ef8cbc | 664 | /* |
e39f223f | 665 | * Called into from start_kernel this initializes memblock, which is used |
0f6b77ca | 666 | * to manage page allocation until mem_init is called. |
40ef8cbc PM |
667 | */ |
668 | void __init setup_arch(char **cmdline_p) | |
669 | { | |
3e47d147 | 670 | *cmdline_p = boot_command_line; |
40ef8cbc PM |
671 | |
672 | /* | |
673 | * Set cache line size based on type of cpu as a default. | |
674 | * Systems with OF can look in the properties on the cpu node(s) | |
675 | * for a possibly more accurate value. | |
676 | */ | |
677 | dcache_bsize = ppc64_caches.dline_size; | |
678 | icache_bsize = ppc64_caches.iline_size; | |
679 | ||
40ef8cbc | 680 | if (ppc_md.panic) |
7e990266 | 681 | setup_panic(); |
40ef8cbc | 682 | |
4846c5de | 683 | init_mm.start_code = (unsigned long)_stext; |
40ef8cbc PM |
684 | init_mm.end_code = (unsigned long) _etext; |
685 | init_mm.end_data = (unsigned long) _edata; | |
686 | init_mm.brk = klimit; | |
5c1f6ee9 AK |
687 | #ifdef CONFIG_PPC_64K_PAGES |
688 | init_mm.context.pte_frag = NULL; | |
689 | #endif | |
40ef8cbc | 690 | irqstack_early_init(); |
2d27cfd3 | 691 | exc_lvl_early_init(); |
40ef8cbc PM |
692 | emergency_stack_init(); |
693 | ||
10239733 | 694 | initmem_init(); |
40ef8cbc | 695 | |
0458060c PM |
696 | #ifdef CONFIG_DUMMY_CONSOLE |
697 | conswitchp = &dummy_con; | |
698 | #endif | |
699 | ||
38db7e74 GL |
700 | if (ppc_md.setup_arch) |
701 | ppc_md.setup_arch(); | |
40ef8cbc | 702 | |
40ef8cbc | 703 | paging_init(); |
6f0ef0f5 BH |
704 | |
705 | /* Initialize the MMU context management stuff */ | |
706 | mmu_context_init(); | |
707 | ||
61e2390e MN |
708 | /* Interrupt code needs to be 64K-aligned */ |
709 | if ((unsigned long)_stext & 0xffff) | |
710 | panic("Kernelbase not 64K-aligned (0x%lx)!\n", | |
711 | (unsigned long)_stext); | |
40ef8cbc PM |
712 | } |
713 | ||
7a0268fa | 714 | #ifdef CONFIG_SMP |
c2a7e818 TH |
715 | #define PCPU_DYN_SIZE () |
716 | ||
717 | static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) | |
7a0268fa | 718 | { |
c2a7e818 TH |
719 | return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, |
720 | __pa(MAX_DMA_ADDRESS)); | |
721 | } | |
7a0268fa | 722 | |
c2a7e818 TH |
723 | static void __init pcpu_fc_free(void *ptr, size_t size) |
724 | { | |
725 | free_bootmem(__pa(ptr), size); | |
726 | } | |
7a0268fa | 727 | |
c2a7e818 TH |
728 | static int pcpu_cpu_distance(unsigned int from, unsigned int to) |
729 | { | |
730 | if (cpu_to_node(from) == cpu_to_node(to)) | |
731 | return LOCAL_DISTANCE; | |
732 | else | |
733 | return REMOTE_DISTANCE; | |
734 | } | |
735 | ||
ae01f84b AB |
736 | unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; |
737 | EXPORT_SYMBOL(__per_cpu_offset); | |
738 | ||
c2a7e818 TH |
739 | void __init setup_per_cpu_areas(void) |
740 | { | |
741 | const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; | |
742 | size_t atom_size; | |
743 | unsigned long delta; | |
744 | unsigned int cpu; | |
745 | int rc; | |
746 | ||
747 | /* | |
748 | * Linear mapping is one of 4K, 1M and 16M. For 4K, no need | |
749 | * to group units. For larger mappings, use 1M atom which | |
750 | * should be large enough to contain a number of units. | |
751 | */ | |
752 | if (mmu_linear_psize == MMU_PAGE_4K) | |
753 | atom_size = PAGE_SIZE; | |
754 | else | |
755 | atom_size = 1 << 20; | |
756 | ||
757 | rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, | |
758 | pcpu_fc_alloc, pcpu_fc_free); | |
759 | if (rc < 0) | |
760 | panic("cannot initialize percpu area (err=%d)", rc); | |
761 | ||
762 | delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; | |
ae01f84b AB |
763 | for_each_possible_cpu(cpu) { |
764 | __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; | |
765 | paca[cpu].data_offset = __per_cpu_offset[cpu]; | |
766 | } | |
7a0268fa AB |
767 | } |
768 | #endif | |
4cb3cee0 | 769 | |
a5d86257 AB |
770 | #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE |
771 | unsigned long memory_block_size_bytes(void) | |
772 | { | |
773 | if (ppc_md.memory_block_size) | |
774 | return ppc_md.memory_block_size(); | |
775 | ||
776 | return MIN_MEMORY_BLOCK_SIZE; | |
777 | } | |
778 | #endif | |
4cb3cee0 | 779 | |
ecd73cc5 | 780 | #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) |
4cb3cee0 BH |
781 | struct ppc_pci_io ppc_pci_io; |
782 | EXPORT_SYMBOL(ppc_pci_io); | |
ecd73cc5 | 783 | #endif |
c54b2bf1 AB |
784 | |
785 | #ifdef CONFIG_HARDLOCKUP_DETECTOR | |
786 | u64 hw_nmi_get_sample_period(int watchdog_thresh) | |
787 | { | |
788 | return ppc_proc_freq * watchdog_thresh; | |
789 | } | |
790 | ||
791 | /* | |
792 | * The hardlockup detector breaks PMU event based branches and is likely | |
793 | * to get false positives in KVM guests, so disable it by default. | |
794 | */ | |
795 | static int __init disable_hardlockup_detector(void) | |
796 | { | |
d19d5efd | 797 | hardlockup_detector_disable(); |
c54b2bf1 AB |
798 | |
799 | return 0; | |
800 | } | |
801 | early_initcall(disable_hardlockup_detector); | |
802 | #endif |