Commit | Line | Data |
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40ef8cbc PM |
1 | /* |
2 | * | |
3 | * Common boot and setup code. | |
4 | * | |
5 | * Copyright (C) 2001 PPC64 Team, IBM Corp | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
7191b615 | 13 | #define DEBUG |
40ef8cbc | 14 | |
4b16f8e2 | 15 | #include <linux/export.h> |
40ef8cbc PM |
16 | #include <linux/string.h> |
17 | #include <linux/sched.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/reboot.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/initrd.h> | |
40ef8cbc PM |
23 | #include <linux/seq_file.h> |
24 | #include <linux/ioport.h> | |
25 | #include <linux/console.h> | |
26 | #include <linux/utsname.h> | |
27 | #include <linux/tty.h> | |
28 | #include <linux/root_dev.h> | |
29 | #include <linux/notifier.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/unistd.h> | |
32 | #include <linux/serial.h> | |
33 | #include <linux/serial_8250.h> | |
7a0268fa | 34 | #include <linux/bootmem.h> |
12d04eef | 35 | #include <linux/pci.h> |
945feb17 | 36 | #include <linux/lockdep.h> |
95f72d1e | 37 | #include <linux/memblock.h> |
a5d86257 | 38 | #include <linux/memory.h> |
c54b2bf1 | 39 | #include <linux/nmi.h> |
a6146888 | 40 | |
40ef8cbc | 41 | #include <asm/io.h> |
0cc4746c | 42 | #include <asm/kdump.h> |
40ef8cbc PM |
43 | #include <asm/prom.h> |
44 | #include <asm/processor.h> | |
45 | #include <asm/pgtable.h> | |
40ef8cbc PM |
46 | #include <asm/smp.h> |
47 | #include <asm/elf.h> | |
48 | #include <asm/machdep.h> | |
49 | #include <asm/paca.h> | |
40ef8cbc PM |
50 | #include <asm/time.h> |
51 | #include <asm/cputable.h> | |
52 | #include <asm/sections.h> | |
53 | #include <asm/btext.h> | |
54 | #include <asm/nvram.h> | |
55 | #include <asm/setup.h> | |
40ef8cbc PM |
56 | #include <asm/rtas.h> |
57 | #include <asm/iommu.h> | |
58 | #include <asm/serial.h> | |
59 | #include <asm/cache.h> | |
60 | #include <asm/page.h> | |
61 | #include <asm/mmu.h> | |
40ef8cbc | 62 | #include <asm/firmware.h> |
f78541dc | 63 | #include <asm/xmon.h> |
dcad47fc | 64 | #include <asm/udbg.h> |
593e537b | 65 | #include <asm/kexec.h> |
d36b4c4f | 66 | #include <asm/code-patching.h> |
5d31a96e | 67 | #include <asm/livepatch.h> |
d3cbff1b | 68 | #include <asm/opal.h> |
b1923caa | 69 | #include <asm/cputhreads.h> |
40ef8cbc PM |
70 | |
71 | #ifdef DEBUG | |
72 | #define DBG(fmt...) udbg_printf(fmt) | |
73 | #else | |
74 | #define DBG(fmt...) | |
75 | #endif | |
76 | ||
8246aca7 | 77 | int spinning_secondaries; |
40ef8cbc PM |
78 | u64 ppc64_pft_size; |
79 | ||
dabcafd3 | 80 | struct ppc64_caches ppc64_caches = { |
e2827fe5 BH |
81 | .l1d = { |
82 | .block_size = 0x40, | |
83 | .log_block_size = 6, | |
84 | }, | |
85 | .l1i = { | |
86 | .block_size = 0x40, | |
87 | .log_block_size = 6 | |
88 | }, | |
dabcafd3 | 89 | }; |
40ef8cbc PM |
90 | EXPORT_SYMBOL_GPL(ppc64_caches); |
91 | ||
28efc35f | 92 | #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) |
b1923caa | 93 | void __init setup_tlb_core_data(void) |
28efc35f SW |
94 | { |
95 | int cpu; | |
96 | ||
82d86de2 SW |
97 | BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); |
98 | ||
28efc35f SW |
99 | for_each_possible_cpu(cpu) { |
100 | int first = cpu_first_thread_sibling(cpu); | |
101 | ||
d9e1831a SW |
102 | /* |
103 | * If we boot via kdump on a non-primary thread, | |
104 | * make sure we point at the thread that actually | |
105 | * set up this TLB. | |
106 | */ | |
107 | if (cpu_first_thread_sibling(boot_cpuid) == first) | |
108 | first = boot_cpuid; | |
109 | ||
28efc35f SW |
110 | paca[cpu].tcd_ptr = &paca[first].tcd; |
111 | ||
112 | /* | |
113 | * If we have threads, we need either tlbsrx. | |
114 | * or e6500 tablewalk mode, or else TLB handlers | |
115 | * will be racy and could produce duplicate entries. | |
0d2b5cdc | 116 | * Should we panic instead? |
28efc35f | 117 | */ |
0d2b5cdc ME |
118 | WARN_ONCE(smt_enabled_at_boot >= 2 && |
119 | !mmu_has_feature(MMU_FTR_USE_TLBRSRV) && | |
120 | book3e_htw_mode != PPC_HTW_E6500, | |
121 | "%s: unsupported MMU configuration\n", __func__); | |
28efc35f SW |
122 | } |
123 | } | |
28efc35f SW |
124 | #endif |
125 | ||
40ef8cbc PM |
126 | #ifdef CONFIG_SMP |
127 | ||
954e6da5 | 128 | static char *smt_enabled_cmdline; |
40ef8cbc PM |
129 | |
130 | /* Look for ibm,smt-enabled OF option */ | |
b1923caa | 131 | void __init check_smt_enabled(void) |
40ef8cbc PM |
132 | { |
133 | struct device_node *dn; | |
a7f67bdf | 134 | const char *smt_option; |
40ef8cbc | 135 | |
954e6da5 NF |
136 | /* Default to enabling all threads */ |
137 | smt_enabled_at_boot = threads_per_core; | |
40ef8cbc | 138 | |
954e6da5 NF |
139 | /* Allow the command line to overrule the OF option */ |
140 | if (smt_enabled_cmdline) { | |
141 | if (!strcmp(smt_enabled_cmdline, "on")) | |
142 | smt_enabled_at_boot = threads_per_core; | |
143 | else if (!strcmp(smt_enabled_cmdline, "off")) | |
144 | smt_enabled_at_boot = 0; | |
145 | else { | |
1618bd53 | 146 | int smt; |
954e6da5 NF |
147 | int rc; |
148 | ||
1618bd53 | 149 | rc = kstrtoint(smt_enabled_cmdline, 10, &smt); |
954e6da5 NF |
150 | if (!rc) |
151 | smt_enabled_at_boot = | |
1618bd53 | 152 | min(threads_per_core, smt); |
954e6da5 NF |
153 | } |
154 | } else { | |
155 | dn = of_find_node_by_path("/options"); | |
156 | if (dn) { | |
157 | smt_option = of_get_property(dn, "ibm,smt-enabled", | |
158 | NULL); | |
159 | ||
160 | if (smt_option) { | |
161 | if (!strcmp(smt_option, "on")) | |
162 | smt_enabled_at_boot = threads_per_core; | |
163 | else if (!strcmp(smt_option, "off")) | |
164 | smt_enabled_at_boot = 0; | |
165 | } | |
166 | ||
167 | of_node_put(dn); | |
168 | } | |
169 | } | |
40ef8cbc PM |
170 | } |
171 | ||
172 | /* Look for smt-enabled= cmdline option */ | |
173 | static int __init early_smt_enabled(char *p) | |
174 | { | |
954e6da5 | 175 | smt_enabled_cmdline = p; |
40ef8cbc PM |
176 | return 0; |
177 | } | |
178 | early_param("smt-enabled", early_smt_enabled); | |
179 | ||
40ef8cbc PM |
180 | #endif /* CONFIG_SMP */ |
181 | ||
25e13814 | 182 | /** Fix up paca fields required for the boot cpu */ |
009776ba | 183 | static void __init fixup_boot_paca(void) |
25e13814 ME |
184 | { |
185 | /* The boot cpu is started */ | |
186 | get_paca()->cpu_start = 1; | |
187 | /* Allow percpu accesses to work until we setup percpu data */ | |
188 | get_paca()->data_offset = 0; | |
189 | } | |
190 | ||
009776ba | 191 | static void __init configure_exceptions(void) |
8f619b54 | 192 | { |
633440f1 | 193 | /* |
d3cbff1b BH |
194 | * Setup the trampolines from the lowmem exception vectors |
195 | * to the kdump kernel when not using a relocatable kernel. | |
633440f1 | 196 | */ |
d3cbff1b BH |
197 | setup_kdump_trampoline(); |
198 | ||
199 | /* Under a PAPR hypervisor, we need hypercalls */ | |
200 | if (firmware_has_feature(FW_FEATURE_SET_MODE)) { | |
201 | /* Enable AIL if possible */ | |
202 | pseries_enable_reloc_on_exc(); | |
203 | ||
204 | /* | |
205 | * Tell the hypervisor that we want our exceptions to | |
206 | * be taken in little endian mode. | |
207 | * | |
208 | * We don't call this for big endian as our calling convention | |
209 | * makes us always enter in BE, and the call may fail under | |
210 | * some circumstances with kdump. | |
211 | */ | |
212 | #ifdef __LITTLE_ENDIAN__ | |
213 | pseries_little_endian_exceptions(); | |
214 | #endif | |
215 | } else { | |
216 | /* Set endian mode using OPAL */ | |
217 | if (firmware_has_feature(FW_FEATURE_OPAL)) | |
218 | opal_configure_cores(); | |
219 | ||
c0a36013 | 220 | /* AIL on native is done in cpu_ready_for_interrupts() */ |
8f619b54 BH |
221 | } |
222 | } | |
223 | ||
d3cbff1b BH |
224 | static void cpu_ready_for_interrupts(void) |
225 | { | |
c0a36013 BH |
226 | /* |
227 | * Enable AIL if supported, and we are in hypervisor mode. This | |
228 | * is called once for every processor. | |
229 | * | |
230 | * If we are not in hypervisor mode the job is done once for | |
231 | * the whole partition in configure_exceptions(). | |
232 | */ | |
233 | if (early_cpu_has_feature(CPU_FTR_HVMODE) && | |
234 | early_cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
235 | unsigned long lpcr = mfspr(SPRN_LPCR); | |
236 | mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3); | |
237 | } | |
238 | ||
d3cbff1b BH |
239 | /* Set IR and DR in PACA MSR */ |
240 | get_paca()->kernel_msr = MSR_KERNEL; | |
241 | } | |
242 | ||
40ef8cbc PM |
243 | /* |
244 | * Early initialization entry point. This is called by head.S | |
245 | * with MMU translation disabled. We rely on the "feature" of | |
246 | * the CPU that ignores the top 2 bits of the address in real | |
247 | * mode so we can access kernel globals normally provided we | |
248 | * only toy with things in the RMO region. From here, we do | |
95f72d1e | 249 | * some early parsing of the device-tree to setup out MEMBLOCK |
40ef8cbc PM |
250 | * data structures, and allocate & initialize the hash table |
251 | * and segment tables so we can start running with translation | |
252 | * enabled. | |
253 | * | |
254 | * It is this function which will call the probe() callback of | |
255 | * the various platform types and copy the matching one to the | |
256 | * global ppc_md structure. Your platform can eventually do | |
257 | * some very early initializations from the probe() routine, but | |
258 | * this is not recommended, be very careful as, for example, the | |
259 | * device-tree is not accessible via normal means at this point. | |
260 | */ | |
261 | ||
262 | void __init early_setup(unsigned long dt_ptr) | |
263 | { | |
6a7e4064 GL |
264 | static __initdata struct paca_struct boot_paca; |
265 | ||
24d96495 BH |
266 | /* -------- printk is _NOT_ safe to use here ! ------- */ |
267 | ||
42c4aaad | 268 | /* Identify CPU type */ |
974a76f5 | 269 | identify_cpu(0, mfspr(SPRN_PVR)); |
42c4aaad | 270 | |
33dbcf72 | 271 | /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ |
1426d5a3 ME |
272 | initialise_paca(&boot_paca, 0); |
273 | setup_paca(&boot_paca); | |
25e13814 | 274 | fixup_boot_paca(); |
33dbcf72 | 275 | |
24d96495 BH |
276 | /* -------- printk is now safe to use ------- */ |
277 | ||
f2fd2513 BH |
278 | /* Enable early debugging if any specified (see udbg.h) */ |
279 | udbg_early_init(); | |
280 | ||
e8222502 | 281 | DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); |
40ef8cbc | 282 | |
40ef8cbc | 283 | /* |
3c607ce2 LV |
284 | * Do early initialization using the flattened device |
285 | * tree, such as retrieving the physical memory map or | |
286 | * calculating/retrieving the hash table size. | |
40ef8cbc PM |
287 | */ |
288 | early_init_devtree(__va(dt_ptr)); | |
289 | ||
4df20460 | 290 | /* Now we know the logical id of our boot cpu, setup the paca. */ |
1426d5a3 | 291 | setup_paca(&paca[boot_cpuid]); |
25e13814 | 292 | fixup_boot_paca(); |
4df20460 | 293 | |
63c254a5 | 294 | /* |
d3cbff1b BH |
295 | * Configure exception handlers. This include setting up trampolines |
296 | * if needed, setting exception endian mode, etc... | |
63c254a5 | 297 | */ |
d3cbff1b | 298 | configure_exceptions(); |
0cc4746c | 299 | |
c4bd6cb8 BH |
300 | /* Apply all the dynamic patching */ |
301 | apply_feature_fixups(); | |
97f6e0cc | 302 | setup_feature_keys(); |
c4bd6cb8 | 303 | |
9e8066f3 ME |
304 | /* Initialize the hash table or TLB handling */ |
305 | early_init_mmu(); | |
306 | ||
a944a9c4 BH |
307 | /* |
308 | * At this point, we can let interrupts switch to virtual mode | |
309 | * (the MMU has been setup), so adjust the MSR in the PACA to | |
8f619b54 | 310 | * have IR and DR set and enable AIL if it exists |
a944a9c4 | 311 | */ |
8f619b54 | 312 | cpu_ready_for_interrupts(); |
a944a9c4 | 313 | |
40ef8cbc | 314 | DBG(" <- early_setup()\n"); |
7191b615 BH |
315 | |
316 | #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX | |
317 | /* | |
318 | * This needs to be done *last* (after the above DBG() even) | |
319 | * | |
320 | * Right after we return from this function, we turn on the MMU | |
321 | * which means the real-mode access trick that btext does will | |
322 | * no longer work, it needs to switch to using a real MMU | |
323 | * mapping. This call will ensure that it does | |
324 | */ | |
325 | btext_map(); | |
326 | #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ | |
40ef8cbc PM |
327 | } |
328 | ||
799d6046 PM |
329 | #ifdef CONFIG_SMP |
330 | void early_setup_secondary(void) | |
331 | { | |
103b7827 | 332 | /* Mark interrupts disabled in PACA */ |
757c74d2 | 333 | get_paca()->soft_enabled = 0; |
799d6046 | 334 | |
757c74d2 BH |
335 | /* Initialize the hash table or TLB handling */ |
336 | early_init_mmu_secondary(); | |
a944a9c4 BH |
337 | |
338 | /* | |
339 | * At this point, we can let interrupts switch to virtual mode | |
340 | * (the MMU has been setup), so adjust the MSR in the PACA to | |
341 | * have IR and DR set. | |
342 | */ | |
8f619b54 | 343 | cpu_ready_for_interrupts(); |
799d6046 PM |
344 | } |
345 | ||
346 | #endif /* CONFIG_SMP */ | |
40ef8cbc | 347 | |
da665885 | 348 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE) |
567cf94d SW |
349 | static bool use_spinloop(void) |
350 | { | |
351 | if (!IS_ENABLED(CONFIG_PPC_BOOK3E)) | |
352 | return true; | |
353 | ||
354 | /* | |
355 | * When book3e boots from kexec, the ePAPR spin table does | |
356 | * not get used. | |
357 | */ | |
358 | return of_property_read_bool(of_chosen, "linux,booted-from-kexec"); | |
359 | } | |
360 | ||
b8f51021 ME |
361 | void smp_release_cpus(void) |
362 | { | |
758438a7 | 363 | unsigned long *ptr; |
9d07bc84 | 364 | int i; |
b8f51021 | 365 | |
567cf94d SW |
366 | if (!use_spinloop()) |
367 | return; | |
368 | ||
b8f51021 ME |
369 | DBG(" -> smp_release_cpus()\n"); |
370 | ||
371 | /* All secondary cpus are spinning on a common spinloop, release them | |
372 | * all now so they can start to spin on their individual paca | |
373 | * spinloops. For non SMP kernels, the secondary cpus never get out | |
374 | * of the common spinloop. | |
1f6a93e4 | 375 | */ |
b8f51021 | 376 | |
758438a7 ME |
377 | ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop |
378 | - PHYSICAL_START); | |
2751b628 | 379 | *ptr = ppc_function_entry(generic_secondary_smp_init); |
9d07bc84 BH |
380 | |
381 | /* And wait a bit for them to catch up */ | |
382 | for (i = 0; i < 100000; i++) { | |
383 | mb(); | |
384 | HMT_low(); | |
7ac87abb | 385 | if (spinning_secondaries == 0) |
9d07bc84 BH |
386 | break; |
387 | udelay(1); | |
388 | } | |
7ac87abb | 389 | DBG("spinning_secondaries = %d\n", spinning_secondaries); |
b8f51021 ME |
390 | |
391 | DBG(" <- smp_release_cpus()\n"); | |
392 | } | |
da665885 | 393 | #endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */ |
b8f51021 | 394 | |
40ef8cbc | 395 | /* |
799d6046 PM |
396 | * Initialize some remaining members of the ppc64_caches and systemcfg |
397 | * structures | |
40ef8cbc PM |
398 | * (at least until we get rid of them completely). This is mostly some |
399 | * cache informations about the CPU that will be used by cache flush | |
400 | * routines and/or provided to userland | |
401 | */ | |
e2827fe5 BH |
402 | |
403 | static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize, | |
404 | u32 bsize, u32 sets) | |
405 | { | |
406 | info->size = size; | |
407 | info->sets = sets; | |
408 | info->line_size = lsize; | |
409 | info->block_size = bsize; | |
410 | info->log_block_size = __ilog2(bsize); | |
6ba422c7 AB |
411 | if (bsize) |
412 | info->blocks_per_page = PAGE_SIZE / bsize; | |
413 | else | |
414 | info->blocks_per_page = 0; | |
98a5f361 BH |
415 | |
416 | if (sets == 0) | |
417 | info->assoc = 0xffff; | |
418 | else | |
419 | info->assoc = size / (sets * lsize); | |
e2827fe5 BH |
420 | } |
421 | ||
422 | static bool __init parse_cache_info(struct device_node *np, | |
423 | bool icache, | |
424 | struct ppc_cache_info *info) | |
425 | { | |
426 | static const char *ipropnames[] __initdata = { | |
427 | "i-cache-size", | |
428 | "i-cache-sets", | |
429 | "i-cache-block-size", | |
430 | "i-cache-line-size", | |
431 | }; | |
432 | static const char *dpropnames[] __initdata = { | |
433 | "d-cache-size", | |
434 | "d-cache-sets", | |
435 | "d-cache-block-size", | |
436 | "d-cache-line-size", | |
437 | }; | |
438 | const char **propnames = icache ? ipropnames : dpropnames; | |
439 | const __be32 *sizep, *lsizep, *bsizep, *setsp; | |
440 | u32 size, lsize, bsize, sets; | |
441 | bool success = true; | |
442 | ||
443 | size = 0; | |
444 | sets = -1u; | |
445 | lsize = bsize = cur_cpu_spec->dcache_bsize; | |
446 | sizep = of_get_property(np, propnames[0], NULL); | |
447 | if (sizep != NULL) | |
448 | size = be32_to_cpu(*sizep); | |
449 | setsp = of_get_property(np, propnames[1], NULL); | |
450 | if (setsp != NULL) | |
451 | sets = be32_to_cpu(*setsp); | |
452 | bsizep = of_get_property(np, propnames[2], NULL); | |
453 | lsizep = of_get_property(np, propnames[3], NULL); | |
454 | if (bsizep == NULL) | |
455 | bsizep = lsizep; | |
456 | if (lsizep != NULL) | |
457 | lsize = be32_to_cpu(*lsizep); | |
458 | if (bsizep != NULL) | |
459 | bsize = be32_to_cpu(*bsizep); | |
460 | if (sizep == NULL || bsizep == NULL || lsizep == NULL) | |
461 | success = false; | |
462 | ||
463 | /* | |
464 | * OF is weird .. it represents fully associative caches | |
465 | * as "1 way" which doesn't make much sense and doesn't | |
466 | * leave room for direct mapped. We'll assume that 0 | |
467 | * in OF means direct mapped for that reason. | |
468 | */ | |
469 | if (sets == 1) | |
470 | sets = 0; | |
471 | else if (sets == 0) | |
472 | sets = 1; | |
473 | ||
474 | init_cache_info(info, size, lsize, bsize, sets); | |
475 | ||
476 | return success; | |
477 | } | |
478 | ||
b1923caa | 479 | void __init initialize_cache_info(void) |
40ef8cbc | 480 | { |
608b4214 BH |
481 | struct device_node *cpu = NULL, *l2, *l3 = NULL; |
482 | u32 pvr; | |
40ef8cbc PM |
483 | |
484 | DBG(" -> initialize_cache_info()\n"); | |
485 | ||
608b4214 BH |
486 | /* |
487 | * All shipping POWER8 machines have a firmware bug that | |
488 | * puts incorrect information in the device-tree. This will | |
489 | * be (hopefully) fixed for future chips but for now hard | |
490 | * code the values if we are running on one of these | |
491 | */ | |
492 | pvr = PVR_VER(mfspr(SPRN_PVR)); | |
493 | if (pvr == PVR_POWER8 || pvr == PVR_POWER8E || | |
494 | pvr == PVR_POWER8NVL) { | |
495 | /* size lsize blk sets */ | |
496 | init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32); | |
497 | init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64); | |
498 | init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512); | |
499 | init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192); | |
500 | } else | |
501 | cpu = of_find_node_by_type(NULL, "cpu"); | |
40ef8cbc | 502 | |
e2827fe5 BH |
503 | /* |
504 | * We're assuming *all* of the CPUs have the same | |
505 | * d-cache and i-cache sizes... -Peter | |
506 | */ | |
65e01f38 BH |
507 | if (cpu) { |
508 | if (!parse_cache_info(cpu, false, &ppc64_caches.l1d)) | |
e2827fe5 BH |
509 | DBG("Argh, can't find dcache properties !\n"); |
510 | ||
65e01f38 | 511 | if (!parse_cache_info(cpu, true, &ppc64_caches.l1i)) |
e2827fe5 | 512 | DBG("Argh, can't find icache properties !\n"); |
65e01f38 BH |
513 | |
514 | /* | |
515 | * Try to find the L2 and L3 if any. Assume they are | |
516 | * unified and use the D-side properties. | |
517 | */ | |
518 | l2 = of_find_next_cache_node(cpu); | |
519 | of_node_put(cpu); | |
520 | if (l2) { | |
521 | parse_cache_info(l2, false, &ppc64_caches.l2); | |
522 | l3 = of_find_next_cache_node(l2); | |
523 | of_node_put(l2); | |
524 | } | |
525 | if (l3) { | |
526 | parse_cache_info(l3, false, &ppc64_caches.l3); | |
527 | of_node_put(l3); | |
528 | } | |
40ef8cbc PM |
529 | } |
530 | ||
9df549af | 531 | /* For use by binfmt_elf */ |
e2827fe5 BH |
532 | dcache_bsize = ppc64_caches.l1d.block_size; |
533 | icache_bsize = ppc64_caches.l1i.block_size; | |
9df549af | 534 | |
40ef8cbc PM |
535 | DBG(" <- initialize_cache_info()\n"); |
536 | } | |
537 | ||
40bd587a BH |
538 | /* This returns the limit below which memory accesses to the linear |
539 | * mapping are guarnateed not to cause a TLB or SLB miss. This is | |
540 | * used to allocate interrupt or emergency stacks for which our | |
541 | * exception entry path doesn't deal with being interrupted. | |
542 | */ | |
009776ba | 543 | static __init u64 safe_stack_limit(void) |
095c7965 | 544 | { |
40bd587a BH |
545 | #ifdef CONFIG_PPC_BOOK3E |
546 | /* Freescale BookE bolts the entire linear mapping */ | |
547 | if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) | |
548 | return linear_map_top; | |
549 | /* Other BookE, we assume the first GB is bolted */ | |
550 | return 1ul << 30; | |
551 | #else | |
552 | /* BookS, the first segment is bolted */ | |
553 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) | |
095c7965 | 554 | return 1UL << SID_SHIFT_1T; |
095c7965 | 555 | return 1UL << SID_SHIFT; |
40bd587a | 556 | #endif |
095c7965 AB |
557 | } |
558 | ||
b1923caa | 559 | void __init irqstack_early_init(void) |
40ef8cbc | 560 | { |
40bd587a | 561 | u64 limit = safe_stack_limit(); |
40ef8cbc PM |
562 | unsigned int i; |
563 | ||
564 | /* | |
8f4da26e AB |
565 | * Interrupt stacks must be in the first segment since we |
566 | * cannot afford to take SLB misses on them. | |
40ef8cbc | 567 | */ |
0e551954 | 568 | for_each_possible_cpu(i) { |
3c726f8d | 569 | softirq_ctx[i] = (struct thread_info *) |
95f72d1e | 570 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 571 | THREAD_SIZE, limit)); |
3c726f8d | 572 | hardirq_ctx[i] = (struct thread_info *) |
95f72d1e | 573 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 574 | THREAD_SIZE, limit)); |
40ef8cbc PM |
575 | } |
576 | } | |
40ef8cbc | 577 | |
2d27cfd3 | 578 | #ifdef CONFIG_PPC_BOOK3E |
b1923caa | 579 | void __init exc_lvl_early_init(void) |
2d27cfd3 BH |
580 | { |
581 | unsigned int i; | |
160c7324 | 582 | unsigned long sp; |
2d27cfd3 BH |
583 | |
584 | for_each_possible_cpu(i) { | |
160c7324 TC |
585 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); |
586 | critirq_ctx[i] = (struct thread_info *)__va(sp); | |
587 | paca[i].crit_kstack = __va(sp + THREAD_SIZE); | |
588 | ||
589 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); | |
590 | dbgirq_ctx[i] = (struct thread_info *)__va(sp); | |
591 | paca[i].dbg_kstack = __va(sp + THREAD_SIZE); | |
592 | ||
593 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); | |
594 | mcheckirq_ctx[i] = (struct thread_info *)__va(sp); | |
595 | paca[i].mc_kstack = __va(sp + THREAD_SIZE); | |
2d27cfd3 | 596 | } |
d36b4c4f KG |
597 | |
598 | if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) | |
565c2f24 | 599 | patch_exception(0x040, exc_debug_debug_book3e); |
2d27cfd3 | 600 | } |
2d27cfd3 BH |
601 | #endif |
602 | ||
40ef8cbc PM |
603 | /* |
604 | * Stack space used when we detect a bad kernel stack pointer, and | |
729b0f71 MS |
605 | * early in SMP boots before relocation is enabled. Exclusive emergency |
606 | * stack for machine checks. | |
40ef8cbc | 607 | */ |
b1923caa | 608 | void __init emergency_stack_init(void) |
40ef8cbc | 609 | { |
095c7965 | 610 | u64 limit; |
40ef8cbc PM |
611 | unsigned int i; |
612 | ||
613 | /* | |
614 | * Emergency stacks must be under 256MB, we cannot afford to take | |
615 | * SLB misses on them. The ABI also requires them to be 128-byte | |
616 | * aligned. | |
617 | * | |
618 | * Since we use these as temporary stacks during secondary CPU | |
619 | * bringup, we need to get at them in real mode. This means they | |
620 | * must also be within the RMO region. | |
621 | */ | |
40bd587a | 622 | limit = min(safe_stack_limit(), ppc64_rma_size); |
40ef8cbc | 623 | |
3243d874 | 624 | for_each_possible_cpu(i) { |
5d31a96e ME |
625 | struct thread_info *ti; |
626 | ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit)); | |
627 | klp_init_thread_info(ti); | |
628 | paca[i].emergency_sp = (void *)ti + THREAD_SIZE; | |
729b0f71 MS |
629 | |
630 | #ifdef CONFIG_PPC_BOOK3S_64 | |
631 | /* emergency stack for machine check exception handling. */ | |
5d31a96e ME |
632 | ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit)); |
633 | klp_init_thread_info(ti); | |
634 | paca[i].mc_emergency_sp = (void *)ti + THREAD_SIZE; | |
729b0f71 | 635 | #endif |
3243d874 | 636 | } |
40ef8cbc PM |
637 | } |
638 | ||
7a0268fa | 639 | #ifdef CONFIG_SMP |
c2a7e818 TH |
640 | #define PCPU_DYN_SIZE () |
641 | ||
642 | static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) | |
7a0268fa | 643 | { |
c2a7e818 TH |
644 | return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, |
645 | __pa(MAX_DMA_ADDRESS)); | |
646 | } | |
7a0268fa | 647 | |
c2a7e818 TH |
648 | static void __init pcpu_fc_free(void *ptr, size_t size) |
649 | { | |
650 | free_bootmem(__pa(ptr), size); | |
651 | } | |
7a0268fa | 652 | |
c2a7e818 TH |
653 | static int pcpu_cpu_distance(unsigned int from, unsigned int to) |
654 | { | |
655 | if (cpu_to_node(from) == cpu_to_node(to)) | |
656 | return LOCAL_DISTANCE; | |
657 | else | |
658 | return REMOTE_DISTANCE; | |
659 | } | |
660 | ||
ae01f84b AB |
661 | unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; |
662 | EXPORT_SYMBOL(__per_cpu_offset); | |
663 | ||
c2a7e818 TH |
664 | void __init setup_per_cpu_areas(void) |
665 | { | |
666 | const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; | |
667 | size_t atom_size; | |
668 | unsigned long delta; | |
669 | unsigned int cpu; | |
670 | int rc; | |
671 | ||
672 | /* | |
673 | * Linear mapping is one of 4K, 1M and 16M. For 4K, no need | |
674 | * to group units. For larger mappings, use 1M atom which | |
675 | * should be large enough to contain a number of units. | |
676 | */ | |
677 | if (mmu_linear_psize == MMU_PAGE_4K) | |
678 | atom_size = PAGE_SIZE; | |
679 | else | |
680 | atom_size = 1 << 20; | |
681 | ||
682 | rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, | |
683 | pcpu_fc_alloc, pcpu_fc_free); | |
684 | if (rc < 0) | |
685 | panic("cannot initialize percpu area (err=%d)", rc); | |
686 | ||
687 | delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; | |
ae01f84b AB |
688 | for_each_possible_cpu(cpu) { |
689 | __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; | |
690 | paca[cpu].data_offset = __per_cpu_offset[cpu]; | |
691 | } | |
7a0268fa AB |
692 | } |
693 | #endif | |
4cb3cee0 | 694 | |
a5d86257 AB |
695 | #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE |
696 | unsigned long memory_block_size_bytes(void) | |
697 | { | |
698 | if (ppc_md.memory_block_size) | |
699 | return ppc_md.memory_block_size(); | |
700 | ||
701 | return MIN_MEMORY_BLOCK_SIZE; | |
702 | } | |
703 | #endif | |
4cb3cee0 | 704 | |
ecd73cc5 | 705 | #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) |
4cb3cee0 BH |
706 | struct ppc_pci_io ppc_pci_io; |
707 | EXPORT_SYMBOL(ppc_pci_io); | |
ecd73cc5 | 708 | #endif |
c54b2bf1 AB |
709 | |
710 | #ifdef CONFIG_HARDLOCKUP_DETECTOR | |
711 | u64 hw_nmi_get_sample_period(int watchdog_thresh) | |
712 | { | |
713 | return ppc_proc_freq * watchdog_thresh; | |
714 | } | |
715 | ||
716 | /* | |
717 | * The hardlockup detector breaks PMU event based branches and is likely | |
718 | * to get false positives in KVM guests, so disable it by default. | |
719 | */ | |
720 | static int __init disable_hardlockup_detector(void) | |
721 | { | |
d19d5efd | 722 | hardlockup_detector_disable(); |
c54b2bf1 AB |
723 | |
724 | return 0; | |
725 | } | |
726 | early_initcall(disable_hardlockup_detector); | |
727 | #endif |