Commit | Line | Data |
---|---|---|
40ef8cbc PM |
1 | /* |
2 | * | |
3 | * Common boot and setup code. | |
4 | * | |
5 | * Copyright (C) 2001 PPC64 Team, IBM Corp | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
7191b615 | 13 | #define DEBUG |
40ef8cbc | 14 | |
4b16f8e2 | 15 | #include <linux/export.h> |
40ef8cbc PM |
16 | #include <linux/string.h> |
17 | #include <linux/sched.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/reboot.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/initrd.h> | |
40ef8cbc PM |
23 | #include <linux/seq_file.h> |
24 | #include <linux/ioport.h> | |
25 | #include <linux/console.h> | |
26 | #include <linux/utsname.h> | |
27 | #include <linux/tty.h> | |
28 | #include <linux/root_dev.h> | |
29 | #include <linux/notifier.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/unistd.h> | |
32 | #include <linux/serial.h> | |
33 | #include <linux/serial_8250.h> | |
7a0268fa | 34 | #include <linux/bootmem.h> |
12d04eef | 35 | #include <linux/pci.h> |
945feb17 | 36 | #include <linux/lockdep.h> |
95f72d1e | 37 | #include <linux/memblock.h> |
a6146888 | 38 | #include <linux/hugetlb.h> |
a5d86257 | 39 | #include <linux/memory.h> |
a6146888 | 40 | |
40ef8cbc | 41 | #include <asm/io.h> |
0cc4746c | 42 | #include <asm/kdump.h> |
40ef8cbc PM |
43 | #include <asm/prom.h> |
44 | #include <asm/processor.h> | |
45 | #include <asm/pgtable.h> | |
40ef8cbc PM |
46 | #include <asm/smp.h> |
47 | #include <asm/elf.h> | |
48 | #include <asm/machdep.h> | |
49 | #include <asm/paca.h> | |
40ef8cbc PM |
50 | #include <asm/time.h> |
51 | #include <asm/cputable.h> | |
52 | #include <asm/sections.h> | |
53 | #include <asm/btext.h> | |
54 | #include <asm/nvram.h> | |
55 | #include <asm/setup.h> | |
40ef8cbc PM |
56 | #include <asm/rtas.h> |
57 | #include <asm/iommu.h> | |
58 | #include <asm/serial.h> | |
59 | #include <asm/cache.h> | |
60 | #include <asm/page.h> | |
61 | #include <asm/mmu.h> | |
40ef8cbc | 62 | #include <asm/firmware.h> |
f78541dc | 63 | #include <asm/xmon.h> |
dcad47fc | 64 | #include <asm/udbg.h> |
593e537b | 65 | #include <asm/kexec.h> |
25d21ad6 | 66 | #include <asm/mmu_context.h> |
d36b4c4f | 67 | #include <asm/code-patching.h> |
aa04b4cc | 68 | #include <asm/kvm_ppc.h> |
a6146888 | 69 | #include <asm/hugetlb.h> |
4e21b94c | 70 | #include <asm/epapr_hcalls.h> |
40ef8cbc PM |
71 | |
72 | #ifdef DEBUG | |
73 | #define DBG(fmt...) udbg_printf(fmt) | |
74 | #else | |
75 | #define DBG(fmt...) | |
76 | #endif | |
77 | ||
8246aca7 | 78 | int spinning_secondaries; |
40ef8cbc PM |
79 | u64 ppc64_pft_size; |
80 | ||
dabcafd3 OJ |
81 | /* Pick defaults since we might want to patch instructions |
82 | * before we've read this from the device tree. | |
83 | */ | |
84 | struct ppc64_caches ppc64_caches = { | |
5a2fe38d OJ |
85 | .dline_size = 0x40, |
86 | .log_dline_size = 6, | |
87 | .iline_size = 0x40, | |
88 | .log_iline_size = 6 | |
dabcafd3 | 89 | }; |
40ef8cbc PM |
90 | EXPORT_SYMBOL_GPL(ppc64_caches); |
91 | ||
92 | /* | |
93 | * These are used in binfmt_elf.c to put aux entries on the stack | |
94 | * for each elf executable being started. | |
95 | */ | |
96 | int dcache_bsize; | |
97 | int icache_bsize; | |
98 | int ucache_bsize; | |
99 | ||
28efc35f SW |
100 | #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) |
101 | static void setup_tlb_core_data(void) | |
102 | { | |
103 | int cpu; | |
104 | ||
82d86de2 SW |
105 | BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); |
106 | ||
28efc35f SW |
107 | for_each_possible_cpu(cpu) { |
108 | int first = cpu_first_thread_sibling(cpu); | |
109 | ||
110 | paca[cpu].tcd_ptr = &paca[first].tcd; | |
111 | ||
112 | /* | |
113 | * If we have threads, we need either tlbsrx. | |
114 | * or e6500 tablewalk mode, or else TLB handlers | |
115 | * will be racy and could produce duplicate entries. | |
116 | */ | |
117 | if (smt_enabled_at_boot >= 2 && | |
118 | !mmu_has_feature(MMU_FTR_USE_TLBRSRV) && | |
119 | book3e_htw_mode != PPC_HTW_E6500) { | |
120 | /* Should we panic instead? */ | |
121 | WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n", | |
122 | __func__); | |
123 | } | |
124 | } | |
125 | } | |
126 | #else | |
127 | static void setup_tlb_core_data(void) | |
128 | { | |
129 | } | |
130 | #endif | |
131 | ||
40ef8cbc PM |
132 | #ifdef CONFIG_SMP |
133 | ||
954e6da5 | 134 | static char *smt_enabled_cmdline; |
40ef8cbc PM |
135 | |
136 | /* Look for ibm,smt-enabled OF option */ | |
137 | static void check_smt_enabled(void) | |
138 | { | |
139 | struct device_node *dn; | |
a7f67bdf | 140 | const char *smt_option; |
40ef8cbc | 141 | |
954e6da5 NF |
142 | /* Default to enabling all threads */ |
143 | smt_enabled_at_boot = threads_per_core; | |
40ef8cbc | 144 | |
954e6da5 NF |
145 | /* Allow the command line to overrule the OF option */ |
146 | if (smt_enabled_cmdline) { | |
147 | if (!strcmp(smt_enabled_cmdline, "on")) | |
148 | smt_enabled_at_boot = threads_per_core; | |
149 | else if (!strcmp(smt_enabled_cmdline, "off")) | |
150 | smt_enabled_at_boot = 0; | |
151 | else { | |
1618bd53 | 152 | int smt; |
954e6da5 NF |
153 | int rc; |
154 | ||
1618bd53 | 155 | rc = kstrtoint(smt_enabled_cmdline, 10, &smt); |
954e6da5 NF |
156 | if (!rc) |
157 | smt_enabled_at_boot = | |
1618bd53 | 158 | min(threads_per_core, smt); |
954e6da5 NF |
159 | } |
160 | } else { | |
161 | dn = of_find_node_by_path("/options"); | |
162 | if (dn) { | |
163 | smt_option = of_get_property(dn, "ibm,smt-enabled", | |
164 | NULL); | |
165 | ||
166 | if (smt_option) { | |
167 | if (!strcmp(smt_option, "on")) | |
168 | smt_enabled_at_boot = threads_per_core; | |
169 | else if (!strcmp(smt_option, "off")) | |
170 | smt_enabled_at_boot = 0; | |
171 | } | |
172 | ||
173 | of_node_put(dn); | |
174 | } | |
175 | } | |
40ef8cbc PM |
176 | } |
177 | ||
178 | /* Look for smt-enabled= cmdline option */ | |
179 | static int __init early_smt_enabled(char *p) | |
180 | { | |
954e6da5 | 181 | smt_enabled_cmdline = p; |
40ef8cbc PM |
182 | return 0; |
183 | } | |
184 | early_param("smt-enabled", early_smt_enabled); | |
185 | ||
5ad57078 PM |
186 | #else |
187 | #define check_smt_enabled() | |
40ef8cbc PM |
188 | #endif /* CONFIG_SMP */ |
189 | ||
25e13814 ME |
190 | /** Fix up paca fields required for the boot cpu */ |
191 | static void fixup_boot_paca(void) | |
192 | { | |
193 | /* The boot cpu is started */ | |
194 | get_paca()->cpu_start = 1; | |
195 | /* Allow percpu accesses to work until we setup percpu data */ | |
196 | get_paca()->data_offset = 0; | |
197 | } | |
198 | ||
8f619b54 BH |
199 | static void cpu_ready_for_interrupts(void) |
200 | { | |
201 | /* Set IR and DR in PACA MSR */ | |
202 | get_paca()->kernel_msr = MSR_KERNEL; | |
203 | ||
633440f1 ME |
204 | /* |
205 | * Enable AIL if supported, and we are in hypervisor mode. If we are | |
206 | * not in hypervisor mode, we enable relocation-on interrupts later | |
207 | * in pSeries_setup_arch() using the H_SET_MODE hcall. | |
208 | */ | |
18aa0da3 PM |
209 | if (cpu_has_feature(CPU_FTR_HVMODE) && |
210 | cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
8f619b54 BH |
211 | unsigned long lpcr = mfspr(SPRN_LPCR); |
212 | mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3); | |
213 | } | |
214 | } | |
215 | ||
40ef8cbc PM |
216 | /* |
217 | * Early initialization entry point. This is called by head.S | |
218 | * with MMU translation disabled. We rely on the "feature" of | |
219 | * the CPU that ignores the top 2 bits of the address in real | |
220 | * mode so we can access kernel globals normally provided we | |
221 | * only toy with things in the RMO region. From here, we do | |
95f72d1e | 222 | * some early parsing of the device-tree to setup out MEMBLOCK |
40ef8cbc PM |
223 | * data structures, and allocate & initialize the hash table |
224 | * and segment tables so we can start running with translation | |
225 | * enabled. | |
226 | * | |
227 | * It is this function which will call the probe() callback of | |
228 | * the various platform types and copy the matching one to the | |
229 | * global ppc_md structure. Your platform can eventually do | |
230 | * some very early initializations from the probe() routine, but | |
231 | * this is not recommended, be very careful as, for example, the | |
232 | * device-tree is not accessible via normal means at this point. | |
233 | */ | |
234 | ||
235 | void __init early_setup(unsigned long dt_ptr) | |
236 | { | |
6a7e4064 GL |
237 | static __initdata struct paca_struct boot_paca; |
238 | ||
24d96495 BH |
239 | /* -------- printk is _NOT_ safe to use here ! ------- */ |
240 | ||
42c4aaad | 241 | /* Identify CPU type */ |
974a76f5 | 242 | identify_cpu(0, mfspr(SPRN_PVR)); |
42c4aaad | 243 | |
33dbcf72 | 244 | /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ |
1426d5a3 ME |
245 | initialise_paca(&boot_paca, 0); |
246 | setup_paca(&boot_paca); | |
25e13814 | 247 | fixup_boot_paca(); |
33dbcf72 | 248 | |
945feb17 BH |
249 | /* Initialize lockdep early or else spinlocks will blow */ |
250 | lockdep_init(); | |
251 | ||
24d96495 BH |
252 | /* -------- printk is now safe to use ------- */ |
253 | ||
f2fd2513 BH |
254 | /* Enable early debugging if any specified (see udbg.h) */ |
255 | udbg_early_init(); | |
256 | ||
e8222502 | 257 | DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); |
40ef8cbc | 258 | |
40ef8cbc | 259 | /* |
3c607ce2 LV |
260 | * Do early initialization using the flattened device |
261 | * tree, such as retrieving the physical memory map or | |
262 | * calculating/retrieving the hash table size. | |
40ef8cbc PM |
263 | */ |
264 | early_init_devtree(__va(dt_ptr)); | |
265 | ||
4e21b94c LT |
266 | epapr_paravirt_early_init(); |
267 | ||
4df20460 | 268 | /* Now we know the logical id of our boot cpu, setup the paca. */ |
1426d5a3 | 269 | setup_paca(&paca[boot_cpuid]); |
25e13814 | 270 | fixup_boot_paca(); |
4df20460 | 271 | |
e8222502 BH |
272 | /* Probe the machine type */ |
273 | probe_machine(); | |
40ef8cbc | 274 | |
47310413 | 275 | setup_kdump_trampoline(); |
0cc4746c | 276 | |
40ef8cbc PM |
277 | DBG("Found, Initializing memory management...\n"); |
278 | ||
757c74d2 BH |
279 | /* Initialize the hash table or TLB handling */ |
280 | early_init_mmu(); | |
40ef8cbc | 281 | |
a944a9c4 BH |
282 | /* |
283 | * At this point, we can let interrupts switch to virtual mode | |
284 | * (the MMU has been setup), so adjust the MSR in the PACA to | |
8f619b54 | 285 | * have IR and DR set and enable AIL if it exists |
a944a9c4 | 286 | */ |
8f619b54 | 287 | cpu_ready_for_interrupts(); |
a944a9c4 BH |
288 | |
289 | /* Reserve large chunks of memory for use by CMA for KVM */ | |
fa61a4e3 AK |
290 | kvm_cma_reserve(); |
291 | ||
a6146888 BB |
292 | /* |
293 | * Reserve any gigantic pages requested on the command line. | |
294 | * memblock needs to have been initialized by the time this is | |
295 | * called since this will reserve memory. | |
296 | */ | |
297 | reserve_hugetlb_gpages(); | |
298 | ||
40ef8cbc | 299 | DBG(" <- early_setup()\n"); |
7191b615 BH |
300 | |
301 | #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX | |
302 | /* | |
303 | * This needs to be done *last* (after the above DBG() even) | |
304 | * | |
305 | * Right after we return from this function, we turn on the MMU | |
306 | * which means the real-mode access trick that btext does will | |
307 | * no longer work, it needs to switch to using a real MMU | |
308 | * mapping. This call will ensure that it does | |
309 | */ | |
310 | btext_map(); | |
311 | #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ | |
40ef8cbc PM |
312 | } |
313 | ||
799d6046 PM |
314 | #ifdef CONFIG_SMP |
315 | void early_setup_secondary(void) | |
316 | { | |
d04c56f7 | 317 | /* Mark interrupts enabled in PACA */ |
757c74d2 | 318 | get_paca()->soft_enabled = 0; |
799d6046 | 319 | |
757c74d2 BH |
320 | /* Initialize the hash table or TLB handling */ |
321 | early_init_mmu_secondary(); | |
a944a9c4 BH |
322 | |
323 | /* | |
324 | * At this point, we can let interrupts switch to virtual mode | |
325 | * (the MMU has been setup), so adjust the MSR in the PACA to | |
326 | * have IR and DR set. | |
327 | */ | |
8f619b54 | 328 | cpu_ready_for_interrupts(); |
799d6046 PM |
329 | } |
330 | ||
331 | #endif /* CONFIG_SMP */ | |
40ef8cbc | 332 | |
b8f51021 ME |
333 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) |
334 | void smp_release_cpus(void) | |
335 | { | |
758438a7 | 336 | unsigned long *ptr; |
9d07bc84 | 337 | int i; |
b8f51021 ME |
338 | |
339 | DBG(" -> smp_release_cpus()\n"); | |
340 | ||
341 | /* All secondary cpus are spinning on a common spinloop, release them | |
342 | * all now so they can start to spin on their individual paca | |
343 | * spinloops. For non SMP kernels, the secondary cpus never get out | |
344 | * of the common spinloop. | |
1f6a93e4 | 345 | */ |
b8f51021 | 346 | |
758438a7 ME |
347 | ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop |
348 | - PHYSICAL_START); | |
2751b628 | 349 | *ptr = ppc_function_entry(generic_secondary_smp_init); |
9d07bc84 BH |
350 | |
351 | /* And wait a bit for them to catch up */ | |
352 | for (i = 0; i < 100000; i++) { | |
353 | mb(); | |
354 | HMT_low(); | |
7ac87abb | 355 | if (spinning_secondaries == 0) |
9d07bc84 BH |
356 | break; |
357 | udelay(1); | |
358 | } | |
7ac87abb | 359 | DBG("spinning_secondaries = %d\n", spinning_secondaries); |
b8f51021 ME |
360 | |
361 | DBG(" <- smp_release_cpus()\n"); | |
362 | } | |
363 | #endif /* CONFIG_SMP || CONFIG_KEXEC */ | |
364 | ||
40ef8cbc | 365 | /* |
799d6046 PM |
366 | * Initialize some remaining members of the ppc64_caches and systemcfg |
367 | * structures | |
40ef8cbc PM |
368 | * (at least until we get rid of them completely). This is mostly some |
369 | * cache informations about the CPU that will be used by cache flush | |
370 | * routines and/or provided to userland | |
371 | */ | |
372 | static void __init initialize_cache_info(void) | |
373 | { | |
374 | struct device_node *np; | |
375 | unsigned long num_cpus = 0; | |
376 | ||
377 | DBG(" -> initialize_cache_info()\n"); | |
378 | ||
94db7c5e | 379 | for_each_node_by_type(np, "cpu") { |
40ef8cbc PM |
380 | num_cpus += 1; |
381 | ||
dfbe93a2 AB |
382 | /* |
383 | * We're assuming *all* of the CPUs have the same | |
40ef8cbc PM |
384 | * d-cache and i-cache sizes... -Peter |
385 | */ | |
dfbe93a2 | 386 | if (num_cpus == 1) { |
7946d5a5 | 387 | const __be32 *sizep, *lsizep; |
40ef8cbc | 388 | u32 size, lsize; |
40ef8cbc PM |
389 | |
390 | size = 0; | |
391 | lsize = cur_cpu_spec->dcache_bsize; | |
e2eb6392 | 392 | sizep = of_get_property(np, "d-cache-size", NULL); |
40ef8cbc | 393 | if (sizep != NULL) |
7946d5a5 | 394 | size = be32_to_cpu(*sizep); |
dfbe93a2 AB |
395 | lsizep = of_get_property(np, "d-cache-block-size", |
396 | NULL); | |
20474abd BH |
397 | /* fallback if block size missing */ |
398 | if (lsizep == NULL) | |
dfbe93a2 AB |
399 | lsizep = of_get_property(np, |
400 | "d-cache-line-size", | |
401 | NULL); | |
40ef8cbc | 402 | if (lsizep != NULL) |
7946d5a5 | 403 | lsize = be32_to_cpu(*lsizep); |
b0d436c7 | 404 | if (sizep == NULL || lsizep == NULL) |
40ef8cbc PM |
405 | DBG("Argh, can't find dcache properties ! " |
406 | "sizep: %p, lsizep: %p\n", sizep, lsizep); | |
407 | ||
a7f290da BH |
408 | ppc64_caches.dsize = size; |
409 | ppc64_caches.dline_size = lsize; | |
40ef8cbc PM |
410 | ppc64_caches.log_dline_size = __ilog2(lsize); |
411 | ppc64_caches.dlines_per_page = PAGE_SIZE / lsize; | |
412 | ||
413 | size = 0; | |
414 | lsize = cur_cpu_spec->icache_bsize; | |
e2eb6392 | 415 | sizep = of_get_property(np, "i-cache-size", NULL); |
40ef8cbc | 416 | if (sizep != NULL) |
7946d5a5 | 417 | size = be32_to_cpu(*sizep); |
dfbe93a2 AB |
418 | lsizep = of_get_property(np, "i-cache-block-size", |
419 | NULL); | |
20474abd | 420 | if (lsizep == NULL) |
dfbe93a2 AB |
421 | lsizep = of_get_property(np, |
422 | "i-cache-line-size", | |
423 | NULL); | |
40ef8cbc | 424 | if (lsizep != NULL) |
7946d5a5 | 425 | lsize = be32_to_cpu(*lsizep); |
b0d436c7 | 426 | if (sizep == NULL || lsizep == NULL) |
40ef8cbc PM |
427 | DBG("Argh, can't find icache properties ! " |
428 | "sizep: %p, lsizep: %p\n", sizep, lsizep); | |
429 | ||
a7f290da BH |
430 | ppc64_caches.isize = size; |
431 | ppc64_caches.iline_size = lsize; | |
40ef8cbc PM |
432 | ppc64_caches.log_iline_size = __ilog2(lsize); |
433 | ppc64_caches.ilines_per_page = PAGE_SIZE / lsize; | |
434 | } | |
435 | } | |
436 | ||
40ef8cbc PM |
437 | DBG(" <- initialize_cache_info()\n"); |
438 | } | |
439 | ||
40ef8cbc PM |
440 | |
441 | /* | |
442 | * Do some initial setup of the system. The parameters are those which | |
443 | * were passed in from the bootloader. | |
444 | */ | |
445 | void __init setup_system(void) | |
446 | { | |
447 | DBG(" -> setup_system()\n"); | |
448 | ||
826ea8f2 TB |
449 | /* Apply the CPUs-specific and firmware specific fixups to kernel |
450 | * text (nop out sections not relevant to this CPU or this firmware) | |
42c4aaad | 451 | */ |
0909c8c2 | 452 | do_feature_fixups(cur_cpu_spec->cpu_features, |
42c4aaad | 453 | &__start___ftr_fixup, &__stop___ftr_fixup); |
7c03d653 BH |
454 | do_feature_fixups(cur_cpu_spec->mmu_features, |
455 | &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); | |
826ea8f2 TB |
456 | do_feature_fixups(powerpc_firmware_features, |
457 | &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); | |
2d1b2027 KG |
458 | do_lwsync_fixups(cur_cpu_spec->cpu_features, |
459 | &__start___lwsync_fixup, &__stop___lwsync_fixup); | |
d715e433 | 460 | do_final_fixups(); |
42c4aaad | 461 | |
40ef8cbc PM |
462 | /* |
463 | * Unflatten the device-tree passed by prom_init or kexec | |
464 | */ | |
465 | unflatten_device_tree(); | |
466 | ||
467 | /* | |
468 | * Fill the ppc64_caches & systemcfg structures with informations | |
0ebfff14 | 469 | * retrieved from the device-tree. |
40ef8cbc PM |
470 | */ |
471 | initialize_cache_info(); | |
472 | ||
473 | #ifdef CONFIG_PPC_RTAS | |
474 | /* | |
475 | * Initialize RTAS if available | |
476 | */ | |
477 | rtas_initialize(); | |
478 | #endif /* CONFIG_PPC_RTAS */ | |
40ef8cbc PM |
479 | |
480 | /* | |
481 | * Check if we have an initrd provided via the device-tree | |
482 | */ | |
483 | check_for_initrd(); | |
40ef8cbc PM |
484 | |
485 | /* | |
486 | * Do some platform specific early initializations, that includes | |
487 | * setting up the hash table pointers. It also sets up some interrupt-mapping | |
488 | * related options that will be used by finish_device_tree() | |
489 | */ | |
57744ea9 GL |
490 | if (ppc_md.init_early) |
491 | ppc_md.init_early(); | |
40ef8cbc | 492 | |
463ce0e1 BH |
493 | /* |
494 | * We can discover serial ports now since the above did setup the | |
495 | * hash table management for us, thus ioremap works. We do that early | |
496 | * so that further code can be debugged | |
497 | */ | |
463ce0e1 | 498 | find_legacy_serial_ports(); |
463ce0e1 | 499 | |
40ef8cbc PM |
500 | /* |
501 | * Register early console | |
502 | */ | |
503 | register_early_udbg_console(); | |
40ef8cbc | 504 | |
47679283 ME |
505 | /* |
506 | * Initialize xmon | |
507 | */ | |
508 | xmon_setup(); | |
480f6f35 | 509 | |
5ad57078 | 510 | smp_setup_cpu_maps(); |
954e6da5 | 511 | check_smt_enabled(); |
28efc35f | 512 | setup_tlb_core_data(); |
40ef8cbc | 513 | |
e16c8765 AF |
514 | /* |
515 | * Freescale Book3e parts spin in a loop provided by firmware, | |
516 | * so smp_release_cpus() does nothing for them | |
517 | */ | |
518 | #if defined(CONFIG_SMP) && !defined(CONFIG_PPC_FSL_BOOK3E) | |
40ef8cbc PM |
519 | /* Release secondary cpus out of their spinloops at 0x60 now that |
520 | * we can map physical -> logical CPU ids | |
521 | */ | |
522 | smp_release_cpus(); | |
f018b36f | 523 | #endif |
40ef8cbc | 524 | |
2c186e05 | 525 | pr_info("Starting Linux PPC64 %s\n", init_utsname()->version); |
40ef8cbc | 526 | |
2c186e05 AB |
527 | pr_info("-----------------------------------------------------\n"); |
528 | pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size); | |
529 | pr_info("phys_mem_size = 0x%llx\n", memblock_phys_mem_size()); | |
bdce97e9 | 530 | |
9697add0 | 531 | if (ppc64_caches.dline_size != 0x80) |
2c186e05 | 532 | pr_info("dcache_line_size = 0x%x\n", ppc64_caches.dline_size); |
9697add0 | 533 | if (ppc64_caches.iline_size != 0x80) |
2c186e05 | 534 | pr_info("icache_line_size = 0x%x\n", ppc64_caches.iline_size); |
bdce97e9 | 535 | |
2c186e05 AB |
536 | pr_info("cpu_features = 0x%016lx\n", cur_cpu_spec->cpu_features); |
537 | pr_info(" possible = 0x%016lx\n", CPU_FTRS_POSSIBLE); | |
538 | pr_info(" always = 0x%016lx\n", CPU_FTRS_ALWAYS); | |
539 | pr_info("cpu_user_features = 0x%08x 0x%08x\n", cur_cpu_spec->cpu_user_features, | |
87d99c0e | 540 | cur_cpu_spec->cpu_user_features2); |
2c186e05 AB |
541 | pr_info("mmu_features = 0x%08x\n", cur_cpu_spec->mmu_features); |
542 | pr_info("firmware_features = 0x%016lx\n", powerpc_firmware_features); | |
87d99c0e | 543 | |
94491685 | 544 | #ifdef CONFIG_PPC_STD_MMU_64 |
9697add0 | 545 | if (htab_address) |
2c186e05 | 546 | pr_info("htab_address = 0x%p\n", htab_address); |
bdce97e9 | 547 | |
2c186e05 | 548 | pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask); |
bdce97e9 ME |
549 | #endif |
550 | ||
b160544c | 551 | if (PHYSICAL_START > 0) |
2c186e05 | 552 | pr_info("physical_start = 0x%llx\n", |
e468455e | 553 | (unsigned long long)PHYSICAL_START); |
2c186e05 | 554 | pr_info("-----------------------------------------------------\n"); |
40ef8cbc | 555 | |
40ef8cbc PM |
556 | DBG(" <- setup_system()\n"); |
557 | } | |
558 | ||
40bd587a BH |
559 | /* This returns the limit below which memory accesses to the linear |
560 | * mapping are guarnateed not to cause a TLB or SLB miss. This is | |
561 | * used to allocate interrupt or emergency stacks for which our | |
562 | * exception entry path doesn't deal with being interrupted. | |
563 | */ | |
564 | static u64 safe_stack_limit(void) | |
095c7965 | 565 | { |
40bd587a BH |
566 | #ifdef CONFIG_PPC_BOOK3E |
567 | /* Freescale BookE bolts the entire linear mapping */ | |
568 | if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) | |
569 | return linear_map_top; | |
570 | /* Other BookE, we assume the first GB is bolted */ | |
571 | return 1ul << 30; | |
572 | #else | |
573 | /* BookS, the first segment is bolted */ | |
574 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) | |
095c7965 | 575 | return 1UL << SID_SHIFT_1T; |
095c7965 | 576 | return 1UL << SID_SHIFT; |
40bd587a | 577 | #endif |
095c7965 AB |
578 | } |
579 | ||
40ef8cbc PM |
580 | static void __init irqstack_early_init(void) |
581 | { | |
40bd587a | 582 | u64 limit = safe_stack_limit(); |
40ef8cbc PM |
583 | unsigned int i; |
584 | ||
585 | /* | |
8f4da26e AB |
586 | * Interrupt stacks must be in the first segment since we |
587 | * cannot afford to take SLB misses on them. | |
40ef8cbc | 588 | */ |
0e551954 | 589 | for_each_possible_cpu(i) { |
3c726f8d | 590 | softirq_ctx[i] = (struct thread_info *) |
95f72d1e | 591 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 592 | THREAD_SIZE, limit)); |
3c726f8d | 593 | hardirq_ctx[i] = (struct thread_info *) |
95f72d1e | 594 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 595 | THREAD_SIZE, limit)); |
40ef8cbc PM |
596 | } |
597 | } | |
40ef8cbc | 598 | |
2d27cfd3 BH |
599 | #ifdef CONFIG_PPC_BOOK3E |
600 | static void __init exc_lvl_early_init(void) | |
601 | { | |
602 | unsigned int i; | |
160c7324 | 603 | unsigned long sp; |
2d27cfd3 BH |
604 | |
605 | for_each_possible_cpu(i) { | |
160c7324 TC |
606 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); |
607 | critirq_ctx[i] = (struct thread_info *)__va(sp); | |
608 | paca[i].crit_kstack = __va(sp + THREAD_SIZE); | |
609 | ||
610 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); | |
611 | dbgirq_ctx[i] = (struct thread_info *)__va(sp); | |
612 | paca[i].dbg_kstack = __va(sp + THREAD_SIZE); | |
613 | ||
614 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); | |
615 | mcheckirq_ctx[i] = (struct thread_info *)__va(sp); | |
616 | paca[i].mc_kstack = __va(sp + THREAD_SIZE); | |
2d27cfd3 | 617 | } |
d36b4c4f KG |
618 | |
619 | if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) | |
565c2f24 | 620 | patch_exception(0x040, exc_debug_debug_book3e); |
2d27cfd3 BH |
621 | } |
622 | #else | |
623 | #define exc_lvl_early_init() | |
624 | #endif | |
625 | ||
40ef8cbc PM |
626 | /* |
627 | * Stack space used when we detect a bad kernel stack pointer, and | |
729b0f71 MS |
628 | * early in SMP boots before relocation is enabled. Exclusive emergency |
629 | * stack for machine checks. | |
40ef8cbc PM |
630 | */ |
631 | static void __init emergency_stack_init(void) | |
632 | { | |
095c7965 | 633 | u64 limit; |
40ef8cbc PM |
634 | unsigned int i; |
635 | ||
636 | /* | |
637 | * Emergency stacks must be under 256MB, we cannot afford to take | |
638 | * SLB misses on them. The ABI also requires them to be 128-byte | |
639 | * aligned. | |
640 | * | |
641 | * Since we use these as temporary stacks during secondary CPU | |
642 | * bringup, we need to get at them in real mode. This means they | |
643 | * must also be within the RMO region. | |
644 | */ | |
40bd587a | 645 | limit = min(safe_stack_limit(), ppc64_rma_size); |
40ef8cbc | 646 | |
3243d874 ME |
647 | for_each_possible_cpu(i) { |
648 | unsigned long sp; | |
95f72d1e | 649 | sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); |
3243d874 ME |
650 | sp += THREAD_SIZE; |
651 | paca[i].emergency_sp = __va(sp); | |
729b0f71 MS |
652 | |
653 | #ifdef CONFIG_PPC_BOOK3S_64 | |
654 | /* emergency stack for machine check exception handling. */ | |
655 | sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit); | |
656 | sp += THREAD_SIZE; | |
657 | paca[i].mc_emergency_sp = __va(sp); | |
658 | #endif | |
3243d874 | 659 | } |
40ef8cbc PM |
660 | } |
661 | ||
40ef8cbc | 662 | /* |
0f6b77ca AIB |
663 | * Called into from start_kernel this initializes bootmem, which is used |
664 | * to manage page allocation until mem_init is called. | |
40ef8cbc PM |
665 | */ |
666 | void __init setup_arch(char **cmdline_p) | |
667 | { | |
3e47d147 | 668 | *cmdline_p = boot_command_line; |
40ef8cbc PM |
669 | |
670 | /* | |
671 | * Set cache line size based on type of cpu as a default. | |
672 | * Systems with OF can look in the properties on the cpu node(s) | |
673 | * for a possibly more accurate value. | |
674 | */ | |
675 | dcache_bsize = ppc64_caches.dline_size; | |
676 | icache_bsize = ppc64_caches.iline_size; | |
677 | ||
40ef8cbc | 678 | if (ppc_md.panic) |
7e990266 | 679 | setup_panic(); |
40ef8cbc | 680 | |
4846c5de | 681 | init_mm.start_code = (unsigned long)_stext; |
40ef8cbc PM |
682 | init_mm.end_code = (unsigned long) _etext; |
683 | init_mm.end_data = (unsigned long) _edata; | |
684 | init_mm.brk = klimit; | |
5c1f6ee9 AK |
685 | #ifdef CONFIG_PPC_64K_PAGES |
686 | init_mm.context.pte_frag = NULL; | |
687 | #endif | |
40ef8cbc | 688 | irqstack_early_init(); |
2d27cfd3 | 689 | exc_lvl_early_init(); |
40ef8cbc PM |
690 | emergency_stack_init(); |
691 | ||
40ef8cbc PM |
692 | /* set up the bootmem stuff with available memory */ |
693 | do_init_bootmem(); | |
694 | sparse_init(); | |
695 | ||
0458060c PM |
696 | #ifdef CONFIG_DUMMY_CONSOLE |
697 | conswitchp = &dummy_con; | |
698 | #endif | |
699 | ||
38db7e74 GL |
700 | if (ppc_md.setup_arch) |
701 | ppc_md.setup_arch(); | |
40ef8cbc | 702 | |
40ef8cbc | 703 | paging_init(); |
6f0ef0f5 BH |
704 | |
705 | /* Initialize the MMU context management stuff */ | |
706 | mmu_context_init(); | |
707 | ||
61e2390e MN |
708 | /* Interrupt code needs to be 64K-aligned */ |
709 | if ((unsigned long)_stext & 0xffff) | |
710 | panic("Kernelbase not 64K-aligned (0x%lx)!\n", | |
711 | (unsigned long)_stext); | |
40ef8cbc PM |
712 | } |
713 | ||
7a0268fa | 714 | #ifdef CONFIG_SMP |
c2a7e818 TH |
715 | #define PCPU_DYN_SIZE () |
716 | ||
717 | static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) | |
7a0268fa | 718 | { |
c2a7e818 TH |
719 | return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align, |
720 | __pa(MAX_DMA_ADDRESS)); | |
721 | } | |
7a0268fa | 722 | |
c2a7e818 TH |
723 | static void __init pcpu_fc_free(void *ptr, size_t size) |
724 | { | |
725 | free_bootmem(__pa(ptr), size); | |
726 | } | |
7a0268fa | 727 | |
c2a7e818 TH |
728 | static int pcpu_cpu_distance(unsigned int from, unsigned int to) |
729 | { | |
730 | if (cpu_to_node(from) == cpu_to_node(to)) | |
731 | return LOCAL_DISTANCE; | |
732 | else | |
733 | return REMOTE_DISTANCE; | |
734 | } | |
735 | ||
ae01f84b AB |
736 | unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; |
737 | EXPORT_SYMBOL(__per_cpu_offset); | |
738 | ||
c2a7e818 TH |
739 | void __init setup_per_cpu_areas(void) |
740 | { | |
741 | const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; | |
742 | size_t atom_size; | |
743 | unsigned long delta; | |
744 | unsigned int cpu; | |
745 | int rc; | |
746 | ||
747 | /* | |
748 | * Linear mapping is one of 4K, 1M and 16M. For 4K, no need | |
749 | * to group units. For larger mappings, use 1M atom which | |
750 | * should be large enough to contain a number of units. | |
751 | */ | |
752 | if (mmu_linear_psize == MMU_PAGE_4K) | |
753 | atom_size = PAGE_SIZE; | |
754 | else | |
755 | atom_size = 1 << 20; | |
756 | ||
757 | rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, | |
758 | pcpu_fc_alloc, pcpu_fc_free); | |
759 | if (rc < 0) | |
760 | panic("cannot initialize percpu area (err=%d)", rc); | |
761 | ||
762 | delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; | |
ae01f84b AB |
763 | for_each_possible_cpu(cpu) { |
764 | __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; | |
765 | paca[cpu].data_offset = __per_cpu_offset[cpu]; | |
766 | } | |
7a0268fa AB |
767 | } |
768 | #endif | |
4cb3cee0 | 769 | |
a5d86257 AB |
770 | #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE |
771 | unsigned long memory_block_size_bytes(void) | |
772 | { | |
773 | if (ppc_md.memory_block_size) | |
774 | return ppc_md.memory_block_size(); | |
775 | ||
776 | return MIN_MEMORY_BLOCK_SIZE; | |
777 | } | |
778 | #endif | |
4cb3cee0 | 779 | |
ecd73cc5 | 780 | #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) |
4cb3cee0 BH |
781 | struct ppc_pci_io ppc_pci_io; |
782 | EXPORT_SYMBOL(ppc_pci_io); | |
ecd73cc5 | 783 | #endif |