Commit | Line | Data |
---|---|---|
40ef8cbc PM |
1 | /* |
2 | * | |
3 | * Common boot and setup code. | |
4 | * | |
5 | * Copyright (C) 2001 PPC64 Team, IBM Corp | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
7191b615 | 13 | #define DEBUG |
40ef8cbc | 14 | |
4b16f8e2 | 15 | #include <linux/export.h> |
40ef8cbc PM |
16 | #include <linux/string.h> |
17 | #include <linux/sched.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/reboot.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/initrd.h> | |
40ef8cbc PM |
23 | #include <linux/seq_file.h> |
24 | #include <linux/ioport.h> | |
25 | #include <linux/console.h> | |
26 | #include <linux/utsname.h> | |
27 | #include <linux/tty.h> | |
28 | #include <linux/root_dev.h> | |
29 | #include <linux/notifier.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/unistd.h> | |
32 | #include <linux/serial.h> | |
33 | #include <linux/serial_8250.h> | |
7a0268fa | 34 | #include <linux/bootmem.h> |
12d04eef | 35 | #include <linux/pci.h> |
945feb17 | 36 | #include <linux/lockdep.h> |
95f72d1e | 37 | #include <linux/memblock.h> |
a5d86257 | 38 | #include <linux/memory.h> |
c54b2bf1 | 39 | #include <linux/nmi.h> |
a6146888 | 40 | |
40ef8cbc | 41 | #include <asm/io.h> |
0cc4746c | 42 | #include <asm/kdump.h> |
40ef8cbc PM |
43 | #include <asm/prom.h> |
44 | #include <asm/processor.h> | |
45 | #include <asm/pgtable.h> | |
40ef8cbc PM |
46 | #include <asm/smp.h> |
47 | #include <asm/elf.h> | |
48 | #include <asm/machdep.h> | |
49 | #include <asm/paca.h> | |
40ef8cbc PM |
50 | #include <asm/time.h> |
51 | #include <asm/cputable.h> | |
5a61ef74 | 52 | #include <asm/dt_cpu_ftrs.h> |
40ef8cbc PM |
53 | #include <asm/sections.h> |
54 | #include <asm/btext.h> | |
55 | #include <asm/nvram.h> | |
56 | #include <asm/setup.h> | |
40ef8cbc PM |
57 | #include <asm/rtas.h> |
58 | #include <asm/iommu.h> | |
59 | #include <asm/serial.h> | |
60 | #include <asm/cache.h> | |
61 | #include <asm/page.h> | |
62 | #include <asm/mmu.h> | |
40ef8cbc | 63 | #include <asm/firmware.h> |
f78541dc | 64 | #include <asm/xmon.h> |
dcad47fc | 65 | #include <asm/udbg.h> |
593e537b | 66 | #include <asm/kexec.h> |
d36b4c4f | 67 | #include <asm/code-patching.h> |
5d31a96e | 68 | #include <asm/livepatch.h> |
d3cbff1b | 69 | #include <asm/opal.h> |
b1923caa | 70 | #include <asm/cputhreads.h> |
40ef8cbc PM |
71 | |
72 | #ifdef DEBUG | |
73 | #define DBG(fmt...) udbg_printf(fmt) | |
74 | #else | |
75 | #define DBG(fmt...) | |
76 | #endif | |
77 | ||
8246aca7 | 78 | int spinning_secondaries; |
40ef8cbc PM |
79 | u64 ppc64_pft_size; |
80 | ||
dabcafd3 | 81 | struct ppc64_caches ppc64_caches = { |
e2827fe5 BH |
82 | .l1d = { |
83 | .block_size = 0x40, | |
84 | .log_block_size = 6, | |
85 | }, | |
86 | .l1i = { | |
87 | .block_size = 0x40, | |
88 | .log_block_size = 6 | |
89 | }, | |
dabcafd3 | 90 | }; |
40ef8cbc PM |
91 | EXPORT_SYMBOL_GPL(ppc64_caches); |
92 | ||
28efc35f | 93 | #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) |
b1923caa | 94 | void __init setup_tlb_core_data(void) |
28efc35f SW |
95 | { |
96 | int cpu; | |
97 | ||
82d86de2 SW |
98 | BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); |
99 | ||
28efc35f SW |
100 | for_each_possible_cpu(cpu) { |
101 | int first = cpu_first_thread_sibling(cpu); | |
102 | ||
d9e1831a SW |
103 | /* |
104 | * If we boot via kdump on a non-primary thread, | |
105 | * make sure we point at the thread that actually | |
106 | * set up this TLB. | |
107 | */ | |
108 | if (cpu_first_thread_sibling(boot_cpuid) == first) | |
109 | first = boot_cpuid; | |
110 | ||
28efc35f SW |
111 | paca[cpu].tcd_ptr = &paca[first].tcd; |
112 | ||
113 | /* | |
114 | * If we have threads, we need either tlbsrx. | |
115 | * or e6500 tablewalk mode, or else TLB handlers | |
116 | * will be racy and could produce duplicate entries. | |
0d2b5cdc | 117 | * Should we panic instead? |
28efc35f | 118 | */ |
0d2b5cdc ME |
119 | WARN_ONCE(smt_enabled_at_boot >= 2 && |
120 | !mmu_has_feature(MMU_FTR_USE_TLBRSRV) && | |
121 | book3e_htw_mode != PPC_HTW_E6500, | |
122 | "%s: unsupported MMU configuration\n", __func__); | |
28efc35f SW |
123 | } |
124 | } | |
28efc35f SW |
125 | #endif |
126 | ||
40ef8cbc PM |
127 | #ifdef CONFIG_SMP |
128 | ||
954e6da5 | 129 | static char *smt_enabled_cmdline; |
40ef8cbc PM |
130 | |
131 | /* Look for ibm,smt-enabled OF option */ | |
b1923caa | 132 | void __init check_smt_enabled(void) |
40ef8cbc PM |
133 | { |
134 | struct device_node *dn; | |
a7f67bdf | 135 | const char *smt_option; |
40ef8cbc | 136 | |
954e6da5 NF |
137 | /* Default to enabling all threads */ |
138 | smt_enabled_at_boot = threads_per_core; | |
40ef8cbc | 139 | |
954e6da5 NF |
140 | /* Allow the command line to overrule the OF option */ |
141 | if (smt_enabled_cmdline) { | |
142 | if (!strcmp(smt_enabled_cmdline, "on")) | |
143 | smt_enabled_at_boot = threads_per_core; | |
144 | else if (!strcmp(smt_enabled_cmdline, "off")) | |
145 | smt_enabled_at_boot = 0; | |
146 | else { | |
1618bd53 | 147 | int smt; |
954e6da5 NF |
148 | int rc; |
149 | ||
1618bd53 | 150 | rc = kstrtoint(smt_enabled_cmdline, 10, &smt); |
954e6da5 NF |
151 | if (!rc) |
152 | smt_enabled_at_boot = | |
1618bd53 | 153 | min(threads_per_core, smt); |
954e6da5 NF |
154 | } |
155 | } else { | |
156 | dn = of_find_node_by_path("/options"); | |
157 | if (dn) { | |
158 | smt_option = of_get_property(dn, "ibm,smt-enabled", | |
159 | NULL); | |
160 | ||
161 | if (smt_option) { | |
162 | if (!strcmp(smt_option, "on")) | |
163 | smt_enabled_at_boot = threads_per_core; | |
164 | else if (!strcmp(smt_option, "off")) | |
165 | smt_enabled_at_boot = 0; | |
166 | } | |
167 | ||
168 | of_node_put(dn); | |
169 | } | |
170 | } | |
40ef8cbc PM |
171 | } |
172 | ||
173 | /* Look for smt-enabled= cmdline option */ | |
174 | static int __init early_smt_enabled(char *p) | |
175 | { | |
954e6da5 | 176 | smt_enabled_cmdline = p; |
40ef8cbc PM |
177 | return 0; |
178 | } | |
179 | early_param("smt-enabled", early_smt_enabled); | |
180 | ||
40ef8cbc PM |
181 | #endif /* CONFIG_SMP */ |
182 | ||
25e13814 | 183 | /** Fix up paca fields required for the boot cpu */ |
009776ba | 184 | static void __init fixup_boot_paca(void) |
25e13814 ME |
185 | { |
186 | /* The boot cpu is started */ | |
187 | get_paca()->cpu_start = 1; | |
188 | /* Allow percpu accesses to work until we setup percpu data */ | |
189 | get_paca()->data_offset = 0; | |
190 | } | |
191 | ||
009776ba | 192 | static void __init configure_exceptions(void) |
8f619b54 | 193 | { |
633440f1 | 194 | /* |
d3cbff1b BH |
195 | * Setup the trampolines from the lowmem exception vectors |
196 | * to the kdump kernel when not using a relocatable kernel. | |
633440f1 | 197 | */ |
d3cbff1b BH |
198 | setup_kdump_trampoline(); |
199 | ||
200 | /* Under a PAPR hypervisor, we need hypercalls */ | |
201 | if (firmware_has_feature(FW_FEATURE_SET_MODE)) { | |
202 | /* Enable AIL if possible */ | |
203 | pseries_enable_reloc_on_exc(); | |
204 | ||
205 | /* | |
206 | * Tell the hypervisor that we want our exceptions to | |
207 | * be taken in little endian mode. | |
208 | * | |
209 | * We don't call this for big endian as our calling convention | |
210 | * makes us always enter in BE, and the call may fail under | |
211 | * some circumstances with kdump. | |
212 | */ | |
213 | #ifdef __LITTLE_ENDIAN__ | |
214 | pseries_little_endian_exceptions(); | |
215 | #endif | |
216 | } else { | |
217 | /* Set endian mode using OPAL */ | |
218 | if (firmware_has_feature(FW_FEATURE_OPAL)) | |
219 | opal_configure_cores(); | |
220 | ||
c0a36013 | 221 | /* AIL on native is done in cpu_ready_for_interrupts() */ |
8f619b54 BH |
222 | } |
223 | } | |
224 | ||
d3cbff1b BH |
225 | static void cpu_ready_for_interrupts(void) |
226 | { | |
c0a36013 BH |
227 | /* |
228 | * Enable AIL if supported, and we are in hypervisor mode. This | |
229 | * is called once for every processor. | |
230 | * | |
231 | * If we are not in hypervisor mode the job is done once for | |
232 | * the whole partition in configure_exceptions(). | |
233 | */ | |
5511a45f ME |
234 | if (cpu_has_feature(CPU_FTR_HVMODE) && |
235 | cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
c0a36013 BH |
236 | unsigned long lpcr = mfspr(SPRN_LPCR); |
237 | mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3); | |
238 | } | |
239 | ||
7ed23e1b BH |
240 | /* |
241 | * Fixup HFSCR:TM based on CPU features. The bit is set by our | |
242 | * early asm init because at that point we haven't updated our | |
243 | * CPU features from firmware and device-tree. Here we have, | |
244 | * so let's do it. | |
245 | */ | |
246 | if (cpu_has_feature(CPU_FTR_HVMODE) && !cpu_has_feature(CPU_FTR_TM_COMP)) | |
247 | mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM); | |
248 | ||
d3cbff1b BH |
249 | /* Set IR and DR in PACA MSR */ |
250 | get_paca()->kernel_msr = MSR_KERNEL; | |
251 | } | |
252 | ||
40ef8cbc PM |
253 | /* |
254 | * Early initialization entry point. This is called by head.S | |
255 | * with MMU translation disabled. We rely on the "feature" of | |
256 | * the CPU that ignores the top 2 bits of the address in real | |
257 | * mode so we can access kernel globals normally provided we | |
258 | * only toy with things in the RMO region. From here, we do | |
95f72d1e | 259 | * some early parsing of the device-tree to setup out MEMBLOCK |
40ef8cbc PM |
260 | * data structures, and allocate & initialize the hash table |
261 | * and segment tables so we can start running with translation | |
262 | * enabled. | |
263 | * | |
264 | * It is this function which will call the probe() callback of | |
265 | * the various platform types and copy the matching one to the | |
266 | * global ppc_md structure. Your platform can eventually do | |
267 | * some very early initializations from the probe() routine, but | |
268 | * this is not recommended, be very careful as, for example, the | |
269 | * device-tree is not accessible via normal means at this point. | |
270 | */ | |
271 | ||
272 | void __init early_setup(unsigned long dt_ptr) | |
273 | { | |
6a7e4064 GL |
274 | static __initdata struct paca_struct boot_paca; |
275 | ||
24d96495 BH |
276 | /* -------- printk is _NOT_ safe to use here ! ------- */ |
277 | ||
5a61ef74 NP |
278 | /* Try new device tree based feature discovery ... */ |
279 | if (!dt_cpu_ftrs_init(__va(dt_ptr))) | |
280 | /* Otherwise use the old style CPU table */ | |
281 | identify_cpu(0, mfspr(SPRN_PVR)); | |
42c4aaad | 282 | |
33dbcf72 | 283 | /* Assume we're on cpu 0 for now. Don't write to the paca yet! */ |
1426d5a3 ME |
284 | initialise_paca(&boot_paca, 0); |
285 | setup_paca(&boot_paca); | |
25e13814 | 286 | fixup_boot_paca(); |
33dbcf72 | 287 | |
24d96495 BH |
288 | /* -------- printk is now safe to use ------- */ |
289 | ||
f2fd2513 BH |
290 | /* Enable early debugging if any specified (see udbg.h) */ |
291 | udbg_early_init(); | |
292 | ||
e8222502 | 293 | DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr); |
40ef8cbc | 294 | |
40ef8cbc | 295 | /* |
3c607ce2 LV |
296 | * Do early initialization using the flattened device |
297 | * tree, such as retrieving the physical memory map or | |
298 | * calculating/retrieving the hash table size. | |
40ef8cbc PM |
299 | */ |
300 | early_init_devtree(__va(dt_ptr)); | |
301 | ||
4df20460 | 302 | /* Now we know the logical id of our boot cpu, setup the paca. */ |
1426d5a3 | 303 | setup_paca(&paca[boot_cpuid]); |
25e13814 | 304 | fixup_boot_paca(); |
4df20460 | 305 | |
63c254a5 | 306 | /* |
d3cbff1b BH |
307 | * Configure exception handlers. This include setting up trampolines |
308 | * if needed, setting exception endian mode, etc... | |
63c254a5 | 309 | */ |
d3cbff1b | 310 | configure_exceptions(); |
0cc4746c | 311 | |
c4bd6cb8 BH |
312 | /* Apply all the dynamic patching */ |
313 | apply_feature_fixups(); | |
97f6e0cc | 314 | setup_feature_keys(); |
c4bd6cb8 | 315 | |
9e8066f3 ME |
316 | /* Initialize the hash table or TLB handling */ |
317 | early_init_mmu(); | |
318 | ||
a944a9c4 BH |
319 | /* |
320 | * At this point, we can let interrupts switch to virtual mode | |
321 | * (the MMU has been setup), so adjust the MSR in the PACA to | |
8f619b54 | 322 | * have IR and DR set and enable AIL if it exists |
a944a9c4 | 323 | */ |
8f619b54 | 324 | cpu_ready_for_interrupts(); |
a944a9c4 | 325 | |
40ef8cbc | 326 | DBG(" <- early_setup()\n"); |
7191b615 BH |
327 | |
328 | #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX | |
329 | /* | |
330 | * This needs to be done *last* (after the above DBG() even) | |
331 | * | |
332 | * Right after we return from this function, we turn on the MMU | |
333 | * which means the real-mode access trick that btext does will | |
334 | * no longer work, it needs to switch to using a real MMU | |
335 | * mapping. This call will ensure that it does | |
336 | */ | |
337 | btext_map(); | |
338 | #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ | |
40ef8cbc PM |
339 | } |
340 | ||
799d6046 PM |
341 | #ifdef CONFIG_SMP |
342 | void early_setup_secondary(void) | |
343 | { | |
103b7827 | 344 | /* Mark interrupts disabled in PACA */ |
757c74d2 | 345 | get_paca()->soft_enabled = 0; |
799d6046 | 346 | |
757c74d2 BH |
347 | /* Initialize the hash table or TLB handling */ |
348 | early_init_mmu_secondary(); | |
a944a9c4 BH |
349 | |
350 | /* | |
351 | * At this point, we can let interrupts switch to virtual mode | |
352 | * (the MMU has been setup), so adjust the MSR in the PACA to | |
353 | * have IR and DR set. | |
354 | */ | |
8f619b54 | 355 | cpu_ready_for_interrupts(); |
799d6046 PM |
356 | } |
357 | ||
358 | #endif /* CONFIG_SMP */ | |
40ef8cbc | 359 | |
da665885 | 360 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE) |
567cf94d SW |
361 | static bool use_spinloop(void) |
362 | { | |
363 | if (!IS_ENABLED(CONFIG_PPC_BOOK3E)) | |
364 | return true; | |
365 | ||
366 | /* | |
367 | * When book3e boots from kexec, the ePAPR spin table does | |
368 | * not get used. | |
369 | */ | |
370 | return of_property_read_bool(of_chosen, "linux,booted-from-kexec"); | |
371 | } | |
372 | ||
b8f51021 ME |
373 | void smp_release_cpus(void) |
374 | { | |
758438a7 | 375 | unsigned long *ptr; |
9d07bc84 | 376 | int i; |
b8f51021 | 377 | |
567cf94d SW |
378 | if (!use_spinloop()) |
379 | return; | |
380 | ||
b8f51021 ME |
381 | DBG(" -> smp_release_cpus()\n"); |
382 | ||
383 | /* All secondary cpus are spinning on a common spinloop, release them | |
384 | * all now so they can start to spin on their individual paca | |
385 | * spinloops. For non SMP kernels, the secondary cpus never get out | |
386 | * of the common spinloop. | |
1f6a93e4 | 387 | */ |
b8f51021 | 388 | |
758438a7 ME |
389 | ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop |
390 | - PHYSICAL_START); | |
2751b628 | 391 | *ptr = ppc_function_entry(generic_secondary_smp_init); |
9d07bc84 BH |
392 | |
393 | /* And wait a bit for them to catch up */ | |
394 | for (i = 0; i < 100000; i++) { | |
395 | mb(); | |
396 | HMT_low(); | |
7ac87abb | 397 | if (spinning_secondaries == 0) |
9d07bc84 BH |
398 | break; |
399 | udelay(1); | |
400 | } | |
7ac87abb | 401 | DBG("spinning_secondaries = %d\n", spinning_secondaries); |
b8f51021 ME |
402 | |
403 | DBG(" <- smp_release_cpus()\n"); | |
404 | } | |
da665885 | 405 | #endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */ |
b8f51021 | 406 | |
40ef8cbc | 407 | /* |
799d6046 PM |
408 | * Initialize some remaining members of the ppc64_caches and systemcfg |
409 | * structures | |
40ef8cbc PM |
410 | * (at least until we get rid of them completely). This is mostly some |
411 | * cache informations about the CPU that will be used by cache flush | |
412 | * routines and/or provided to userland | |
413 | */ | |
e2827fe5 BH |
414 | |
415 | static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize, | |
416 | u32 bsize, u32 sets) | |
417 | { | |
418 | info->size = size; | |
419 | info->sets = sets; | |
420 | info->line_size = lsize; | |
421 | info->block_size = bsize; | |
422 | info->log_block_size = __ilog2(bsize); | |
6ba422c7 AB |
423 | if (bsize) |
424 | info->blocks_per_page = PAGE_SIZE / bsize; | |
425 | else | |
426 | info->blocks_per_page = 0; | |
98a5f361 BH |
427 | |
428 | if (sets == 0) | |
429 | info->assoc = 0xffff; | |
430 | else | |
431 | info->assoc = size / (sets * lsize); | |
e2827fe5 BH |
432 | } |
433 | ||
434 | static bool __init parse_cache_info(struct device_node *np, | |
435 | bool icache, | |
436 | struct ppc_cache_info *info) | |
437 | { | |
438 | static const char *ipropnames[] __initdata = { | |
439 | "i-cache-size", | |
440 | "i-cache-sets", | |
441 | "i-cache-block-size", | |
442 | "i-cache-line-size", | |
443 | }; | |
444 | static const char *dpropnames[] __initdata = { | |
445 | "d-cache-size", | |
446 | "d-cache-sets", | |
447 | "d-cache-block-size", | |
448 | "d-cache-line-size", | |
449 | }; | |
450 | const char **propnames = icache ? ipropnames : dpropnames; | |
451 | const __be32 *sizep, *lsizep, *bsizep, *setsp; | |
452 | u32 size, lsize, bsize, sets; | |
453 | bool success = true; | |
454 | ||
455 | size = 0; | |
456 | sets = -1u; | |
457 | lsize = bsize = cur_cpu_spec->dcache_bsize; | |
458 | sizep = of_get_property(np, propnames[0], NULL); | |
459 | if (sizep != NULL) | |
460 | size = be32_to_cpu(*sizep); | |
461 | setsp = of_get_property(np, propnames[1], NULL); | |
462 | if (setsp != NULL) | |
463 | sets = be32_to_cpu(*setsp); | |
464 | bsizep = of_get_property(np, propnames[2], NULL); | |
465 | lsizep = of_get_property(np, propnames[3], NULL); | |
466 | if (bsizep == NULL) | |
467 | bsizep = lsizep; | |
468 | if (lsizep != NULL) | |
469 | lsize = be32_to_cpu(*lsizep); | |
470 | if (bsizep != NULL) | |
471 | bsize = be32_to_cpu(*bsizep); | |
472 | if (sizep == NULL || bsizep == NULL || lsizep == NULL) | |
473 | success = false; | |
474 | ||
475 | /* | |
476 | * OF is weird .. it represents fully associative caches | |
477 | * as "1 way" which doesn't make much sense and doesn't | |
478 | * leave room for direct mapped. We'll assume that 0 | |
479 | * in OF means direct mapped for that reason. | |
480 | */ | |
481 | if (sets == 1) | |
482 | sets = 0; | |
483 | else if (sets == 0) | |
484 | sets = 1; | |
485 | ||
486 | init_cache_info(info, size, lsize, bsize, sets); | |
487 | ||
488 | return success; | |
489 | } | |
490 | ||
b1923caa | 491 | void __init initialize_cache_info(void) |
40ef8cbc | 492 | { |
608b4214 BH |
493 | struct device_node *cpu = NULL, *l2, *l3 = NULL; |
494 | u32 pvr; | |
40ef8cbc PM |
495 | |
496 | DBG(" -> initialize_cache_info()\n"); | |
497 | ||
608b4214 BH |
498 | /* |
499 | * All shipping POWER8 machines have a firmware bug that | |
500 | * puts incorrect information in the device-tree. This will | |
501 | * be (hopefully) fixed for future chips but for now hard | |
502 | * code the values if we are running on one of these | |
503 | */ | |
504 | pvr = PVR_VER(mfspr(SPRN_PVR)); | |
505 | if (pvr == PVR_POWER8 || pvr == PVR_POWER8E || | |
506 | pvr == PVR_POWER8NVL) { | |
507 | /* size lsize blk sets */ | |
508 | init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32); | |
509 | init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64); | |
510 | init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512); | |
511 | init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192); | |
512 | } else | |
513 | cpu = of_find_node_by_type(NULL, "cpu"); | |
40ef8cbc | 514 | |
e2827fe5 BH |
515 | /* |
516 | * We're assuming *all* of the CPUs have the same | |
517 | * d-cache and i-cache sizes... -Peter | |
518 | */ | |
65e01f38 BH |
519 | if (cpu) { |
520 | if (!parse_cache_info(cpu, false, &ppc64_caches.l1d)) | |
e2827fe5 BH |
521 | DBG("Argh, can't find dcache properties !\n"); |
522 | ||
65e01f38 | 523 | if (!parse_cache_info(cpu, true, &ppc64_caches.l1i)) |
e2827fe5 | 524 | DBG("Argh, can't find icache properties !\n"); |
65e01f38 BH |
525 | |
526 | /* | |
527 | * Try to find the L2 and L3 if any. Assume they are | |
528 | * unified and use the D-side properties. | |
529 | */ | |
530 | l2 = of_find_next_cache_node(cpu); | |
531 | of_node_put(cpu); | |
532 | if (l2) { | |
533 | parse_cache_info(l2, false, &ppc64_caches.l2); | |
534 | l3 = of_find_next_cache_node(l2); | |
535 | of_node_put(l2); | |
536 | } | |
537 | if (l3) { | |
538 | parse_cache_info(l3, false, &ppc64_caches.l3); | |
539 | of_node_put(l3); | |
540 | } | |
40ef8cbc PM |
541 | } |
542 | ||
9df549af | 543 | /* For use by binfmt_elf */ |
e2827fe5 BH |
544 | dcache_bsize = ppc64_caches.l1d.block_size; |
545 | icache_bsize = ppc64_caches.l1i.block_size; | |
9df549af | 546 | |
5a61ef74 NP |
547 | cur_cpu_spec->dcache_bsize = dcache_bsize; |
548 | cur_cpu_spec->icache_bsize = icache_bsize; | |
549 | ||
40ef8cbc PM |
550 | DBG(" <- initialize_cache_info()\n"); |
551 | } | |
552 | ||
40bd587a BH |
553 | /* This returns the limit below which memory accesses to the linear |
554 | * mapping are guarnateed not to cause a TLB or SLB miss. This is | |
555 | * used to allocate interrupt or emergency stacks for which our | |
556 | * exception entry path doesn't deal with being interrupted. | |
557 | */ | |
009776ba | 558 | static __init u64 safe_stack_limit(void) |
095c7965 | 559 | { |
40bd587a BH |
560 | #ifdef CONFIG_PPC_BOOK3E |
561 | /* Freescale BookE bolts the entire linear mapping */ | |
562 | if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) | |
563 | return linear_map_top; | |
564 | /* Other BookE, we assume the first GB is bolted */ | |
565 | return 1ul << 30; | |
566 | #else | |
d5507190 NP |
567 | if (early_radix_enabled()) |
568 | return ULONG_MAX; | |
569 | ||
40bd587a BH |
570 | /* BookS, the first segment is bolted */ |
571 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) | |
095c7965 | 572 | return 1UL << SID_SHIFT_1T; |
095c7965 | 573 | return 1UL << SID_SHIFT; |
40bd587a | 574 | #endif |
095c7965 AB |
575 | } |
576 | ||
b1923caa | 577 | void __init irqstack_early_init(void) |
40ef8cbc | 578 | { |
40bd587a | 579 | u64 limit = safe_stack_limit(); |
40ef8cbc PM |
580 | unsigned int i; |
581 | ||
582 | /* | |
8f4da26e | 583 | * Interrupt stacks must be in the first segment since we |
d5507190 NP |
584 | * cannot afford to take SLB misses on them. They are not |
585 | * accessed in realmode. | |
40ef8cbc | 586 | */ |
0e551954 | 587 | for_each_possible_cpu(i) { |
3c726f8d | 588 | softirq_ctx[i] = (struct thread_info *) |
95f72d1e | 589 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 590 | THREAD_SIZE, limit)); |
3c726f8d | 591 | hardirq_ctx[i] = (struct thread_info *) |
95f72d1e | 592 | __va(memblock_alloc_base(THREAD_SIZE, |
095c7965 | 593 | THREAD_SIZE, limit)); |
40ef8cbc PM |
594 | } |
595 | } | |
40ef8cbc | 596 | |
2d27cfd3 | 597 | #ifdef CONFIG_PPC_BOOK3E |
b1923caa | 598 | void __init exc_lvl_early_init(void) |
2d27cfd3 BH |
599 | { |
600 | unsigned int i; | |
160c7324 | 601 | unsigned long sp; |
2d27cfd3 BH |
602 | |
603 | for_each_possible_cpu(i) { | |
160c7324 TC |
604 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); |
605 | critirq_ctx[i] = (struct thread_info *)__va(sp); | |
606 | paca[i].crit_kstack = __va(sp + THREAD_SIZE); | |
607 | ||
608 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); | |
609 | dbgirq_ctx[i] = (struct thread_info *)__va(sp); | |
610 | paca[i].dbg_kstack = __va(sp + THREAD_SIZE); | |
611 | ||
612 | sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE); | |
613 | mcheckirq_ctx[i] = (struct thread_info *)__va(sp); | |
614 | paca[i].mc_kstack = __va(sp + THREAD_SIZE); | |
2d27cfd3 | 615 | } |
d36b4c4f KG |
616 | |
617 | if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) | |
565c2f24 | 618 | patch_exception(0x040, exc_debug_debug_book3e); |
2d27cfd3 | 619 | } |
2d27cfd3 BH |
620 | #endif |
621 | ||
34f19ff1 NP |
622 | /* |
623 | * Emergency stacks are used for a range of things, from asynchronous | |
624 | * NMIs (system reset, machine check) to synchronous, process context. | |
625 | * We set preempt_count to zero, even though that isn't necessarily correct. To | |
626 | * get the right value we'd need to copy it from the previous thread_info, but | |
627 | * doing that might fault causing more problems. | |
628 | * TODO: what to do with accounting? | |
629 | */ | |
630 | static void emerg_stack_init_thread_info(struct thread_info *ti, int cpu) | |
631 | { | |
632 | ti->task = NULL; | |
633 | ti->cpu = cpu; | |
634 | ti->preempt_count = 0; | |
635 | ti->local_flags = 0; | |
636 | ti->flags = 0; | |
637 | klp_init_thread_info(ti); | |
638 | } | |
639 | ||
40ef8cbc PM |
640 | /* |
641 | * Stack space used when we detect a bad kernel stack pointer, and | |
729b0f71 MS |
642 | * early in SMP boots before relocation is enabled. Exclusive emergency |
643 | * stack for machine checks. | |
40ef8cbc | 644 | */ |
b1923caa | 645 | void __init emergency_stack_init(void) |
40ef8cbc | 646 | { |
095c7965 | 647 | u64 limit; |
40ef8cbc PM |
648 | unsigned int i; |
649 | ||
650 | /* | |
651 | * Emergency stacks must be under 256MB, we cannot afford to take | |
652 | * SLB misses on them. The ABI also requires them to be 128-byte | |
653 | * aligned. | |
654 | * | |
655 | * Since we use these as temporary stacks during secondary CPU | |
d5507190 NP |
656 | * bringup, machine check, system reset, and HMI, we need to get |
657 | * at them in real mode. This means they must also be within the RMO | |
658 | * region. | |
34f19ff1 NP |
659 | * |
660 | * The IRQ stacks allocated elsewhere in this file are zeroed and | |
661 | * initialized in kernel/irq.c. These are initialized here in order | |
662 | * to have emergency stacks available as early as possible. | |
40ef8cbc | 663 | */ |
40bd587a | 664 | limit = min(safe_stack_limit(), ppc64_rma_size); |
40ef8cbc | 665 | |
3243d874 | 666 | for_each_possible_cpu(i) { |
5d31a96e ME |
667 | struct thread_info *ti; |
668 | ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit)); | |
34f19ff1 NP |
669 | memset(ti, 0, THREAD_SIZE); |
670 | emerg_stack_init_thread_info(ti, i); | |
5d31a96e | 671 | paca[i].emergency_sp = (void *)ti + THREAD_SIZE; |
729b0f71 MS |
672 | |
673 | #ifdef CONFIG_PPC_BOOK3S_64 | |
b1ee8a3d NP |
674 | /* emergency stack for NMI exception handling. */ |
675 | ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit)); | |
34f19ff1 NP |
676 | memset(ti, 0, THREAD_SIZE); |
677 | emerg_stack_init_thread_info(ti, i); | |
b1ee8a3d NP |
678 | paca[i].nmi_emergency_sp = (void *)ti + THREAD_SIZE; |
679 | ||
729b0f71 | 680 | /* emergency stack for machine check exception handling. */ |
5d31a96e | 681 | ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit)); |
34f19ff1 NP |
682 | memset(ti, 0, THREAD_SIZE); |
683 | emerg_stack_init_thread_info(ti, i); | |
5d31a96e | 684 | paca[i].mc_emergency_sp = (void *)ti + THREAD_SIZE; |
729b0f71 | 685 | #endif |
3243d874 | 686 | } |
40ef8cbc PM |
687 | } |
688 | ||
7a0268fa | 689 | #ifdef CONFIG_SMP |
c2a7e818 TH |
690 | #define PCPU_DYN_SIZE () |
691 | ||
692 | static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align) | |
7a0268fa | 693 | { |
ba4a648f | 694 | return __alloc_bootmem_node(NODE_DATA(early_cpu_to_node(cpu)), size, align, |
c2a7e818 TH |
695 | __pa(MAX_DMA_ADDRESS)); |
696 | } | |
7a0268fa | 697 | |
c2a7e818 TH |
698 | static void __init pcpu_fc_free(void *ptr, size_t size) |
699 | { | |
700 | free_bootmem(__pa(ptr), size); | |
701 | } | |
7a0268fa | 702 | |
c2a7e818 TH |
703 | static int pcpu_cpu_distance(unsigned int from, unsigned int to) |
704 | { | |
ba4a648f | 705 | if (early_cpu_to_node(from) == early_cpu_to_node(to)) |
c2a7e818 TH |
706 | return LOCAL_DISTANCE; |
707 | else | |
708 | return REMOTE_DISTANCE; | |
709 | } | |
710 | ||
ae01f84b AB |
711 | unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; |
712 | EXPORT_SYMBOL(__per_cpu_offset); | |
713 | ||
c2a7e818 TH |
714 | void __init setup_per_cpu_areas(void) |
715 | { | |
716 | const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; | |
717 | size_t atom_size; | |
718 | unsigned long delta; | |
719 | unsigned int cpu; | |
720 | int rc; | |
721 | ||
722 | /* | |
723 | * Linear mapping is one of 4K, 1M and 16M. For 4K, no need | |
724 | * to group units. For larger mappings, use 1M atom which | |
725 | * should be large enough to contain a number of units. | |
726 | */ | |
727 | if (mmu_linear_psize == MMU_PAGE_4K) | |
728 | atom_size = PAGE_SIZE; | |
729 | else | |
730 | atom_size = 1 << 20; | |
731 | ||
732 | rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, | |
733 | pcpu_fc_alloc, pcpu_fc_free); | |
734 | if (rc < 0) | |
735 | panic("cannot initialize percpu area (err=%d)", rc); | |
736 | ||
737 | delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; | |
ae01f84b AB |
738 | for_each_possible_cpu(cpu) { |
739 | __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; | |
740 | paca[cpu].data_offset = __per_cpu_offset[cpu]; | |
741 | } | |
7a0268fa AB |
742 | } |
743 | #endif | |
4cb3cee0 | 744 | |
a5d86257 AB |
745 | #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE |
746 | unsigned long memory_block_size_bytes(void) | |
747 | { | |
748 | if (ppc_md.memory_block_size) | |
749 | return ppc_md.memory_block_size(); | |
750 | ||
751 | return MIN_MEMORY_BLOCK_SIZE; | |
752 | } | |
753 | #endif | |
4cb3cee0 | 754 | |
ecd73cc5 | 755 | #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) |
4cb3cee0 BH |
756 | struct ppc_pci_io ppc_pci_io; |
757 | EXPORT_SYMBOL(ppc_pci_io); | |
ecd73cc5 | 758 | #endif |
70412c55 NP |
759 | |
760 | #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF | |
761 | u64 hw_nmi_get_sample_period(int watchdog_thresh) | |
762 | { | |
763 | return ppc_proc_freq * watchdog_thresh; | |
764 | } | |
765 | #endif | |
766 | ||
767 | /* | |
768 | * The perf based hardlockup detector breaks PMU event based branches, so | |
769 | * disable it by default. Book3S has a soft-nmi hardlockup detector based | |
770 | * on the decrementer interrupt, so it does not suffer from this problem. | |
771 | * | |
772 | * It is likely to get false positives in VM guests, so disable it there | |
773 | * by default too. | |
774 | */ | |
775 | static int __init disable_hardlockup_detector(void) | |
776 | { | |
777 | #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF | |
778 | hardlockup_detector_disable(); | |
779 | #else | |
780 | if (firmware_has_feature(FW_FEATURE_LPAR)) | |
781 | hardlockup_detector_disable(); | |
782 | #endif | |
783 | ||
784 | return 0; | |
785 | } | |
786 | early_initcall(disable_hardlockup_detector); |