Commit | Line | Data |
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9b6b563c PM |
1 | /* |
2 | * Common prep/pmac/chrp boot and setup code. | |
3 | */ | |
4 | ||
9b6b563c PM |
5 | #include <linux/module.h> |
6 | #include <linux/string.h> | |
7 | #include <linux/sched.h> | |
8 | #include <linux/init.h> | |
9 | #include <linux/kernel.h> | |
10 | #include <linux/reboot.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/initrd.h> | |
13 | #include <linux/ide.h> | |
14 | #include <linux/tty.h> | |
15 | #include <linux/bootmem.h> | |
16 | #include <linux/seq_file.h> | |
17 | #include <linux/root_dev.h> | |
18 | #include <linux/cpu.h> | |
19 | #include <linux/console.h> | |
20 | ||
21 | #include <asm/residual.h> | |
22 | #include <asm/io.h> | |
23 | #include <asm/prom.h> | |
24 | #include <asm/processor.h> | |
25 | #include <asm/pgtable.h> | |
9b6b563c PM |
26 | #include <asm/setup.h> |
27 | #include <asm/amigappc.h> | |
28 | #include <asm/smp.h> | |
29 | #include <asm/elf.h> | |
30 | #include <asm/cputable.h> | |
31 | #include <asm/bootx.h> | |
32 | #include <asm/btext.h> | |
33 | #include <asm/machdep.h> | |
34 | #include <asm/uaccess.h> | |
35 | #include <asm/system.h> | |
36 | #include <asm/pmac_feature.h> | |
37 | #include <asm/sections.h> | |
38 | #include <asm/nvram.h> | |
39 | #include <asm/xmon.h> | |
6d7f58b0 | 40 | #include <asm/time.h> |
463ce0e1 | 41 | #include <asm/serial.h> |
51d3082f | 42 | #include <asm/udbg.h> |
9b6b563c | 43 | |
66ba135c SR |
44 | #include "setup.h" |
45 | ||
03501dab PM |
46 | #define DBG(fmt...) |
47 | ||
9b6b563c PM |
48 | #if defined CONFIG_KGDB |
49 | #include <asm/kgdb.h> | |
50 | #endif | |
51 | ||
9b6b563c PM |
52 | extern void bootx_init(unsigned long r4, unsigned long phys); |
53 | ||
9b6b563c PM |
54 | struct ide_machdep_calls ppc_ide_md; |
55 | ||
80579e1f PM |
56 | int boot_cpuid; |
57 | EXPORT_SYMBOL_GPL(boot_cpuid); | |
58 | int boot_cpuid_phys; | |
59 | ||
9b6b563c PM |
60 | unsigned long ISA_DMA_THRESHOLD; |
61 | unsigned int DMA_MODE_READ; | |
62 | unsigned int DMA_MODE_WRITE; | |
63 | ||
e574d238 PM |
64 | int have_of = 1; |
65 | ||
9b6b563c PM |
66 | #ifdef CONFIG_VGA_CONSOLE |
67 | unsigned long vgacon_remap_base; | |
68 | #endif | |
69 | ||
9b6b563c PM |
70 | /* |
71 | * These are used in binfmt_elf.c to put aux entries on the stack | |
72 | * for each elf executable being started. | |
73 | */ | |
74 | int dcache_bsize; | |
75 | int icache_bsize; | |
76 | int ucache_bsize; | |
77 | ||
9b6b563c PM |
78 | /* |
79 | * We're called here very early in the boot. We determine the machine | |
80 | * type and call the appropriate low-level setup functions. | |
81 | * -- Cort <cort@fsmlabs.com> | |
82 | * | |
83 | * Note that the kernel may be running at an address which is different | |
84 | * from the address that it was linked at, so we must use RELOC/PTRRELOC | |
85 | * to access static data (including strings). -- paulus | |
86 | */ | |
87 | unsigned long __init early_init(unsigned long dt_ptr) | |
88 | { | |
89 | unsigned long offset = reloc_offset(); | |
42c4aaad | 90 | struct cpu_spec *spec; |
9b6b563c | 91 | |
dd184343 PM |
92 | /* First zero the BSS -- use memset_io, some platforms don't have |
93 | * caches on yet */ | |
af308377 | 94 | memset_io((void __iomem *)PTRRELOC(&__bss_start), 0, _end - __bss_start); |
dd184343 | 95 | |
9b6b563c PM |
96 | /* |
97 | * Identify the CPU type and fix up code sections | |
98 | * that depend on which cpu we have. | |
99 | */ | |
974a76f5 | 100 | spec = identify_cpu(offset, mfspr(SPRN_PVR)); |
42c4aaad | 101 | |
0909c8c2 | 102 | do_feature_fixups(spec->cpu_features, |
42c4aaad BH |
103 | PTRRELOC(&__start___ftr_fixup), |
104 | PTRRELOC(&__stop___ftr_fixup)); | |
9b6b563c | 105 | |
9b6b563c PM |
106 | return KERNELBASE + offset; |
107 | } | |
108 | ||
9b6b563c | 109 | |
9b6b563c PM |
110 | /* |
111 | * Find out what kind of machine we're on and save any data we need | |
112 | * from the early boot process (devtree is copied on pmac by prom_init()). | |
113 | * This is called very early on the boot process, after a minimal | |
114 | * MMU environment has been set up but before MMU_init is called. | |
115 | */ | |
116 | void __init machine_init(unsigned long dt_ptr, unsigned long phys) | |
117 | { | |
51d3082f BH |
118 | /* If btext is enabled, we might have a BAT setup for early display, |
119 | * thus we do enable some very basic udbg output | |
120 | */ | |
121 | #ifdef CONFIG_BOOTX_TEXT | |
122 | udbg_putc = btext_drawchar; | |
123 | #endif | |
124 | ||
125 | /* Do some early initialization based on the flat device tree */ | |
9b6b563c PM |
126 | early_init_devtree(__va(dt_ptr)); |
127 | ||
e8222502 | 128 | probe_machine(); |
35499c01 | 129 | |
9b6b563c | 130 | #ifdef CONFIG_6xx |
a0652fc9 PM |
131 | if (cpu_has_feature(CPU_FTR_CAN_DOZE) || |
132 | cpu_has_feature(CPU_FTR_CAN_NAP)) | |
133 | ppc_md.power_save = ppc6xx_idle; | |
9b6b563c | 134 | #endif |
9b6b563c PM |
135 | |
136 | if (ppc_md.progress) | |
137 | ppc_md.progress("id mach(): done", 0x200); | |
138 | } | |
139 | ||
140 | #ifdef CONFIG_BOOKE_WDT | |
141 | /* Checks wdt=x and wdt_period=xx command-line option */ | |
142 | int __init early_parse_wdt(char *p) | |
143 | { | |
144 | if (p && strncmp(p, "0", 1) != 0) | |
145 | booke_wdt_enabled = 1; | |
146 | ||
147 | return 0; | |
148 | } | |
149 | early_param("wdt", early_parse_wdt); | |
150 | ||
151 | int __init early_parse_wdt_period (char *p) | |
152 | { | |
153 | if (p) | |
154 | booke_wdt_period = simple_strtoul(p, NULL, 0); | |
155 | ||
156 | return 0; | |
157 | } | |
158 | early_param("wdt_period", early_parse_wdt_period); | |
159 | #endif /* CONFIG_BOOKE_WDT */ | |
160 | ||
161 | /* Checks "l2cr=xxxx" command-line option */ | |
162 | int __init ppc_setup_l2cr(char *str) | |
163 | { | |
164 | if (cpu_has_feature(CPU_FTR_L2CR)) { | |
165 | unsigned long val = simple_strtoul(str, NULL, 0); | |
166 | printk(KERN_INFO "l2cr set to %lx\n", val); | |
167 | _set_L2CR(0); /* force invalidate by disable cache */ | |
168 | _set_L2CR(val); /* and enable it */ | |
169 | } | |
170 | return 1; | |
171 | } | |
172 | __setup("l2cr=", ppc_setup_l2cr); | |
173 | ||
174 | #ifdef CONFIG_GENERIC_NVRAM | |
175 | ||
176 | /* Generic nvram hooks used by drivers/char/gen_nvram.c */ | |
177 | unsigned char nvram_read_byte(int addr) | |
178 | { | |
179 | if (ppc_md.nvram_read_val) | |
180 | return ppc_md.nvram_read_val(addr); | |
181 | return 0xff; | |
182 | } | |
183 | EXPORT_SYMBOL(nvram_read_byte); | |
184 | ||
185 | void nvram_write_byte(unsigned char val, int addr) | |
186 | { | |
187 | if (ppc_md.nvram_write_val) | |
188 | ppc_md.nvram_write_val(addr, val); | |
189 | } | |
190 | EXPORT_SYMBOL(nvram_write_byte); | |
191 | ||
192 | void nvram_sync(void) | |
193 | { | |
194 | if (ppc_md.nvram_sync) | |
195 | ppc_md.nvram_sync(); | |
196 | } | |
197 | EXPORT_SYMBOL(nvram_sync); | |
198 | ||
199 | #endif /* CONFIG_NVRAM */ | |
200 | ||
201 | static struct cpu cpu_devices[NR_CPUS]; | |
202 | ||
203 | int __init ppc_init(void) | |
204 | { | |
205 | int i; | |
206 | ||
207 | /* clear the progress line */ | |
208 | if ( ppc_md.progress ) ppc_md.progress(" ", 0xffff); | |
209 | ||
210 | /* register CPU devices */ | |
0e551954 | 211 | for_each_possible_cpu(i) |
76b67ed9 | 212 | register_cpu(&cpu_devices[i], i); |
9b6b563c PM |
213 | |
214 | /* call platform init */ | |
215 | if (ppc_md.init != NULL) { | |
216 | ppc_md.init(); | |
217 | } | |
218 | return 0; | |
219 | } | |
220 | ||
221 | arch_initcall(ppc_init); | |
222 | ||
223 | /* Warning, IO base is not yet inited */ | |
224 | void __init setup_arch(char **cmdline_p) | |
225 | { | |
846f77b0 ME |
226 | *cmdline_p = cmd_line; |
227 | ||
9b6b563c PM |
228 | /* so udelay does something sensible, assume <= 1000 bogomips */ |
229 | loops_per_jiffy = 500000000 / HZ; | |
230 | ||
9b6b563c | 231 | unflatten_device_tree(); |
a82765b6 | 232 | check_for_initrd(); |
463ce0e1 BH |
233 | |
234 | if (ppc_md.init_early) | |
235 | ppc_md.init_early(); | |
236 | ||
463ce0e1 | 237 | find_legacy_serial_ports(); |
9b6b563c | 238 | |
5ad57078 PM |
239 | smp_setup_cpu_maps(); |
240 | ||
51d3082f BH |
241 | /* Register early console */ |
242 | register_early_udbg_console(); | |
9b6b563c | 243 | |
47679283 ME |
244 | xmon_setup(); |
245 | ||
9b6b563c PM |
246 | #if defined(CONFIG_KGDB) |
247 | if (ppc_md.kgdb_map_scc) | |
248 | ppc_md.kgdb_map_scc(); | |
249 | set_debug_traps(); | |
250 | if (strstr(cmd_line, "gdb")) { | |
251 | if (ppc_md.progress) | |
252 | ppc_md.progress("setup_arch: kgdb breakpoint", 0x4000); | |
253 | printk("kgdb breakpoint activated\n"); | |
254 | breakpoint(); | |
255 | } | |
256 | #endif | |
257 | ||
258 | /* | |
259 | * Set cache line size based on type of cpu as a default. | |
260 | * Systems with OF can look in the properties on the cpu node(s) | |
261 | * for a possibly more accurate value. | |
262 | */ | |
263 | if (cpu_has_feature(CPU_FTR_SPLIT_ID_CACHE)) { | |
264 | dcache_bsize = cur_cpu_spec->dcache_bsize; | |
265 | icache_bsize = cur_cpu_spec->icache_bsize; | |
266 | ucache_bsize = 0; | |
267 | } else | |
268 | ucache_bsize = dcache_bsize = icache_bsize | |
269 | = cur_cpu_spec->dcache_bsize; | |
270 | ||
271 | /* reboot on panic */ | |
272 | panic_timeout = 180; | |
273 | ||
7e990266 KG |
274 | if (ppc_md.panic) |
275 | setup_panic(); | |
276 | ||
9b6b563c PM |
277 | init_mm.start_code = PAGE_OFFSET; |
278 | init_mm.end_code = (unsigned long) _etext; | |
279 | init_mm.end_data = (unsigned long) _edata; | |
49b09853 | 280 | init_mm.brk = klimit; |
9b6b563c | 281 | |
9b6b563c PM |
282 | /* set up the bootmem stuff with available memory */ |
283 | do_init_bootmem(); | |
284 | if ( ppc_md.progress ) ppc_md.progress("setup_arch: bootmem", 0x3eab); | |
285 | ||
9b6b563c PM |
286 | #ifdef CONFIG_DUMMY_CONSOLE |
287 | conswitchp = &dummy_con; | |
288 | #endif | |
289 | ||
290 | ppc_md.setup_arch(); | |
291 | if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab); | |
292 | ||
293 | paging_init(); | |
9b6b563c | 294 | } |