powerpc: Properly handshake CPUs going out of boot spin loop
[linux-2.6-block.git] / arch / powerpc / kernel / setup_32.c
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1/*
2 * Common prep/pmac/chrp boot and setup code.
3 */
4
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5#include <linux/module.h>
6#include <linux/string.h>
7#include <linux/sched.h>
8#include <linux/init.h>
9#include <linux/kernel.h>
10#include <linux/reboot.h>
11#include <linux/delay.h>
12#include <linux/initrd.h>
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13#include <linux/tty.h>
14#include <linux/bootmem.h>
15#include <linux/seq_file.h>
16#include <linux/root_dev.h>
17#include <linux/cpu.h>
18#include <linux/console.h>
95f72d1e 19#include <linux/memblock.h>
9b6b563c 20
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21#include <asm/io.h>
22#include <asm/prom.h>
23#include <asm/processor.h>
24#include <asm/pgtable.h>
9b6b563c 25#include <asm/setup.h>
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26#include <asm/smp.h>
27#include <asm/elf.h>
28#include <asm/cputable.h>
29#include <asm/bootx.h>
30#include <asm/btext.h>
31#include <asm/machdep.h>
32#include <asm/uaccess.h>
33#include <asm/system.h>
34#include <asm/pmac_feature.h>
35#include <asm/sections.h>
36#include <asm/nvram.h>
37#include <asm/xmon.h>
6d7f58b0 38#include <asm/time.h>
463ce0e1 39#include <asm/serial.h>
51d3082f 40#include <asm/udbg.h>
77520351 41#include <asm/mmu_context.h>
9b6b563c 42
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43#include "setup.h"
44
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45#define DBG(fmt...)
46
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47extern void bootx_init(unsigned long r4, unsigned long phys);
48
2ed38b23 49int boot_cpuid = -1;
80579e1f 50EXPORT_SYMBOL_GPL(boot_cpuid);
9d07bc84 51int __initdata boot_cpu_count;
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52int boot_cpuid_phys;
53
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54int smp_hw_index[NR_CPUS];
55
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56unsigned long ISA_DMA_THRESHOLD;
57unsigned int DMA_MODE_READ;
58unsigned int DMA_MODE_WRITE;
59
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60#ifdef CONFIG_VGA_CONSOLE
61unsigned long vgacon_remap_base;
d003e7a1 62EXPORT_SYMBOL(vgacon_remap_base);
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63#endif
64
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65/*
66 * These are used in binfmt_elf.c to put aux entries on the stack
67 * for each elf executable being started.
68 */
69int dcache_bsize;
70int icache_bsize;
71int ucache_bsize;
72
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73/*
74 * We're called here very early in the boot. We determine the machine
75 * type and call the appropriate low-level setup functions.
76 * -- Cort <cort@fsmlabs.com>
77 *
78 * Note that the kernel may be running at an address which is different
79 * from the address that it was linked at, so we must use RELOC/PTRRELOC
80 * to access static data (including strings). -- paulus
81 */
4e491d14 82notrace unsigned long __init early_init(unsigned long dt_ptr)
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83{
84 unsigned long offset = reloc_offset();
42c4aaad 85 struct cpu_spec *spec;
9b6b563c 86
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87 /* First zero the BSS -- use memset_io, some platforms don't have
88 * caches on yet */
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89 memset_io((void __iomem *)PTRRELOC(&__bss_start), 0,
90 __bss_stop - __bss_start);
dd184343 91
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92 /*
93 * Identify the CPU type and fix up code sections
94 * that depend on which cpu we have.
95 */
974a76f5 96 spec = identify_cpu(offset, mfspr(SPRN_PVR));
42c4aaad 97
0909c8c2 98 do_feature_fixups(spec->cpu_features,
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99 PTRRELOC(&__start___ftr_fixup),
100 PTRRELOC(&__stop___ftr_fixup));
9b6b563c 101
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102 do_feature_fixups(spec->mmu_features,
103 PTRRELOC(&__start___mmu_ftr_fixup),
104 PTRRELOC(&__stop___mmu_ftr_fixup));
105
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106 do_lwsync_fixups(spec->cpu_features,
107 PTRRELOC(&__start___lwsync_fixup),
108 PTRRELOC(&__stop___lwsync_fixup));
109
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110 return KERNELBASE + offset;
111}
112
9b6b563c 113
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114/*
115 * Find out what kind of machine we're on and save any data we need
116 * from the early boot process (devtree is copied on pmac by prom_init()).
117 * This is called very early on the boot process, after a minimal
118 * MMU environment has been set up but before MMU_init is called.
119 */
cd301c7b 120notrace void __init machine_init(unsigned long dt_ptr)
9b6b563c 121{
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122 lockdep_init();
123
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124 /* Enable early debugging if any specified (see udbg.h) */
125 udbg_early_init();
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126
127 /* Do some early initialization based on the flat device tree */
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128 early_init_devtree(__va(dt_ptr));
129
e8222502 130 probe_machine();
35499c01 131
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132 setup_kdump_trampoline();
133
9b6b563c 134#ifdef CONFIG_6xx
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135 if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
136 cpu_has_feature(CPU_FTR_CAN_NAP))
137 ppc_md.power_save = ppc6xx_idle;
9b6b563c 138#endif
9b6b563c 139
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140#ifdef CONFIG_E500
141 if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
142 cpu_has_feature(CPU_FTR_CAN_NAP))
143 ppc_md.power_save = e500_idle;
144#endif
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145 if (ppc_md.progress)
146 ppc_md.progress("id mach(): done", 0x200);
147}
148
149#ifdef CONFIG_BOOKE_WDT
150/* Checks wdt=x and wdt_period=xx command-line option */
4e491d14 151notrace int __init early_parse_wdt(char *p)
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152{
153 if (p && strncmp(p, "0", 1) != 0)
154 booke_wdt_enabled = 1;
155
156 return 0;
157}
158early_param("wdt", early_parse_wdt);
159
160int __init early_parse_wdt_period (char *p)
161{
162 if (p)
163 booke_wdt_period = simple_strtoul(p, NULL, 0);
164
165 return 0;
166}
167early_param("wdt_period", early_parse_wdt_period);
168#endif /* CONFIG_BOOKE_WDT */
169
170/* Checks "l2cr=xxxx" command-line option */
171int __init ppc_setup_l2cr(char *str)
172{
173 if (cpu_has_feature(CPU_FTR_L2CR)) {
174 unsigned long val = simple_strtoul(str, NULL, 0);
175 printk(KERN_INFO "l2cr set to %lx\n", val);
176 _set_L2CR(0); /* force invalidate by disable cache */
177 _set_L2CR(val); /* and enable it */
178 }
179 return 1;
180}
181__setup("l2cr=", ppc_setup_l2cr);
182
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183/* Checks "l3cr=xxxx" command-line option */
184int __init ppc_setup_l3cr(char *str)
185{
186 if (cpu_has_feature(CPU_FTR_L3CR)) {
187 unsigned long val = simple_strtoul(str, NULL, 0);
188 printk(KERN_INFO "l3cr set to %lx\n", val);
189 _set_L3CR(val); /* and enable it */
190 }
191 return 1;
192}
193__setup("l3cr=", ppc_setup_l3cr);
194
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195#ifdef CONFIG_GENERIC_NVRAM
196
197/* Generic nvram hooks used by drivers/char/gen_nvram.c */
198unsigned char nvram_read_byte(int addr)
199{
200 if (ppc_md.nvram_read_val)
201 return ppc_md.nvram_read_val(addr);
202 return 0xff;
203}
204EXPORT_SYMBOL(nvram_read_byte);
205
206void nvram_write_byte(unsigned char val, int addr)
207{
208 if (ppc_md.nvram_write_val)
209 ppc_md.nvram_write_val(addr, val);
210}
211EXPORT_SYMBOL(nvram_write_byte);
212
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213ssize_t nvram_get_size(void)
214{
215 if (ppc_md.nvram_size)
216 return ppc_md.nvram_size();
217 return -1;
218}
219EXPORT_SYMBOL(nvram_get_size);
220
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221void nvram_sync(void)
222{
223 if (ppc_md.nvram_sync)
224 ppc_md.nvram_sync();
225}
226EXPORT_SYMBOL(nvram_sync);
227
228#endif /* CONFIG_NVRAM */
229
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230int __init ppc_init(void)
231{
9b6b563c 232 /* clear the progress line */
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233 if (ppc_md.progress)
234 ppc_md.progress(" ", 0xffff);
9b6b563c 235
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236 /* call platform init */
237 if (ppc_md.init != NULL) {
238 ppc_md.init();
239 }
240 return 0;
241}
242
243arch_initcall(ppc_init);
244
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245static void __init irqstack_early_init(void)
246{
247 unsigned int i;
248
249 /* interrupt stacks must be in lowmem, we get that for free on ppc32
e63075a3 250 * as the memblock is limited to lowmem by default */
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251 for_each_possible_cpu(i) {
252 softirq_ctx[i] = (struct thread_info *)
95f72d1e 253 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
85218827 254 hardirq_ctx[i] = (struct thread_info *)
95f72d1e 255 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
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256 }
257}
85218827 258
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259#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
260static void __init exc_lvl_early_init(void)
261{
3e7f45ad 262 unsigned int i, hw_cpu;
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263
264 /* interrupt stacks must be in lowmem, we get that for free on ppc32
95f72d1e 265 * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
bcf0b088 266 for_each_possible_cpu(i) {
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267 hw_cpu = get_hard_smp_processor_id(i);
268 critirq_ctx[hw_cpu] = (struct thread_info *)
95f72d1e 269 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
bcf0b088 270#ifdef CONFIG_BOOKE
3e7f45ad 271 dbgirq_ctx[hw_cpu] = (struct thread_info *)
95f72d1e 272 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
3e7f45ad 273 mcheckirq_ctx[hw_cpu] = (struct thread_info *)
95f72d1e 274 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
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275#endif
276 }
277}
278#else
279#define exc_lvl_early_init()
280#endif
281
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282/* Warning, IO base is not yet inited */
283void __init setup_arch(char **cmdline_p)
284{
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285 *cmdline_p = cmd_line;
286
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287 /* so udelay does something sensible, assume <= 1000 bogomips */
288 loops_per_jiffy = 500000000 / HZ;
289
9b6b563c 290 unflatten_device_tree();
a82765b6 291 check_for_initrd();
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292
293 if (ppc_md.init_early)
294 ppc_md.init_early();
295
463ce0e1 296 find_legacy_serial_ports();
9b6b563c 297
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298 smp_setup_cpu_maps();
299
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300 /* Register early console */
301 register_early_udbg_console();
9b6b563c 302
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303 xmon_setup();
304
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305 /*
306 * Set cache line size based on type of cpu as a default.
307 * Systems with OF can look in the properties on the cpu node(s)
308 * for a possibly more accurate value.
309 */
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310 dcache_bsize = cur_cpu_spec->dcache_bsize;
311 icache_bsize = cur_cpu_spec->icache_bsize;
312 ucache_bsize = 0;
313 if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
314 ucache_bsize = icache_bsize = dcache_bsize;
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315
316 /* reboot on panic */
317 panic_timeout = 180;
318
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319 if (ppc_md.panic)
320 setup_panic();
321
4846c5de 322 init_mm.start_code = (unsigned long)_stext;
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323 init_mm.end_code = (unsigned long) _etext;
324 init_mm.end_data = (unsigned long) _edata;
49b09853 325 init_mm.brk = klimit;
9b6b563c 326
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327 exc_lvl_early_init();
328
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329 irqstack_early_init();
330
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331 /* set up the bootmem stuff with available memory */
332 do_init_bootmem();
333 if ( ppc_md.progress ) ppc_md.progress("setup_arch: bootmem", 0x3eab);
334
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335#ifdef CONFIG_DUMMY_CONSOLE
336 conswitchp = &dummy_con;
337#endif
338
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339 if (ppc_md.setup_arch)
340 ppc_md.setup_arch();
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341 if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab);
342
343 paging_init();
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344
345 /* Initialize the MMU context management stuff */
346 mmu_context_init();
347
9b6b563c 348}