Commit | Line | Data |
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9b6b563c PM |
1 | /* |
2 | * Common prep/pmac/chrp boot and setup code. | |
3 | */ | |
4 | ||
9b6b563c PM |
5 | #include <linux/module.h> |
6 | #include <linux/string.h> | |
7 | #include <linux/sched.h> | |
8 | #include <linux/init.h> | |
9 | #include <linux/kernel.h> | |
10 | #include <linux/reboot.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/initrd.h> | |
9b6b563c | 13 | #include <linux/tty.h> |
9b6b563c PM |
14 | #include <linux/seq_file.h> |
15 | #include <linux/root_dev.h> | |
16 | #include <linux/cpu.h> | |
17 | #include <linux/console.h> | |
95f72d1e | 18 | #include <linux/memblock.h> |
9445aa1a | 19 | #include <linux/export.h> |
9b6b563c | 20 | |
9b6b563c PM |
21 | #include <asm/io.h> |
22 | #include <asm/prom.h> | |
23 | #include <asm/processor.h> | |
24 | #include <asm/pgtable.h> | |
9b6b563c | 25 | #include <asm/setup.h> |
9b6b563c PM |
26 | #include <asm/smp.h> |
27 | #include <asm/elf.h> | |
28 | #include <asm/cputable.h> | |
29 | #include <asm/bootx.h> | |
30 | #include <asm/btext.h> | |
31 | #include <asm/machdep.h> | |
7c0f6ba6 | 32 | #include <linux/uaccess.h> |
9b6b563c PM |
33 | #include <asm/pmac_feature.h> |
34 | #include <asm/sections.h> | |
35 | #include <asm/nvram.h> | |
36 | #include <asm/xmon.h> | |
6d7f58b0 | 37 | #include <asm/time.h> |
463ce0e1 | 38 | #include <asm/serial.h> |
51d3082f | 39 | #include <asm/udbg.h> |
1cd03890 | 40 | #include <asm/code-patching.h> |
b92a226e | 41 | #include <asm/cpu_has_feature.h> |
e82d70cf | 42 | #include <asm/asm-prototypes.h> |
db0a2b63 | 43 | #include <asm/kdump.h> |
2c86cd18 | 44 | #include <asm/feature-fixups.h> |
9b6b563c | 45 | |
f2c6d0d1 MM |
46 | #include "setup.h" |
47 | ||
03501dab PM |
48 | #define DBG(fmt...) |
49 | ||
9b6b563c PM |
50 | extern void bootx_init(unsigned long r4, unsigned long phys); |
51 | ||
80579e1f | 52 | int boot_cpuid_phys; |
9974eec2 | 53 | EXPORT_SYMBOL_GPL(boot_cpuid_phys); |
80579e1f | 54 | |
13a9801e | 55 | int smp_hw_index[NR_CPUS]; |
9445aa1a | 56 | EXPORT_SYMBOL(smp_hw_index); |
13a9801e | 57 | |
9b6b563c PM |
58 | unsigned long ISA_DMA_THRESHOLD; |
59 | unsigned int DMA_MODE_READ; | |
60 | unsigned int DMA_MODE_WRITE; | |
61 | ||
9445aa1a AV |
62 | EXPORT_SYMBOL(ISA_DMA_THRESHOLD); |
63 | EXPORT_SYMBOL(DMA_MODE_READ); | |
64 | EXPORT_SYMBOL(DMA_MODE_WRITE); | |
65 | ||
9b6b563c | 66 | /* |
bd7c93cc | 67 | * We're called here very early in the boot. |
9b6b563c PM |
68 | * |
69 | * Note that the kernel may be running at an address which is different | |
70 | * from the address that it was linked at, so we must use RELOC/PTRRELOC | |
71 | * to access static data (including strings). -- paulus | |
72 | */ | |
4e491d14 | 73 | notrace unsigned long __init early_init(unsigned long dt_ptr) |
9b6b563c PM |
74 | { |
75 | unsigned long offset = reloc_offset(); | |
76 | ||
dd184343 PM |
77 | /* First zero the BSS -- use memset_io, some platforms don't have |
78 | * caches on yet */ | |
556b09c8 MG |
79 | memset_io((void __iomem *)PTRRELOC(&__bss_start), 0, |
80 | __bss_stop - __bss_start); | |
dd184343 | 81 | |
9b6b563c PM |
82 | /* |
83 | * Identify the CPU type and fix up code sections | |
84 | * that depend on which cpu we have. | |
85 | */ | |
9402c684 | 86 | identify_cpu(offset, mfspr(SPRN_PVR)); |
42c4aaad | 87 | |
9402c684 | 88 | apply_feature_fixups(); |
d715e433 | 89 | |
9b6b563c PM |
90 | return KERNELBASE + offset; |
91 | } | |
92 | ||
9b6b563c | 93 | |
9b6b563c | 94 | /* |
bd7c93cc BH |
95 | * This is run before start_kernel(), the kernel has been relocated |
96 | * and we are running with enough of the MMU enabled to have our | |
97 | * proper kernel virtual addresses | |
98 | * | |
f9cc1d1f BH |
99 | * We do the initial parsing of the flat device-tree and prepares |
100 | * for the MMU to be fully initialized. | |
9b6b563c | 101 | */ |
6dece0eb | 102 | notrace void __init machine_init(u64 dt_ptr) |
9b6b563c | 103 | { |
fa54a981 CL |
104 | unsigned int *addr = (unsigned int *)((unsigned long)&patch__memset_nocache + |
105 | patch__memset_nocache); | |
ad1b0122 CL |
106 | unsigned long insn; |
107 | ||
97f6e0cc BH |
108 | /* Configure static keys first, now that we're relocated. */ |
109 | setup_feature_keys(); | |
110 | ||
719c91cc DG |
111 | /* Enable early debugging if any specified (see udbg.h) */ |
112 | udbg_early_init(); | |
51d3082f | 113 | |
fa54a981 | 114 | patch_instruction_site(&patch__memcpy_nocache, PPC_INST_NOP); |
ad1b0122 CL |
115 | |
116 | insn = create_cond_branch(addr, branch_target(addr), 0x820000); | |
117 | patch_instruction(addr, insn); /* replace b by bne cr0 */ | |
1cd03890 | 118 | |
51d3082f | 119 | /* Do some early initialization based on the flat device tree */ |
9b6b563c PM |
120 | early_init_devtree(__va(dt_ptr)); |
121 | ||
91b191c7 DK |
122 | early_init_mmu(); |
123 | ||
f8f50b1b | 124 | setup_kdump_trampoline(); |
9b6b563c PM |
125 | } |
126 | ||
9b6b563c | 127 | /* Checks "l2cr=xxxx" command-line option */ |
d15a261d | 128 | static int __init ppc_setup_l2cr(char *str) |
9b6b563c PM |
129 | { |
130 | if (cpu_has_feature(CPU_FTR_L2CR)) { | |
131 | unsigned long val = simple_strtoul(str, NULL, 0); | |
132 | printk(KERN_INFO "l2cr set to %lx\n", val); | |
133 | _set_L2CR(0); /* force invalidate by disable cache */ | |
134 | _set_L2CR(val); /* and enable it */ | |
135 | } | |
136 | return 1; | |
137 | } | |
138 | __setup("l2cr=", ppc_setup_l2cr); | |
139 | ||
a78bfbfc | 140 | /* Checks "l3cr=xxxx" command-line option */ |
d15a261d | 141 | static int __init ppc_setup_l3cr(char *str) |
a78bfbfc RB |
142 | { |
143 | if (cpu_has_feature(CPU_FTR_L3CR)) { | |
144 | unsigned long val = simple_strtoul(str, NULL, 0); | |
145 | printk(KERN_INFO "l3cr set to %lx\n", val); | |
146 | _set_L3CR(val); /* and enable it */ | |
147 | } | |
148 | return 1; | |
149 | } | |
150 | __setup("l3cr=", ppc_setup_l3cr); | |
151 | ||
9b6b563c PM |
152 | #ifdef CONFIG_GENERIC_NVRAM |
153 | ||
154 | /* Generic nvram hooks used by drivers/char/gen_nvram.c */ | |
155 | unsigned char nvram_read_byte(int addr) | |
156 | { | |
157 | if (ppc_md.nvram_read_val) | |
158 | return ppc_md.nvram_read_val(addr); | |
159 | return 0xff; | |
160 | } | |
161 | EXPORT_SYMBOL(nvram_read_byte); | |
162 | ||
163 | void nvram_write_byte(unsigned char val, int addr) | |
164 | { | |
165 | if (ppc_md.nvram_write_val) | |
166 | ppc_md.nvram_write_val(addr, val); | |
167 | } | |
168 | EXPORT_SYMBOL(nvram_write_byte); | |
169 | ||
d331d830 MW |
170 | ssize_t nvram_get_size(void) |
171 | { | |
172 | if (ppc_md.nvram_size) | |
173 | return ppc_md.nvram_size(); | |
174 | return -1; | |
175 | } | |
176 | EXPORT_SYMBOL(nvram_get_size); | |
177 | ||
9b6b563c PM |
178 | void nvram_sync(void) |
179 | { | |
180 | if (ppc_md.nvram_sync) | |
181 | ppc_md.nvram_sync(); | |
182 | } | |
183 | EXPORT_SYMBOL(nvram_sync); | |
184 | ||
185 | #endif /* CONFIG_NVRAM */ | |
186 | ||
d15a261d | 187 | static int __init ppc_init(void) |
9b6b563c | 188 | { |
9b6b563c | 189 | /* clear the progress line */ |
5e41763a GP |
190 | if (ppc_md.progress) |
191 | ppc_md.progress(" ", 0xffff); | |
9b6b563c | 192 | |
9b6b563c PM |
193 | /* call platform init */ |
194 | if (ppc_md.init != NULL) { | |
195 | ppc_md.init(); | |
196 | } | |
197 | return 0; | |
198 | } | |
9b6b563c PM |
199 | arch_initcall(ppc_init); |
200 | ||
b1923caa | 201 | void __init irqstack_early_init(void) |
85218827 KG |
202 | { |
203 | unsigned int i; | |
204 | ||
205 | /* interrupt stacks must be in lowmem, we get that for free on ppc32 | |
e63075a3 | 206 | * as the memblock is limited to lowmem by default */ |
85218827 KG |
207 | for_each_possible_cpu(i) { |
208 | softirq_ctx[i] = (struct thread_info *) | |
9a8dd708 | 209 | __va(memblock_phys_alloc(THREAD_SIZE, THREAD_SIZE)); |
85218827 | 210 | hardirq_ctx[i] = (struct thread_info *) |
9a8dd708 | 211 | __va(memblock_phys_alloc(THREAD_SIZE, THREAD_SIZE)); |
85218827 KG |
212 | } |
213 | } | |
85218827 | 214 | |
bcf0b088 | 215 | #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) |
b1923caa | 216 | void __init exc_lvl_early_init(void) |
bcf0b088 | 217 | { |
3e7f45ad | 218 | unsigned int i, hw_cpu; |
bcf0b088 KG |
219 | |
220 | /* interrupt stacks must be in lowmem, we get that for free on ppc32 | |
95f72d1e | 221 | * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */ |
bcf0b088 | 222 | for_each_possible_cpu(i) { |
04a34113 | 223 | #ifdef CONFIG_SMP |
3e7f45ad | 224 | hw_cpu = get_hard_smp_processor_id(i); |
04a34113 KH |
225 | #else |
226 | hw_cpu = 0; | |
227 | #endif | |
228 | ||
3e7f45ad | 229 | critirq_ctx[hw_cpu] = (struct thread_info *) |
9a8dd708 | 230 | __va(memblock_phys_alloc(THREAD_SIZE, THREAD_SIZE)); |
bcf0b088 | 231 | #ifdef CONFIG_BOOKE |
3e7f45ad | 232 | dbgirq_ctx[hw_cpu] = (struct thread_info *) |
9a8dd708 | 233 | __va(memblock_phys_alloc(THREAD_SIZE, THREAD_SIZE)); |
3e7f45ad | 234 | mcheckirq_ctx[hw_cpu] = (struct thread_info *) |
9a8dd708 | 235 | __va(memblock_phys_alloc(THREAD_SIZE, THREAD_SIZE)); |
bcf0b088 KG |
236 | #endif |
237 | } | |
238 | } | |
bcf0b088 KG |
239 | #endif |
240 | ||
b1923caa | 241 | void __init setup_power_save(void) |
56571384 BH |
242 | { |
243 | #ifdef CONFIG_6xx | |
244 | if (cpu_has_feature(CPU_FTR_CAN_DOZE) || | |
245 | cpu_has_feature(CPU_FTR_CAN_NAP)) | |
246 | ppc_md.power_save = ppc6xx_idle; | |
247 | #endif | |
248 | ||
249 | #ifdef CONFIG_E500 | |
250 | if (cpu_has_feature(CPU_FTR_CAN_DOZE) || | |
251 | cpu_has_feature(CPU_FTR_CAN_NAP)) | |
252 | ppc_md.power_save = e500_idle; | |
253 | #endif | |
254 | } | |
255 | ||
b1923caa | 256 | __init void initialize_cache_info(void) |
8f212cb2 BH |
257 | { |
258 | /* | |
259 | * Set cache line size based on type of cpu as a default. | |
260 | * Systems with OF can look in the properties on the cpu node(s) | |
261 | * for a possibly more accurate value. | |
262 | */ | |
263 | dcache_bsize = cur_cpu_spec->dcache_bsize; | |
264 | icache_bsize = cur_cpu_spec->icache_bsize; | |
265 | ucache_bsize = 0; | |
266 | if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE)) | |
267 | ucache_bsize = icache_bsize = dcache_bsize; | |
268 | } |