Commit | Line | Data |
---|---|---|
9b6b563c PM |
1 | /* |
2 | * Common prep/pmac/chrp boot and setup code. | |
3 | */ | |
4 | ||
9b6b563c PM |
5 | #include <linux/module.h> |
6 | #include <linux/string.h> | |
7 | #include <linux/sched.h> | |
8 | #include <linux/init.h> | |
9 | #include <linux/kernel.h> | |
10 | #include <linux/reboot.h> | |
11 | #include <linux/delay.h> | |
12 | #include <linux/initrd.h> | |
9b6b563c | 13 | #include <linux/tty.h> |
9b6b563c PM |
14 | #include <linux/seq_file.h> |
15 | #include <linux/root_dev.h> | |
16 | #include <linux/cpu.h> | |
17 | #include <linux/console.h> | |
95f72d1e | 18 | #include <linux/memblock.h> |
9b6b563c | 19 | |
9b6b563c PM |
20 | #include <asm/io.h> |
21 | #include <asm/prom.h> | |
22 | #include <asm/processor.h> | |
23 | #include <asm/pgtable.h> | |
9b6b563c | 24 | #include <asm/setup.h> |
9b6b563c PM |
25 | #include <asm/smp.h> |
26 | #include <asm/elf.h> | |
27 | #include <asm/cputable.h> | |
28 | #include <asm/bootx.h> | |
29 | #include <asm/btext.h> | |
30 | #include <asm/machdep.h> | |
31 | #include <asm/uaccess.h> | |
9b6b563c PM |
32 | #include <asm/pmac_feature.h> |
33 | #include <asm/sections.h> | |
34 | #include <asm/nvram.h> | |
35 | #include <asm/xmon.h> | |
6d7f58b0 | 36 | #include <asm/time.h> |
463ce0e1 | 37 | #include <asm/serial.h> |
51d3082f | 38 | #include <asm/udbg.h> |
77520351 | 39 | #include <asm/mmu_context.h> |
4e21b94c | 40 | #include <asm/epapr_hcalls.h> |
9b6b563c | 41 | |
03501dab PM |
42 | #define DBG(fmt...) |
43 | ||
9b6b563c PM |
44 | extern void bootx_init(unsigned long r4, unsigned long phys); |
45 | ||
80579e1f | 46 | int boot_cpuid_phys; |
9974eec2 | 47 | EXPORT_SYMBOL_GPL(boot_cpuid_phys); |
80579e1f | 48 | |
13a9801e NL |
49 | int smp_hw_index[NR_CPUS]; |
50 | ||
9b6b563c PM |
51 | unsigned long ISA_DMA_THRESHOLD; |
52 | unsigned int DMA_MODE_READ; | |
53 | unsigned int DMA_MODE_WRITE; | |
54 | ||
9b6b563c PM |
55 | #ifdef CONFIG_VGA_CONSOLE |
56 | unsigned long vgacon_remap_base; | |
d003e7a1 | 57 | EXPORT_SYMBOL(vgacon_remap_base); |
9b6b563c PM |
58 | #endif |
59 | ||
9b6b563c PM |
60 | /* |
61 | * These are used in binfmt_elf.c to put aux entries on the stack | |
62 | * for each elf executable being started. | |
63 | */ | |
64 | int dcache_bsize; | |
65 | int icache_bsize; | |
66 | int ucache_bsize; | |
67 | ||
9b6b563c PM |
68 | /* |
69 | * We're called here very early in the boot. We determine the machine | |
70 | * type and call the appropriate low-level setup functions. | |
71 | * -- Cort <cort@fsmlabs.com> | |
72 | * | |
73 | * Note that the kernel may be running at an address which is different | |
74 | * from the address that it was linked at, so we must use RELOC/PTRRELOC | |
75 | * to access static data (including strings). -- paulus | |
76 | */ | |
4e491d14 | 77 | notrace unsigned long __init early_init(unsigned long dt_ptr) |
9b6b563c PM |
78 | { |
79 | unsigned long offset = reloc_offset(); | |
42c4aaad | 80 | struct cpu_spec *spec; |
9b6b563c | 81 | |
dd184343 PM |
82 | /* First zero the BSS -- use memset_io, some platforms don't have |
83 | * caches on yet */ | |
556b09c8 MG |
84 | memset_io((void __iomem *)PTRRELOC(&__bss_start), 0, |
85 | __bss_stop - __bss_start); | |
dd184343 | 86 | |
9b6b563c PM |
87 | /* |
88 | * Identify the CPU type and fix up code sections | |
89 | * that depend on which cpu we have. | |
90 | */ | |
974a76f5 | 91 | spec = identify_cpu(offset, mfspr(SPRN_PVR)); |
42c4aaad | 92 | |
0909c8c2 | 93 | do_feature_fixups(spec->cpu_features, |
42c4aaad BH |
94 | PTRRELOC(&__start___ftr_fixup), |
95 | PTRRELOC(&__stop___ftr_fixup)); | |
9b6b563c | 96 | |
7c03d653 BH |
97 | do_feature_fixups(spec->mmu_features, |
98 | PTRRELOC(&__start___mmu_ftr_fixup), | |
99 | PTRRELOC(&__stop___mmu_ftr_fixup)); | |
100 | ||
2d1b2027 KG |
101 | do_lwsync_fixups(spec->cpu_features, |
102 | PTRRELOC(&__start___lwsync_fixup), | |
103 | PTRRELOC(&__stop___lwsync_fixup)); | |
104 | ||
d715e433 AB |
105 | do_final_fixups(); |
106 | ||
9b6b563c PM |
107 | return KERNELBASE + offset; |
108 | } | |
109 | ||
9b6b563c | 110 | |
9b6b563c PM |
111 | /* |
112 | * Find out what kind of machine we're on and save any data we need | |
113 | * from the early boot process (devtree is copied on pmac by prom_init()). | |
114 | * This is called very early on the boot process, after a minimal | |
115 | * MMU environment has been set up but before MMU_init is called. | |
116 | */ | |
6dece0eb | 117 | notrace void __init machine_init(u64 dt_ptr) |
9b6b563c | 118 | { |
5d38902c BH |
119 | lockdep_init(); |
120 | ||
719c91cc DG |
121 | /* Enable early debugging if any specified (see udbg.h) */ |
122 | udbg_early_init(); | |
51d3082f BH |
123 | |
124 | /* Do some early initialization based on the flat device tree */ | |
9b6b563c PM |
125 | early_init_devtree(__va(dt_ptr)); |
126 | ||
4e21b94c LT |
127 | epapr_paravirt_early_init(); |
128 | ||
91b191c7 DK |
129 | early_init_mmu(); |
130 | ||
e8222502 | 131 | probe_machine(); |
35499c01 | 132 | |
f8f50b1b DF |
133 | setup_kdump_trampoline(); |
134 | ||
9b6b563c | 135 | #ifdef CONFIG_6xx |
a0652fc9 PM |
136 | if (cpu_has_feature(CPU_FTR_CAN_DOZE) || |
137 | cpu_has_feature(CPU_FTR_CAN_NAP)) | |
138 | ppc_md.power_save = ppc6xx_idle; | |
9b6b563c | 139 | #endif |
9b6b563c | 140 | |
fc4033b2 KG |
141 | #ifdef CONFIG_E500 |
142 | if (cpu_has_feature(CPU_FTR_CAN_DOZE) || | |
143 | cpu_has_feature(CPU_FTR_CAN_NAP)) | |
144 | ppc_md.power_save = e500_idle; | |
145 | #endif | |
9b6b563c PM |
146 | if (ppc_md.progress) |
147 | ppc_md.progress("id mach(): done", 0x200); | |
148 | } | |
149 | ||
9b6b563c PM |
150 | /* Checks "l2cr=xxxx" command-line option */ |
151 | int __init ppc_setup_l2cr(char *str) | |
152 | { | |
153 | if (cpu_has_feature(CPU_FTR_L2CR)) { | |
154 | unsigned long val = simple_strtoul(str, NULL, 0); | |
155 | printk(KERN_INFO "l2cr set to %lx\n", val); | |
156 | _set_L2CR(0); /* force invalidate by disable cache */ | |
157 | _set_L2CR(val); /* and enable it */ | |
158 | } | |
159 | return 1; | |
160 | } | |
161 | __setup("l2cr=", ppc_setup_l2cr); | |
162 | ||
a78bfbfc RB |
163 | /* Checks "l3cr=xxxx" command-line option */ |
164 | int __init ppc_setup_l3cr(char *str) | |
165 | { | |
166 | if (cpu_has_feature(CPU_FTR_L3CR)) { | |
167 | unsigned long val = simple_strtoul(str, NULL, 0); | |
168 | printk(KERN_INFO "l3cr set to %lx\n", val); | |
169 | _set_L3CR(val); /* and enable it */ | |
170 | } | |
171 | return 1; | |
172 | } | |
173 | __setup("l3cr=", ppc_setup_l3cr); | |
174 | ||
9b6b563c PM |
175 | #ifdef CONFIG_GENERIC_NVRAM |
176 | ||
177 | /* Generic nvram hooks used by drivers/char/gen_nvram.c */ | |
178 | unsigned char nvram_read_byte(int addr) | |
179 | { | |
180 | if (ppc_md.nvram_read_val) | |
181 | return ppc_md.nvram_read_val(addr); | |
182 | return 0xff; | |
183 | } | |
184 | EXPORT_SYMBOL(nvram_read_byte); | |
185 | ||
186 | void nvram_write_byte(unsigned char val, int addr) | |
187 | { | |
188 | if (ppc_md.nvram_write_val) | |
189 | ppc_md.nvram_write_val(addr, val); | |
190 | } | |
191 | EXPORT_SYMBOL(nvram_write_byte); | |
192 | ||
d331d830 MW |
193 | ssize_t nvram_get_size(void) |
194 | { | |
195 | if (ppc_md.nvram_size) | |
196 | return ppc_md.nvram_size(); | |
197 | return -1; | |
198 | } | |
199 | EXPORT_SYMBOL(nvram_get_size); | |
200 | ||
9b6b563c PM |
201 | void nvram_sync(void) |
202 | { | |
203 | if (ppc_md.nvram_sync) | |
204 | ppc_md.nvram_sync(); | |
205 | } | |
206 | EXPORT_SYMBOL(nvram_sync); | |
207 | ||
208 | #endif /* CONFIG_NVRAM */ | |
209 | ||
9b6b563c PM |
210 | int __init ppc_init(void) |
211 | { | |
9b6b563c | 212 | /* clear the progress line */ |
5e41763a GP |
213 | if (ppc_md.progress) |
214 | ppc_md.progress(" ", 0xffff); | |
9b6b563c | 215 | |
9b6b563c PM |
216 | /* call platform init */ |
217 | if (ppc_md.init != NULL) { | |
218 | ppc_md.init(); | |
219 | } | |
220 | return 0; | |
221 | } | |
222 | ||
223 | arch_initcall(ppc_init); | |
224 | ||
85218827 KG |
225 | static void __init irqstack_early_init(void) |
226 | { | |
227 | unsigned int i; | |
228 | ||
229 | /* interrupt stacks must be in lowmem, we get that for free on ppc32 | |
e63075a3 | 230 | * as the memblock is limited to lowmem by default */ |
85218827 KG |
231 | for_each_possible_cpu(i) { |
232 | softirq_ctx[i] = (struct thread_info *) | |
95f72d1e | 233 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
85218827 | 234 | hardirq_ctx[i] = (struct thread_info *) |
95f72d1e | 235 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
85218827 KG |
236 | } |
237 | } | |
85218827 | 238 | |
bcf0b088 KG |
239 | #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) |
240 | static void __init exc_lvl_early_init(void) | |
241 | { | |
3e7f45ad | 242 | unsigned int i, hw_cpu; |
bcf0b088 KG |
243 | |
244 | /* interrupt stacks must be in lowmem, we get that for free on ppc32 | |
95f72d1e | 245 | * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */ |
bcf0b088 | 246 | for_each_possible_cpu(i) { |
04a34113 | 247 | #ifdef CONFIG_SMP |
3e7f45ad | 248 | hw_cpu = get_hard_smp_processor_id(i); |
04a34113 KH |
249 | #else |
250 | hw_cpu = 0; | |
251 | #endif | |
252 | ||
3e7f45ad | 253 | critirq_ctx[hw_cpu] = (struct thread_info *) |
95f72d1e | 254 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
bcf0b088 | 255 | #ifdef CONFIG_BOOKE |
3e7f45ad | 256 | dbgirq_ctx[hw_cpu] = (struct thread_info *) |
95f72d1e | 257 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
3e7f45ad | 258 | mcheckirq_ctx[hw_cpu] = (struct thread_info *) |
95f72d1e | 259 | __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); |
bcf0b088 KG |
260 | #endif |
261 | } | |
262 | } | |
263 | #else | |
264 | #define exc_lvl_early_init() | |
265 | #endif | |
266 | ||
9b6b563c PM |
267 | /* Warning, IO base is not yet inited */ |
268 | void __init setup_arch(char **cmdline_p) | |
269 | { | |
3e47d147 | 270 | *cmdline_p = boot_command_line; |
846f77b0 | 271 | |
9b6b563c PM |
272 | /* so udelay does something sensible, assume <= 1000 bogomips */ |
273 | loops_per_jiffy = 500000000 / HZ; | |
274 | ||
9b6b563c | 275 | unflatten_device_tree(); |
a82765b6 | 276 | check_for_initrd(); |
463ce0e1 BH |
277 | |
278 | if (ppc_md.init_early) | |
279 | ppc_md.init_early(); | |
280 | ||
463ce0e1 | 281 | find_legacy_serial_ports(); |
9b6b563c | 282 | |
5ad57078 PM |
283 | smp_setup_cpu_maps(); |
284 | ||
51d3082f BH |
285 | /* Register early console */ |
286 | register_early_udbg_console(); | |
9b6b563c | 287 | |
47679283 ME |
288 | xmon_setup(); |
289 | ||
9b6b563c PM |
290 | /* |
291 | * Set cache line size based on type of cpu as a default. | |
292 | * Systems with OF can look in the properties on the cpu node(s) | |
293 | * for a possibly more accurate value. | |
294 | */ | |
4508dc21 DG |
295 | dcache_bsize = cur_cpu_spec->dcache_bsize; |
296 | icache_bsize = cur_cpu_spec->icache_bsize; | |
297 | ucache_bsize = 0; | |
298 | if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE)) | |
299 | ucache_bsize = icache_bsize = dcache_bsize; | |
9b6b563c | 300 | |
7e990266 KG |
301 | if (ppc_md.panic) |
302 | setup_panic(); | |
303 | ||
4846c5de | 304 | init_mm.start_code = (unsigned long)_stext; |
9b6b563c PM |
305 | init_mm.end_code = (unsigned long) _etext; |
306 | init_mm.end_data = (unsigned long) _edata; | |
49b09853 | 307 | init_mm.brk = klimit; |
9b6b563c | 308 | |
bcf0b088 KG |
309 | exc_lvl_early_init(); |
310 | ||
85218827 KG |
311 | irqstack_early_init(); |
312 | ||
10239733 AB |
313 | initmem_init(); |
314 | if ( ppc_md.progress ) ppc_md.progress("setup_arch: initmem", 0x3eab); | |
9b6b563c | 315 | |
9b6b563c PM |
316 | #ifdef CONFIG_DUMMY_CONSOLE |
317 | conswitchp = &dummy_con; | |
318 | #endif | |
319 | ||
38db7e74 GL |
320 | if (ppc_md.setup_arch) |
321 | ppc_md.setup_arch(); | |
9b6b563c PM |
322 | if ( ppc_md.progress ) ppc_md.progress("arch: exit", 0x3eab); |
323 | ||
324 | paging_init(); | |
77520351 BH |
325 | |
326 | /* Initialize the MMU context management stuff */ | |
327 | mmu_context_init(); | |
9b6b563c | 328 | } |