[linux-2.6-block.git] / arch / powerpc / kernel / rtas_pci.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
 *
 * RTAS specific routines for PCI.
 *
 * Based on code from pci.c, chrp_pci.c and pSeries_pci.c
 */

#include <linux/kernel.h>
#include <linux/threads.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/pgtable.h>
#include <linux/of_address.h>
#include <linux/of_fdt.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/iommu.h>
#include <asm/rtas.h>
#include <asm/mpic.h>
#include <asm/ppc-pci.h>
#include <asm/eeh.h>

/* RTAS tokens */
static int read_pci_config;
static int write_pci_config;
static int ibm_read_pci_config;
static int ibm_write_pci_config;

static inline int config_access_valid(struct pci_dn *dn, int where)
{
	if (where < 256)
		return 1;
	if (where < 4096 && dn->pci_ext_config_space)
		return 1;

	return 0;
}

int rtas_pci_dn_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
{
	int returnval = -1;
	unsigned long buid, addr;
	int ret;

	if (!pdn)
		return PCIBIOS_DEVICE_NOT_FOUND;
	if (!config_access_valid(pdn, where))
		return PCIBIOS_BAD_REGISTER_NUMBER;
#ifdef CONFIG_EEH
	if (pdn->edev && pdn->edev->pe &&
	    (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))
		return PCIBIOS_SET_FAILED;
#endif

	addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
	buid = pdn->phb->buid;
	if (buid) {
		ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval,
				addr, BUID_HI(buid), BUID_LO(buid), size);
	} else {
		ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size);
	}
	*val = returnval;

	if (ret)
		return PCIBIOS_DEVICE_NOT_FOUND;

	return PCIBIOS_SUCCESSFUL;
}

static int rtas_pci_read_config(struct pci_bus *bus,
				unsigned int devfn,
				int where, int size, u32 *val)
{
	struct pci_dn *pdn;
	int ret;

	*val = 0xFFFFFFFF;

	pdn = pci_get_pdn_by_devfn(bus, devfn);

	/* Validity of pdn is checked in here */
	ret = rtas_pci_dn_read_config(pdn, where, size, val);
	if (*val == EEH_IO_ERROR_VALUE(size) &&
	    eeh_dev_check_failure(pdn_to_eeh_dev(pdn)))
		return PCIBIOS_DEVICE_NOT_FOUND;

	return ret;
}

int rtas_pci_dn_write_config(struct pci_dn *pdn, int where, int size, u32 val)
{
	unsigned long buid, addr;
	int ret;

	if (!pdn)
		return PCIBIOS_DEVICE_NOT_FOUND;
	if (!config_access_valid(pdn, where))
		return PCIBIOS_BAD_REGISTER_NUMBER;
#ifdef CONFIG_EEH
	if (pdn->edev && pdn->edev->pe &&
	    (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))
		return PCIBIOS_SET_FAILED;
#endif

	addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
	buid = pdn->phb->buid;
	if (buid) {
		ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr,
			BUID_HI(buid), BUID_LO(buid), size, (ulong) val);
	} else {
		ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val);
	}

	if (ret)
		return PCIBIOS_DEVICE_NOT_FOUND;

	return PCIBIOS_SUCCESSFUL;
}

static int rtas_pci_write_config(struct pci_bus *bus,
				 unsigned int devfn,
				 int where, int size, u32 val)
{
	struct pci_dn *pdn;

	pdn = pci_get_pdn_by_devfn(bus, devfn);

	/* Validity of pdn is checked in here. */
	return rtas_pci_dn_write_config(pdn, where, size, val);
}

static struct pci_ops rtas_pci_ops = {
	.read = rtas_pci_read_config,
	.write = rtas_pci_write_config,
};

static int is_python(struct device_node *dev)
{
	const char *model = of_get_property(dev, "model", NULL);

	if (model && strstr(model, "Python"))
		return 1;

	return 0;
}

static void python_countermeasures(struct device_node *dev)
{
	struct resource registers;
	void __iomem *chip_regs;
	volatile u32 val;

	if (of_address_to_resource(dev, 0, &registers)) {
		printk(KERN_ERR "Can't get address for Python workarounds !\n");
		return;
	}

	/* Python's register file is 1 MB in size. */
	chip_regs = ioremap(registers.start & ~(0xfffffUL), 0x100000);

	/*
	 * Firmware doesn't always clear this bit which is critical
	 * for good performance - Anton
	 */

#define PRG_CL_RESET_VALID 0x00010000

	val = in_be32(chip_regs + 0xf6030);
	if (val & PRG_CL_RESET_VALID) {
		printk(KERN_INFO "Python workaround: ");
		val &= ~PRG_CL_RESET_VALID;
		out_be32(chip_regs + 0xf6030, val);
		/*
		 * We must read it back for changes to
		 * take effect
		 */
		val = in_be32(chip_regs + 0xf6030);
		printk("reg0: %x\n", val);
	}

	iounmap(chip_regs);
}

void __init init_pci_config_tokens(void)
{
	read_pci_config = rtas_function_token(RTAS_FN_READ_PCI_CONFIG);
	write_pci_config = rtas_function_token(RTAS_FN_WRITE_PCI_CONFIG);
	ibm_read_pci_config = rtas_function_token(RTAS_FN_IBM_READ_PCI_CONFIG);
	ibm_write_pci_config = rtas_function_token(RTAS_FN_IBM_WRITE_PCI_CONFIG);
}

unsigned long get_phb_buid(struct device_node *phb)
{
	struct resource r;

	if (ibm_read_pci_config == -1)
		return 0;
	if (of_address_to_resource(phb, 0, &r))
		return 0;
	return r.start;
}

static int phb_set_bus_ranges(struct device_node *dev,
			      struct pci_controller *phb)
{
	const __be32 *bus_range;
	unsigned int len;

	bus_range = of_get_property(dev, "bus-range", &len);
	if (bus_range == NULL || len < 2 * sizeof(int)) {
		return 1;
 	}

	phb->first_busno = be32_to_cpu(bus_range[0]);
	phb->last_busno  = be32_to_cpu(bus_range[1]);

	return 0;
}

int rtas_setup_phb(struct pci_controller *phb)
{
	struct device_node *dev = phb->dn;

	if (is_python(dev))
		python_countermeasures(dev);

	if (phb_set_bus_ranges(dev, phb))
		return 1;

	phb->ops = &rtas_pci_ops;
	phb->buid = get_phb_buid(dev);

	return 0;
}
Commit	Line	Data
1a59d1b8	1	// SPDX-License-Identifier: GPL-2.0-or-later
c5a3c2e5	2	/*
c5a3c2e5 AB	3	* Copyright (C) 2001 Dave Engebretsen, IBM Corporation
	4	* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
	5	*
	6	* RTAS specific routines for PCI.
ae65a391	7	*
c5a3c2e5	8	* Based on code from pci.c, chrp_pci.c and pSeries_pci.c
c5a3c2e5 AB	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/threads.h>
	13	#include <linux/pci.h>
	14	#include <linux/string.h>
	15	#include <linux/init.h>
65fddcfc	16	#include <linux/pgtable.h>
e6f6390a CL	17	#include <linux/of_address.h>
e6f6390a CL	18	#include <linux/of_fdt.h>
c5a3c2e5 AB	19
c5a3c2e5 AB	20	#include <asm/io.h>
c5a3c2e5	21	#include <asm/irq.h>
c5a3c2e5 AB	22	#include <asm/machdep.h>
	23	#include <asm/pci-bridge.h>
	24	#include <asm/iommu.h>
	25	#include <asm/rtas.h>
bbeb3f4c	26	#include <asm/mpic.h>
d387899f	27	#include <asm/ppc-pci.h>
68a64357	28	#include <asm/eeh.h>
c5a3c2e5 AB	29
	30	/* RTAS tokens */
	31	static int read_pci_config;
	32	static int write_pci_config;
	33	static int ibm_read_pci_config;
	34	static int ibm_write_pci_config;
	35
ae65a391	36	static inline int config_access_valid(struct pci_dn *dn, int where)
c5a3c2e5 AB	37	{
	38	if (where < 256)
	39	return 1;
	40	if (where < 4096 && dn->pci_ext_config_space)
	41	return 1;
	42
	43	return 0;
	44	}
	45
9be4feb7	46	int rtas_pci_dn_read_config(struct pci_dn pdn, int where, int size, u32 val)
c5a3c2e5 AB	47	{
	48	int returnval = -1;
	49	unsigned long buid, addr;
	50	int ret;
	51
ae65a391	52	if (!pdn)
c5a3c2e5	53	return PCIBIOS_DEVICE_NOT_FOUND;
1635317f	54	if (!config_access_valid(pdn, where))
c5a3c2e5	55	return PCIBIOS_BAD_REGISTER_NUMBER;
3409eb4e GS	56	#ifdef CONFIG_EEH
	57	if (pdn->edev && pdn->edev->pe &&
	58	(pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))
	59	return PCIBIOS_SET_FAILED;
	60	#endif
c5a3c2e5	61
6f3d5d3c	62	addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
1635317f	63	buid = pdn->phb->buid;
c5a3c2e5 AB	64	if (buid) {
c5a3c2e5 AB	65	ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval,
ae65a391	66	addr, BUID_HI(buid), BUID_LO(buid), size);
c5a3c2e5 AB	67	} else {
	68	ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size);
	69	}
	70	*val = returnval;
	71
	72	if (ret)
	73	return PCIBIOS_DEVICE_NOT_FOUND;
	74
c5a3c2e5 AB	75	return PCIBIOS_SUCCESSFUL;
	76	}
	77
	78	static int rtas_pci_read_config(struct pci_bus *bus,
	79	unsigned int devfn,
	80	int where, int size, u32 *val)
	81	{
d0914f50	82	struct pci_dn *pdn;
d0914f50	83	int ret;
c5a3c2e5	84
d0914f50	85	*val = 0xFFFFFFFF;
1635317f	86
f9df74df	87	pdn = pci_get_pdn_by_devfn(bus, devfn);
d0914f50	88
f9df74df	89	/* Validity of pdn is checked in here */
9be4feb7	90	ret = rtas_pci_dn_read_config(pdn, where, size, val);
d0914f50	91	if (*val == EEH_IO_ERROR_VALUE(size) &&
c6406d8f	92	eeh_dev_check_failure(pdn_to_eeh_dev(pdn)))
d0914f50 GS	93	return PCIBIOS_DEVICE_NOT_FOUND;
	94
	95	return ret;
c5a3c2e5 AB	96	}
c5a3c2e5 AB	97
9be4feb7	98	int rtas_pci_dn_write_config(struct pci_dn *pdn, int where, int size, u32 val)
c5a3c2e5 AB	99	{
	100	unsigned long buid, addr;
	101	int ret;
	102
ae65a391	103	if (!pdn)
c5a3c2e5	104	return PCIBIOS_DEVICE_NOT_FOUND;
1635317f	105	if (!config_access_valid(pdn, where))
c5a3c2e5	106	return PCIBIOS_BAD_REGISTER_NUMBER;
3409eb4e GS	107	#ifdef CONFIG_EEH
	108	if (pdn->edev && pdn->edev->pe &&
	109	(pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))
	110	return PCIBIOS_SET_FAILED;
	111	#endif
c5a3c2e5	112
6f3d5d3c	113	addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
1635317f	114	buid = pdn->phb->buid;
c5a3c2e5	115	if (buid) {
ae65a391	116	ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr,
ae65a391	117	BUID_HI(buid), BUID_LO(buid), size, (ulong) val);
c5a3c2e5 AB	118	} else {
	119	ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val);
	120	}
	121
	122	if (ret)
	123	return PCIBIOS_DEVICE_NOT_FOUND;
	124
	125	return PCIBIOS_SUCCESSFUL;
	126	}
	127
	128	static int rtas_pci_write_config(struct pci_bus *bus,
	129	unsigned int devfn,
	130	int where, int size, u32 val)
	131	{
d0914f50	132	struct pci_dn *pdn;
d0914f50	133
f9df74df	134	pdn = pci_get_pdn_by_devfn(bus, devfn);
d0914f50	135
f9df74df	136	/* Validity of pdn is checked in here. */
9be4feb7	137	return rtas_pci_dn_write_config(pdn, where, size, val);
c5a3c2e5 AB	138	}
c5a3c2e5 AB	139
1c21a293	140	static struct pci_ops rtas_pci_ops = {
8674e0c9 NL	141	.read = rtas_pci_read_config,
8674e0c9 NL	142	.write = rtas_pci_write_config,
c5a3c2e5 AB	143	};
c5a3c2e5 AB	144
1c21a293	145	static int is_python(struct device_node *dev)
c5a3c2e5	146	{
e2eb6392	147	const char *model = of_get_property(dev, "model", NULL);
c5a3c2e5 AB	148
	149	if (model && strstr(model, "Python"))
	150	return 1;
	151
	152	return 0;
	153	}
	154
cc5d0189	155	static void python_countermeasures(struct device_node *dev)
c5a3c2e5	156	{
cc5d0189	157	struct resource registers;
c5a3c2e5 AB	158	void __iomem *chip_regs;
	159	volatile u32 val;
	160
cc5d0189 BH	161	if (of_address_to_resource(dev, 0, &registers)) {
cc5d0189 BH	162	printk(KERN_ERR "Can't get address for Python workarounds !\n");
c5a3c2e5	163	return;
cc5d0189	164	}
c5a3c2e5 AB	165
c5a3c2e5 AB	166	/* Python's register file is 1 MB in size. */
cc5d0189	167	chip_regs = ioremap(registers.start & ~(0xfffffUL), 0x100000);
c5a3c2e5	168
ae65a391	169	/*
c5a3c2e5 AB	170	* Firmware doesn't always clear this bit which is critical
	171	* for good performance - Anton
	172	*/
	173
	174	#define PRG_CL_RESET_VALID 0x00010000
	175
	176	val = in_be32(chip_regs + 0xf6030);
	177	if (val & PRG_CL_RESET_VALID) {
	178	printk(KERN_INFO "Python workaround: ");
	179	val &= ~PRG_CL_RESET_VALID;
	180	out_be32(chip_regs + 0xf6030, val);
	181	/*
	182	* We must read it back for changes to
	183	* take effect
	184	*/
	185	val = in_be32(chip_regs + 0xf6030);
	186	printk("reg0: %x\n", val);
	187	}
	188
	189	iounmap(chip_regs);
	190	}
	191
db38f290	192	void __init init_pci_config_tokens(void)
c5a3c2e5	193	{
08273c9f NL	194	read_pci_config = rtas_function_token(RTAS_FN_READ_PCI_CONFIG);
	195	write_pci_config = rtas_function_token(RTAS_FN_WRITE_PCI_CONFIG);
	196	ibm_read_pci_config = rtas_function_token(RTAS_FN_IBM_READ_PCI_CONFIG);
	197	ibm_write_pci_config = rtas_function_token(RTAS_FN_IBM_WRITE_PCI_CONFIG);
c5a3c2e5 AB	198	}
c5a3c2e5 AB	199
db38f290	200	unsigned long get_phb_buid(struct device_node *phb)
c5a3c2e5	201	{
6506e710	202	struct resource r;
c5a3c2e5	203
6506e710	204	if (ibm_read_pci_config == -1)
c5a3c2e5	205	return 0;
6506e710	206	if (of_address_to_resource(phb, 0, &r))
c5a3c2e5	207	return 0;
6506e710	208	return r.start;
c5a3c2e5 AB	209	}
	210
	211	static int phb_set_bus_ranges(struct device_node *dev,
	212	struct pci_controller *phb)
	213	{
cf059965	214	const __be32 *bus_range;
c5a3c2e5 AB	215	unsigned int len;
c5a3c2e5 AB	216
e2eb6392	217	bus_range = of_get_property(dev, "bus-range", &len);
c5a3c2e5 AB	218	if (bus_range == NULL \|\| len < 2 * sizeof(int)) {
	219	return 1;
	220	}
ae65a391	221
cf059965 CLG	222	phb->first_busno = be32_to_cpu(bus_range[0]);
cf059965 CLG	223	phb->last_busno = be32_to_cpu(bus_range[1]);
c5a3c2e5 AB	224
	225	return 0;
	226	}
	227
cad5cef6	228	int rtas_setup_phb(struct pci_controller *phb)
c5a3c2e5	229	{
44ef3390	230	struct device_node *dev = phb->dn;
4c9d2800	231
c5a3c2e5	232	if (is_python(dev))
cc5d0189	233	python_countermeasures(dev);
c5a3c2e5 AB	234
	235	if (phb_set_bus_ranges(dev, phb))
	236	return 1;
	237
c5a3c2e5 AB	238	phb->ops = &rtas_pci_ops;
	239	phb->buid = get_phb_buid(dev);
	240
	241	return 0;
	242	}