Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Derived from "arch/m68k/kernel/ptrace.c" | |
6 | * Copyright (C) 1994 by Hamish Macdonald | |
7 | * Taken from linux/kernel/ptrace.c and modified for M680x0. | |
8 | * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds | |
9 | * | |
10 | * Modified by Cort Dougan (cort@hq.fsmlabs.com) | |
b123923d | 11 | * and Paul Mackerras (paulus@samba.org). |
1da177e4 LT |
12 | * |
13 | * This file is subject to the terms and conditions of the GNU General | |
14 | * Public License. See the file README.legal in the main directory of | |
15 | * this archive for more details. | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/smp.h> | |
1da177e4 LT |
22 | #include <linux/errno.h> |
23 | #include <linux/ptrace.h> | |
f65255e8 | 24 | #include <linux/regset.h> |
4f72c427 | 25 | #include <linux/tracehook.h> |
3caf06c6 | 26 | #include <linux/elf.h> |
1da177e4 LT |
27 | #include <linux/user.h> |
28 | #include <linux/security.h> | |
7ed20e1a | 29 | #include <linux/signal.h> |
ea9c102c DW |
30 | #include <linux/seccomp.h> |
31 | #include <linux/audit.h> | |
02424d89 | 32 | #include <trace/syscall.h> |
5aae8a53 P |
33 | #include <linux/hw_breakpoint.h> |
34 | #include <linux/perf_event.h> | |
22ecbe8d | 35 | #include <linux/context_tracking.h> |
1da177e4 LT |
36 | |
37 | #include <asm/uaccess.h> | |
38 | #include <asm/page.h> | |
39 | #include <asm/pgtable.h> | |
ae3a197e | 40 | #include <asm/switch_to.h> |
c7a318ba | 41 | #include <asm/tm.h> |
0545d543 | 42 | #include <asm/asm-prototypes.h> |
21a62902 | 43 | |
02424d89 IM |
44 | #define CREATE_TRACE_POINTS |
45 | #include <trace/events/syscalls.h> | |
46 | ||
359e4284 MS |
47 | /* |
48 | * The parameter save area on the stack is used to store arguments being passed | |
49 | * to callee function and is located at fixed offset from stack pointer. | |
50 | */ | |
51 | #ifdef CONFIG_PPC32 | |
52 | #define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */ | |
53 | #else /* CONFIG_PPC32 */ | |
54 | #define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */ | |
55 | #endif | |
56 | ||
57 | struct pt_regs_offset { | |
58 | const char *name; | |
59 | int offset; | |
60 | }; | |
61 | ||
62 | #define STR(s) #s /* convert to string */ | |
63 | #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} | |
64 | #define GPR_OFFSET_NAME(num) \ | |
343c3327 | 65 | {.name = STR(r##num), .offset = offsetof(struct pt_regs, gpr[num])}, \ |
359e4284 MS |
66 | {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])} |
67 | #define REG_OFFSET_END {.name = NULL, .offset = 0} | |
68 | ||
8c13f599 | 69 | #define TVSO(f) (offsetof(struct thread_vr_state, f)) |
9d3918f7 | 70 | #define TFSO(f) (offsetof(struct thread_fp_state, f)) |
08e1c01d | 71 | #define TSO(f) (offsetof(struct thread_struct, f)) |
8c13f599 | 72 | |
359e4284 MS |
73 | static const struct pt_regs_offset regoffset_table[] = { |
74 | GPR_OFFSET_NAME(0), | |
75 | GPR_OFFSET_NAME(1), | |
76 | GPR_OFFSET_NAME(2), | |
77 | GPR_OFFSET_NAME(3), | |
78 | GPR_OFFSET_NAME(4), | |
79 | GPR_OFFSET_NAME(5), | |
80 | GPR_OFFSET_NAME(6), | |
81 | GPR_OFFSET_NAME(7), | |
82 | GPR_OFFSET_NAME(8), | |
83 | GPR_OFFSET_NAME(9), | |
84 | GPR_OFFSET_NAME(10), | |
85 | GPR_OFFSET_NAME(11), | |
86 | GPR_OFFSET_NAME(12), | |
87 | GPR_OFFSET_NAME(13), | |
88 | GPR_OFFSET_NAME(14), | |
89 | GPR_OFFSET_NAME(15), | |
90 | GPR_OFFSET_NAME(16), | |
91 | GPR_OFFSET_NAME(17), | |
92 | GPR_OFFSET_NAME(18), | |
93 | GPR_OFFSET_NAME(19), | |
94 | GPR_OFFSET_NAME(20), | |
95 | GPR_OFFSET_NAME(21), | |
96 | GPR_OFFSET_NAME(22), | |
97 | GPR_OFFSET_NAME(23), | |
98 | GPR_OFFSET_NAME(24), | |
99 | GPR_OFFSET_NAME(25), | |
100 | GPR_OFFSET_NAME(26), | |
101 | GPR_OFFSET_NAME(27), | |
102 | GPR_OFFSET_NAME(28), | |
103 | GPR_OFFSET_NAME(29), | |
104 | GPR_OFFSET_NAME(30), | |
105 | GPR_OFFSET_NAME(31), | |
106 | REG_OFFSET_NAME(nip), | |
107 | REG_OFFSET_NAME(msr), | |
108 | REG_OFFSET_NAME(ctr), | |
109 | REG_OFFSET_NAME(link), | |
110 | REG_OFFSET_NAME(xer), | |
111 | REG_OFFSET_NAME(ccr), | |
112 | #ifdef CONFIG_PPC64 | |
113 | REG_OFFSET_NAME(softe), | |
114 | #else | |
115 | REG_OFFSET_NAME(mq), | |
116 | #endif | |
117 | REG_OFFSET_NAME(trap), | |
118 | REG_OFFSET_NAME(dar), | |
119 | REG_OFFSET_NAME(dsisr), | |
120 | REG_OFFSET_END, | |
121 | }; | |
122 | ||
c7a318ba CB |
123 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
124 | static void flush_tmregs_to_thread(struct task_struct *tsk) | |
125 | { | |
126 | /* | |
127 | * If task is not current, it will have been flushed already to | |
128 | * it's thread_struct during __switch_to(). | |
129 | * | |
130 | * A reclaim flushes ALL the state. | |
131 | */ | |
132 | ||
133 | if (tsk == current && MSR_TM_SUSPENDED(mfmsr())) | |
134 | tm_reclaim_current(TM_CAUSE_SIGNAL); | |
135 | ||
136 | } | |
137 | #else | |
138 | static inline void flush_tmregs_to_thread(struct task_struct *tsk) { } | |
139 | #endif | |
140 | ||
359e4284 MS |
141 | /** |
142 | * regs_query_register_offset() - query register offset from its name | |
143 | * @name: the name of a register | |
144 | * | |
145 | * regs_query_register_offset() returns the offset of a register in struct | |
146 | * pt_regs from its name. If the name is invalid, this returns -EINVAL; | |
147 | */ | |
148 | int regs_query_register_offset(const char *name) | |
149 | { | |
150 | const struct pt_regs_offset *roff; | |
151 | for (roff = regoffset_table; roff->name != NULL; roff++) | |
152 | if (!strcmp(roff->name, name)) | |
153 | return roff->offset; | |
154 | return -EINVAL; | |
155 | } | |
156 | ||
157 | /** | |
158 | * regs_query_register_name() - query register name from its offset | |
159 | * @offset: the offset of a register in struct pt_regs. | |
160 | * | |
161 | * regs_query_register_name() returns the name of a register from its | |
162 | * offset in struct pt_regs. If the @offset is invalid, this returns NULL; | |
163 | */ | |
164 | const char *regs_query_register_name(unsigned int offset) | |
165 | { | |
166 | const struct pt_regs_offset *roff; | |
167 | for (roff = regoffset_table; roff->name != NULL; roff++) | |
168 | if (roff->offset == offset) | |
169 | return roff->name; | |
170 | return NULL; | |
171 | } | |
172 | ||
abd06505 BH |
173 | /* |
174 | * does not yet catch signals sent when the child dies. | |
175 | * in exit.c or in signal.c. | |
176 | */ | |
177 | ||
178 | /* | |
179 | * Set of msr bits that gdb can change on behalf of a process. | |
180 | */ | |
172ae2e7 | 181 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
abd06505 | 182 | #define MSR_DEBUGCHANGE 0 |
1da177e4 | 183 | #else |
abd06505 | 184 | #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE) |
1da177e4 | 185 | #endif |
acd89828 | 186 | |
1da177e4 | 187 | /* |
abd06505 | 188 | * Max register writeable via put_reg |
1da177e4 | 189 | */ |
abd06505 BH |
190 | #ifdef CONFIG_PPC32 |
191 | #define PT_MAX_PUT_REG PT_MQ | |
192 | #else | |
193 | #define PT_MAX_PUT_REG PT_CCR | |
194 | #endif | |
1da177e4 | 195 | |
26f77130 RM |
196 | static unsigned long get_user_msr(struct task_struct *task) |
197 | { | |
198 | return task->thread.regs->msr | task->thread.fpexc_mode; | |
199 | } | |
200 | ||
201 | static int set_user_msr(struct task_struct *task, unsigned long msr) | |
202 | { | |
203 | task->thread.regs->msr &= ~MSR_DEBUGCHANGE; | |
204 | task->thread.regs->msr |= msr & MSR_DEBUGCHANGE; | |
205 | return 0; | |
206 | } | |
207 | ||
25847fb1 AK |
208 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
209 | static unsigned long get_user_ckpt_msr(struct task_struct *task) | |
210 | { | |
211 | return task->thread.ckpt_regs.msr | task->thread.fpexc_mode; | |
212 | } | |
213 | ||
214 | static int set_user_ckpt_msr(struct task_struct *task, unsigned long msr) | |
215 | { | |
216 | task->thread.ckpt_regs.msr &= ~MSR_DEBUGCHANGE; | |
217 | task->thread.ckpt_regs.msr |= msr & MSR_DEBUGCHANGE; | |
218 | return 0; | |
219 | } | |
220 | ||
221 | static int set_user_ckpt_trap(struct task_struct *task, unsigned long trap) | |
222 | { | |
223 | task->thread.ckpt_regs.trap = trap & 0xfff0; | |
224 | return 0; | |
225 | } | |
226 | #endif | |
227 | ||
1715a826 | 228 | #ifdef CONFIG_PPC64 |
ee4a3916 | 229 | static int get_user_dscr(struct task_struct *task, unsigned long *data) |
1715a826 | 230 | { |
ee4a3916 AK |
231 | *data = task->thread.dscr; |
232 | return 0; | |
1715a826 AK |
233 | } |
234 | ||
235 | static int set_user_dscr(struct task_struct *task, unsigned long dscr) | |
236 | { | |
237 | task->thread.dscr = dscr; | |
238 | task->thread.dscr_inherit = 1; | |
239 | return 0; | |
240 | } | |
241 | #else | |
ee4a3916 | 242 | static int get_user_dscr(struct task_struct *task, unsigned long *data) |
1715a826 AK |
243 | { |
244 | return -EIO; | |
245 | } | |
246 | ||
247 | static int set_user_dscr(struct task_struct *task, unsigned long dscr) | |
248 | { | |
249 | return -EIO; | |
250 | } | |
251 | #endif | |
252 | ||
26f77130 RM |
253 | /* |
254 | * We prevent mucking around with the reserved area of trap | |
255 | * which are used internally by the kernel. | |
256 | */ | |
257 | static int set_user_trap(struct task_struct *task, unsigned long trap) | |
258 | { | |
259 | task->thread.regs->trap = trap & 0xfff0; | |
260 | return 0; | |
261 | } | |
262 | ||
865418d8 BH |
263 | /* |
264 | * Get contents of register REGNO in task TASK. | |
265 | */ | |
ee4a3916 | 266 | int ptrace_get_reg(struct task_struct *task, int regno, unsigned long *data) |
865418d8 | 267 | { |
ee4a3916 | 268 | if ((task->thread.regs == NULL) || !data) |
865418d8 BH |
269 | return -EIO; |
270 | ||
ee4a3916 AK |
271 | if (regno == PT_MSR) { |
272 | *data = get_user_msr(task); | |
273 | return 0; | |
274 | } | |
865418d8 | 275 | |
1715a826 | 276 | if (regno == PT_DSCR) |
ee4a3916 | 277 | return get_user_dscr(task, data); |
1715a826 | 278 | |
ee4a3916 AK |
279 | if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) { |
280 | *data = ((unsigned long *)task->thread.regs)[regno]; | |
281 | return 0; | |
282 | } | |
865418d8 BH |
283 | |
284 | return -EIO; | |
285 | } | |
286 | ||
287 | /* | |
288 | * Write contents of register REGNO in task TASK. | |
289 | */ | |
290 | int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data) | |
291 | { | |
292 | if (task->thread.regs == NULL) | |
293 | return -EIO; | |
294 | ||
26f77130 RM |
295 | if (regno == PT_MSR) |
296 | return set_user_msr(task, data); | |
297 | if (regno == PT_TRAP) | |
298 | return set_user_trap(task, data); | |
1715a826 AK |
299 | if (regno == PT_DSCR) |
300 | return set_user_dscr(task, data); | |
26f77130 RM |
301 | |
302 | if (regno <= PT_MAX_PUT_REG) { | |
865418d8 BH |
303 | ((unsigned long *)task->thread.regs)[regno] = data; |
304 | return 0; | |
305 | } | |
306 | return -EIO; | |
307 | } | |
308 | ||
44dd3f50 RM |
309 | static int gpr_get(struct task_struct *target, const struct user_regset *regset, |
310 | unsigned int pos, unsigned int count, | |
311 | void *kbuf, void __user *ubuf) | |
312 | { | |
a71f5d5d | 313 | int i, ret; |
44dd3f50 RM |
314 | |
315 | if (target->thread.regs == NULL) | |
316 | return -EIO; | |
317 | ||
a71f5d5d MW |
318 | if (!FULL_REGS(target->thread.regs)) { |
319 | /* We have a partial register set. Fill 14-31 with bogus values */ | |
320 | for (i = 14; i < 32; i++) | |
321 | target->thread.regs->gpr[i] = NV_REG_POISON; | |
322 | } | |
44dd3f50 RM |
323 | |
324 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
325 | target->thread.regs, | |
326 | 0, offsetof(struct pt_regs, msr)); | |
327 | if (!ret) { | |
328 | unsigned long msr = get_user_msr(target); | |
329 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr, | |
330 | offsetof(struct pt_regs, msr), | |
331 | offsetof(struct pt_regs, msr) + | |
332 | sizeof(msr)); | |
333 | } | |
334 | ||
335 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
336 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
337 | ||
338 | if (!ret) | |
339 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
340 | &target->thread.regs->orig_gpr3, | |
341 | offsetof(struct pt_regs, orig_gpr3), | |
342 | sizeof(struct pt_regs)); | |
343 | if (!ret) | |
344 | ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, | |
345 | sizeof(struct pt_regs), -1); | |
346 | ||
347 | return ret; | |
348 | } | |
349 | ||
350 | static int gpr_set(struct task_struct *target, const struct user_regset *regset, | |
351 | unsigned int pos, unsigned int count, | |
352 | const void *kbuf, const void __user *ubuf) | |
353 | { | |
354 | unsigned long reg; | |
355 | int ret; | |
356 | ||
357 | if (target->thread.regs == NULL) | |
358 | return -EIO; | |
359 | ||
360 | CHECK_FULL_REGS(target->thread.regs); | |
361 | ||
362 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
363 | target->thread.regs, | |
364 | 0, PT_MSR * sizeof(reg)); | |
365 | ||
366 | if (!ret && count > 0) { | |
367 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
368 | PT_MSR * sizeof(reg), | |
369 | (PT_MSR + 1) * sizeof(reg)); | |
370 | if (!ret) | |
371 | ret = set_user_msr(target, reg); | |
372 | } | |
373 | ||
374 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
375 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
376 | ||
377 | if (!ret) | |
378 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
379 | &target->thread.regs->orig_gpr3, | |
380 | PT_ORIG_R3 * sizeof(reg), | |
381 | (PT_MAX_PUT_REG + 1) * sizeof(reg)); | |
382 | ||
383 | if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret) | |
384 | ret = user_regset_copyin_ignore( | |
385 | &pos, &count, &kbuf, &ubuf, | |
386 | (PT_MAX_PUT_REG + 1) * sizeof(reg), | |
387 | PT_TRAP * sizeof(reg)); | |
388 | ||
389 | if (!ret && count > 0) { | |
390 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
391 | PT_TRAP * sizeof(reg), | |
392 | (PT_TRAP + 1) * sizeof(reg)); | |
393 | if (!ret) | |
394 | ret = set_user_trap(target, reg); | |
395 | } | |
396 | ||
397 | if (!ret) | |
398 | ret = user_regset_copyin_ignore( | |
399 | &pos, &count, &kbuf, &ubuf, | |
400 | (PT_TRAP + 1) * sizeof(reg), -1); | |
401 | ||
402 | return ret; | |
403 | } | |
865418d8 | 404 | |
1ec8549d | 405 | /* |
dc310669 | 406 | * Regardless of transactions, 'fp_state' holds the current running |
000ec280 | 407 | * value of all FPR registers and 'ckfp_state' holds the last checkpointed |
dc310669 | 408 | * value of all FPR registers for the current transaction. |
1ec8549d AK |
409 | * |
410 | * Userspace interface buffer layout: | |
411 | * | |
412 | * struct data { | |
413 | * u64 fpr[32]; | |
414 | * u64 fpscr; | |
415 | * }; | |
1ec8549d | 416 | */ |
f65255e8 RM |
417 | static int fpr_get(struct task_struct *target, const struct user_regset *regset, |
418 | unsigned int pos, unsigned int count, | |
419 | void *kbuf, void __user *ubuf) | |
420 | { | |
c6e6771b | 421 | #ifdef CONFIG_VSX |
de79f7b9 | 422 | u64 buf[33]; |
c6e6771b | 423 | int i; |
f65255e8 | 424 | |
dc310669 | 425 | flush_fp_to_thread(target); |
1ec8549d | 426 | |
c6e6771b MN |
427 | /* copy to local buffer then write that out */ |
428 | for (i = 0; i < 32 ; i++) | |
429 | buf[i] = target->thread.TS_FPR(i); | |
de79f7b9 | 430 | buf[32] = target->thread.fp_state.fpscr; |
c6e6771b | 431 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1); |
dc310669 | 432 | #else |
de79f7b9 | 433 | BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) != |
1e407ee3 | 434 | offsetof(struct thread_fp_state, fpr[32])); |
f65255e8 | 435 | |
dc310669 CB |
436 | flush_fp_to_thread(target); |
437 | ||
f65255e8 | 438 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
de79f7b9 | 439 | &target->thread.fp_state, 0, -1); |
c6e6771b | 440 | #endif |
f65255e8 RM |
441 | } |
442 | ||
1ec8549d | 443 | /* |
dc310669 | 444 | * Regardless of transactions, 'fp_state' holds the current running |
000ec280 | 445 | * value of all FPR registers and 'ckfp_state' holds the last checkpointed |
dc310669 | 446 | * value of all FPR registers for the current transaction. |
1ec8549d AK |
447 | * |
448 | * Userspace interface buffer layout: | |
449 | * | |
450 | * struct data { | |
451 | * u64 fpr[32]; | |
452 | * u64 fpscr; | |
453 | * }; | |
454 | * | |
1ec8549d | 455 | */ |
f65255e8 RM |
456 | static int fpr_set(struct task_struct *target, const struct user_regset *regset, |
457 | unsigned int pos, unsigned int count, | |
458 | const void *kbuf, const void __user *ubuf) | |
459 | { | |
c6e6771b | 460 | #ifdef CONFIG_VSX |
de79f7b9 | 461 | u64 buf[33]; |
c6e6771b | 462 | int i; |
dc310669 | 463 | |
f65255e8 RM |
464 | flush_fp_to_thread(target); |
465 | ||
1ec8549d AK |
466 | /* copy to local buffer then write that out */ |
467 | i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
468 | if (i) | |
469 | return i; | |
470 | ||
c6e6771b MN |
471 | for (i = 0; i < 32 ; i++) |
472 | target->thread.TS_FPR(i) = buf[i]; | |
de79f7b9 | 473 | target->thread.fp_state.fpscr = buf[32]; |
c6e6771b | 474 | return 0; |
dc310669 | 475 | #else |
de79f7b9 | 476 | BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) != |
1e407ee3 | 477 | offsetof(struct thread_fp_state, fpr[32])); |
f65255e8 | 478 | |
dc310669 CB |
479 | flush_fp_to_thread(target); |
480 | ||
f65255e8 | 481 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
de79f7b9 | 482 | &target->thread.fp_state, 0, -1); |
c6e6771b | 483 | #endif |
f65255e8 RM |
484 | } |
485 | ||
865418d8 BH |
486 | #ifdef CONFIG_ALTIVEC |
487 | /* | |
488 | * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. | |
489 | * The transfer totals 34 quadword. Quadwords 0-31 contain the | |
490 | * corresponding vector registers. Quadword 32 contains the vscr as the | |
491 | * last word (offset 12) within that quadword. Quadword 33 contains the | |
492 | * vrsave as the first word (offset 0) within the quadword. | |
493 | * | |
494 | * This definition of the VMX state is compatible with the current PPC32 | |
495 | * ptrace interface. This allows signal handling and ptrace to use the | |
496 | * same structures. This also simplifies the implementation of a bi-arch | |
497 | * (combined (32- and 64-bit) gdb. | |
498 | */ | |
499 | ||
3caf06c6 RM |
500 | static int vr_active(struct task_struct *target, |
501 | const struct user_regset *regset) | |
502 | { | |
503 | flush_altivec_to_thread(target); | |
504 | return target->thread.used_vr ? regset->n : 0; | |
505 | } | |
506 | ||
d844e279 | 507 | /* |
dc310669 | 508 | * Regardless of transactions, 'vr_state' holds the current running |
000ec280 | 509 | * value of all the VMX registers and 'ckvr_state' holds the last |
dc310669 CB |
510 | * checkpointed value of all the VMX registers for the current |
511 | * transaction to fall back on in case it aborts. | |
d844e279 AK |
512 | * |
513 | * Userspace interface buffer layout: | |
514 | * | |
515 | * struct data { | |
516 | * vector128 vr[32]; | |
517 | * vector128 vscr; | |
518 | * vector128 vrsave; | |
519 | * }; | |
520 | */ | |
3caf06c6 RM |
521 | static int vr_get(struct task_struct *target, const struct user_regset *regset, |
522 | unsigned int pos, unsigned int count, | |
523 | void *kbuf, void __user *ubuf) | |
524 | { | |
525 | int ret; | |
526 | ||
527 | flush_altivec_to_thread(target); | |
528 | ||
de79f7b9 PM |
529 | BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) != |
530 | offsetof(struct thread_vr_state, vr[32])); | |
3caf06c6 RM |
531 | |
532 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
dc310669 | 533 | &target->thread.vr_state, 0, |
3caf06c6 RM |
534 | 33 * sizeof(vector128)); |
535 | if (!ret) { | |
536 | /* | |
537 | * Copy out only the low-order word of vrsave. | |
538 | */ | |
539 | union { | |
540 | elf_vrreg_t reg; | |
541 | u32 word; | |
542 | } vrsave; | |
543 | memset(&vrsave, 0, sizeof(vrsave)); | |
d844e279 | 544 | |
3caf06c6 | 545 | vrsave.word = target->thread.vrsave; |
d844e279 | 546 | |
3caf06c6 RM |
547 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave, |
548 | 33 * sizeof(vector128), -1); | |
549 | } | |
550 | ||
551 | return ret; | |
552 | } | |
553 | ||
d844e279 | 554 | /* |
dc310669 | 555 | * Regardless of transactions, 'vr_state' holds the current running |
000ec280 | 556 | * value of all the VMX registers and 'ckvr_state' holds the last |
dc310669 CB |
557 | * checkpointed value of all the VMX registers for the current |
558 | * transaction to fall back on in case it aborts. | |
d844e279 AK |
559 | * |
560 | * Userspace interface buffer layout: | |
561 | * | |
562 | * struct data { | |
563 | * vector128 vr[32]; | |
564 | * vector128 vscr; | |
565 | * vector128 vrsave; | |
566 | * }; | |
567 | */ | |
3caf06c6 RM |
568 | static int vr_set(struct task_struct *target, const struct user_regset *regset, |
569 | unsigned int pos, unsigned int count, | |
570 | const void *kbuf, const void __user *ubuf) | |
571 | { | |
572 | int ret; | |
573 | ||
574 | flush_altivec_to_thread(target); | |
575 | ||
de79f7b9 PM |
576 | BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) != |
577 | offsetof(struct thread_vr_state, vr[32])); | |
3caf06c6 RM |
578 | |
579 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
dc310669 | 580 | &target->thread.vr_state, 0, |
de79f7b9 | 581 | 33 * sizeof(vector128)); |
3caf06c6 RM |
582 | if (!ret && count > 0) { |
583 | /* | |
584 | * We use only the first word of vrsave. | |
585 | */ | |
586 | union { | |
587 | elf_vrreg_t reg; | |
588 | u32 word; | |
589 | } vrsave; | |
590 | memset(&vrsave, 0, sizeof(vrsave)); | |
d844e279 | 591 | |
3caf06c6 | 592 | vrsave.word = target->thread.vrsave; |
dc310669 | 593 | |
3caf06c6 RM |
594 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave, |
595 | 33 * sizeof(vector128), -1); | |
dc310669 | 596 | if (!ret) |
3caf06c6 RM |
597 | target->thread.vrsave = vrsave.word; |
598 | } | |
599 | ||
600 | return ret; | |
601 | } | |
865418d8 BH |
602 | #endif /* CONFIG_ALTIVEC */ |
603 | ||
ce48b210 MN |
604 | #ifdef CONFIG_VSX |
605 | /* | |
606 | * Currently to set and and get all the vsx state, you need to call | |
25985edc | 607 | * the fp and VMX calls as well. This only get/sets the lower 32 |
ce48b210 MN |
608 | * 128bit VSX registers. |
609 | */ | |
610 | ||
611 | static int vsr_active(struct task_struct *target, | |
612 | const struct user_regset *regset) | |
613 | { | |
614 | flush_vsx_to_thread(target); | |
615 | return target->thread.used_vsr ? regset->n : 0; | |
616 | } | |
617 | ||
94b7d361 | 618 | /* |
dc310669 | 619 | * Regardless of transactions, 'fp_state' holds the current running |
000ec280 | 620 | * value of all FPR registers and 'ckfp_state' holds the last |
dc310669 CB |
621 | * checkpointed value of all FPR registers for the current |
622 | * transaction. | |
94b7d361 AK |
623 | * |
624 | * Userspace interface buffer layout: | |
625 | * | |
626 | * struct data { | |
627 | * u64 vsx[32]; | |
628 | * }; | |
629 | */ | |
ce48b210 MN |
630 | static int vsr_get(struct task_struct *target, const struct user_regset *regset, |
631 | unsigned int pos, unsigned int count, | |
632 | void *kbuf, void __user *ubuf) | |
633 | { | |
de79f7b9 | 634 | u64 buf[32]; |
f3e909c2 | 635 | int ret, i; |
ce48b210 | 636 | |
dc310669 | 637 | flush_tmregs_to_thread(target); |
94b7d361 AK |
638 | flush_fp_to_thread(target); |
639 | flush_altivec_to_thread(target); | |
ce48b210 MN |
640 | flush_vsx_to_thread(target); |
641 | ||
f3e909c2 | 642 | for (i = 0; i < 32 ; i++) |
de79f7b9 | 643 | buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET]; |
dc310669 | 644 | |
ce48b210 | 645 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
f3e909c2 | 646 | buf, 0, 32 * sizeof(double)); |
ce48b210 MN |
647 | |
648 | return ret; | |
649 | } | |
650 | ||
94b7d361 | 651 | /* |
dc310669 | 652 | * Regardless of transactions, 'fp_state' holds the current running |
000ec280 | 653 | * value of all FPR registers and 'ckfp_state' holds the last |
dc310669 CB |
654 | * checkpointed value of all FPR registers for the current |
655 | * transaction. | |
94b7d361 AK |
656 | * |
657 | * Userspace interface buffer layout: | |
658 | * | |
659 | * struct data { | |
660 | * u64 vsx[32]; | |
661 | * }; | |
662 | */ | |
ce48b210 MN |
663 | static int vsr_set(struct task_struct *target, const struct user_regset *regset, |
664 | unsigned int pos, unsigned int count, | |
665 | const void *kbuf, const void __user *ubuf) | |
666 | { | |
de79f7b9 | 667 | u64 buf[32]; |
f3e909c2 | 668 | int ret,i; |
ce48b210 | 669 | |
dc310669 | 670 | flush_tmregs_to_thread(target); |
94b7d361 AK |
671 | flush_fp_to_thread(target); |
672 | flush_altivec_to_thread(target); | |
ce48b210 MN |
673 | flush_vsx_to_thread(target); |
674 | ||
675 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
f3e909c2 | 676 | buf, 0, 32 * sizeof(double)); |
dc310669 | 677 | if (!ret) |
94b7d361 | 678 | for (i = 0; i < 32 ; i++) |
dc310669 | 679 | target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i]; |
ce48b210 MN |
680 | |
681 | return ret; | |
682 | } | |
683 | #endif /* CONFIG_VSX */ | |
684 | ||
865418d8 BH |
685 | #ifdef CONFIG_SPE |
686 | ||
687 | /* | |
688 | * For get_evrregs/set_evrregs functions 'data' has the following layout: | |
689 | * | |
690 | * struct { | |
691 | * u32 evr[32]; | |
692 | * u64 acc; | |
693 | * u32 spefscr; | |
694 | * } | |
695 | */ | |
696 | ||
a4e4b175 RM |
697 | static int evr_active(struct task_struct *target, |
698 | const struct user_regset *regset) | |
865418d8 | 699 | { |
a4e4b175 RM |
700 | flush_spe_to_thread(target); |
701 | return target->thread.used_spe ? regset->n : 0; | |
702 | } | |
865418d8 | 703 | |
a4e4b175 RM |
704 | static int evr_get(struct task_struct *target, const struct user_regset *regset, |
705 | unsigned int pos, unsigned int count, | |
706 | void *kbuf, void __user *ubuf) | |
707 | { | |
708 | int ret; | |
865418d8 | 709 | |
a4e4b175 | 710 | flush_spe_to_thread(target); |
865418d8 | 711 | |
a4e4b175 RM |
712 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
713 | &target->thread.evr, | |
714 | 0, sizeof(target->thread.evr)); | |
865418d8 | 715 | |
a4e4b175 RM |
716 | BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) != |
717 | offsetof(struct thread_struct, spefscr)); | |
718 | ||
719 | if (!ret) | |
720 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
721 | &target->thread.acc, | |
722 | sizeof(target->thread.evr), -1); | |
723 | ||
724 | return ret; | |
725 | } | |
726 | ||
727 | static int evr_set(struct task_struct *target, const struct user_regset *regset, | |
728 | unsigned int pos, unsigned int count, | |
729 | const void *kbuf, const void __user *ubuf) | |
730 | { | |
731 | int ret; | |
732 | ||
733 | flush_spe_to_thread(target); | |
734 | ||
735 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
736 | &target->thread.evr, | |
737 | 0, sizeof(target->thread.evr)); | |
865418d8 | 738 | |
a4e4b175 RM |
739 | BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) != |
740 | offsetof(struct thread_struct, spefscr)); | |
741 | ||
742 | if (!ret) | |
743 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
744 | &target->thread.acc, | |
745 | sizeof(target->thread.evr), -1); | |
746 | ||
747 | return ret; | |
865418d8 | 748 | } |
865418d8 BH |
749 | #endif /* CONFIG_SPE */ |
750 | ||
25847fb1 AK |
751 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
752 | /** | |
753 | * tm_cgpr_active - get active number of registers in CGPR | |
754 | * @target: The target task. | |
755 | * @regset: The user regset structure. | |
756 | * | |
757 | * This function checks for the active number of available | |
758 | * regisers in transaction checkpointed GPR category. | |
759 | */ | |
760 | static int tm_cgpr_active(struct task_struct *target, | |
761 | const struct user_regset *regset) | |
762 | { | |
763 | if (!cpu_has_feature(CPU_FTR_TM)) | |
764 | return -ENODEV; | |
765 | ||
766 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
767 | return 0; | |
768 | ||
769 | return regset->n; | |
770 | } | |
771 | ||
772 | /** | |
773 | * tm_cgpr_get - get CGPR registers | |
774 | * @target: The target task. | |
775 | * @regset: The user regset structure. | |
776 | * @pos: The buffer position. | |
777 | * @count: Number of bytes to copy. | |
778 | * @kbuf: Kernel buffer to copy from. | |
779 | * @ubuf: User buffer to copy into. | |
780 | * | |
781 | * This function gets transaction checkpointed GPR registers. | |
782 | * | |
783 | * When the transaction is active, 'ckpt_regs' holds all the checkpointed | |
784 | * GPR register values for the current transaction to fall back on if it | |
785 | * aborts in between. This function gets those checkpointed GPR registers. | |
786 | * The userspace interface buffer layout is as follows. | |
787 | * | |
788 | * struct data { | |
789 | * struct pt_regs ckpt_regs; | |
790 | * }; | |
791 | */ | |
792 | static int tm_cgpr_get(struct task_struct *target, | |
793 | const struct user_regset *regset, | |
794 | unsigned int pos, unsigned int count, | |
795 | void *kbuf, void __user *ubuf) | |
796 | { | |
797 | int ret; | |
798 | ||
799 | if (!cpu_has_feature(CPU_FTR_TM)) | |
800 | return -ENODEV; | |
801 | ||
802 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
803 | return -ENODATA; | |
804 | ||
dc310669 | 805 | flush_tmregs_to_thread(target); |
25847fb1 AK |
806 | flush_fp_to_thread(target); |
807 | flush_altivec_to_thread(target); | |
25847fb1 AK |
808 | |
809 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
810 | &target->thread.ckpt_regs, | |
811 | 0, offsetof(struct pt_regs, msr)); | |
812 | if (!ret) { | |
813 | unsigned long msr = get_user_ckpt_msr(target); | |
814 | ||
815 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr, | |
816 | offsetof(struct pt_regs, msr), | |
817 | offsetof(struct pt_regs, msr) + | |
818 | sizeof(msr)); | |
819 | } | |
820 | ||
821 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
822 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
823 | ||
824 | if (!ret) | |
825 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
826 | &target->thread.ckpt_regs.orig_gpr3, | |
827 | offsetof(struct pt_regs, orig_gpr3), | |
828 | sizeof(struct pt_regs)); | |
829 | if (!ret) | |
830 | ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, | |
831 | sizeof(struct pt_regs), -1); | |
832 | ||
833 | return ret; | |
834 | } | |
835 | ||
836 | /* | |
837 | * tm_cgpr_set - set the CGPR registers | |
838 | * @target: The target task. | |
839 | * @regset: The user regset structure. | |
840 | * @pos: The buffer position. | |
841 | * @count: Number of bytes to copy. | |
842 | * @kbuf: Kernel buffer to copy into. | |
843 | * @ubuf: User buffer to copy from. | |
844 | * | |
845 | * This function sets in transaction checkpointed GPR registers. | |
846 | * | |
847 | * When the transaction is active, 'ckpt_regs' holds the checkpointed | |
848 | * GPR register values for the current transaction to fall back on if it | |
849 | * aborts in between. This function sets those checkpointed GPR registers. | |
850 | * The userspace interface buffer layout is as follows. | |
851 | * | |
852 | * struct data { | |
853 | * struct pt_regs ckpt_regs; | |
854 | * }; | |
855 | */ | |
856 | static int tm_cgpr_set(struct task_struct *target, | |
857 | const struct user_regset *regset, | |
858 | unsigned int pos, unsigned int count, | |
859 | const void *kbuf, const void __user *ubuf) | |
860 | { | |
861 | unsigned long reg; | |
862 | int ret; | |
863 | ||
864 | if (!cpu_has_feature(CPU_FTR_TM)) | |
865 | return -ENODEV; | |
866 | ||
867 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
868 | return -ENODATA; | |
869 | ||
dc310669 | 870 | flush_tmregs_to_thread(target); |
25847fb1 AK |
871 | flush_fp_to_thread(target); |
872 | flush_altivec_to_thread(target); | |
25847fb1 AK |
873 | |
874 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
875 | &target->thread.ckpt_regs, | |
876 | 0, PT_MSR * sizeof(reg)); | |
877 | ||
878 | if (!ret && count > 0) { | |
879 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
880 | PT_MSR * sizeof(reg), | |
881 | (PT_MSR + 1) * sizeof(reg)); | |
882 | if (!ret) | |
883 | ret = set_user_ckpt_msr(target, reg); | |
884 | } | |
885 | ||
886 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
887 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
888 | ||
889 | if (!ret) | |
890 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
891 | &target->thread.ckpt_regs.orig_gpr3, | |
892 | PT_ORIG_R3 * sizeof(reg), | |
893 | (PT_MAX_PUT_REG + 1) * sizeof(reg)); | |
894 | ||
895 | if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret) | |
896 | ret = user_regset_copyin_ignore( | |
897 | &pos, &count, &kbuf, &ubuf, | |
898 | (PT_MAX_PUT_REG + 1) * sizeof(reg), | |
899 | PT_TRAP * sizeof(reg)); | |
900 | ||
901 | if (!ret && count > 0) { | |
902 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
903 | PT_TRAP * sizeof(reg), | |
904 | (PT_TRAP + 1) * sizeof(reg)); | |
905 | if (!ret) | |
906 | ret = set_user_ckpt_trap(target, reg); | |
907 | } | |
908 | ||
909 | if (!ret) | |
910 | ret = user_regset_copyin_ignore( | |
911 | &pos, &count, &kbuf, &ubuf, | |
912 | (PT_TRAP + 1) * sizeof(reg), -1); | |
913 | ||
914 | return ret; | |
915 | } | |
19cbcbf7 AK |
916 | |
917 | /** | |
918 | * tm_cfpr_active - get active number of registers in CFPR | |
919 | * @target: The target task. | |
920 | * @regset: The user regset structure. | |
921 | * | |
922 | * This function checks for the active number of available | |
923 | * regisers in transaction checkpointed FPR category. | |
924 | */ | |
925 | static int tm_cfpr_active(struct task_struct *target, | |
926 | const struct user_regset *regset) | |
927 | { | |
928 | if (!cpu_has_feature(CPU_FTR_TM)) | |
929 | return -ENODEV; | |
930 | ||
931 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
932 | return 0; | |
933 | ||
934 | return regset->n; | |
935 | } | |
936 | ||
937 | /** | |
938 | * tm_cfpr_get - get CFPR registers | |
939 | * @target: The target task. | |
940 | * @regset: The user regset structure. | |
941 | * @pos: The buffer position. | |
942 | * @count: Number of bytes to copy. | |
943 | * @kbuf: Kernel buffer to copy from. | |
944 | * @ubuf: User buffer to copy into. | |
945 | * | |
946 | * This function gets in transaction checkpointed FPR registers. | |
947 | * | |
000ec280 | 948 | * When the transaction is active 'ckfp_state' holds the checkpointed |
19cbcbf7 AK |
949 | * values for the current transaction to fall back on if it aborts |
950 | * in between. This function gets those checkpointed FPR registers. | |
951 | * The userspace interface buffer layout is as follows. | |
952 | * | |
953 | * struct data { | |
954 | * u64 fpr[32]; | |
955 | * u64 fpscr; | |
956 | *}; | |
957 | */ | |
958 | static int tm_cfpr_get(struct task_struct *target, | |
959 | const struct user_regset *regset, | |
960 | unsigned int pos, unsigned int count, | |
961 | void *kbuf, void __user *ubuf) | |
962 | { | |
963 | u64 buf[33]; | |
964 | int i; | |
965 | ||
966 | if (!cpu_has_feature(CPU_FTR_TM)) | |
967 | return -ENODEV; | |
968 | ||
969 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
970 | return -ENODATA; | |
971 | ||
dc310669 | 972 | flush_tmregs_to_thread(target); |
19cbcbf7 AK |
973 | flush_fp_to_thread(target); |
974 | flush_altivec_to_thread(target); | |
19cbcbf7 AK |
975 | |
976 | /* copy to local buffer then write that out */ | |
977 | for (i = 0; i < 32 ; i++) | |
000ec280 CB |
978 | buf[i] = target->thread.TS_CKFPR(i); |
979 | buf[32] = target->thread.ckfp_state.fpscr; | |
19cbcbf7 AK |
980 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1); |
981 | } | |
982 | ||
983 | /** | |
984 | * tm_cfpr_set - set CFPR registers | |
985 | * @target: The target task. | |
986 | * @regset: The user regset structure. | |
987 | * @pos: The buffer position. | |
988 | * @count: Number of bytes to copy. | |
989 | * @kbuf: Kernel buffer to copy into. | |
990 | * @ubuf: User buffer to copy from. | |
991 | * | |
992 | * This function sets in transaction checkpointed FPR registers. | |
993 | * | |
000ec280 | 994 | * When the transaction is active 'ckfp_state' holds the checkpointed |
19cbcbf7 AK |
995 | * FPR register values for the current transaction to fall back on |
996 | * if it aborts in between. This function sets these checkpointed | |
997 | * FPR registers. The userspace interface buffer layout is as follows. | |
998 | * | |
999 | * struct data { | |
1000 | * u64 fpr[32]; | |
1001 | * u64 fpscr; | |
1002 | *}; | |
1003 | */ | |
1004 | static int tm_cfpr_set(struct task_struct *target, | |
1005 | const struct user_regset *regset, | |
1006 | unsigned int pos, unsigned int count, | |
1007 | const void *kbuf, const void __user *ubuf) | |
1008 | { | |
1009 | u64 buf[33]; | |
1010 | int i; | |
1011 | ||
1012 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1013 | return -ENODEV; | |
1014 | ||
1015 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1016 | return -ENODATA; | |
1017 | ||
dc310669 | 1018 | flush_tmregs_to_thread(target); |
19cbcbf7 AK |
1019 | flush_fp_to_thread(target); |
1020 | flush_altivec_to_thread(target); | |
19cbcbf7 AK |
1021 | |
1022 | /* copy to local buffer then write that out */ | |
1023 | i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
1024 | if (i) | |
1025 | return i; | |
1026 | for (i = 0; i < 32 ; i++) | |
000ec280 CB |
1027 | target->thread.TS_CKFPR(i) = buf[i]; |
1028 | target->thread.ckfp_state.fpscr = buf[32]; | |
19cbcbf7 AK |
1029 | return 0; |
1030 | } | |
8c13f599 AK |
1031 | |
1032 | /** | |
1033 | * tm_cvmx_active - get active number of registers in CVMX | |
1034 | * @target: The target task. | |
1035 | * @regset: The user regset structure. | |
1036 | * | |
1037 | * This function checks for the active number of available | |
1038 | * regisers in checkpointed VMX category. | |
1039 | */ | |
1040 | static int tm_cvmx_active(struct task_struct *target, | |
1041 | const struct user_regset *regset) | |
1042 | { | |
1043 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1044 | return -ENODEV; | |
1045 | ||
1046 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1047 | return 0; | |
1048 | ||
1049 | return regset->n; | |
1050 | } | |
1051 | ||
1052 | /** | |
1053 | * tm_cvmx_get - get CMVX registers | |
1054 | * @target: The target task. | |
1055 | * @regset: The user regset structure. | |
1056 | * @pos: The buffer position. | |
1057 | * @count: Number of bytes to copy. | |
1058 | * @kbuf: Kernel buffer to copy from. | |
1059 | * @ubuf: User buffer to copy into. | |
1060 | * | |
1061 | * This function gets in transaction checkpointed VMX registers. | |
1062 | * | |
000ec280 | 1063 | * When the transaction is active 'ckvr_state' and 'ckvrsave' hold |
8c13f599 AK |
1064 | * the checkpointed values for the current transaction to fall |
1065 | * back on if it aborts in between. The userspace interface buffer | |
1066 | * layout is as follows. | |
1067 | * | |
1068 | * struct data { | |
1069 | * vector128 vr[32]; | |
1070 | * vector128 vscr; | |
1071 | * vector128 vrsave; | |
1072 | *}; | |
1073 | */ | |
1074 | static int tm_cvmx_get(struct task_struct *target, | |
1075 | const struct user_regset *regset, | |
1076 | unsigned int pos, unsigned int count, | |
1077 | void *kbuf, void __user *ubuf) | |
1078 | { | |
1079 | int ret; | |
1080 | ||
1081 | BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32])); | |
1082 | ||
1083 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1084 | return -ENODEV; | |
1085 | ||
1086 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1087 | return -ENODATA; | |
1088 | ||
1089 | /* Flush the state */ | |
dc310669 | 1090 | flush_tmregs_to_thread(target); |
8c13f599 AK |
1091 | flush_fp_to_thread(target); |
1092 | flush_altivec_to_thread(target); | |
8c13f599 AK |
1093 | |
1094 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
000ec280 | 1095 | &target->thread.ckvr_state, 0, |
8c13f599 AK |
1096 | 33 * sizeof(vector128)); |
1097 | if (!ret) { | |
1098 | /* | |
1099 | * Copy out only the low-order word of vrsave. | |
1100 | */ | |
1101 | union { | |
1102 | elf_vrreg_t reg; | |
1103 | u32 word; | |
1104 | } vrsave; | |
1105 | memset(&vrsave, 0, sizeof(vrsave)); | |
000ec280 | 1106 | vrsave.word = target->thread.ckvrsave; |
8c13f599 AK |
1107 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave, |
1108 | 33 * sizeof(vector128), -1); | |
1109 | } | |
1110 | ||
1111 | return ret; | |
1112 | } | |
1113 | ||
1114 | /** | |
1115 | * tm_cvmx_set - set CMVX registers | |
1116 | * @target: The target task. | |
1117 | * @regset: The user regset structure. | |
1118 | * @pos: The buffer position. | |
1119 | * @count: Number of bytes to copy. | |
1120 | * @kbuf: Kernel buffer to copy into. | |
1121 | * @ubuf: User buffer to copy from. | |
1122 | * | |
1123 | * This function sets in transaction checkpointed VMX registers. | |
1124 | * | |
000ec280 | 1125 | * When the transaction is active 'ckvr_state' and 'ckvrsave' hold |
8c13f599 AK |
1126 | * the checkpointed values for the current transaction to fall |
1127 | * back on if it aborts in between. The userspace interface buffer | |
1128 | * layout is as follows. | |
1129 | * | |
1130 | * struct data { | |
1131 | * vector128 vr[32]; | |
1132 | * vector128 vscr; | |
1133 | * vector128 vrsave; | |
1134 | *}; | |
1135 | */ | |
1136 | static int tm_cvmx_set(struct task_struct *target, | |
1137 | const struct user_regset *regset, | |
1138 | unsigned int pos, unsigned int count, | |
1139 | const void *kbuf, const void __user *ubuf) | |
1140 | { | |
1141 | int ret; | |
1142 | ||
1143 | BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32])); | |
1144 | ||
1145 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1146 | return -ENODEV; | |
1147 | ||
1148 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1149 | return -ENODATA; | |
1150 | ||
dc310669 | 1151 | flush_tmregs_to_thread(target); |
8c13f599 AK |
1152 | flush_fp_to_thread(target); |
1153 | flush_altivec_to_thread(target); | |
8c13f599 AK |
1154 | |
1155 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
000ec280 | 1156 | &target->thread.ckvr_state, 0, |
8c13f599 AK |
1157 | 33 * sizeof(vector128)); |
1158 | if (!ret && count > 0) { | |
1159 | /* | |
1160 | * We use only the low-order word of vrsave. | |
1161 | */ | |
1162 | union { | |
1163 | elf_vrreg_t reg; | |
1164 | u32 word; | |
1165 | } vrsave; | |
1166 | memset(&vrsave, 0, sizeof(vrsave)); | |
000ec280 | 1167 | vrsave.word = target->thread.ckvrsave; |
8c13f599 AK |
1168 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave, |
1169 | 33 * sizeof(vector128), -1); | |
1170 | if (!ret) | |
000ec280 | 1171 | target->thread.ckvrsave = vrsave.word; |
8c13f599 AK |
1172 | } |
1173 | ||
1174 | return ret; | |
1175 | } | |
9d3918f7 AK |
1176 | |
1177 | /** | |
1178 | * tm_cvsx_active - get active number of registers in CVSX | |
1179 | * @target: The target task. | |
1180 | * @regset: The user regset structure. | |
1181 | * | |
1182 | * This function checks for the active number of available | |
1183 | * regisers in transaction checkpointed VSX category. | |
1184 | */ | |
1185 | static int tm_cvsx_active(struct task_struct *target, | |
1186 | const struct user_regset *regset) | |
1187 | { | |
1188 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1189 | return -ENODEV; | |
1190 | ||
1191 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1192 | return 0; | |
1193 | ||
1194 | flush_vsx_to_thread(target); | |
1195 | return target->thread.used_vsr ? regset->n : 0; | |
1196 | } | |
1197 | ||
1198 | /** | |
1199 | * tm_cvsx_get - get CVSX registers | |
1200 | * @target: The target task. | |
1201 | * @regset: The user regset structure. | |
1202 | * @pos: The buffer position. | |
1203 | * @count: Number of bytes to copy. | |
1204 | * @kbuf: Kernel buffer to copy from. | |
1205 | * @ubuf: User buffer to copy into. | |
1206 | * | |
1207 | * This function gets in transaction checkpointed VSX registers. | |
1208 | * | |
000ec280 | 1209 | * When the transaction is active 'ckfp_state' holds the checkpointed |
9d3918f7 AK |
1210 | * values for the current transaction to fall back on if it aborts |
1211 | * in between. This function gets those checkpointed VSX registers. | |
1212 | * The userspace interface buffer layout is as follows. | |
1213 | * | |
1214 | * struct data { | |
1215 | * u64 vsx[32]; | |
1216 | *}; | |
1217 | */ | |
1218 | static int tm_cvsx_get(struct task_struct *target, | |
1219 | const struct user_regset *regset, | |
1220 | unsigned int pos, unsigned int count, | |
1221 | void *kbuf, void __user *ubuf) | |
1222 | { | |
1223 | u64 buf[32]; | |
1224 | int ret, i; | |
1225 | ||
1226 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1227 | return -ENODEV; | |
1228 | ||
1229 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1230 | return -ENODATA; | |
1231 | ||
1232 | /* Flush the state */ | |
dc310669 | 1233 | flush_tmregs_to_thread(target); |
9d3918f7 AK |
1234 | flush_fp_to_thread(target); |
1235 | flush_altivec_to_thread(target); | |
9d3918f7 AK |
1236 | flush_vsx_to_thread(target); |
1237 | ||
1238 | for (i = 0; i < 32 ; i++) | |
000ec280 | 1239 | buf[i] = target->thread.ckfp_state.fpr[i][TS_VSRLOWOFFSET]; |
9d3918f7 AK |
1240 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
1241 | buf, 0, 32 * sizeof(double)); | |
1242 | ||
1243 | return ret; | |
1244 | } | |
1245 | ||
1246 | /** | |
1247 | * tm_cvsx_set - set CFPR registers | |
1248 | * @target: The target task. | |
1249 | * @regset: The user regset structure. | |
1250 | * @pos: The buffer position. | |
1251 | * @count: Number of bytes to copy. | |
1252 | * @kbuf: Kernel buffer to copy into. | |
1253 | * @ubuf: User buffer to copy from. | |
1254 | * | |
1255 | * This function sets in transaction checkpointed VSX registers. | |
1256 | * | |
000ec280 | 1257 | * When the transaction is active 'ckfp_state' holds the checkpointed |
9d3918f7 AK |
1258 | * VSX register values for the current transaction to fall back on |
1259 | * if it aborts in between. This function sets these checkpointed | |
1260 | * FPR registers. The userspace interface buffer layout is as follows. | |
1261 | * | |
1262 | * struct data { | |
1263 | * u64 vsx[32]; | |
1264 | *}; | |
1265 | */ | |
1266 | static int tm_cvsx_set(struct task_struct *target, | |
1267 | const struct user_regset *regset, | |
1268 | unsigned int pos, unsigned int count, | |
1269 | const void *kbuf, const void __user *ubuf) | |
1270 | { | |
1271 | u64 buf[32]; | |
1272 | int ret, i; | |
1273 | ||
1274 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1275 | return -ENODEV; | |
1276 | ||
1277 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1278 | return -ENODATA; | |
1279 | ||
1280 | /* Flush the state */ | |
dc310669 | 1281 | flush_tmregs_to_thread(target); |
9d3918f7 AK |
1282 | flush_fp_to_thread(target); |
1283 | flush_altivec_to_thread(target); | |
9d3918f7 AK |
1284 | flush_vsx_to_thread(target); |
1285 | ||
1286 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1287 | buf, 0, 32 * sizeof(double)); | |
dc310669 CB |
1288 | if (!ret) |
1289 | for (i = 0; i < 32 ; i++) | |
000ec280 | 1290 | target->thread.ckfp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i]; |
9d3918f7 AK |
1291 | |
1292 | return ret; | |
1293 | } | |
08e1c01d AK |
1294 | |
1295 | /** | |
1296 | * tm_spr_active - get active number of registers in TM SPR | |
1297 | * @target: The target task. | |
1298 | * @regset: The user regset structure. | |
1299 | * | |
1300 | * This function checks the active number of available | |
1301 | * regisers in the transactional memory SPR category. | |
1302 | */ | |
1303 | static int tm_spr_active(struct task_struct *target, | |
1304 | const struct user_regset *regset) | |
1305 | { | |
1306 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1307 | return -ENODEV; | |
1308 | ||
1309 | return regset->n; | |
1310 | } | |
1311 | ||
1312 | /** | |
1313 | * tm_spr_get - get the TM related SPR registers | |
1314 | * @target: The target task. | |
1315 | * @regset: The user regset structure. | |
1316 | * @pos: The buffer position. | |
1317 | * @count: Number of bytes to copy. | |
1318 | * @kbuf: Kernel buffer to copy from. | |
1319 | * @ubuf: User buffer to copy into. | |
1320 | * | |
1321 | * This function gets transactional memory related SPR registers. | |
1322 | * The userspace interface buffer layout is as follows. | |
1323 | * | |
1324 | * struct { | |
1325 | * u64 tm_tfhar; | |
1326 | * u64 tm_texasr; | |
1327 | * u64 tm_tfiar; | |
1328 | * }; | |
1329 | */ | |
1330 | static int tm_spr_get(struct task_struct *target, | |
1331 | const struct user_regset *regset, | |
1332 | unsigned int pos, unsigned int count, | |
1333 | void *kbuf, void __user *ubuf) | |
1334 | { | |
1335 | int ret; | |
1336 | ||
1337 | /* Build tests */ | |
1338 | BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr)); | |
1339 | BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar)); | |
1340 | BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(ckpt_regs)); | |
1341 | ||
1342 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1343 | return -ENODEV; | |
1344 | ||
1345 | /* Flush the states */ | |
dc310669 | 1346 | flush_tmregs_to_thread(target); |
08e1c01d AK |
1347 | flush_fp_to_thread(target); |
1348 | flush_altivec_to_thread(target); | |
08e1c01d AK |
1349 | |
1350 | /* TFHAR register */ | |
1351 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1352 | &target->thread.tm_tfhar, 0, sizeof(u64)); | |
1353 | ||
1354 | /* TEXASR register */ | |
1355 | if (!ret) | |
1356 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1357 | &target->thread.tm_texasr, sizeof(u64), | |
1358 | 2 * sizeof(u64)); | |
1359 | ||
1360 | /* TFIAR register */ | |
1361 | if (!ret) | |
1362 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1363 | &target->thread.tm_tfiar, | |
1364 | 2 * sizeof(u64), 3 * sizeof(u64)); | |
1365 | return ret; | |
1366 | } | |
1367 | ||
1368 | /** | |
1369 | * tm_spr_set - set the TM related SPR registers | |
1370 | * @target: The target task. | |
1371 | * @regset: The user regset structure. | |
1372 | * @pos: The buffer position. | |
1373 | * @count: Number of bytes to copy. | |
1374 | * @kbuf: Kernel buffer to copy into. | |
1375 | * @ubuf: User buffer to copy from. | |
1376 | * | |
1377 | * This function sets transactional memory related SPR registers. | |
1378 | * The userspace interface buffer layout is as follows. | |
1379 | * | |
1380 | * struct { | |
1381 | * u64 tm_tfhar; | |
1382 | * u64 tm_texasr; | |
1383 | * u64 tm_tfiar; | |
1384 | * }; | |
1385 | */ | |
1386 | static int tm_spr_set(struct task_struct *target, | |
1387 | const struct user_regset *regset, | |
1388 | unsigned int pos, unsigned int count, | |
1389 | const void *kbuf, const void __user *ubuf) | |
1390 | { | |
1391 | int ret; | |
1392 | ||
1393 | /* Build tests */ | |
1394 | BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr)); | |
1395 | BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar)); | |
1396 | BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(ckpt_regs)); | |
1397 | ||
1398 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1399 | return -ENODEV; | |
1400 | ||
1401 | /* Flush the states */ | |
dc310669 | 1402 | flush_tmregs_to_thread(target); |
08e1c01d AK |
1403 | flush_fp_to_thread(target); |
1404 | flush_altivec_to_thread(target); | |
08e1c01d AK |
1405 | |
1406 | /* TFHAR register */ | |
1407 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1408 | &target->thread.tm_tfhar, 0, sizeof(u64)); | |
1409 | ||
1410 | /* TEXASR register */ | |
1411 | if (!ret) | |
1412 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1413 | &target->thread.tm_texasr, sizeof(u64), | |
1414 | 2 * sizeof(u64)); | |
1415 | ||
1416 | /* TFIAR register */ | |
1417 | if (!ret) | |
1418 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1419 | &target->thread.tm_tfiar, | |
1420 | 2 * sizeof(u64), 3 * sizeof(u64)); | |
1421 | return ret; | |
1422 | } | |
c45dc900 AK |
1423 | |
1424 | static int tm_tar_active(struct task_struct *target, | |
1425 | const struct user_regset *regset) | |
1426 | { | |
1427 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1428 | return -ENODEV; | |
1429 | ||
1430 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1431 | return regset->n; | |
1432 | ||
1433 | return 0; | |
1434 | } | |
1435 | ||
1436 | static int tm_tar_get(struct task_struct *target, | |
1437 | const struct user_regset *regset, | |
1438 | unsigned int pos, unsigned int count, | |
1439 | void *kbuf, void __user *ubuf) | |
1440 | { | |
1441 | int ret; | |
1442 | ||
1443 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1444 | return -ENODEV; | |
1445 | ||
1446 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1447 | return -ENODATA; | |
1448 | ||
1449 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1450 | &target->thread.tm_tar, 0, sizeof(u64)); | |
1451 | return ret; | |
1452 | } | |
1453 | ||
1454 | static int tm_tar_set(struct task_struct *target, | |
1455 | const struct user_regset *regset, | |
1456 | unsigned int pos, unsigned int count, | |
1457 | const void *kbuf, const void __user *ubuf) | |
1458 | { | |
1459 | int ret; | |
1460 | ||
1461 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1462 | return -ENODEV; | |
1463 | ||
1464 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1465 | return -ENODATA; | |
1466 | ||
1467 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1468 | &target->thread.tm_tar, 0, sizeof(u64)); | |
1469 | return ret; | |
1470 | } | |
1471 | ||
1472 | static int tm_ppr_active(struct task_struct *target, | |
1473 | const struct user_regset *regset) | |
1474 | { | |
1475 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1476 | return -ENODEV; | |
1477 | ||
1478 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1479 | return regset->n; | |
1480 | ||
1481 | return 0; | |
1482 | } | |
1483 | ||
1484 | ||
1485 | static int tm_ppr_get(struct task_struct *target, | |
1486 | const struct user_regset *regset, | |
1487 | unsigned int pos, unsigned int count, | |
1488 | void *kbuf, void __user *ubuf) | |
1489 | { | |
1490 | int ret; | |
1491 | ||
1492 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1493 | return -ENODEV; | |
1494 | ||
1495 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1496 | return -ENODATA; | |
1497 | ||
1498 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1499 | &target->thread.tm_ppr, 0, sizeof(u64)); | |
1500 | return ret; | |
1501 | } | |
1502 | ||
1503 | static int tm_ppr_set(struct task_struct *target, | |
1504 | const struct user_regset *regset, | |
1505 | unsigned int pos, unsigned int count, | |
1506 | const void *kbuf, const void __user *ubuf) | |
1507 | { | |
1508 | int ret; | |
1509 | ||
1510 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1511 | return -ENODEV; | |
1512 | ||
1513 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1514 | return -ENODATA; | |
1515 | ||
1516 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1517 | &target->thread.tm_ppr, 0, sizeof(u64)); | |
1518 | return ret; | |
1519 | } | |
1520 | ||
1521 | static int tm_dscr_active(struct task_struct *target, | |
1522 | const struct user_regset *regset) | |
1523 | { | |
1524 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1525 | return -ENODEV; | |
1526 | ||
1527 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1528 | return regset->n; | |
1529 | ||
1530 | return 0; | |
1531 | } | |
1532 | ||
1533 | static int tm_dscr_get(struct task_struct *target, | |
1534 | const struct user_regset *regset, | |
1535 | unsigned int pos, unsigned int count, | |
1536 | void *kbuf, void __user *ubuf) | |
1537 | { | |
1538 | int ret; | |
1539 | ||
1540 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1541 | return -ENODEV; | |
1542 | ||
1543 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1544 | return -ENODATA; | |
1545 | ||
1546 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1547 | &target->thread.tm_dscr, 0, sizeof(u64)); | |
1548 | return ret; | |
1549 | } | |
1550 | ||
1551 | static int tm_dscr_set(struct task_struct *target, | |
1552 | const struct user_regset *regset, | |
1553 | unsigned int pos, unsigned int count, | |
1554 | const void *kbuf, const void __user *ubuf) | |
1555 | { | |
1556 | int ret; | |
1557 | ||
1558 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1559 | return -ENODEV; | |
1560 | ||
1561 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1562 | return -ENODATA; | |
1563 | ||
1564 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1565 | &target->thread.tm_dscr, 0, sizeof(u64)); | |
1566 | return ret; | |
1567 | } | |
08e1c01d | 1568 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
865418d8 | 1569 | |
fa439810 AK |
1570 | #ifdef CONFIG_PPC64 |
1571 | static int ppr_get(struct task_struct *target, | |
1572 | const struct user_regset *regset, | |
1573 | unsigned int pos, unsigned int count, | |
1574 | void *kbuf, void __user *ubuf) | |
1575 | { | |
1576 | int ret; | |
1577 | ||
1578 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1579 | &target->thread.ppr, 0, sizeof(u64)); | |
1580 | return ret; | |
1581 | } | |
1582 | ||
1583 | static int ppr_set(struct task_struct *target, | |
1584 | const struct user_regset *regset, | |
1585 | unsigned int pos, unsigned int count, | |
1586 | const void *kbuf, const void __user *ubuf) | |
1587 | { | |
1588 | int ret; | |
1589 | ||
1590 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1591 | &target->thread.ppr, 0, sizeof(u64)); | |
1592 | return ret; | |
1593 | } | |
1594 | ||
1595 | static int dscr_get(struct task_struct *target, | |
1596 | const struct user_regset *regset, | |
1597 | unsigned int pos, unsigned int count, | |
1598 | void *kbuf, void __user *ubuf) | |
1599 | { | |
1600 | int ret; | |
1601 | ||
1602 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1603 | &target->thread.dscr, 0, sizeof(u64)); | |
1604 | return ret; | |
1605 | } | |
1606 | static int dscr_set(struct task_struct *target, | |
1607 | const struct user_regset *regset, | |
1608 | unsigned int pos, unsigned int count, | |
1609 | const void *kbuf, const void __user *ubuf) | |
1610 | { | |
1611 | int ret; | |
1612 | ||
1613 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1614 | &target->thread.dscr, 0, sizeof(u64)); | |
1615 | return ret; | |
1616 | } | |
1617 | #endif | |
1618 | #ifdef CONFIG_PPC_BOOK3S_64 | |
1619 | static int tar_get(struct task_struct *target, | |
1620 | const struct user_regset *regset, | |
1621 | unsigned int pos, unsigned int count, | |
1622 | void *kbuf, void __user *ubuf) | |
1623 | { | |
1624 | int ret; | |
1625 | ||
1626 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1627 | &target->thread.tar, 0, sizeof(u64)); | |
1628 | return ret; | |
1629 | } | |
1630 | static int tar_set(struct task_struct *target, | |
1631 | const struct user_regset *regset, | |
1632 | unsigned int pos, unsigned int count, | |
1633 | const void *kbuf, const void __user *ubuf) | |
1634 | { | |
1635 | int ret; | |
1636 | ||
1637 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1638 | &target->thread.tar, 0, sizeof(u64)); | |
1639 | return ret; | |
1640 | } | |
cf89d4e1 AK |
1641 | |
1642 | static int ebb_active(struct task_struct *target, | |
1643 | const struct user_regset *regset) | |
1644 | { | |
1645 | if (!cpu_has_feature(CPU_FTR_ARCH_207S)) | |
1646 | return -ENODEV; | |
1647 | ||
1648 | if (target->thread.used_ebb) | |
1649 | return regset->n; | |
1650 | ||
1651 | return 0; | |
1652 | } | |
1653 | ||
1654 | static int ebb_get(struct task_struct *target, | |
1655 | const struct user_regset *regset, | |
1656 | unsigned int pos, unsigned int count, | |
1657 | void *kbuf, void __user *ubuf) | |
1658 | { | |
1659 | /* Build tests */ | |
1660 | BUILD_BUG_ON(TSO(ebbrr) + sizeof(unsigned long) != TSO(ebbhr)); | |
1661 | BUILD_BUG_ON(TSO(ebbhr) + sizeof(unsigned long) != TSO(bescr)); | |
1662 | ||
1663 | if (!cpu_has_feature(CPU_FTR_ARCH_207S)) | |
1664 | return -ENODEV; | |
1665 | ||
1666 | if (!target->thread.used_ebb) | |
1667 | return -ENODATA; | |
1668 | ||
1669 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1670 | &target->thread.ebbrr, 0, 3 * sizeof(unsigned long)); | |
1671 | } | |
1672 | ||
1673 | static int ebb_set(struct task_struct *target, | |
1674 | const struct user_regset *regset, | |
1675 | unsigned int pos, unsigned int count, | |
1676 | const void *kbuf, const void __user *ubuf) | |
1677 | { | |
1678 | int ret = 0; | |
1679 | ||
1680 | /* Build tests */ | |
1681 | BUILD_BUG_ON(TSO(ebbrr) + sizeof(unsigned long) != TSO(ebbhr)); | |
1682 | BUILD_BUG_ON(TSO(ebbhr) + sizeof(unsigned long) != TSO(bescr)); | |
1683 | ||
1684 | if (!cpu_has_feature(CPU_FTR_ARCH_207S)) | |
1685 | return -ENODEV; | |
1686 | ||
1687 | if (target->thread.used_ebb) | |
1688 | return -ENODATA; | |
1689 | ||
1690 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1691 | &target->thread.ebbrr, 0, sizeof(unsigned long)); | |
1692 | ||
1693 | if (!ret) | |
1694 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1695 | &target->thread.ebbhr, sizeof(unsigned long), | |
1696 | 2 * sizeof(unsigned long)); | |
1697 | ||
1698 | if (!ret) | |
1699 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1700 | &target->thread.bescr, | |
1701 | 2 * sizeof(unsigned long), 3 * sizeof(unsigned long)); | |
1702 | ||
1703 | return ret; | |
1704 | } | |
a67ae758 AK |
1705 | static int pmu_active(struct task_struct *target, |
1706 | const struct user_regset *regset) | |
1707 | { | |
1708 | if (!cpu_has_feature(CPU_FTR_ARCH_207S)) | |
1709 | return -ENODEV; | |
1710 | ||
1711 | return regset->n; | |
1712 | } | |
1713 | ||
1714 | static int pmu_get(struct task_struct *target, | |
1715 | const struct user_regset *regset, | |
1716 | unsigned int pos, unsigned int count, | |
1717 | void *kbuf, void __user *ubuf) | |
1718 | { | |
1719 | /* Build tests */ | |
1720 | BUILD_BUG_ON(TSO(siar) + sizeof(unsigned long) != TSO(sdar)); | |
1721 | BUILD_BUG_ON(TSO(sdar) + sizeof(unsigned long) != TSO(sier)); | |
1722 | BUILD_BUG_ON(TSO(sier) + sizeof(unsigned long) != TSO(mmcr2)); | |
1723 | BUILD_BUG_ON(TSO(mmcr2) + sizeof(unsigned long) != TSO(mmcr0)); | |
1724 | ||
1725 | if (!cpu_has_feature(CPU_FTR_ARCH_207S)) | |
1726 | return -ENODEV; | |
1727 | ||
1728 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1729 | &target->thread.siar, 0, | |
1730 | 5 * sizeof(unsigned long)); | |
1731 | } | |
1732 | ||
1733 | static int pmu_set(struct task_struct *target, | |
1734 | const struct user_regset *regset, | |
1735 | unsigned int pos, unsigned int count, | |
1736 | const void *kbuf, const void __user *ubuf) | |
1737 | { | |
1738 | int ret = 0; | |
1739 | ||
1740 | /* Build tests */ | |
1741 | BUILD_BUG_ON(TSO(siar) + sizeof(unsigned long) != TSO(sdar)); | |
1742 | BUILD_BUG_ON(TSO(sdar) + sizeof(unsigned long) != TSO(sier)); | |
1743 | BUILD_BUG_ON(TSO(sier) + sizeof(unsigned long) != TSO(mmcr2)); | |
1744 | BUILD_BUG_ON(TSO(mmcr2) + sizeof(unsigned long) != TSO(mmcr0)); | |
1745 | ||
1746 | if (!cpu_has_feature(CPU_FTR_ARCH_207S)) | |
1747 | return -ENODEV; | |
1748 | ||
1749 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1750 | &target->thread.siar, 0, | |
1751 | sizeof(unsigned long)); | |
1752 | ||
1753 | if (!ret) | |
1754 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1755 | &target->thread.sdar, sizeof(unsigned long), | |
1756 | 2 * sizeof(unsigned long)); | |
1757 | ||
1758 | if (!ret) | |
1759 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1760 | &target->thread.sier, 2 * sizeof(unsigned long), | |
1761 | 3 * sizeof(unsigned long)); | |
1762 | ||
1763 | if (!ret) | |
1764 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1765 | &target->thread.mmcr2, 3 * sizeof(unsigned long), | |
1766 | 4 * sizeof(unsigned long)); | |
1767 | ||
1768 | if (!ret) | |
1769 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1770 | &target->thread.mmcr0, 4 * sizeof(unsigned long), | |
1771 | 5 * sizeof(unsigned long)); | |
1772 | return ret; | |
1773 | } | |
fa439810 | 1774 | #endif |
80fdf470 RM |
1775 | /* |
1776 | * These are our native regset flavors. | |
1777 | */ | |
1778 | enum powerpc_regset { | |
1779 | REGSET_GPR, | |
1780 | REGSET_FPR, | |
1781 | #ifdef CONFIG_ALTIVEC | |
1782 | REGSET_VMX, | |
1783 | #endif | |
ce48b210 MN |
1784 | #ifdef CONFIG_VSX |
1785 | REGSET_VSX, | |
1786 | #endif | |
80fdf470 RM |
1787 | #ifdef CONFIG_SPE |
1788 | REGSET_SPE, | |
1789 | #endif | |
25847fb1 AK |
1790 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1791 | REGSET_TM_CGPR, /* TM checkpointed GPR registers */ | |
19cbcbf7 | 1792 | REGSET_TM_CFPR, /* TM checkpointed FPR registers */ |
8c13f599 | 1793 | REGSET_TM_CVMX, /* TM checkpointed VMX registers */ |
9d3918f7 | 1794 | REGSET_TM_CVSX, /* TM checkpointed VSX registers */ |
08e1c01d | 1795 | REGSET_TM_SPR, /* TM specific SPR registers */ |
c45dc900 AK |
1796 | REGSET_TM_CTAR, /* TM checkpointed TAR register */ |
1797 | REGSET_TM_CPPR, /* TM checkpointed PPR register */ | |
1798 | REGSET_TM_CDSCR, /* TM checkpointed DSCR register */ | |
25847fb1 | 1799 | #endif |
fa439810 AK |
1800 | #ifdef CONFIG_PPC64 |
1801 | REGSET_PPR, /* PPR register */ | |
1802 | REGSET_DSCR, /* DSCR register */ | |
1803 | #endif | |
1804 | #ifdef CONFIG_PPC_BOOK3S_64 | |
1805 | REGSET_TAR, /* TAR register */ | |
cf89d4e1 | 1806 | REGSET_EBB, /* EBB registers */ |
a67ae758 | 1807 | REGSET_PMR, /* Performance Monitor Registers */ |
fa439810 | 1808 | #endif |
80fdf470 RM |
1809 | }; |
1810 | ||
1811 | static const struct user_regset native_regsets[] = { | |
1812 | [REGSET_GPR] = { | |
1813 | .core_note_type = NT_PRSTATUS, .n = ELF_NGREG, | |
1814 | .size = sizeof(long), .align = sizeof(long), | |
1815 | .get = gpr_get, .set = gpr_set | |
1816 | }, | |
1817 | [REGSET_FPR] = { | |
1818 | .core_note_type = NT_PRFPREG, .n = ELF_NFPREG, | |
1819 | .size = sizeof(double), .align = sizeof(double), | |
1820 | .get = fpr_get, .set = fpr_set | |
1821 | }, | |
1822 | #ifdef CONFIG_ALTIVEC | |
1823 | [REGSET_VMX] = { | |
1824 | .core_note_type = NT_PPC_VMX, .n = 34, | |
1825 | .size = sizeof(vector128), .align = sizeof(vector128), | |
1826 | .active = vr_active, .get = vr_get, .set = vr_set | |
1827 | }, | |
1828 | #endif | |
ce48b210 MN |
1829 | #ifdef CONFIG_VSX |
1830 | [REGSET_VSX] = { | |
f3e909c2 MN |
1831 | .core_note_type = NT_PPC_VSX, .n = 32, |
1832 | .size = sizeof(double), .align = sizeof(double), | |
ce48b210 MN |
1833 | .active = vsr_active, .get = vsr_get, .set = vsr_set |
1834 | }, | |
1835 | #endif | |
80fdf470 RM |
1836 | #ifdef CONFIG_SPE |
1837 | [REGSET_SPE] = { | |
a0b38b4e | 1838 | .core_note_type = NT_PPC_SPE, .n = 35, |
80fdf470 RM |
1839 | .size = sizeof(u32), .align = sizeof(u32), |
1840 | .active = evr_active, .get = evr_get, .set = evr_set | |
1841 | }, | |
1842 | #endif | |
25847fb1 AK |
1843 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1844 | [REGSET_TM_CGPR] = { | |
1845 | .core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG, | |
1846 | .size = sizeof(long), .align = sizeof(long), | |
1847 | .active = tm_cgpr_active, .get = tm_cgpr_get, .set = tm_cgpr_set | |
1848 | }, | |
19cbcbf7 AK |
1849 | [REGSET_TM_CFPR] = { |
1850 | .core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG, | |
1851 | .size = sizeof(double), .align = sizeof(double), | |
1852 | .active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set | |
1853 | }, | |
8c13f599 AK |
1854 | [REGSET_TM_CVMX] = { |
1855 | .core_note_type = NT_PPC_TM_CVMX, .n = ELF_NVMX, | |
1856 | .size = sizeof(vector128), .align = sizeof(vector128), | |
1857 | .active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set | |
1858 | }, | |
9d3918f7 AK |
1859 | [REGSET_TM_CVSX] = { |
1860 | .core_note_type = NT_PPC_TM_CVSX, .n = ELF_NVSX, | |
1861 | .size = sizeof(double), .align = sizeof(double), | |
1862 | .active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set | |
1863 | }, | |
08e1c01d AK |
1864 | [REGSET_TM_SPR] = { |
1865 | .core_note_type = NT_PPC_TM_SPR, .n = ELF_NTMSPRREG, | |
1866 | .size = sizeof(u64), .align = sizeof(u64), | |
1867 | .active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set | |
1868 | }, | |
c45dc900 AK |
1869 | [REGSET_TM_CTAR] = { |
1870 | .core_note_type = NT_PPC_TM_CTAR, .n = 1, | |
1871 | .size = sizeof(u64), .align = sizeof(u64), | |
1872 | .active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set | |
1873 | }, | |
1874 | [REGSET_TM_CPPR] = { | |
1875 | .core_note_type = NT_PPC_TM_CPPR, .n = 1, | |
1876 | .size = sizeof(u64), .align = sizeof(u64), | |
1877 | .active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set | |
1878 | }, | |
1879 | [REGSET_TM_CDSCR] = { | |
1880 | .core_note_type = NT_PPC_TM_CDSCR, .n = 1, | |
1881 | .size = sizeof(u64), .align = sizeof(u64), | |
1882 | .active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set | |
1883 | }, | |
25847fb1 | 1884 | #endif |
fa439810 AK |
1885 | #ifdef CONFIG_PPC64 |
1886 | [REGSET_PPR] = { | |
1887 | .core_note_type = NT_PPC_PPR, .n = 1, | |
1888 | .size = sizeof(u64), .align = sizeof(u64), | |
1889 | .get = ppr_get, .set = ppr_set | |
1890 | }, | |
1891 | [REGSET_DSCR] = { | |
1892 | .core_note_type = NT_PPC_DSCR, .n = 1, | |
1893 | .size = sizeof(u64), .align = sizeof(u64), | |
1894 | .get = dscr_get, .set = dscr_set | |
1895 | }, | |
1896 | #endif | |
1897 | #ifdef CONFIG_PPC_BOOK3S_64 | |
1898 | [REGSET_TAR] = { | |
1899 | .core_note_type = NT_PPC_TAR, .n = 1, | |
1900 | .size = sizeof(u64), .align = sizeof(u64), | |
1901 | .get = tar_get, .set = tar_set | |
1902 | }, | |
cf89d4e1 AK |
1903 | [REGSET_EBB] = { |
1904 | .core_note_type = NT_PPC_EBB, .n = ELF_NEBB, | |
1905 | .size = sizeof(u64), .align = sizeof(u64), | |
1906 | .active = ebb_active, .get = ebb_get, .set = ebb_set | |
1907 | }, | |
a67ae758 AK |
1908 | [REGSET_PMR] = { |
1909 | .core_note_type = NT_PPC_PMU, .n = ELF_NPMU, | |
1910 | .size = sizeof(u64), .align = sizeof(u64), | |
1911 | .active = pmu_active, .get = pmu_get, .set = pmu_set | |
1912 | }, | |
fa439810 | 1913 | #endif |
80fdf470 RM |
1914 | }; |
1915 | ||
1916 | static const struct user_regset_view user_ppc_native_view = { | |
1917 | .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI, | |
1918 | .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets) | |
1919 | }; | |
1920 | ||
fa8f5cb0 RM |
1921 | #ifdef CONFIG_PPC64 |
1922 | #include <linux/compat.h> | |
1923 | ||
04fcadce | 1924 | static int gpr32_get_common(struct task_struct *target, |
fa8f5cb0 RM |
1925 | const struct user_regset *regset, |
1926 | unsigned int pos, unsigned int count, | |
26183116 SG |
1927 | void *kbuf, void __user *ubuf, |
1928 | unsigned long *regs) | |
fa8f5cb0 | 1929 | { |
fa8f5cb0 RM |
1930 | compat_ulong_t *k = kbuf; |
1931 | compat_ulong_t __user *u = ubuf; | |
1932 | compat_ulong_t reg; | |
fa8f5cb0 RM |
1933 | |
1934 | pos /= sizeof(reg); | |
1935 | count /= sizeof(reg); | |
1936 | ||
1937 | if (kbuf) | |
1938 | for (; count > 0 && pos < PT_MSR; --count) | |
1939 | *k++ = regs[pos++]; | |
1940 | else | |
1941 | for (; count > 0 && pos < PT_MSR; --count) | |
1942 | if (__put_user((compat_ulong_t) regs[pos++], u++)) | |
1943 | return -EFAULT; | |
1944 | ||
1945 | if (count > 0 && pos == PT_MSR) { | |
1946 | reg = get_user_msr(target); | |
1947 | if (kbuf) | |
1948 | *k++ = reg; | |
1949 | else if (__put_user(reg, u++)) | |
1950 | return -EFAULT; | |
1951 | ++pos; | |
1952 | --count; | |
1953 | } | |
1954 | ||
1955 | if (kbuf) | |
1956 | for (; count > 0 && pos < PT_REGS_COUNT; --count) | |
1957 | *k++ = regs[pos++]; | |
1958 | else | |
1959 | for (; count > 0 && pos < PT_REGS_COUNT; --count) | |
1960 | if (__put_user((compat_ulong_t) regs[pos++], u++)) | |
1961 | return -EFAULT; | |
1962 | ||
1963 | kbuf = k; | |
1964 | ubuf = u; | |
1965 | pos *= sizeof(reg); | |
1966 | count *= sizeof(reg); | |
1967 | return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, | |
1968 | PT_REGS_COUNT * sizeof(reg), -1); | |
1969 | } | |
1970 | ||
04fcadce | 1971 | static int gpr32_set_common(struct task_struct *target, |
fa8f5cb0 RM |
1972 | const struct user_regset *regset, |
1973 | unsigned int pos, unsigned int count, | |
26183116 SG |
1974 | const void *kbuf, const void __user *ubuf, |
1975 | unsigned long *regs) | |
fa8f5cb0 | 1976 | { |
fa8f5cb0 RM |
1977 | const compat_ulong_t *k = kbuf; |
1978 | const compat_ulong_t __user *u = ubuf; | |
1979 | compat_ulong_t reg; | |
1980 | ||
fa8f5cb0 RM |
1981 | pos /= sizeof(reg); |
1982 | count /= sizeof(reg); | |
1983 | ||
1984 | if (kbuf) | |
1985 | for (; count > 0 && pos < PT_MSR; --count) | |
1986 | regs[pos++] = *k++; | |
1987 | else | |
1988 | for (; count > 0 && pos < PT_MSR; --count) { | |
1989 | if (__get_user(reg, u++)) | |
1990 | return -EFAULT; | |
1991 | regs[pos++] = reg; | |
1992 | } | |
1993 | ||
1994 | ||
1995 | if (count > 0 && pos == PT_MSR) { | |
1996 | if (kbuf) | |
1997 | reg = *k++; | |
1998 | else if (__get_user(reg, u++)) | |
1999 | return -EFAULT; | |
2000 | set_user_msr(target, reg); | |
2001 | ++pos; | |
2002 | --count; | |
2003 | } | |
2004 | ||
c2372eb9 | 2005 | if (kbuf) { |
fa8f5cb0 RM |
2006 | for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) |
2007 | regs[pos++] = *k++; | |
c2372eb9 RM |
2008 | for (; count > 0 && pos < PT_TRAP; --count, ++pos) |
2009 | ++k; | |
2010 | } else { | |
fa8f5cb0 RM |
2011 | for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) { |
2012 | if (__get_user(reg, u++)) | |
2013 | return -EFAULT; | |
2014 | regs[pos++] = reg; | |
2015 | } | |
c2372eb9 RM |
2016 | for (; count > 0 && pos < PT_TRAP; --count, ++pos) |
2017 | if (__get_user(reg, u++)) | |
2018 | return -EFAULT; | |
2019 | } | |
fa8f5cb0 RM |
2020 | |
2021 | if (count > 0 && pos == PT_TRAP) { | |
2022 | if (kbuf) | |
2023 | reg = *k++; | |
2024 | else if (__get_user(reg, u++)) | |
2025 | return -EFAULT; | |
2026 | set_user_trap(target, reg); | |
2027 | ++pos; | |
2028 | --count; | |
2029 | } | |
2030 | ||
2031 | kbuf = k; | |
2032 | ubuf = u; | |
2033 | pos *= sizeof(reg); | |
2034 | count *= sizeof(reg); | |
2035 | return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, | |
2036 | (PT_TRAP + 1) * sizeof(reg), -1); | |
2037 | } | |
2038 | ||
25847fb1 AK |
2039 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
2040 | static int tm_cgpr32_get(struct task_struct *target, | |
2041 | const struct user_regset *regset, | |
2042 | unsigned int pos, unsigned int count, | |
2043 | void *kbuf, void __user *ubuf) | |
2044 | { | |
26183116 SG |
2045 | return gpr32_get_common(target, regset, pos, count, kbuf, ubuf, |
2046 | &target->thread.ckpt_regs.gpr[0]); | |
25847fb1 AK |
2047 | } |
2048 | ||
2049 | static int tm_cgpr32_set(struct task_struct *target, | |
2050 | const struct user_regset *regset, | |
2051 | unsigned int pos, unsigned int count, | |
2052 | const void *kbuf, const void __user *ubuf) | |
2053 | { | |
26183116 SG |
2054 | return gpr32_set_common(target, regset, pos, count, kbuf, ubuf, |
2055 | &target->thread.ckpt_regs.gpr[0]); | |
25847fb1 AK |
2056 | } |
2057 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ | |
2058 | ||
04fcadce AK |
2059 | static int gpr32_get(struct task_struct *target, |
2060 | const struct user_regset *regset, | |
2061 | unsigned int pos, unsigned int count, | |
2062 | void *kbuf, void __user *ubuf) | |
2063 | { | |
26183116 SG |
2064 | int i; |
2065 | ||
2066 | if (target->thread.regs == NULL) | |
2067 | return -EIO; | |
2068 | ||
2069 | if (!FULL_REGS(target->thread.regs)) { | |
2070 | /* | |
2071 | * We have a partial register set. | |
2072 | * Fill 14-31 with bogus values. | |
2073 | */ | |
2074 | for (i = 14; i < 32; i++) | |
2075 | target->thread.regs->gpr[i] = NV_REG_POISON; | |
2076 | } | |
2077 | return gpr32_get_common(target, regset, pos, count, kbuf, ubuf, | |
2078 | &target->thread.regs->gpr[0]); | |
04fcadce AK |
2079 | } |
2080 | ||
2081 | static int gpr32_set(struct task_struct *target, | |
2082 | const struct user_regset *regset, | |
2083 | unsigned int pos, unsigned int count, | |
2084 | const void *kbuf, const void __user *ubuf) | |
2085 | { | |
26183116 SG |
2086 | if (target->thread.regs == NULL) |
2087 | return -EIO; | |
2088 | ||
2089 | CHECK_FULL_REGS(target->thread.regs); | |
2090 | return gpr32_set_common(target, regset, pos, count, kbuf, ubuf, | |
2091 | &target->thread.regs->gpr[0]); | |
04fcadce AK |
2092 | } |
2093 | ||
fa8f5cb0 RM |
2094 | /* |
2095 | * These are the regset flavors matching the CONFIG_PPC32 native set. | |
2096 | */ | |
2097 | static const struct user_regset compat_regsets[] = { | |
2098 | [REGSET_GPR] = { | |
2099 | .core_note_type = NT_PRSTATUS, .n = ELF_NGREG, | |
2100 | .size = sizeof(compat_long_t), .align = sizeof(compat_long_t), | |
2101 | .get = gpr32_get, .set = gpr32_set | |
2102 | }, | |
2103 | [REGSET_FPR] = { | |
2104 | .core_note_type = NT_PRFPREG, .n = ELF_NFPREG, | |
2105 | .size = sizeof(double), .align = sizeof(double), | |
2106 | .get = fpr_get, .set = fpr_set | |
2107 | }, | |
2108 | #ifdef CONFIG_ALTIVEC | |
2109 | [REGSET_VMX] = { | |
2110 | .core_note_type = NT_PPC_VMX, .n = 34, | |
2111 | .size = sizeof(vector128), .align = sizeof(vector128), | |
2112 | .active = vr_active, .get = vr_get, .set = vr_set | |
2113 | }, | |
2114 | #endif | |
2115 | #ifdef CONFIG_SPE | |
2116 | [REGSET_SPE] = { | |
24f1a849 | 2117 | .core_note_type = NT_PPC_SPE, .n = 35, |
fa8f5cb0 RM |
2118 | .size = sizeof(u32), .align = sizeof(u32), |
2119 | .active = evr_active, .get = evr_get, .set = evr_set | |
2120 | }, | |
2121 | #endif | |
25847fb1 AK |
2122 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
2123 | [REGSET_TM_CGPR] = { | |
2124 | .core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG, | |
2125 | .size = sizeof(long), .align = sizeof(long), | |
2126 | .active = tm_cgpr_active, | |
2127 | .get = tm_cgpr32_get, .set = tm_cgpr32_set | |
2128 | }, | |
19cbcbf7 AK |
2129 | [REGSET_TM_CFPR] = { |
2130 | .core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG, | |
2131 | .size = sizeof(double), .align = sizeof(double), | |
2132 | .active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set | |
2133 | }, | |
8c13f599 AK |
2134 | [REGSET_TM_CVMX] = { |
2135 | .core_note_type = NT_PPC_TM_CVMX, .n = ELF_NVMX, | |
2136 | .size = sizeof(vector128), .align = sizeof(vector128), | |
2137 | .active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set | |
2138 | }, | |
9d3918f7 AK |
2139 | [REGSET_TM_CVSX] = { |
2140 | .core_note_type = NT_PPC_TM_CVSX, .n = ELF_NVSX, | |
2141 | .size = sizeof(double), .align = sizeof(double), | |
2142 | .active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set | |
2143 | }, | |
08e1c01d AK |
2144 | [REGSET_TM_SPR] = { |
2145 | .core_note_type = NT_PPC_TM_SPR, .n = ELF_NTMSPRREG, | |
2146 | .size = sizeof(u64), .align = sizeof(u64), | |
2147 | .active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set | |
2148 | }, | |
c45dc900 AK |
2149 | [REGSET_TM_CTAR] = { |
2150 | .core_note_type = NT_PPC_TM_CTAR, .n = 1, | |
2151 | .size = sizeof(u64), .align = sizeof(u64), | |
2152 | .active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set | |
2153 | }, | |
2154 | [REGSET_TM_CPPR] = { | |
2155 | .core_note_type = NT_PPC_TM_CPPR, .n = 1, | |
2156 | .size = sizeof(u64), .align = sizeof(u64), | |
2157 | .active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set | |
2158 | }, | |
2159 | [REGSET_TM_CDSCR] = { | |
2160 | .core_note_type = NT_PPC_TM_CDSCR, .n = 1, | |
2161 | .size = sizeof(u64), .align = sizeof(u64), | |
2162 | .active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set | |
2163 | }, | |
25847fb1 | 2164 | #endif |
fa439810 AK |
2165 | #ifdef CONFIG_PPC64 |
2166 | [REGSET_PPR] = { | |
2167 | .core_note_type = NT_PPC_PPR, .n = 1, | |
2168 | .size = sizeof(u64), .align = sizeof(u64), | |
2169 | .get = ppr_get, .set = ppr_set | |
2170 | }, | |
2171 | [REGSET_DSCR] = { | |
2172 | .core_note_type = NT_PPC_DSCR, .n = 1, | |
2173 | .size = sizeof(u64), .align = sizeof(u64), | |
2174 | .get = dscr_get, .set = dscr_set | |
2175 | }, | |
2176 | #endif | |
2177 | #ifdef CONFIG_PPC_BOOK3S_64 | |
2178 | [REGSET_TAR] = { | |
2179 | .core_note_type = NT_PPC_TAR, .n = 1, | |
2180 | .size = sizeof(u64), .align = sizeof(u64), | |
2181 | .get = tar_get, .set = tar_set | |
2182 | }, | |
cf89d4e1 AK |
2183 | [REGSET_EBB] = { |
2184 | .core_note_type = NT_PPC_EBB, .n = ELF_NEBB, | |
2185 | .size = sizeof(u64), .align = sizeof(u64), | |
2186 | .active = ebb_active, .get = ebb_get, .set = ebb_set | |
2187 | }, | |
fa439810 | 2188 | #endif |
fa8f5cb0 RM |
2189 | }; |
2190 | ||
2191 | static const struct user_regset_view user_ppc_compat_view = { | |
2192 | .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI, | |
2193 | .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets) | |
2194 | }; | |
2195 | #endif /* CONFIG_PPC64 */ | |
2196 | ||
80fdf470 RM |
2197 | const struct user_regset_view *task_user_regset_view(struct task_struct *task) |
2198 | { | |
fa8f5cb0 RM |
2199 | #ifdef CONFIG_PPC64 |
2200 | if (test_tsk_thread_flag(task, TIF_32BIT)) | |
2201 | return &user_ppc_compat_view; | |
2202 | #endif | |
80fdf470 RM |
2203 | return &user_ppc_native_view; |
2204 | } | |
2205 | ||
2206 | ||
2a84b0d7 | 2207 | void user_enable_single_step(struct task_struct *task) |
865418d8 BH |
2208 | { |
2209 | struct pt_regs *regs = task->thread.regs; | |
2210 | ||
2211 | if (regs != NULL) { | |
172ae2e7 | 2212 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
51ae8d4a BB |
2213 | task->thread.debug.dbcr0 &= ~DBCR0_BT; |
2214 | task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
865418d8 BH |
2215 | regs->msr |= MSR_DE; |
2216 | #else | |
ec097c84 | 2217 | regs->msr &= ~MSR_BE; |
865418d8 BH |
2218 | regs->msr |= MSR_SE; |
2219 | #endif | |
2220 | } | |
2221 | set_tsk_thread_flag(task, TIF_SINGLESTEP); | |
2222 | } | |
2223 | ||
ec097c84 RM |
2224 | void user_enable_block_step(struct task_struct *task) |
2225 | { | |
2226 | struct pt_regs *regs = task->thread.regs; | |
2227 | ||
2228 | if (regs != NULL) { | |
172ae2e7 | 2229 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
51ae8d4a BB |
2230 | task->thread.debug.dbcr0 &= ~DBCR0_IC; |
2231 | task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT; | |
ec097c84 RM |
2232 | regs->msr |= MSR_DE; |
2233 | #else | |
2234 | regs->msr &= ~MSR_SE; | |
2235 | regs->msr |= MSR_BE; | |
2236 | #endif | |
2237 | } | |
2238 | set_tsk_thread_flag(task, TIF_SINGLESTEP); | |
2239 | } | |
2240 | ||
2a84b0d7 | 2241 | void user_disable_single_step(struct task_struct *task) |
865418d8 BH |
2242 | { |
2243 | struct pt_regs *regs = task->thread.regs; | |
2244 | ||
2245 | if (regs != NULL) { | |
172ae2e7 | 2246 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3bffb652 DK |
2247 | /* |
2248 | * The logic to disable single stepping should be as | |
2249 | * simple as turning off the Instruction Complete flag. | |
2250 | * And, after doing so, if all debug flags are off, turn | |
2251 | * off DBCR0(IDM) and MSR(DE) .... Torez | |
2252 | */ | |
682775b8 | 2253 | task->thread.debug.dbcr0 &= ~(DBCR0_IC|DBCR0_BT); |
3bffb652 DK |
2254 | /* |
2255 | * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set. | |
2256 | */ | |
51ae8d4a BB |
2257 | if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0, |
2258 | task->thread.debug.dbcr1)) { | |
3bffb652 DK |
2259 | /* |
2260 | * All debug events were off..... | |
2261 | */ | |
51ae8d4a | 2262 | task->thread.debug.dbcr0 &= ~DBCR0_IDM; |
28477fb1 DK |
2263 | regs->msr &= ~MSR_DE; |
2264 | } | |
865418d8 | 2265 | #else |
ec097c84 | 2266 | regs->msr &= ~(MSR_SE | MSR_BE); |
865418d8 BH |
2267 | #endif |
2268 | } | |
2269 | clear_tsk_thread_flag(task, TIF_SINGLESTEP); | |
2270 | } | |
2271 | ||
5aae8a53 | 2272 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
a8b0ca17 | 2273 | void ptrace_triggered(struct perf_event *bp, |
5aae8a53 P |
2274 | struct perf_sample_data *data, struct pt_regs *regs) |
2275 | { | |
2276 | struct perf_event_attr attr; | |
2277 | ||
2278 | /* | |
2279 | * Disable the breakpoint request here since ptrace has defined a | |
2280 | * one-shot behaviour for breakpoint exceptions in PPC64. | |
2281 | * The SIGTRAP signal is generated automatically for us in do_dabr(). | |
2282 | * We don't have to do anything about that here | |
2283 | */ | |
2284 | attr = bp->attr; | |
2285 | attr.disabled = true; | |
2286 | modify_user_hw_breakpoint(bp, &attr); | |
2287 | } | |
2288 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
2289 | ||
e51df2c1 | 2290 | static int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, |
abd06505 BH |
2291 | unsigned long data) |
2292 | { | |
5aae8a53 P |
2293 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
2294 | int ret; | |
2295 | struct thread_struct *thread = &(task->thread); | |
2296 | struct perf_event *bp; | |
2297 | struct perf_event_attr attr; | |
2298 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e MN |
2299 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
2300 | struct arch_hw_breakpoint hw_brk; | |
2301 | #endif | |
5aae8a53 | 2302 | |
d6a61bfc LM |
2303 | /* For ppc64 we support one DABR and no IABR's at the moment (ppc64). |
2304 | * For embedded processors we support one DAC and no IAC's at the | |
2305 | * moment. | |
2306 | */ | |
abd06505 BH |
2307 | if (addr > 0) |
2308 | return -EINVAL; | |
2309 | ||
2325f0a0 | 2310 | /* The bottom 3 bits in dabr are flags */ |
abd06505 BH |
2311 | if ((data & ~0x7UL) >= TASK_SIZE) |
2312 | return -EIO; | |
2313 | ||
172ae2e7 | 2314 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
d6a61bfc LM |
2315 | /* For processors using DABR (i.e. 970), the bottom 3 bits are flags. |
2316 | * It was assumed, on previous implementations, that 3 bits were | |
2317 | * passed together with the data address, fitting the design of the | |
2318 | * DABR register, as follows: | |
2319 | * | |
2320 | * bit 0: Read flag | |
2321 | * bit 1: Write flag | |
2322 | * bit 2: Breakpoint translation | |
2323 | * | |
2324 | * Thus, we use them here as so. | |
2325 | */ | |
2326 | ||
2327 | /* Ensure breakpoint translation bit is set */ | |
9422de3e | 2328 | if (data && !(data & HW_BRK_TYPE_TRANSLATE)) |
abd06505 | 2329 | return -EIO; |
9422de3e MN |
2330 | hw_brk.address = data & (~HW_BRK_TYPE_DABR); |
2331 | hw_brk.type = (data & HW_BRK_TYPE_DABR) | HW_BRK_TYPE_PRIV_ALL; | |
2332 | hw_brk.len = 8; | |
5aae8a53 P |
2333 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
2334 | bp = thread->ptrace_bps[0]; | |
9422de3e | 2335 | if ((!data) || !(hw_brk.type & HW_BRK_TYPE_RDWR)) { |
5aae8a53 P |
2336 | if (bp) { |
2337 | unregister_hw_breakpoint(bp); | |
2338 | thread->ptrace_bps[0] = NULL; | |
2339 | } | |
2340 | return 0; | |
2341 | } | |
2342 | if (bp) { | |
2343 | attr = bp->attr; | |
9422de3e MN |
2344 | attr.bp_addr = hw_brk.address; |
2345 | arch_bp_generic_fields(hw_brk.type, &attr.bp_type); | |
a53fd61a AP |
2346 | |
2347 | /* Enable breakpoint */ | |
2348 | attr.disabled = false; | |
2349 | ||
5aae8a53 | 2350 | ret = modify_user_hw_breakpoint(bp, &attr); |
925f83c0 | 2351 | if (ret) { |
5aae8a53 | 2352 | return ret; |
925f83c0 | 2353 | } |
5aae8a53 | 2354 | thread->ptrace_bps[0] = bp; |
9422de3e | 2355 | thread->hw_brk = hw_brk; |
5aae8a53 P |
2356 | return 0; |
2357 | } | |
2358 | ||
2359 | /* Create a new breakpoint request if one doesn't exist already */ | |
2360 | hw_breakpoint_init(&attr); | |
9422de3e MN |
2361 | attr.bp_addr = hw_brk.address; |
2362 | arch_bp_generic_fields(hw_brk.type, | |
2363 | &attr.bp_type); | |
5aae8a53 P |
2364 | |
2365 | thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr, | |
4dc0da86 | 2366 | ptrace_triggered, NULL, task); |
5aae8a53 P |
2367 | if (IS_ERR(bp)) { |
2368 | thread->ptrace_bps[0] = NULL; | |
2369 | return PTR_ERR(bp); | |
2370 | } | |
2371 | ||
2372 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e | 2373 | task->thread.hw_brk = hw_brk; |
172ae2e7 | 2374 | #else /* CONFIG_PPC_ADV_DEBUG_REGS */ |
d6a61bfc LM |
2375 | /* As described above, it was assumed 3 bits were passed with the data |
2376 | * address, but we will assume only the mode bits will be passed | |
2377 | * as to not cause alignment restrictions for DAC-based processors. | |
2378 | */ | |
2379 | ||
2380 | /* DAC's hold the whole address without any mode flags */ | |
51ae8d4a | 2381 | task->thread.debug.dac1 = data & ~0x3UL; |
3bffb652 | 2382 | |
51ae8d4a | 2383 | if (task->thread.debug.dac1 == 0) { |
3bffb652 | 2384 | dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
51ae8d4a BB |
2385 | if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0, |
2386 | task->thread.debug.dbcr1)) { | |
3bffb652 | 2387 | task->thread.regs->msr &= ~MSR_DE; |
51ae8d4a | 2388 | task->thread.debug.dbcr0 &= ~DBCR0_IDM; |
3bffb652 | 2389 | } |
d6a61bfc LM |
2390 | return 0; |
2391 | } | |
2392 | ||
2393 | /* Read or Write bits must be set */ | |
2394 | ||
2395 | if (!(data & 0x3UL)) | |
2396 | return -EINVAL; | |
2397 | ||
2398 | /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0 | |
2399 | register */ | |
51ae8d4a | 2400 | task->thread.debug.dbcr0 |= DBCR0_IDM; |
d6a61bfc LM |
2401 | |
2402 | /* Check for write and read flags and set DBCR0 | |
2403 | accordingly */ | |
3bffb652 | 2404 | dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W); |
d6a61bfc | 2405 | if (data & 0x1UL) |
3bffb652 | 2406 | dbcr_dac(task) |= DBCR_DAC1R; |
d6a61bfc | 2407 | if (data & 0x2UL) |
3bffb652 | 2408 | dbcr_dac(task) |= DBCR_DAC1W; |
d6a61bfc | 2409 | task->thread.regs->msr |= MSR_DE; |
172ae2e7 | 2410 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
abd06505 BH |
2411 | return 0; |
2412 | } | |
abd06505 | 2413 | |
1da177e4 LT |
2414 | /* |
2415 | * Called by kernel/ptrace.c when detaching.. | |
2416 | * | |
2417 | * Make sure single step bits etc are not set. | |
2418 | */ | |
2419 | void ptrace_disable(struct task_struct *child) | |
2420 | { | |
2421 | /* make sure the single step bit is not set. */ | |
2a84b0d7 | 2422 | user_disable_single_step(child); |
1da177e4 LT |
2423 | } |
2424 | ||
3bffb652 | 2425 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
84295dfc | 2426 | static long set_instruction_bp(struct task_struct *child, |
3bffb652 DK |
2427 | struct ppc_hw_breakpoint *bp_info) |
2428 | { | |
2429 | int slot; | |
51ae8d4a BB |
2430 | int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0); |
2431 | int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0); | |
2432 | int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0); | |
2433 | int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0); | |
3bffb652 DK |
2434 | |
2435 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) | |
2436 | slot2_in_use = 1; | |
2437 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) | |
2438 | slot4_in_use = 1; | |
2439 | ||
2440 | if (bp_info->addr >= TASK_SIZE) | |
2441 | return -EIO; | |
2442 | ||
2443 | if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) { | |
2444 | ||
2445 | /* Make sure range is valid. */ | |
2446 | if (bp_info->addr2 >= TASK_SIZE) | |
2447 | return -EIO; | |
2448 | ||
2449 | /* We need a pair of IAC regsisters */ | |
2450 | if ((!slot1_in_use) && (!slot2_in_use)) { | |
2451 | slot = 1; | |
51ae8d4a BB |
2452 | child->thread.debug.iac1 = bp_info->addr; |
2453 | child->thread.debug.iac2 = bp_info->addr2; | |
2454 | child->thread.debug.dbcr0 |= DBCR0_IAC1; | |
3bffb652 DK |
2455 | if (bp_info->addr_mode == |
2456 | PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) | |
2457 | dbcr_iac_range(child) |= DBCR_IAC12X; | |
2458 | else | |
2459 | dbcr_iac_range(child) |= DBCR_IAC12I; | |
2460 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
2461 | } else if ((!slot3_in_use) && (!slot4_in_use)) { | |
2462 | slot = 3; | |
51ae8d4a BB |
2463 | child->thread.debug.iac3 = bp_info->addr; |
2464 | child->thread.debug.iac4 = bp_info->addr2; | |
2465 | child->thread.debug.dbcr0 |= DBCR0_IAC3; | |
3bffb652 DK |
2466 | if (bp_info->addr_mode == |
2467 | PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) | |
2468 | dbcr_iac_range(child) |= DBCR_IAC34X; | |
2469 | else | |
2470 | dbcr_iac_range(child) |= DBCR_IAC34I; | |
2471 | #endif | |
2472 | } else | |
2473 | return -ENOSPC; | |
2474 | } else { | |
2475 | /* We only need one. If possible leave a pair free in | |
2476 | * case a range is needed later | |
2477 | */ | |
2478 | if (!slot1_in_use) { | |
2479 | /* | |
2480 | * Don't use iac1 if iac1-iac2 are free and either | |
2481 | * iac3 or iac4 (but not both) are free | |
2482 | */ | |
2483 | if (slot2_in_use || (slot3_in_use == slot4_in_use)) { | |
2484 | slot = 1; | |
51ae8d4a BB |
2485 | child->thread.debug.iac1 = bp_info->addr; |
2486 | child->thread.debug.dbcr0 |= DBCR0_IAC1; | |
3bffb652 DK |
2487 | goto out; |
2488 | } | |
2489 | } | |
2490 | if (!slot2_in_use) { | |
2491 | slot = 2; | |
51ae8d4a BB |
2492 | child->thread.debug.iac2 = bp_info->addr; |
2493 | child->thread.debug.dbcr0 |= DBCR0_IAC2; | |
3bffb652 DK |
2494 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
2495 | } else if (!slot3_in_use) { | |
2496 | slot = 3; | |
51ae8d4a BB |
2497 | child->thread.debug.iac3 = bp_info->addr; |
2498 | child->thread.debug.dbcr0 |= DBCR0_IAC3; | |
3bffb652 DK |
2499 | } else if (!slot4_in_use) { |
2500 | slot = 4; | |
51ae8d4a BB |
2501 | child->thread.debug.iac4 = bp_info->addr; |
2502 | child->thread.debug.dbcr0 |= DBCR0_IAC4; | |
3bffb652 DK |
2503 | #endif |
2504 | } else | |
2505 | return -ENOSPC; | |
2506 | } | |
2507 | out: | |
51ae8d4a | 2508 | child->thread.debug.dbcr0 |= DBCR0_IDM; |
3bffb652 DK |
2509 | child->thread.regs->msr |= MSR_DE; |
2510 | ||
2511 | return slot; | |
2512 | } | |
2513 | ||
2514 | static int del_instruction_bp(struct task_struct *child, int slot) | |
2515 | { | |
2516 | switch (slot) { | |
2517 | case 1: | |
51ae8d4a | 2518 | if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0) |
3bffb652 DK |
2519 | return -ENOENT; |
2520 | ||
2521 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) { | |
2522 | /* address range - clear slots 1 & 2 */ | |
51ae8d4a | 2523 | child->thread.debug.iac2 = 0; |
3bffb652 DK |
2524 | dbcr_iac_range(child) &= ~DBCR_IAC12MODE; |
2525 | } | |
51ae8d4a BB |
2526 | child->thread.debug.iac1 = 0; |
2527 | child->thread.debug.dbcr0 &= ~DBCR0_IAC1; | |
3bffb652 DK |
2528 | break; |
2529 | case 2: | |
51ae8d4a | 2530 | if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0) |
3bffb652 DK |
2531 | return -ENOENT; |
2532 | ||
2533 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) | |
2534 | /* used in a range */ | |
2535 | return -EINVAL; | |
51ae8d4a BB |
2536 | child->thread.debug.iac2 = 0; |
2537 | child->thread.debug.dbcr0 &= ~DBCR0_IAC2; | |
3bffb652 DK |
2538 | break; |
2539 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
2540 | case 3: | |
51ae8d4a | 2541 | if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0) |
3bffb652 DK |
2542 | return -ENOENT; |
2543 | ||
2544 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) { | |
2545 | /* address range - clear slots 3 & 4 */ | |
51ae8d4a | 2546 | child->thread.debug.iac4 = 0; |
3bffb652 DK |
2547 | dbcr_iac_range(child) &= ~DBCR_IAC34MODE; |
2548 | } | |
51ae8d4a BB |
2549 | child->thread.debug.iac3 = 0; |
2550 | child->thread.debug.dbcr0 &= ~DBCR0_IAC3; | |
3bffb652 DK |
2551 | break; |
2552 | case 4: | |
51ae8d4a | 2553 | if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0) |
3bffb652 DK |
2554 | return -ENOENT; |
2555 | ||
2556 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) | |
2557 | /* Used in a range */ | |
2558 | return -EINVAL; | |
51ae8d4a BB |
2559 | child->thread.debug.iac4 = 0; |
2560 | child->thread.debug.dbcr0 &= ~DBCR0_IAC4; | |
3bffb652 DK |
2561 | break; |
2562 | #endif | |
2563 | default: | |
2564 | return -EINVAL; | |
2565 | } | |
2566 | return 0; | |
2567 | } | |
2568 | ||
2569 | static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info) | |
2570 | { | |
2571 | int byte_enable = | |
2572 | (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT) | |
2573 | & 0xf; | |
2574 | int condition_mode = | |
2575 | bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE; | |
2576 | int slot; | |
2577 | ||
2578 | if (byte_enable && (condition_mode == 0)) | |
2579 | return -EINVAL; | |
2580 | ||
2581 | if (bp_info->addr >= TASK_SIZE) | |
2582 | return -EIO; | |
2583 | ||
2584 | if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) { | |
2585 | slot = 1; | |
2586 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
2587 | dbcr_dac(child) |= DBCR_DAC1R; | |
2588 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) | |
2589 | dbcr_dac(child) |= DBCR_DAC1W; | |
51ae8d4a | 2590 | child->thread.debug.dac1 = (unsigned long)bp_info->addr; |
3bffb652 DK |
2591 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
2592 | if (byte_enable) { | |
51ae8d4a | 2593 | child->thread.debug.dvc1 = |
3bffb652 | 2594 | (unsigned long)bp_info->condition_value; |
51ae8d4a | 2595 | child->thread.debug.dbcr2 |= |
3bffb652 DK |
2596 | ((byte_enable << DBCR2_DVC1BE_SHIFT) | |
2597 | (condition_mode << DBCR2_DVC1M_SHIFT)); | |
2598 | } | |
2599 | #endif | |
2600 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a | 2601 | } else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) { |
3bffb652 DK |
2602 | /* Both dac1 and dac2 are part of a range */ |
2603 | return -ENOSPC; | |
2604 | #endif | |
2605 | } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) { | |
2606 | slot = 2; | |
2607 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
2608 | dbcr_dac(child) |= DBCR_DAC2R; | |
2609 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) | |
2610 | dbcr_dac(child) |= DBCR_DAC2W; | |
51ae8d4a | 2611 | child->thread.debug.dac2 = (unsigned long)bp_info->addr; |
3bffb652 DK |
2612 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
2613 | if (byte_enable) { | |
51ae8d4a | 2614 | child->thread.debug.dvc2 = |
3bffb652 | 2615 | (unsigned long)bp_info->condition_value; |
51ae8d4a | 2616 | child->thread.debug.dbcr2 |= |
3bffb652 DK |
2617 | ((byte_enable << DBCR2_DVC2BE_SHIFT) | |
2618 | (condition_mode << DBCR2_DVC2M_SHIFT)); | |
2619 | } | |
2620 | #endif | |
2621 | } else | |
2622 | return -ENOSPC; | |
51ae8d4a | 2623 | child->thread.debug.dbcr0 |= DBCR0_IDM; |
3bffb652 DK |
2624 | child->thread.regs->msr |= MSR_DE; |
2625 | ||
2626 | return slot + 4; | |
2627 | } | |
2628 | ||
2629 | static int del_dac(struct task_struct *child, int slot) | |
2630 | { | |
2631 | if (slot == 1) { | |
30124d11 | 2632 | if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) |
3bffb652 DK |
2633 | return -ENOENT; |
2634 | ||
51ae8d4a | 2635 | child->thread.debug.dac1 = 0; |
3bffb652 DK |
2636 | dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
2637 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a BB |
2638 | if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) { |
2639 | child->thread.debug.dac2 = 0; | |
2640 | child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; | |
3bffb652 | 2641 | } |
51ae8d4a | 2642 | child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE); |
3bffb652 DK |
2643 | #endif |
2644 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
51ae8d4a | 2645 | child->thread.debug.dvc1 = 0; |
3bffb652 DK |
2646 | #endif |
2647 | } else if (slot == 2) { | |
30124d11 | 2648 | if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) |
3bffb652 DK |
2649 | return -ENOENT; |
2650 | ||
2651 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a | 2652 | if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) |
3bffb652 DK |
2653 | /* Part of a range */ |
2654 | return -EINVAL; | |
51ae8d4a | 2655 | child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE); |
3bffb652 DK |
2656 | #endif |
2657 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
51ae8d4a | 2658 | child->thread.debug.dvc2 = 0; |
3bffb652 | 2659 | #endif |
51ae8d4a | 2660 | child->thread.debug.dac2 = 0; |
3bffb652 DK |
2661 | dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W); |
2662 | } else | |
2663 | return -EINVAL; | |
2664 | ||
2665 | return 0; | |
2666 | } | |
2667 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ | |
2668 | ||
2669 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
2670 | static int set_dac_range(struct task_struct *child, | |
2671 | struct ppc_hw_breakpoint *bp_info) | |
2672 | { | |
2673 | int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK; | |
2674 | ||
2675 | /* We don't allow range watchpoints to be used with DVC */ | |
2676 | if (bp_info->condition_mode) | |
2677 | return -EINVAL; | |
2678 | ||
2679 | /* | |
2680 | * Best effort to verify the address range. The user/supervisor bits | |
2681 | * prevent trapping in kernel space, but let's fail on an obvious bad | |
2682 | * range. The simple test on the mask is not fool-proof, and any | |
2683 | * exclusive range will spill over into kernel space. | |
2684 | */ | |
2685 | if (bp_info->addr >= TASK_SIZE) | |
2686 | return -EIO; | |
2687 | if (mode == PPC_BREAKPOINT_MODE_MASK) { | |
2688 | /* | |
2689 | * dac2 is a bitmask. Don't allow a mask that makes a | |
2690 | * kernel space address from a valid dac1 value | |
2691 | */ | |
2692 | if (~((unsigned long)bp_info->addr2) >= TASK_SIZE) | |
2693 | return -EIO; | |
2694 | } else { | |
2695 | /* | |
2696 | * For range breakpoints, addr2 must also be a valid address | |
2697 | */ | |
2698 | if (bp_info->addr2 >= TASK_SIZE) | |
2699 | return -EIO; | |
2700 | } | |
2701 | ||
51ae8d4a | 2702 | if (child->thread.debug.dbcr0 & |
3bffb652 DK |
2703 | (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W)) |
2704 | return -ENOSPC; | |
2705 | ||
2706 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
51ae8d4a | 2707 | child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM); |
3bffb652 | 2708 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) |
51ae8d4a BB |
2709 | child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM); |
2710 | child->thread.debug.dac1 = bp_info->addr; | |
2711 | child->thread.debug.dac2 = bp_info->addr2; | |
3bffb652 | 2712 | if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) |
51ae8d4a | 2713 | child->thread.debug.dbcr2 |= DBCR2_DAC12M; |
3bffb652 | 2714 | else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) |
51ae8d4a | 2715 | child->thread.debug.dbcr2 |= DBCR2_DAC12MX; |
3bffb652 | 2716 | else /* PPC_BREAKPOINT_MODE_MASK */ |
51ae8d4a | 2717 | child->thread.debug.dbcr2 |= DBCR2_DAC12MM; |
3bffb652 DK |
2718 | child->thread.regs->msr |= MSR_DE; |
2719 | ||
2720 | return 5; | |
2721 | } | |
2722 | #endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */ | |
2723 | ||
3162d92d DK |
2724 | static long ppc_set_hwdebug(struct task_struct *child, |
2725 | struct ppc_hw_breakpoint *bp_info) | |
2726 | { | |
6c7a2856 P |
2727 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
2728 | int len = 0; | |
2729 | struct thread_struct *thread = &(child->thread); | |
2730 | struct perf_event *bp; | |
2731 | struct perf_event_attr attr; | |
2732 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
4dfbf290 | 2733 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
9422de3e | 2734 | struct arch_hw_breakpoint brk; |
4dfbf290 AS |
2735 | #endif |
2736 | ||
3bffb652 DK |
2737 | if (bp_info->version != 1) |
2738 | return -ENOTSUPP; | |
2739 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS | |
2740 | /* | |
2741 | * Check for invalid flags and combinations | |
2742 | */ | |
2743 | if ((bp_info->trigger_type == 0) || | |
2744 | (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE | | |
2745 | PPC_BREAKPOINT_TRIGGER_RW)) || | |
2746 | (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) || | |
2747 | (bp_info->condition_mode & | |
2748 | ~(PPC_BREAKPOINT_CONDITION_MODE | | |
2749 | PPC_BREAKPOINT_CONDITION_BE_ALL))) | |
2750 | return -EINVAL; | |
2751 | #if CONFIG_PPC_ADV_DEBUG_DVCS == 0 | |
2752 | if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE) | |
2753 | return -EINVAL; | |
2754 | #endif | |
2755 | ||
2756 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) { | |
2757 | if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) || | |
2758 | (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)) | |
2759 | return -EINVAL; | |
84295dfc | 2760 | return set_instruction_bp(child, bp_info); |
3bffb652 DK |
2761 | } |
2762 | if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT) | |
2763 | return set_dac(child, bp_info); | |
2764 | ||
2765 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
2766 | return set_dac_range(child, bp_info); | |
2767 | #else | |
2768 | return -EINVAL; | |
2769 | #endif | |
2770 | #else /* !CONFIG_PPC_ADV_DEBUG_DVCS */ | |
3162d92d | 2771 | /* |
3bffb652 | 2772 | * We only support one data breakpoint |
3162d92d | 2773 | */ |
4dfbf290 AS |
2774 | if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 || |
2775 | (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 || | |
4dfbf290 | 2776 | bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE) |
3162d92d DK |
2777 | return -EINVAL; |
2778 | ||
3162d92d DK |
2779 | if ((unsigned long)bp_info->addr >= TASK_SIZE) |
2780 | return -EIO; | |
2781 | ||
9422de3e MN |
2782 | brk.address = bp_info->addr & ~7UL; |
2783 | brk.type = HW_BRK_TYPE_TRANSLATE; | |
2bb78efa | 2784 | brk.len = 8; |
4dfbf290 | 2785 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) |
9422de3e | 2786 | brk.type |= HW_BRK_TYPE_READ; |
4dfbf290 | 2787 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) |
9422de3e | 2788 | brk.type |= HW_BRK_TYPE_WRITE; |
6c7a2856 | 2789 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
6c7a2856 P |
2790 | /* |
2791 | * Check if the request is for 'range' breakpoints. We can | |
2792 | * support it if range < 8 bytes. | |
2793 | */ | |
6961ed96 | 2794 | if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) |
6c7a2856 | 2795 | len = bp_info->addr2 - bp_info->addr; |
6961ed96 | 2796 | else if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT) |
b0b0aa9c | 2797 | len = 1; |
6961ed96 | 2798 | else |
6c7a2856 | 2799 | return -EINVAL; |
6c7a2856 | 2800 | bp = thread->ptrace_bps[0]; |
6961ed96 | 2801 | if (bp) |
6c7a2856 | 2802 | return -ENOSPC; |
6c7a2856 P |
2803 | |
2804 | /* Create a new breakpoint request if one doesn't exist already */ | |
2805 | hw_breakpoint_init(&attr); | |
2806 | attr.bp_addr = (unsigned long)bp_info->addr & ~HW_BREAKPOINT_ALIGN; | |
2807 | attr.bp_len = len; | |
9422de3e | 2808 | arch_bp_generic_fields(brk.type, &attr.bp_type); |
6c7a2856 P |
2809 | |
2810 | thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr, | |
2811 | ptrace_triggered, NULL, child); | |
2812 | if (IS_ERR(bp)) { | |
2813 | thread->ptrace_bps[0] = NULL; | |
6c7a2856 P |
2814 | return PTR_ERR(bp); |
2815 | } | |
2816 | ||
6c7a2856 P |
2817 | return 1; |
2818 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
2819 | ||
2820 | if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) | |
2821 | return -EINVAL; | |
2822 | ||
9422de3e | 2823 | if (child->thread.hw_brk.address) |
6c7a2856 | 2824 | return -ENOSPC; |
4dfbf290 | 2825 | |
9422de3e | 2826 | child->thread.hw_brk = brk; |
3bffb652 | 2827 | |
3162d92d | 2828 | return 1; |
3bffb652 | 2829 | #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */ |
3162d92d DK |
2830 | } |
2831 | ||
ec1b33dc | 2832 | static long ppc_del_hwdebug(struct task_struct *child, long data) |
3162d92d | 2833 | { |
6c7a2856 P |
2834 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
2835 | int ret = 0; | |
2836 | struct thread_struct *thread = &(child->thread); | |
2837 | struct perf_event *bp; | |
2838 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
3bffb652 DK |
2839 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
2840 | int rc; | |
2841 | ||
2842 | if (data <= 4) | |
2843 | rc = del_instruction_bp(child, (int)data); | |
2844 | else | |
2845 | rc = del_dac(child, (int)data - 4); | |
2846 | ||
2847 | if (!rc) { | |
51ae8d4a BB |
2848 | if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0, |
2849 | child->thread.debug.dbcr1)) { | |
2850 | child->thread.debug.dbcr0 &= ~DBCR0_IDM; | |
3bffb652 DK |
2851 | child->thread.regs->msr &= ~MSR_DE; |
2852 | } | |
2853 | } | |
2854 | return rc; | |
2855 | #else | |
3162d92d DK |
2856 | if (data != 1) |
2857 | return -EINVAL; | |
6c7a2856 P |
2858 | |
2859 | #ifdef CONFIG_HAVE_HW_BREAKPOINT | |
6c7a2856 P |
2860 | bp = thread->ptrace_bps[0]; |
2861 | if (bp) { | |
2862 | unregister_hw_breakpoint(bp); | |
2863 | thread->ptrace_bps[0] = NULL; | |
2864 | } else | |
2865 | ret = -ENOENT; | |
6c7a2856 P |
2866 | return ret; |
2867 | #else /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e | 2868 | if (child->thread.hw_brk.address == 0) |
3162d92d DK |
2869 | return -ENOENT; |
2870 | ||
9422de3e MN |
2871 | child->thread.hw_brk.address = 0; |
2872 | child->thread.hw_brk.type = 0; | |
6c7a2856 | 2873 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 2874 | |
3162d92d | 2875 | return 0; |
3bffb652 | 2876 | #endif |
3162d92d DK |
2877 | } |
2878 | ||
9b05a69e NK |
2879 | long arch_ptrace(struct task_struct *child, long request, |
2880 | unsigned long addr, unsigned long data) | |
1da177e4 | 2881 | { |
1da177e4 | 2882 | int ret = -EPERM; |
f68d2048 NK |
2883 | void __user *datavp = (void __user *) data; |
2884 | unsigned long __user *datalp = datavp; | |
1da177e4 | 2885 | |
1da177e4 | 2886 | switch (request) { |
1da177e4 | 2887 | /* read the word at location addr in the USER area. */ |
1da177e4 LT |
2888 | case PTRACE_PEEKUSR: { |
2889 | unsigned long index, tmp; | |
2890 | ||
2891 | ret = -EIO; | |
2892 | /* convert to index and check */ | |
e8a30302 | 2893 | #ifdef CONFIG_PPC32 |
9b05a69e | 2894 | index = addr >> 2; |
e8a30302 SR |
2895 | if ((addr & 3) || (index > PT_FPSCR) |
2896 | || (child->thread.regs == NULL)) | |
2897 | #else | |
9b05a69e | 2898 | index = addr >> 3; |
e8a30302 SR |
2899 | if ((addr & 7) || (index > PT_FPSCR)) |
2900 | #endif | |
1da177e4 LT |
2901 | break; |
2902 | ||
2903 | CHECK_FULL_REGS(child->thread.regs); | |
2904 | if (index < PT_FPR0) { | |
ee4a3916 AK |
2905 | ret = ptrace_get_reg(child, (int) index, &tmp); |
2906 | if (ret) | |
2907 | break; | |
1da177e4 | 2908 | } else { |
e69b742a BH |
2909 | unsigned int fpidx = index - PT_FPR0; |
2910 | ||
e8a30302 | 2911 | flush_fp_to_thread(child); |
e69b742a | 2912 | if (fpidx < (PT_FPSCR - PT_FPR0)) |
36aa1b18 | 2913 | memcpy(&tmp, &child->thread.TS_FPR(fpidx), |
87fec051 | 2914 | sizeof(long)); |
e69b742a | 2915 | else |
de79f7b9 | 2916 | tmp = child->thread.fp_state.fpscr; |
1da177e4 | 2917 | } |
f68d2048 | 2918 | ret = put_user(tmp, datalp); |
1da177e4 LT |
2919 | break; |
2920 | } | |
2921 | ||
1da177e4 LT |
2922 | /* write the word at location addr in the USER area */ |
2923 | case PTRACE_POKEUSR: { | |
2924 | unsigned long index; | |
2925 | ||
2926 | ret = -EIO; | |
2927 | /* convert to index and check */ | |
e8a30302 | 2928 | #ifdef CONFIG_PPC32 |
9b05a69e | 2929 | index = addr >> 2; |
e8a30302 SR |
2930 | if ((addr & 3) || (index > PT_FPSCR) |
2931 | || (child->thread.regs == NULL)) | |
2932 | #else | |
9b05a69e | 2933 | index = addr >> 3; |
e8a30302 SR |
2934 | if ((addr & 7) || (index > PT_FPSCR)) |
2935 | #endif | |
1da177e4 LT |
2936 | break; |
2937 | ||
2938 | CHECK_FULL_REGS(child->thread.regs); | |
1da177e4 | 2939 | if (index < PT_FPR0) { |
865418d8 | 2940 | ret = ptrace_put_reg(child, index, data); |
1da177e4 | 2941 | } else { |
e69b742a BH |
2942 | unsigned int fpidx = index - PT_FPR0; |
2943 | ||
e8a30302 | 2944 | flush_fp_to_thread(child); |
e69b742a | 2945 | if (fpidx < (PT_FPSCR - PT_FPR0)) |
36aa1b18 | 2946 | memcpy(&child->thread.TS_FPR(fpidx), &data, |
87fec051 | 2947 | sizeof(long)); |
e69b742a | 2948 | else |
de79f7b9 | 2949 | child->thread.fp_state.fpscr = data; |
1da177e4 LT |
2950 | ret = 0; |
2951 | } | |
2952 | break; | |
2953 | } | |
2954 | ||
3162d92d DK |
2955 | case PPC_PTRACE_GETHWDBGINFO: { |
2956 | struct ppc_debug_info dbginfo; | |
2957 | ||
2958 | dbginfo.version = 1; | |
3bffb652 DK |
2959 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
2960 | dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS; | |
2961 | dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS; | |
2962 | dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS; | |
2963 | dbginfo.data_bp_alignment = 4; | |
2964 | dbginfo.sizeof_condition = 4; | |
2965 | dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE | | |
2966 | PPC_DEBUG_FEATURE_INSN_BP_MASK; | |
2967 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
2968 | dbginfo.features |= | |
2969 | PPC_DEBUG_FEATURE_DATA_BP_RANGE | | |
2970 | PPC_DEBUG_FEATURE_DATA_BP_MASK; | |
2971 | #endif | |
2972 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ | |
3162d92d DK |
2973 | dbginfo.num_instruction_bps = 0; |
2974 | dbginfo.num_data_bps = 1; | |
2975 | dbginfo.num_condition_regs = 0; | |
2976 | #ifdef CONFIG_PPC64 | |
2977 | dbginfo.data_bp_alignment = 8; | |
2978 | #else | |
2979 | dbginfo.data_bp_alignment = 4; | |
2980 | #endif | |
2981 | dbginfo.sizeof_condition = 0; | |
6c7a2856 P |
2982 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
2983 | dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE; | |
517b7314 MN |
2984 | if (cpu_has_feature(CPU_FTR_DAWR)) |
2985 | dbginfo.features |= PPC_DEBUG_FEATURE_DATA_BP_DAWR; | |
6c7a2856 | 2986 | #else |
3162d92d | 2987 | dbginfo.features = 0; |
6c7a2856 | 2988 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 2989 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
3162d92d | 2990 | |
f68d2048 | 2991 | if (!access_ok(VERIFY_WRITE, datavp, |
3162d92d DK |
2992 | sizeof(struct ppc_debug_info))) |
2993 | return -EFAULT; | |
f68d2048 NK |
2994 | ret = __copy_to_user(datavp, &dbginfo, |
2995 | sizeof(struct ppc_debug_info)) ? | |
3162d92d DK |
2996 | -EFAULT : 0; |
2997 | break; | |
2998 | } | |
2999 | ||
3000 | case PPC_PTRACE_SETHWDEBUG: { | |
3001 | struct ppc_hw_breakpoint bp_info; | |
3002 | ||
f68d2048 | 3003 | if (!access_ok(VERIFY_READ, datavp, |
3162d92d DK |
3004 | sizeof(struct ppc_hw_breakpoint))) |
3005 | return -EFAULT; | |
f68d2048 | 3006 | ret = __copy_from_user(&bp_info, datavp, |
3162d92d DK |
3007 | sizeof(struct ppc_hw_breakpoint)) ? |
3008 | -EFAULT : 0; | |
3009 | if (!ret) | |
3010 | ret = ppc_set_hwdebug(child, &bp_info); | |
3011 | break; | |
3012 | } | |
3013 | ||
3014 | case PPC_PTRACE_DELHWDEBUG: { | |
ec1b33dc | 3015 | ret = ppc_del_hwdebug(child, data); |
3162d92d DK |
3016 | break; |
3017 | } | |
3018 | ||
e8a30302 | 3019 | case PTRACE_GET_DEBUGREG: { |
9422de3e MN |
3020 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
3021 | unsigned long dabr_fake; | |
3022 | #endif | |
e8a30302 SR |
3023 | ret = -EINVAL; |
3024 | /* We only support one DABR and no IABRS at the moment */ | |
3025 | if (addr > 0) | |
3026 | break; | |
3bffb652 | 3027 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
51ae8d4a | 3028 | ret = put_user(child->thread.debug.dac1, datalp); |
3bffb652 | 3029 | #else |
9422de3e MN |
3030 | dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) | |
3031 | (child->thread.hw_brk.type & HW_BRK_TYPE_DABR)); | |
3032 | ret = put_user(dabr_fake, datalp); | |
3bffb652 | 3033 | #endif |
e8a30302 SR |
3034 | break; |
3035 | } | |
3036 | ||
3037 | case PTRACE_SET_DEBUGREG: | |
3038 | ret = ptrace_set_debugreg(child, addr, data); | |
3039 | break; | |
e8a30302 | 3040 | |
e17666ba BH |
3041 | #ifdef CONFIG_PPC64 |
3042 | case PTRACE_GETREGS64: | |
3043 | #endif | |
c391cd00 RM |
3044 | case PTRACE_GETREGS: /* Get all pt_regs from the child. */ |
3045 | return copy_regset_to_user(child, &user_ppc_native_view, | |
3046 | REGSET_GPR, | |
3047 | 0, sizeof(struct pt_regs), | |
f68d2048 | 3048 | datavp); |
e8a30302 | 3049 | |
e17666ba BH |
3050 | #ifdef CONFIG_PPC64 |
3051 | case PTRACE_SETREGS64: | |
3052 | #endif | |
c391cd00 RM |
3053 | case PTRACE_SETREGS: /* Set all gp regs in the child. */ |
3054 | return copy_regset_from_user(child, &user_ppc_native_view, | |
3055 | REGSET_GPR, | |
3056 | 0, sizeof(struct pt_regs), | |
f68d2048 | 3057 | datavp); |
c391cd00 RM |
3058 | |
3059 | case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */ | |
3060 | return copy_regset_to_user(child, &user_ppc_native_view, | |
3061 | REGSET_FPR, | |
3062 | 0, sizeof(elf_fpregset_t), | |
f68d2048 | 3063 | datavp); |
c391cd00 RM |
3064 | |
3065 | case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */ | |
3066 | return copy_regset_from_user(child, &user_ppc_native_view, | |
3067 | REGSET_FPR, | |
3068 | 0, sizeof(elf_fpregset_t), | |
f68d2048 | 3069 | datavp); |
e8a30302 | 3070 | |
1da177e4 LT |
3071 | #ifdef CONFIG_ALTIVEC |
3072 | case PTRACE_GETVRREGS: | |
c391cd00 RM |
3073 | return copy_regset_to_user(child, &user_ppc_native_view, |
3074 | REGSET_VMX, | |
3075 | 0, (33 * sizeof(vector128) + | |
3076 | sizeof(u32)), | |
f68d2048 | 3077 | datavp); |
1da177e4 LT |
3078 | |
3079 | case PTRACE_SETVRREGS: | |
c391cd00 RM |
3080 | return copy_regset_from_user(child, &user_ppc_native_view, |
3081 | REGSET_VMX, | |
3082 | 0, (33 * sizeof(vector128) + | |
3083 | sizeof(u32)), | |
f68d2048 | 3084 | datavp); |
1da177e4 | 3085 | #endif |
ce48b210 MN |
3086 | #ifdef CONFIG_VSX |
3087 | case PTRACE_GETVSRREGS: | |
3088 | return copy_regset_to_user(child, &user_ppc_native_view, | |
3089 | REGSET_VSX, | |
1ac42ef8 | 3090 | 0, 32 * sizeof(double), |
f68d2048 | 3091 | datavp); |
ce48b210 MN |
3092 | |
3093 | case PTRACE_SETVSRREGS: | |
3094 | return copy_regset_from_user(child, &user_ppc_native_view, | |
3095 | REGSET_VSX, | |
1ac42ef8 | 3096 | 0, 32 * sizeof(double), |
f68d2048 | 3097 | datavp); |
ce48b210 | 3098 | #endif |
1da177e4 LT |
3099 | #ifdef CONFIG_SPE |
3100 | case PTRACE_GETEVRREGS: | |
3101 | /* Get the child spe register state. */ | |
c391cd00 RM |
3102 | return copy_regset_to_user(child, &user_ppc_native_view, |
3103 | REGSET_SPE, 0, 35 * sizeof(u32), | |
f68d2048 | 3104 | datavp); |
1da177e4 LT |
3105 | |
3106 | case PTRACE_SETEVRREGS: | |
3107 | /* Set the child spe register state. */ | |
c391cd00 RM |
3108 | return copy_regset_from_user(child, &user_ppc_native_view, |
3109 | REGSET_SPE, 0, 35 * sizeof(u32), | |
f68d2048 | 3110 | datavp); |
1da177e4 LT |
3111 | #endif |
3112 | ||
3113 | default: | |
3114 | ret = ptrace_request(child, request, addr, data); | |
3115 | break; | |
3116 | } | |
1da177e4 LT |
3117 | return ret; |
3118 | } | |
3119 | ||
2449acc5 ME |
3120 | #ifdef CONFIG_SECCOMP |
3121 | static int do_seccomp(struct pt_regs *regs) | |
3122 | { | |
3123 | if (!test_thread_flag(TIF_SECCOMP)) | |
3124 | return 0; | |
3125 | ||
3126 | /* | |
3127 | * The ABI we present to seccomp tracers is that r3 contains | |
3128 | * the syscall return value and orig_gpr3 contains the first | |
3129 | * syscall parameter. This is different to the ptrace ABI where | |
3130 | * both r3 and orig_gpr3 contain the first syscall parameter. | |
3131 | */ | |
3132 | regs->gpr[3] = -ENOSYS; | |
3133 | ||
3134 | /* | |
3135 | * We use the __ version here because we have already checked | |
3136 | * TIF_SECCOMP. If this fails, there is nothing left to do, we | |
3137 | * have already loaded -ENOSYS into r3, or seccomp has put | |
3138 | * something else in r3 (via SECCOMP_RET_ERRNO/TRACE). | |
3139 | */ | |
2f275de5 | 3140 | if (__secure_computing(NULL)) |
2449acc5 ME |
3141 | return -1; |
3142 | ||
3143 | /* | |
3144 | * The syscall was allowed by seccomp, restore the register | |
1addc57e | 3145 | * state to what audit expects. |
2449acc5 ME |
3146 | * Note that we use orig_gpr3, which means a seccomp tracer can |
3147 | * modify the first syscall parameter (in orig_gpr3) and also | |
3148 | * allow the syscall to proceed. | |
3149 | */ | |
3150 | regs->gpr[3] = regs->orig_gpr3; | |
3151 | ||
3152 | return 0; | |
3153 | } | |
3154 | #else | |
3155 | static inline int do_seccomp(struct pt_regs *regs) { return 0; } | |
3156 | #endif /* CONFIG_SECCOMP */ | |
3157 | ||
d3837414 ME |
3158 | /** |
3159 | * do_syscall_trace_enter() - Do syscall tracing on kernel entry. | |
3160 | * @regs: the pt_regs of the task to trace (current) | |
3161 | * | |
3162 | * Performs various types of tracing on syscall entry. This includes seccomp, | |
3163 | * ptrace, syscall tracepoints and audit. | |
3164 | * | |
3165 | * The pt_regs are potentially visible to userspace via ptrace, so their | |
3166 | * contents is ABI. | |
3167 | * | |
3168 | * One or more of the tracers may modify the contents of pt_regs, in particular | |
3169 | * to modify arguments or even the syscall number itself. | |
3170 | * | |
3171 | * It's also possible that a tracer can choose to reject the system call. In | |
3172 | * that case this function will return an illegal syscall number, and will put | |
3173 | * an appropriate return value in regs->r3. | |
3174 | * | |
3175 | * Return: the (possibly changed) syscall number. | |
4f72c427 RM |
3176 | */ |
3177 | long do_syscall_trace_enter(struct pt_regs *regs) | |
1da177e4 | 3178 | { |
22ecbe8d LZ |
3179 | user_exit(); |
3180 | ||
1addc57e KC |
3181 | /* |
3182 | * The tracer may decide to abort the syscall, if so tracehook | |
3183 | * will return !0. Note that the tracer may also just change | |
3184 | * regs->gpr[0] to an invalid syscall number, that is handled | |
3185 | * below on the exit path. | |
3186 | */ | |
3187 | if (test_thread_flag(TIF_SYSCALL_TRACE) && | |
3188 | tracehook_report_syscall_entry(regs)) | |
3189 | goto skip; | |
3190 | ||
3191 | /* Run seccomp after ptrace; allow it to set gpr[3]. */ | |
2449acc5 ME |
3192 | if (do_seccomp(regs)) |
3193 | return -1; | |
e8a30302 | 3194 | |
1addc57e KC |
3195 | /* Avoid trace and audit when syscall is invalid. */ |
3196 | if (regs->gpr[0] >= NR_syscalls) | |
3197 | goto skip; | |
ea9c102c | 3198 | |
02424d89 IM |
3199 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
3200 | trace_sys_enter(regs, regs->gpr[0]); | |
3201 | ||
cfcd1705 | 3202 | #ifdef CONFIG_PPC64 |
b05d8447 | 3203 | if (!is_32bit_task()) |
91397401 | 3204 | audit_syscall_entry(regs->gpr[0], regs->gpr[3], regs->gpr[4], |
b05d8447 EP |
3205 | regs->gpr[5], regs->gpr[6]); |
3206 | else | |
e8a30302 | 3207 | #endif |
91397401 | 3208 | audit_syscall_entry(regs->gpr[0], |
b05d8447 EP |
3209 | regs->gpr[3] & 0xffffffff, |
3210 | regs->gpr[4] & 0xffffffff, | |
3211 | regs->gpr[5] & 0xffffffff, | |
3212 | regs->gpr[6] & 0xffffffff); | |
4f72c427 | 3213 | |
d3837414 ME |
3214 | /* Return the possibly modified but valid syscall number */ |
3215 | return regs->gpr[0]; | |
1addc57e KC |
3216 | |
3217 | skip: | |
3218 | /* | |
3219 | * If we are aborting explicitly, or if the syscall number is | |
3220 | * now invalid, set the return value to -ENOSYS. | |
3221 | */ | |
3222 | regs->gpr[3] = -ENOSYS; | |
3223 | return -1; | |
ea9c102c DW |
3224 | } |
3225 | ||
3226 | void do_syscall_trace_leave(struct pt_regs *regs) | |
3227 | { | |
4f72c427 RM |
3228 | int step; |
3229 | ||
d7e7528b | 3230 | audit_syscall_exit(regs); |
ea9c102c | 3231 | |
02424d89 IM |
3232 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
3233 | trace_sys_exit(regs, regs->result); | |
3234 | ||
4f72c427 RM |
3235 | step = test_thread_flag(TIF_SINGLESTEP); |
3236 | if (step || test_thread_flag(TIF_SYSCALL_TRACE)) | |
3237 | tracehook_report_syscall_exit(regs, step); | |
22ecbe8d LZ |
3238 | |
3239 | user_enter(); | |
ea9c102c | 3240 | } |