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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
14cf11af | 2 | /* |
14cf11af PM |
3 | * Derived from "arch/i386/kernel/process.c" |
4 | * Copyright (C) 1995 Linus Torvalds | |
5 | * | |
6 | * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and | |
7 | * Paul Mackerras (paulus@cs.anu.edu.au) | |
8 | * | |
9 | * PowerPC version | |
10 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
14cf11af PM |
11 | */ |
12 | ||
14cf11af PM |
13 | #include <linux/errno.h> |
14 | #include <linux/sched.h> | |
b17b0153 | 15 | #include <linux/sched/debug.h> |
29930025 | 16 | #include <linux/sched/task.h> |
68db0cf1 | 17 | #include <linux/sched/task_stack.h> |
14cf11af PM |
18 | #include <linux/kernel.h> |
19 | #include <linux/mm.h> | |
20 | #include <linux/smp.h> | |
14cf11af PM |
21 | #include <linux/stddef.h> |
22 | #include <linux/unistd.h> | |
23 | #include <linux/ptrace.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/user.h> | |
26 | #include <linux/elf.h> | |
14cf11af PM |
27 | #include <linux/prctl.h> |
28 | #include <linux/init_task.h> | |
4b16f8e2 | 29 | #include <linux/export.h> |
14cf11af PM |
30 | #include <linux/kallsyms.h> |
31 | #include <linux/mqueue.h> | |
32 | #include <linux/hardirq.h> | |
06d67d54 | 33 | #include <linux/utsname.h> |
6794c782 | 34 | #include <linux/ftrace.h> |
79741dd3 | 35 | #include <linux/kernel_stat.h> |
d839088c | 36 | #include <linux/personality.h> |
5aae8a53 | 37 | #include <linux/hw_breakpoint.h> |
7b051f66 | 38 | #include <linux/uaccess.h> |
06bb53b3 | 39 | #include <linux/pkeys.h> |
fb2d9505 | 40 | #include <linux/seq_buf.h> |
14cf11af | 41 | |
3a96570f | 42 | #include <asm/interrupt.h> |
14cf11af PM |
43 | #include <asm/io.h> |
44 | #include <asm/processor.h> | |
45 | #include <asm/mmu.h> | |
76032de8 | 46 | #include <asm/machdep.h> |
c6622f63 | 47 | #include <asm/time.h> |
ae3a197e | 48 | #include <asm/runlatch.h> |
a7f31841 | 49 | #include <asm/syscalls.h> |
ae3a197e | 50 | #include <asm/switch_to.h> |
fb09692e | 51 | #include <asm/tm.h> |
ae3a197e | 52 | #include <asm/debug.h> |
06d67d54 PM |
53 | #ifdef CONFIG_PPC64 |
54 | #include <asm/firmware.h> | |
c2e480ba | 55 | #include <asm/hw_irq.h> |
06d67d54 | 56 | #endif |
7cedd601 | 57 | #include <asm/code-patching.h> |
7f92bc56 | 58 | #include <asm/exec.h> |
5d31a96e | 59 | #include <asm/livepatch.h> |
b92a226e | 60 | #include <asm/cpu_has_feature.h> |
0545d543 | 61 | #include <asm/asm-prototypes.h> |
c9386bfd | 62 | #include <asm/stacktrace.h> |
c1fe190c | 63 | #include <asm/hw_breakpoint.h> |
5d31a96e | 64 | |
d6a61bfc LM |
65 | #include <linux/kprobes.h> |
66 | #include <linux/kdebug.h> | |
14cf11af | 67 | |
8b3c34cf MN |
68 | /* Transactional Memory debug */ |
69 | #ifdef TM_DEBUG_SW | |
70 | #define TM_DEBUG(x...) printk(KERN_INFO x) | |
71 | #else | |
72 | #define TM_DEBUG(x...) do { } while(0) | |
73 | #endif | |
74 | ||
14cf11af PM |
75 | extern unsigned long _get_SP(void); |
76 | ||
d31626f7 | 77 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
54820530 ME |
78 | /* |
79 | * Are we running in "Suspend disabled" mode? If so we have to block any | |
80 | * sigreturn that would get us into suspended state, and we also warn in some | |
81 | * other paths that we should never reach with suspend disabled. | |
82 | */ | |
83 | bool tm_suspend_disabled __ro_after_init = false; | |
84 | ||
b86fd2bd | 85 | static void check_if_tm_restore_required(struct task_struct *tsk) |
d31626f7 PM |
86 | { |
87 | /* | |
88 | * If we are saving the current thread's registers, and the | |
89 | * thread is in a transactional state, set the TIF_RESTORE_TM | |
90 | * bit so that we know to restore the registers before | |
91 | * returning to userspace. | |
92 | */ | |
93 | if (tsk == current && tsk->thread.regs && | |
94 | MSR_TM_ACTIVE(tsk->thread.regs->msr) && | |
95 | !test_thread_flag(TIF_RESTORE_TM)) { | |
59dc5bfc NP |
96 | regs_set_return_msr(&tsk->thread.ckpt_regs, |
97 | tsk->thread.regs->msr); | |
d31626f7 PM |
98 | set_thread_flag(TIF_RESTORE_TM); |
99 | } | |
d31626f7 | 100 | } |
dc16b553 | 101 | |
d31626f7 | 102 | #else |
b86fd2bd | 103 | static inline void check_if_tm_restore_required(struct task_struct *tsk) { } |
d31626f7 PM |
104 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
105 | ||
3eb5d588 AB |
106 | bool strict_msr_control; |
107 | EXPORT_SYMBOL(strict_msr_control); | |
108 | ||
109 | static int __init enable_strict_msr_control(char *str) | |
110 | { | |
111 | strict_msr_control = true; | |
112 | pr_info("Enabling strict facility control\n"); | |
113 | ||
114 | return 0; | |
115 | } | |
116 | early_param("ppc_strict_facility_enable", enable_strict_msr_control); | |
117 | ||
e2b36d59 NP |
118 | /* notrace because it's called by restore_math */ |
119 | unsigned long notrace msr_check_and_set(unsigned long bits) | |
98da581e | 120 | { |
a0e72cf1 AB |
121 | unsigned long oldmsr = mfmsr(); |
122 | unsigned long newmsr; | |
98da581e | 123 | |
a0e72cf1 | 124 | newmsr = oldmsr | bits; |
98da581e | 125 | |
a0e72cf1 | 126 | if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) |
98da581e | 127 | newmsr |= MSR_VSX; |
a0e72cf1 | 128 | |
98da581e | 129 | if (oldmsr != newmsr) |
0fa68318 | 130 | newmsr = mtmsr_isync_irqsafe(newmsr); |
3cee070a CB |
131 | |
132 | return newmsr; | |
a0e72cf1 | 133 | } |
d1c72112 | 134 | EXPORT_SYMBOL_GPL(msr_check_and_set); |
98da581e | 135 | |
e2b36d59 NP |
136 | /* notrace because it's called by restore_math */ |
137 | void notrace __msr_check_and_clear(unsigned long bits) | |
a0e72cf1 AB |
138 | { |
139 | unsigned long oldmsr = mfmsr(); | |
140 | unsigned long newmsr; | |
141 | ||
142 | newmsr = oldmsr & ~bits; | |
143 | ||
a0e72cf1 AB |
144 | if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) |
145 | newmsr &= ~MSR_VSX; | |
a0e72cf1 AB |
146 | |
147 | if (oldmsr != newmsr) | |
0fa68318 | 148 | mtmsr_isync_irqsafe(newmsr); |
a0e72cf1 | 149 | } |
3eb5d588 | 150 | EXPORT_SYMBOL(__msr_check_and_clear); |
a0e72cf1 AB |
151 | |
152 | #ifdef CONFIG_PPC_FPU | |
1cdf039b | 153 | static void __giveup_fpu(struct task_struct *tsk) |
8792468d | 154 | { |
8eb98037 AB |
155 | unsigned long msr; |
156 | ||
8792468d | 157 | save_fpu(tsk); |
8eb98037 | 158 | msr = tsk->thread.regs->msr; |
fe1ef6bc | 159 | msr &= ~(MSR_FP|MSR_FE0|MSR_FE1); |
8792468d | 160 | if (cpu_has_feature(CPU_FTR_VSX)) |
8eb98037 | 161 | msr &= ~MSR_VSX; |
59dc5bfc | 162 | regs_set_return_msr(tsk->thread.regs, msr); |
8792468d CB |
163 | } |
164 | ||
a0e72cf1 AB |
165 | void giveup_fpu(struct task_struct *tsk) |
166 | { | |
167 | check_if_tm_restore_required(tsk); | |
168 | ||
169 | msr_check_and_set(MSR_FP); | |
98da581e | 170 | __giveup_fpu(tsk); |
a0e72cf1 | 171 | msr_check_and_clear(MSR_FP); |
98da581e AB |
172 | } |
173 | EXPORT_SYMBOL(giveup_fpu); | |
174 | ||
14cf11af PM |
175 | /* |
176 | * Make sure the floating-point register state in the | |
177 | * the thread_struct is up to date for task tsk. | |
178 | */ | |
179 | void flush_fp_to_thread(struct task_struct *tsk) | |
180 | { | |
181 | if (tsk->thread.regs) { | |
182 | /* | |
183 | * We need to disable preemption here because if we didn't, | |
184 | * another process could get scheduled after the regs->msr | |
185 | * test but before we have finished saving the FP registers | |
186 | * to the thread_struct. That process could take over the | |
187 | * FPU, and then when we get scheduled again we would store | |
188 | * bogus values for the remaining FP registers. | |
189 | */ | |
190 | preempt_disable(); | |
191 | if (tsk->thread.regs->msr & MSR_FP) { | |
14cf11af PM |
192 | /* |
193 | * This should only ever be called for current or | |
194 | * for a stopped child process. Since we save away | |
af1bbc3d | 195 | * the FP register state on context switch, |
14cf11af PM |
196 | * there is something wrong if a stopped child appears |
197 | * to still have its FP state in the CPU registers. | |
198 | */ | |
199 | BUG_ON(tsk != current); | |
b86fd2bd | 200 | giveup_fpu(tsk); |
14cf11af PM |
201 | } |
202 | preempt_enable(); | |
203 | } | |
204 | } | |
de56a948 | 205 | EXPORT_SYMBOL_GPL(flush_fp_to_thread); |
14cf11af PM |
206 | |
207 | void enable_kernel_fp(void) | |
208 | { | |
e909fb83 CB |
209 | unsigned long cpumsr; |
210 | ||
14cf11af PM |
211 | WARN_ON(preemptible()); |
212 | ||
e909fb83 | 213 | cpumsr = msr_check_and_set(MSR_FP); |
611b0e5c | 214 | |
d64d02ce AB |
215 | if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { |
216 | check_if_tm_restore_required(current); | |
e909fb83 CB |
217 | /* |
218 | * If a thread has already been reclaimed then the | |
219 | * checkpointed registers are on the CPU but have definitely | |
220 | * been saved by the reclaim code. Don't need to and *cannot* | |
221 | * giveup as this would save to the 'live' structure not the | |
222 | * checkpointed structure. | |
223 | */ | |
5c784c84 BL |
224 | if (!MSR_TM_ACTIVE(cpumsr) && |
225 | MSR_TM_ACTIVE(current->thread.regs->msr)) | |
e909fb83 | 226 | return; |
a0e72cf1 | 227 | __giveup_fpu(current); |
d64d02ce | 228 | } |
14cf11af PM |
229 | } |
230 | EXPORT_SYMBOL(enable_kernel_fp); | |
c83c192a CL |
231 | #else |
232 | static inline void __giveup_fpu(struct task_struct *tsk) { } | |
d1e1cf2e | 233 | #endif /* CONFIG_PPC_FPU */ |
14cf11af | 234 | |
14cf11af | 235 | #ifdef CONFIG_ALTIVEC |
6f515d84 CB |
236 | static void __giveup_altivec(struct task_struct *tsk) |
237 | { | |
8eb98037 AB |
238 | unsigned long msr; |
239 | ||
6f515d84 | 240 | save_altivec(tsk); |
8eb98037 AB |
241 | msr = tsk->thread.regs->msr; |
242 | msr &= ~MSR_VEC; | |
6f515d84 | 243 | if (cpu_has_feature(CPU_FTR_VSX)) |
8eb98037 | 244 | msr &= ~MSR_VSX; |
59dc5bfc | 245 | regs_set_return_msr(tsk->thread.regs, msr); |
6f515d84 CB |
246 | } |
247 | ||
98da581e AB |
248 | void giveup_altivec(struct task_struct *tsk) |
249 | { | |
98da581e AB |
250 | check_if_tm_restore_required(tsk); |
251 | ||
a0e72cf1 | 252 | msr_check_and_set(MSR_VEC); |
98da581e | 253 | __giveup_altivec(tsk); |
a0e72cf1 | 254 | msr_check_and_clear(MSR_VEC); |
98da581e AB |
255 | } |
256 | EXPORT_SYMBOL(giveup_altivec); | |
257 | ||
14cf11af PM |
258 | void enable_kernel_altivec(void) |
259 | { | |
e909fb83 CB |
260 | unsigned long cpumsr; |
261 | ||
14cf11af PM |
262 | WARN_ON(preemptible()); |
263 | ||
e909fb83 | 264 | cpumsr = msr_check_and_set(MSR_VEC); |
611b0e5c | 265 | |
d64d02ce AB |
266 | if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { |
267 | check_if_tm_restore_required(current); | |
e909fb83 CB |
268 | /* |
269 | * If a thread has already been reclaimed then the | |
270 | * checkpointed registers are on the CPU but have definitely | |
271 | * been saved by the reclaim code. Don't need to and *cannot* | |
272 | * giveup as this would save to the 'live' structure not the | |
273 | * checkpointed structure. | |
274 | */ | |
5c784c84 BL |
275 | if (!MSR_TM_ACTIVE(cpumsr) && |
276 | MSR_TM_ACTIVE(current->thread.regs->msr)) | |
e909fb83 | 277 | return; |
a0e72cf1 | 278 | __giveup_altivec(current); |
d64d02ce | 279 | } |
14cf11af PM |
280 | } |
281 | EXPORT_SYMBOL(enable_kernel_altivec); | |
282 | ||
283 | /* | |
284 | * Make sure the VMX/Altivec register state in the | |
285 | * the thread_struct is up to date for task tsk. | |
286 | */ | |
287 | void flush_altivec_to_thread(struct task_struct *tsk) | |
288 | { | |
289 | if (tsk->thread.regs) { | |
290 | preempt_disable(); | |
291 | if (tsk->thread.regs->msr & MSR_VEC) { | |
14cf11af | 292 | BUG_ON(tsk != current); |
b86fd2bd | 293 | giveup_altivec(tsk); |
14cf11af PM |
294 | } |
295 | preempt_enable(); | |
296 | } | |
297 | } | |
de56a948 | 298 | EXPORT_SYMBOL_GPL(flush_altivec_to_thread); |
14cf11af PM |
299 | #endif /* CONFIG_ALTIVEC */ |
300 | ||
ce48b210 | 301 | #ifdef CONFIG_VSX |
bf6a4d5b | 302 | static void __giveup_vsx(struct task_struct *tsk) |
a7d623d4 | 303 | { |
dc801081 BH |
304 | unsigned long msr = tsk->thread.regs->msr; |
305 | ||
306 | /* | |
1fd02f66 | 307 | * We should never be setting MSR_VSX without also setting |
dc801081 BH |
308 | * MSR_FP and MSR_VEC |
309 | */ | |
310 | WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC))); | |
311 | ||
312 | /* __giveup_fpu will clear MSR_VSX */ | |
313 | if (msr & MSR_FP) | |
a7d623d4 | 314 | __giveup_fpu(tsk); |
dc801081 | 315 | if (msr & MSR_VEC) |
a7d623d4 | 316 | __giveup_altivec(tsk); |
bf6a4d5b CB |
317 | } |
318 | ||
319 | static void giveup_vsx(struct task_struct *tsk) | |
320 | { | |
321 | check_if_tm_restore_required(tsk); | |
322 | ||
323 | msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); | |
a7d623d4 | 324 | __giveup_vsx(tsk); |
a0e72cf1 | 325 | msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); |
a7d623d4 | 326 | } |
bf6a4d5b | 327 | |
ce48b210 MN |
328 | void enable_kernel_vsx(void) |
329 | { | |
e909fb83 CB |
330 | unsigned long cpumsr; |
331 | ||
ce48b210 MN |
332 | WARN_ON(preemptible()); |
333 | ||
e909fb83 | 334 | cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); |
611b0e5c | 335 | |
5a69aec9 BH |
336 | if (current->thread.regs && |
337 | (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) { | |
d64d02ce | 338 | check_if_tm_restore_required(current); |
e909fb83 CB |
339 | /* |
340 | * If a thread has already been reclaimed then the | |
341 | * checkpointed registers are on the CPU but have definitely | |
342 | * been saved by the reclaim code. Don't need to and *cannot* | |
343 | * giveup as this would save to the 'live' structure not the | |
344 | * checkpointed structure. | |
345 | */ | |
5c784c84 BL |
346 | if (!MSR_TM_ACTIVE(cpumsr) && |
347 | MSR_TM_ACTIVE(current->thread.regs->msr)) | |
e909fb83 | 348 | return; |
a0e72cf1 | 349 | __giveup_vsx(current); |
611b0e5c | 350 | } |
ce48b210 MN |
351 | } |
352 | EXPORT_SYMBOL(enable_kernel_vsx); | |
ce48b210 MN |
353 | |
354 | void flush_vsx_to_thread(struct task_struct *tsk) | |
355 | { | |
356 | if (tsk->thread.regs) { | |
357 | preempt_disable(); | |
5a69aec9 | 358 | if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) { |
ce48b210 | 359 | BUG_ON(tsk != current); |
ce48b210 MN |
360 | giveup_vsx(tsk); |
361 | } | |
362 | preempt_enable(); | |
363 | } | |
364 | } | |
de56a948 | 365 | EXPORT_SYMBOL_GPL(flush_vsx_to_thread); |
ce48b210 MN |
366 | #endif /* CONFIG_VSX */ |
367 | ||
14cf11af | 368 | #ifdef CONFIG_SPE |
98da581e AB |
369 | void giveup_spe(struct task_struct *tsk) |
370 | { | |
98da581e AB |
371 | check_if_tm_restore_required(tsk); |
372 | ||
a0e72cf1 | 373 | msr_check_and_set(MSR_SPE); |
98da581e | 374 | __giveup_spe(tsk); |
a0e72cf1 | 375 | msr_check_and_clear(MSR_SPE); |
98da581e AB |
376 | } |
377 | EXPORT_SYMBOL(giveup_spe); | |
14cf11af PM |
378 | |
379 | void enable_kernel_spe(void) | |
380 | { | |
381 | WARN_ON(preemptible()); | |
382 | ||
a0e72cf1 | 383 | msr_check_and_set(MSR_SPE); |
611b0e5c | 384 | |
d64d02ce AB |
385 | if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { |
386 | check_if_tm_restore_required(current); | |
a0e72cf1 | 387 | __giveup_spe(current); |
d64d02ce | 388 | } |
14cf11af PM |
389 | } |
390 | EXPORT_SYMBOL(enable_kernel_spe); | |
391 | ||
392 | void flush_spe_to_thread(struct task_struct *tsk) | |
393 | { | |
394 | if (tsk->thread.regs) { | |
395 | preempt_disable(); | |
396 | if (tsk->thread.regs->msr & MSR_SPE) { | |
14cf11af | 397 | BUG_ON(tsk != current); |
685659ee | 398 | tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); |
0ee6c15e | 399 | giveup_spe(tsk); |
14cf11af PM |
400 | } |
401 | preempt_enable(); | |
402 | } | |
403 | } | |
14cf11af PM |
404 | #endif /* CONFIG_SPE */ |
405 | ||
c2085059 AB |
406 | static unsigned long msr_all_available; |
407 | ||
408 | static int __init init_msr_all_available(void) | |
409 | { | |
c83c192a CL |
410 | if (IS_ENABLED(CONFIG_PPC_FPU)) |
411 | msr_all_available |= MSR_FP; | |
c2085059 AB |
412 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) |
413 | msr_all_available |= MSR_VEC; | |
c2085059 AB |
414 | if (cpu_has_feature(CPU_FTR_VSX)) |
415 | msr_all_available |= MSR_VSX; | |
c2085059 AB |
416 | if (cpu_has_feature(CPU_FTR_SPE)) |
417 | msr_all_available |= MSR_SPE; | |
c2085059 AB |
418 | |
419 | return 0; | |
420 | } | |
421 | early_initcall(init_msr_all_available); | |
422 | ||
423 | void giveup_all(struct task_struct *tsk) | |
424 | { | |
425 | unsigned long usermsr; | |
426 | ||
427 | if (!tsk->thread.regs) | |
428 | return; | |
429 | ||
8205d5d9 GR |
430 | check_if_tm_restore_required(tsk); |
431 | ||
c2085059 AB |
432 | usermsr = tsk->thread.regs->msr; |
433 | ||
434 | if ((usermsr & msr_all_available) == 0) | |
435 | return; | |
436 | ||
437 | msr_check_and_set(msr_all_available); | |
438 | ||
96c79b6b BH |
439 | WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); |
440 | ||
c2085059 AB |
441 | if (usermsr & MSR_FP) |
442 | __giveup_fpu(tsk); | |
c2085059 AB |
443 | if (usermsr & MSR_VEC) |
444 | __giveup_altivec(tsk); | |
c2085059 AB |
445 | if (usermsr & MSR_SPE) |
446 | __giveup_spe(tsk); | |
c2085059 AB |
447 | |
448 | msr_check_and_clear(msr_all_available); | |
449 | } | |
450 | EXPORT_SYMBOL(giveup_all); | |
451 | ||
6cc0c16d NP |
452 | #ifdef CONFIG_PPC_BOOK3S_64 |
453 | #ifdef CONFIG_PPC_FPU | |
01eb0187 | 454 | static bool should_restore_fp(void) |
6cc0c16d | 455 | { |
01eb0187 | 456 | if (current->thread.load_fp) { |
6cc0c16d | 457 | current->thread.load_fp++; |
01eb0187 | 458 | return true; |
6cc0c16d | 459 | } |
01eb0187 NP |
460 | return false; |
461 | } | |
462 | ||
463 | static void do_restore_fp(void) | |
464 | { | |
465 | load_fp_state(¤t->thread.fp_state); | |
6cc0c16d NP |
466 | } |
467 | #else | |
01eb0187 NP |
468 | static bool should_restore_fp(void) { return false; } |
469 | static void do_restore_fp(void) { } | |
6cc0c16d NP |
470 | #endif /* CONFIG_PPC_FPU */ |
471 | ||
472 | #ifdef CONFIG_ALTIVEC | |
01eb0187 | 473 | static bool should_restore_altivec(void) |
6cc0c16d | 474 | { |
01eb0187 NP |
475 | if (cpu_has_feature(CPU_FTR_ALTIVEC) && (current->thread.load_vec)) { |
476 | current->thread.load_vec++; | |
477 | return true; | |
6cc0c16d | 478 | } |
01eb0187 NP |
479 | return false; |
480 | } | |
481 | ||
482 | static void do_restore_altivec(void) | |
483 | { | |
484 | load_vr_state(¤t->thread.vr_state); | |
485 | current->thread.used_vr = 1; | |
6cc0c16d NP |
486 | } |
487 | #else | |
01eb0187 NP |
488 | static bool should_restore_altivec(void) { return false; } |
489 | static void do_restore_altivec(void) { } | |
6cc0c16d NP |
490 | #endif /* CONFIG_ALTIVEC */ |
491 | ||
01eb0187 | 492 | static bool should_restore_vsx(void) |
6cc0c16d | 493 | { |
01eb0187 NP |
494 | if (cpu_has_feature(CPU_FTR_VSX)) |
495 | return true; | |
496 | return false; | |
497 | } | |
80739c2b | 498 | #ifdef CONFIG_VSX |
01eb0187 NP |
499 | static void do_restore_vsx(void) |
500 | { | |
501 | current->thread.used_vsr = 1; | |
6cc0c16d NP |
502 | } |
503 | #else | |
01eb0187 | 504 | static void do_restore_vsx(void) { } |
6cc0c16d NP |
505 | #endif /* CONFIG_VSX */ |
506 | ||
e2b36d59 NP |
507 | /* |
508 | * The exception exit path calls restore_math() with interrupts hard disabled | |
509 | * but the soft irq state not "reconciled". ftrace code that calls | |
510 | * local_irq_save/restore causes warnings. | |
511 | * | |
512 | * Rather than complicate the exit path, just don't trace restore_math. This | |
513 | * could be done by having ftrace entry code check for this un-reconciled | |
514 | * condition where MSR[EE]=0 and PACA_IRQ_HARD_DIS is not set, and | |
515 | * temporarily fix it up for the duration of the ftrace call. | |
516 | */ | |
517 | void notrace restore_math(struct pt_regs *regs) | |
70fe3d98 CB |
518 | { |
519 | unsigned long msr; | |
01eb0187 | 520 | unsigned long new_msr = 0; |
70fe3d98 CB |
521 | |
522 | msr = regs->msr; | |
70fe3d98 CB |
523 | |
524 | /* | |
01eb0187 NP |
525 | * new_msr tracks the facilities that are to be restored. Only reload |
526 | * if the bit is not set in the user MSR (if it is set, the registers | |
527 | * are live for the user thread). | |
70fe3d98 | 528 | */ |
01eb0187 | 529 | if ((!(msr & MSR_FP)) && should_restore_fp()) |
b91eb518 | 530 | new_msr |= MSR_FP; |
70fe3d98 | 531 | |
01eb0187 NP |
532 | if ((!(msr & MSR_VEC)) && should_restore_altivec()) |
533 | new_msr |= MSR_VEC; | |
70fe3d98 | 534 | |
01eb0187 NP |
535 | if ((!(msr & MSR_VSX)) && should_restore_vsx()) { |
536 | if (((msr | new_msr) & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC)) | |
537 | new_msr |= MSR_VSX; | |
70fe3d98 CB |
538 | } |
539 | ||
01eb0187 | 540 | if (new_msr) { |
b91eb518 ME |
541 | unsigned long fpexc_mode = 0; |
542 | ||
01eb0187 NP |
543 | msr_check_and_set(new_msr); |
544 | ||
b91eb518 | 545 | if (new_msr & MSR_FP) { |
01eb0187 NP |
546 | do_restore_fp(); |
547 | ||
b91eb518 ME |
548 | // This also covers VSX, because VSX implies FP |
549 | fpexc_mode = current->thread.fpexc_mode; | |
550 | } | |
551 | ||
01eb0187 NP |
552 | if (new_msr & MSR_VEC) |
553 | do_restore_altivec(); | |
70fe3d98 | 554 | |
01eb0187 NP |
555 | if (new_msr & MSR_VSX) |
556 | do_restore_vsx(); | |
557 | ||
558 | msr_check_and_clear(new_msr); | |
559 | ||
59dc5bfc | 560 | regs_set_return_msr(regs, regs->msr | new_msr | fpexc_mode); |
01eb0187 | 561 | } |
70fe3d98 | 562 | } |
60d62bfd | 563 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
70fe3d98 | 564 | |
1cdf039b | 565 | static void save_all(struct task_struct *tsk) |
de2a20aa CB |
566 | { |
567 | unsigned long usermsr; | |
568 | ||
569 | if (!tsk->thread.regs) | |
570 | return; | |
571 | ||
572 | usermsr = tsk->thread.regs->msr; | |
573 | ||
574 | if ((usermsr & msr_all_available) == 0) | |
575 | return; | |
576 | ||
577 | msr_check_and_set(msr_all_available); | |
578 | ||
96c79b6b BH |
579 | WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); |
580 | ||
581 | if (usermsr & MSR_FP) | |
582 | save_fpu(tsk); | |
583 | ||
584 | if (usermsr & MSR_VEC) | |
585 | save_altivec(tsk); | |
de2a20aa CB |
586 | |
587 | if (usermsr & MSR_SPE) | |
588 | __giveup_spe(tsk); | |
589 | ||
590 | msr_check_and_clear(msr_all_available); | |
591 | } | |
592 | ||
579e633e AB |
593 | void flush_all_to_thread(struct task_struct *tsk) |
594 | { | |
595 | if (tsk->thread.regs) { | |
596 | preempt_disable(); | |
597 | BUG_ON(tsk != current); | |
579e633e AB |
598 | #ifdef CONFIG_SPE |
599 | if (tsk->thread.regs->msr & MSR_SPE) | |
600 | tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); | |
601 | #endif | |
e9013785 | 602 | save_all(tsk); |
579e633e AB |
603 | |
604 | preempt_enable(); | |
605 | } | |
606 | } | |
607 | EXPORT_SYMBOL(flush_all_to_thread); | |
608 | ||
3bffb652 DK |
609 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
610 | void do_send_trap(struct pt_regs *regs, unsigned long address, | |
47355040 | 611 | unsigned long error_code, int breakpt) |
3bffb652 | 612 | { |
47355040 | 613 | current->thread.trap_nr = TRAP_HWBKPT; |
3bffb652 DK |
614 | if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, |
615 | 11, SIGSEGV) == NOTIFY_STOP) | |
616 | return; | |
617 | ||
618 | /* Deliver the signal to userspace */ | |
f71dd7dc EB |
619 | force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */ |
620 | (void __user *)address); | |
3bffb652 DK |
621 | } |
622 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ | |
5b905d77 RB |
623 | |
624 | static void do_break_handler(struct pt_regs *regs) | |
625 | { | |
626 | struct arch_hw_breakpoint null_brk = {0}; | |
627 | struct arch_hw_breakpoint *info; | |
c545b9f0 | 628 | ppc_inst_t instr = ppc_inst(0); |
5b905d77 RB |
629 | int type = 0; |
630 | int size = 0; | |
631 | unsigned long ea; | |
632 | int i; | |
633 | ||
634 | /* | |
635 | * If underneath hw supports only one watchpoint, we know it | |
636 | * caused exception. 8xx also falls into this category. | |
637 | */ | |
638 | if (nr_wp_slots() == 1) { | |
639 | __set_breakpoint(0, &null_brk); | |
640 | current->thread.hw_brk[0] = null_brk; | |
641 | current->thread.hw_brk[0].flags |= HW_BRK_FLAG_DISABLED; | |
642 | return; | |
643 | } | |
644 | ||
1fd02f66 | 645 | /* Otherwise find out which DAWR caused exception and disable it. */ |
5b905d77 RB |
646 | wp_get_instr_detail(regs, &instr, &type, &size, &ea); |
647 | ||
648 | for (i = 0; i < nr_wp_slots(); i++) { | |
649 | info = ¤t->thread.hw_brk[i]; | |
650 | if (!info->address) | |
651 | continue; | |
652 | ||
653 | if (wp_check_constraints(regs, instr, ea, type, size, info)) { | |
654 | __set_breakpoint(i, &null_brk); | |
655 | current->thread.hw_brk[i] = null_brk; | |
656 | current->thread.hw_brk[i].flags |= HW_BRK_FLAG_DISABLED; | |
657 | } | |
658 | } | |
659 | } | |
660 | ||
3a96570f | 661 | DEFINE_INTERRUPT_HANDLER(do_break) |
d6a61bfc | 662 | { |
41ab5266 | 663 | current->thread.trap_nr = TRAP_HWBKPT; |
18722ecf | 664 | if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, regs->dsisr, |
d6a61bfc LM |
665 | 11, SIGSEGV) == NOTIFY_STOP) |
666 | return; | |
667 | ||
9422de3e | 668 | if (debugger_break_match(regs)) |
d6a61bfc LM |
669 | return; |
670 | ||
5b905d77 RB |
671 | /* |
672 | * We reach here only when watchpoint exception is generated by ptrace | |
673 | * event (or hw is buggy!). Now if CONFIG_HAVE_HW_BREAKPOINT is set, | |
674 | * watchpoint is already handled by hw_breakpoint_handler() so we don't | |
675 | * have to do anything. But when CONFIG_HAVE_HW_BREAKPOINT is not set, | |
676 | * we need to manually handle the watchpoint here. | |
677 | */ | |
678 | if (!IS_ENABLED(CONFIG_HAVE_HW_BREAKPOINT)) | |
679 | do_break_handler(regs); | |
680 | ||
d6a61bfc | 681 | /* Deliver the signal to userspace */ |
18722ecf | 682 | force_sig_fault(SIGTRAP, TRAP_HWBKPT, (void __user *)regs->dar); |
d6a61bfc | 683 | } |
3bffb652 | 684 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
d6a61bfc | 685 | |
4a8a9379 | 686 | static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk[HBP_NUM_MAX]); |
a2ceff5e | 687 | |
3bffb652 DK |
688 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
689 | /* | |
690 | * Set the debug registers back to their default "safe" values. | |
691 | */ | |
692 | static void set_debug_reg_defaults(struct thread_struct *thread) | |
693 | { | |
51ae8d4a | 694 | thread->debug.iac1 = thread->debug.iac2 = 0; |
3bffb652 | 695 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
51ae8d4a | 696 | thread->debug.iac3 = thread->debug.iac4 = 0; |
3bffb652 | 697 | #endif |
51ae8d4a | 698 | thread->debug.dac1 = thread->debug.dac2 = 0; |
3bffb652 | 699 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
51ae8d4a | 700 | thread->debug.dvc1 = thread->debug.dvc2 = 0; |
3bffb652 | 701 | #endif |
51ae8d4a | 702 | thread->debug.dbcr0 = 0; |
3bffb652 DK |
703 | #ifdef CONFIG_BOOKE |
704 | /* | |
705 | * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) | |
706 | */ | |
51ae8d4a | 707 | thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | |
3bffb652 DK |
708 | DBCR1_IAC3US | DBCR1_IAC4US; |
709 | /* | |
710 | * Force Data Address Compare User/Supervisor bits to be User-only | |
711 | * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. | |
712 | */ | |
51ae8d4a | 713 | thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; |
3bffb652 | 714 | #else |
51ae8d4a | 715 | thread->debug.dbcr1 = 0; |
3bffb652 DK |
716 | #endif |
717 | } | |
718 | ||
f5f97210 | 719 | static void prime_debug_regs(struct debug_reg *debug) |
3bffb652 | 720 | { |
6cecf76b SW |
721 | /* |
722 | * We could have inherited MSR_DE from userspace, since | |
723 | * it doesn't get cleared on exception entry. Make sure | |
724 | * MSR_DE is clear before we enable any debug events. | |
725 | */ | |
726 | mtmsr(mfmsr() & ~MSR_DE); | |
727 | ||
f5f97210 SW |
728 | mtspr(SPRN_IAC1, debug->iac1); |
729 | mtspr(SPRN_IAC2, debug->iac2); | |
3bffb652 | 730 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
f5f97210 SW |
731 | mtspr(SPRN_IAC3, debug->iac3); |
732 | mtspr(SPRN_IAC4, debug->iac4); | |
3bffb652 | 733 | #endif |
f5f97210 SW |
734 | mtspr(SPRN_DAC1, debug->dac1); |
735 | mtspr(SPRN_DAC2, debug->dac2); | |
3bffb652 | 736 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
f5f97210 SW |
737 | mtspr(SPRN_DVC1, debug->dvc1); |
738 | mtspr(SPRN_DVC2, debug->dvc2); | |
3bffb652 | 739 | #endif |
f5f97210 SW |
740 | mtspr(SPRN_DBCR0, debug->dbcr0); |
741 | mtspr(SPRN_DBCR1, debug->dbcr1); | |
3bffb652 | 742 | #ifdef CONFIG_BOOKE |
f5f97210 | 743 | mtspr(SPRN_DBCR2, debug->dbcr2); |
3bffb652 DK |
744 | #endif |
745 | } | |
746 | /* | |
747 | * Unless neither the old or new thread are making use of the | |
748 | * debug registers, set the debug registers from the values | |
749 | * stored in the new thread. | |
750 | */ | |
f5f97210 | 751 | void switch_booke_debug_regs(struct debug_reg *new_debug) |
3bffb652 | 752 | { |
51ae8d4a | 753 | if ((current->thread.debug.dbcr0 & DBCR0_IDM) |
f5f97210 SW |
754 | || (new_debug->dbcr0 & DBCR0_IDM)) |
755 | prime_debug_regs(new_debug); | |
3bffb652 | 756 | } |
3743c9b8 | 757 | EXPORT_SYMBOL_GPL(switch_booke_debug_regs); |
3bffb652 | 758 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ |
e0780b72 | 759 | #ifndef CONFIG_HAVE_HW_BREAKPOINT |
303e6a9d | 760 | static void set_breakpoint(int i, struct arch_hw_breakpoint *brk) |
b5ac51d7 CL |
761 | { |
762 | preempt_disable(); | |
303e6a9d | 763 | __set_breakpoint(i, brk); |
b5ac51d7 CL |
764 | preempt_enable(); |
765 | } | |
766 | ||
3bffb652 DK |
767 | static void set_debug_reg_defaults(struct thread_struct *thread) |
768 | { | |
303e6a9d RB |
769 | int i; |
770 | struct arch_hw_breakpoint null_brk = {0}; | |
771 | ||
772 | for (i = 0; i < nr_wp_slots(); i++) { | |
773 | thread->hw_brk[i] = null_brk; | |
774 | if (ppc_breakpoint_available()) | |
775 | set_breakpoint(i, &thread->hw_brk[i]); | |
776 | } | |
777 | } | |
778 | ||
779 | static inline bool hw_brk_match(struct arch_hw_breakpoint *a, | |
780 | struct arch_hw_breakpoint *b) | |
781 | { | |
782 | if (a->address != b->address) | |
783 | return false; | |
784 | if (a->type != b->type) | |
785 | return false; | |
786 | if (a->len != b->len) | |
787 | return false; | |
788 | /* no need to check hw_len. it's calculated from address and len */ | |
789 | return true; | |
790 | } | |
791 | ||
792 | static void switch_hw_breakpoint(struct task_struct *new) | |
793 | { | |
794 | int i; | |
795 | ||
796 | for (i = 0; i < nr_wp_slots(); i++) { | |
797 | if (likely(hw_brk_match(this_cpu_ptr(¤t_brk[i]), | |
798 | &new->thread.hw_brk[i]))) | |
799 | continue; | |
800 | ||
801 | __set_breakpoint(i, &new->thread.hw_brk[i]); | |
802 | } | |
3bffb652 | 803 | } |
e0780b72 | 804 | #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 DK |
805 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
806 | ||
9422de3e MN |
807 | static inline int set_dabr(struct arch_hw_breakpoint *brk) |
808 | { | |
809 | unsigned long dabr, dabrx; | |
810 | ||
811 | dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); | |
812 | dabrx = ((brk->type >> 3) & 0x7); | |
813 | ||
814 | if (ppc_md.set_dabr) | |
815 | return ppc_md.set_dabr(dabr, dabrx); | |
816 | ||
ad3ed15c CL |
817 | if (IS_ENABLED(CONFIG_PPC_ADV_DEBUG_REGS)) { |
818 | mtspr(SPRN_DAC1, dabr); | |
819 | if (IS_ENABLED(CONFIG_PPC_47x)) | |
820 | isync(); | |
821 | return 0; | |
822 | } else if (IS_ENABLED(CONFIG_PPC_BOOK3S)) { | |
823 | mtspr(SPRN_DABR, dabr); | |
824 | if (cpu_has_feature(CPU_FTR_DABRX)) | |
825 | mtspr(SPRN_DABRX, dabrx); | |
826 | return 0; | |
827 | } else { | |
828 | return -EINVAL; | |
829 | } | |
9422de3e MN |
830 | } |
831 | ||
39413ae0 CL |
832 | static inline int set_breakpoint_8xx(struct arch_hw_breakpoint *brk) |
833 | { | |
834 | unsigned long lctrl1 = LCTRL1_CTE_GT | LCTRL1_CTF_LT | LCTRL1_CRWE_RW | | |
835 | LCTRL1_CRWF_RW; | |
836 | unsigned long lctrl2 = LCTRL2_LW0EN | LCTRL2_LW0LADC | LCTRL2_SLW0EN; | |
e68ef121 RB |
837 | unsigned long start_addr = ALIGN_DOWN(brk->address, HW_BREAKPOINT_SIZE); |
838 | unsigned long end_addr = ALIGN(brk->address + brk->len, HW_BREAKPOINT_SIZE); | |
39413ae0 CL |
839 | |
840 | if (start_addr == 0) | |
841 | lctrl2 |= LCTRL2_LW0LA_F; | |
e68ef121 | 842 | else if (end_addr == 0) |
39413ae0 CL |
843 | lctrl2 |= LCTRL2_LW0LA_E; |
844 | else | |
845 | lctrl2 |= LCTRL2_LW0LA_EandF; | |
846 | ||
847 | mtspr(SPRN_LCTRL2, 0); | |
848 | ||
849 | if ((brk->type & HW_BRK_TYPE_RDWR) == 0) | |
850 | return 0; | |
851 | ||
852 | if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ) | |
853 | lctrl1 |= LCTRL1_CRWE_RO | LCTRL1_CRWF_RO; | |
854 | if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE) | |
855 | lctrl1 |= LCTRL1_CRWE_WO | LCTRL1_CRWF_WO; | |
856 | ||
857 | mtspr(SPRN_CMPE, start_addr - 1); | |
e68ef121 | 858 | mtspr(SPRN_CMPF, end_addr); |
39413ae0 CL |
859 | mtspr(SPRN_LCTRL1, lctrl1); |
860 | mtspr(SPRN_LCTRL2, lctrl2); | |
861 | ||
862 | return 0; | |
863 | } | |
864 | ||
3671f4eb | 865 | static void set_hw_breakpoint(int nr, struct arch_hw_breakpoint *brk) |
9422de3e | 866 | { |
c1fe190c | 867 | if (dawr_enabled()) |
252988cb | 868 | // Power8 or later |
4a8a9379 | 869 | set_dawr(nr, brk); |
39413ae0 CL |
870 | else if (IS_ENABLED(CONFIG_PPC_8xx)) |
871 | set_breakpoint_8xx(brk); | |
252988cb NP |
872 | else if (!cpu_has_feature(CPU_FTR_ARCH_207S)) |
873 | // Power7 or earlier | |
04c32a51 | 874 | set_dabr(brk); |
252988cb NP |
875 | else |
876 | // Shouldn't happen due to higher level checks | |
877 | WARN_ON_ONCE(1); | |
9422de3e | 878 | } |
14cf11af | 879 | |
3671f4eb JN |
880 | void __set_breakpoint(int nr, struct arch_hw_breakpoint *brk) |
881 | { | |
882 | memcpy(this_cpu_ptr(¤t_brk[nr]), brk, sizeof(*brk)); | |
883 | set_hw_breakpoint(nr, brk); | |
884 | } | |
885 | ||
404b27d6 MN |
886 | /* Check if we have DAWR or DABR hardware */ |
887 | bool ppc_breakpoint_available(void) | |
888 | { | |
c1fe190c MN |
889 | if (dawr_enabled()) |
890 | return true; /* POWER8 DAWR or POWER9 forced DAWR */ | |
404b27d6 MN |
891 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) |
892 | return false; /* POWER9 with DAWR disabled */ | |
893 | /* DABR: Everything but POWER8 and POWER9 */ | |
894 | return true; | |
895 | } | |
896 | EXPORT_SYMBOL_GPL(ppc_breakpoint_available); | |
897 | ||
3671f4eb JN |
898 | /* Disable the breakpoint in hardware without touching current_brk[] */ |
899 | void suspend_breakpoints(void) | |
900 | { | |
901 | struct arch_hw_breakpoint brk = {0}; | |
902 | int i; | |
903 | ||
904 | if (!ppc_breakpoint_available()) | |
905 | return; | |
906 | ||
907 | for (i = 0; i < nr_wp_slots(); i++) | |
908 | set_hw_breakpoint(i, &brk); | |
909 | } | |
910 | ||
911 | /* | |
912 | * Re-enable breakpoints suspended by suspend_breakpoints() in hardware | |
913 | * from current_brk[] | |
914 | */ | |
915 | void restore_breakpoints(void) | |
916 | { | |
917 | int i; | |
918 | ||
919 | if (!ppc_breakpoint_available()) | |
920 | return; | |
921 | ||
922 | for (i = 0; i < nr_wp_slots(); i++) | |
923 | set_hw_breakpoint(i, this_cpu_ptr(¤t_brk[i])); | |
924 | } | |
925 | ||
fb09692e | 926 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
5d176f75 CB |
927 | |
928 | static inline bool tm_enabled(struct task_struct *tsk) | |
929 | { | |
930 | return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM); | |
931 | } | |
932 | ||
edd00b83 | 933 | static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause) |
d31626f7 | 934 | { |
7f821fc9 MN |
935 | /* |
936 | * Use the current MSR TM suspended bit to track if we have | |
937 | * checkpointed state outstanding. | |
938 | * On signal delivery, we'd normally reclaim the checkpointed | |
939 | * state to obtain stack pointer (see:get_tm_stackpointer()). | |
940 | * This will then directly return to userspace without going | |
941 | * through __switch_to(). However, if the stack frame is bad, | |
942 | * we need to exit this thread which calls __switch_to() which | |
943 | * will again attempt to reclaim the already saved tm state. | |
944 | * Hence we need to check that we've not already reclaimed | |
945 | * this state. | |
946 | * We do this using the current MSR, rather tracking it in | |
947 | * some specific thread_struct bit, as it has the additional | |
027dfac6 | 948 | * benefit of checking for a potential TM bad thing exception. |
7f821fc9 MN |
949 | */ |
950 | if (!MSR_TM_SUSPENDED(mfmsr())) | |
951 | return; | |
952 | ||
91381b9c CB |
953 | giveup_all(container_of(thr, struct task_struct, thread)); |
954 | ||
eb5c3f1c CB |
955 | tm_reclaim(thr, cause); |
956 | ||
f48e91e8 MN |
957 | /* |
958 | * If we are in a transaction and FP is off then we can't have | |
959 | * used FP inside that transaction. Hence the checkpointed | |
960 | * state is the same as the live state. We need to copy the | |
961 | * live state to the checkpointed state so that when the | |
962 | * transaction is restored, the checkpointed state is correct | |
963 | * and the aborted transaction sees the correct state. We use | |
964 | * ckpt_regs.msr here as that's what tm_reclaim will use to | |
965 | * determine if it's going to write the checkpointed state or | |
966 | * not. So either this will write the checkpointed registers, | |
967 | * or reclaim will. Similarly for VMX. | |
968 | */ | |
969 | if ((thr->ckpt_regs.msr & MSR_FP) == 0) | |
970 | memcpy(&thr->ckfp_state, &thr->fp_state, | |
971 | sizeof(struct thread_fp_state)); | |
972 | if ((thr->ckpt_regs.msr & MSR_VEC) == 0) | |
973 | memcpy(&thr->ckvr_state, &thr->vr_state, | |
974 | sizeof(struct thread_vr_state)); | |
d31626f7 PM |
975 | } |
976 | ||
977 | void tm_reclaim_current(uint8_t cause) | |
978 | { | |
979 | tm_enable(); | |
edd00b83 | 980 | tm_reclaim_thread(¤t->thread, cause); |
d31626f7 PM |
981 | } |
982 | ||
fb09692e MN |
983 | static inline void tm_reclaim_task(struct task_struct *tsk) |
984 | { | |
985 | /* We have to work out if we're switching from/to a task that's in the | |
986 | * middle of a transaction. | |
987 | * | |
988 | * In switching we need to maintain a 2nd register state as | |
989 | * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the | |
000ec280 CB |
990 | * checkpointed (tbegin) state in ckpt_regs, ckfp_state and |
991 | * ckvr_state | |
fb09692e MN |
992 | * |
993 | * We also context switch (save) TFHAR/TEXASR/TFIAR in here. | |
994 | */ | |
995 | struct thread_struct *thr = &tsk->thread; | |
996 | ||
997 | if (!thr->regs) | |
998 | return; | |
999 | ||
1000 | if (!MSR_TM_ACTIVE(thr->regs->msr)) | |
1001 | goto out_and_saveregs; | |
1002 | ||
92fb8690 MN |
1003 | WARN_ON(tm_suspend_disabled); |
1004 | ||
fb09692e MN |
1005 | TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " |
1006 | "ccr=%lx, msr=%lx, trap=%lx)\n", | |
1007 | tsk->pid, thr->regs->nip, | |
1008 | thr->regs->ccr, thr->regs->msr, | |
1009 | thr->regs->trap); | |
1010 | ||
edd00b83 | 1011 | tm_reclaim_thread(thr, TM_CAUSE_RESCHED); |
fb09692e MN |
1012 | |
1013 | TM_DEBUG("--- tm_reclaim on pid %d complete\n", | |
1014 | tsk->pid); | |
1015 | ||
1016 | out_and_saveregs: | |
1017 | /* Always save the regs here, even if a transaction's not active. | |
1018 | * This context-switches a thread's TM info SPRs. We do it here to | |
1019 | * be consistent with the restore path (in recheckpoint) which | |
1020 | * cannot happen later in _switch(). | |
1021 | */ | |
1022 | tm_save_sprs(thr); | |
1023 | } | |
1024 | ||
eb5c3f1c | 1025 | extern void __tm_recheckpoint(struct thread_struct *thread); |
e6b8fd02 | 1026 | |
eb5c3f1c | 1027 | void tm_recheckpoint(struct thread_struct *thread) |
e6b8fd02 MN |
1028 | { |
1029 | unsigned long flags; | |
1030 | ||
5d176f75 CB |
1031 | if (!(thread->regs->msr & MSR_TM)) |
1032 | return; | |
1033 | ||
e6b8fd02 MN |
1034 | /* We really can't be interrupted here as the TEXASR registers can't |
1035 | * change and later in the trecheckpoint code, we have a userspace R1. | |
1036 | * So let's hard disable over this region. | |
1037 | */ | |
1038 | local_irq_save(flags); | |
1039 | hard_irq_disable(); | |
1040 | ||
1041 | /* The TM SPRs are restored here, so that TEXASR.FS can be set | |
1042 | * before the trecheckpoint and no explosion occurs. | |
1043 | */ | |
1044 | tm_restore_sprs(thread); | |
1045 | ||
eb5c3f1c | 1046 | __tm_recheckpoint(thread); |
e6b8fd02 MN |
1047 | |
1048 | local_irq_restore(flags); | |
1049 | } | |
1050 | ||
bc2a9408 | 1051 | static inline void tm_recheckpoint_new_task(struct task_struct *new) |
fb09692e | 1052 | { |
fb09692e MN |
1053 | if (!cpu_has_feature(CPU_FTR_TM)) |
1054 | return; | |
1055 | ||
1056 | /* Recheckpoint the registers of the thread we're about to switch to. | |
1057 | * | |
1058 | * If the task was using FP, we non-lazily reload both the original and | |
1059 | * the speculative FP register states. This is because the kernel | |
1060 | * doesn't see if/when a TM rollback occurs, so if we take an FP | |
dc310669 | 1061 | * unavailable later, we are unable to determine which set of FP regs |
fb09692e MN |
1062 | * need to be restored. |
1063 | */ | |
5d176f75 | 1064 | if (!tm_enabled(new)) |
fb09692e MN |
1065 | return; |
1066 | ||
e6b8fd02 MN |
1067 | if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ |
1068 | tm_restore_sprs(&new->thread); | |
fb09692e | 1069 | return; |
e6b8fd02 | 1070 | } |
fb09692e | 1071 | /* Recheckpoint to restore original checkpointed register state. */ |
eb5c3f1c CB |
1072 | TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n", |
1073 | new->pid, new->thread.regs->msr); | |
fb09692e | 1074 | |
eb5c3f1c | 1075 | tm_recheckpoint(&new->thread); |
fb09692e | 1076 | |
dc310669 CB |
1077 | /* |
1078 | * The checkpointed state has been restored but the live state has | |
1079 | * not, ensure all the math functionality is turned off to trigger | |
1080 | * restore_math() to reload. | |
1081 | */ | |
1082 | new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX); | |
fb09692e MN |
1083 | |
1084 | TM_DEBUG("*** tm_recheckpoint of pid %d complete " | |
1085 | "(kernel msr 0x%lx)\n", | |
1086 | new->pid, mfmsr()); | |
1087 | } | |
1088 | ||
dc310669 CB |
1089 | static inline void __switch_to_tm(struct task_struct *prev, |
1090 | struct task_struct *new) | |
fb09692e MN |
1091 | { |
1092 | if (cpu_has_feature(CPU_FTR_TM)) { | |
5d176f75 CB |
1093 | if (tm_enabled(prev) || tm_enabled(new)) |
1094 | tm_enable(); | |
1095 | ||
1096 | if (tm_enabled(prev)) { | |
1097 | prev->thread.load_tm++; | |
1098 | tm_reclaim_task(prev); | |
1099 | if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0) | |
1100 | prev->thread.regs->msr &= ~MSR_TM; | |
1101 | } | |
1102 | ||
dc310669 | 1103 | tm_recheckpoint_new_task(new); |
fb09692e MN |
1104 | } |
1105 | } | |
d31626f7 PM |
1106 | |
1107 | /* | |
1108 | * This is called if we are on the way out to userspace and the | |
1109 | * TIF_RESTORE_TM flag is set. It checks if we need to reload | |
1110 | * FP and/or vector state and does so if necessary. | |
1111 | * If userspace is inside a transaction (whether active or | |
1112 | * suspended) and FP/VMX/VSX instructions have ever been enabled | |
1113 | * inside that transaction, then we have to keep them enabled | |
1114 | * and keep the FP/VMX/VSX state loaded while ever the transaction | |
1115 | * continues. The reason is that if we didn't, and subsequently | |
1116 | * got a FP/VMX/VSX unavailable interrupt inside a transaction, | |
1117 | * we don't know whether it's the same transaction, and thus we | |
1118 | * don't know which of the checkpointed state and the transactional | |
1119 | * state to use. | |
1120 | */ | |
1121 | void restore_tm_state(struct pt_regs *regs) | |
1122 | { | |
1123 | unsigned long msr_diff; | |
1124 | ||
dc310669 CB |
1125 | /* |
1126 | * This is the only moment we should clear TIF_RESTORE_TM as | |
1127 | * it is here that ckpt_regs.msr and pt_regs.msr become the same | |
1128 | * again, anything else could lead to an incorrect ckpt_msr being | |
1129 | * saved and therefore incorrect signal contexts. | |
1130 | */ | |
d31626f7 PM |
1131 | clear_thread_flag(TIF_RESTORE_TM); |
1132 | if (!MSR_TM_ACTIVE(regs->msr)) | |
1133 | return; | |
1134 | ||
829023df | 1135 | msr_diff = current->thread.ckpt_regs.msr & ~regs->msr; |
d31626f7 | 1136 | msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; |
70fe3d98 | 1137 | |
dc16b553 CB |
1138 | /* Ensure that restore_math() will restore */ |
1139 | if (msr_diff & MSR_FP) | |
1140 | current->thread.load_fp = 1; | |
39715bf9 | 1141 | #ifdef CONFIG_ALTIVEC |
dc16b553 CB |
1142 | if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC) |
1143 | current->thread.load_vec = 1; | |
1144 | #endif | |
70fe3d98 CB |
1145 | restore_math(regs); |
1146 | ||
59dc5bfc | 1147 | regs_set_return_msr(regs, regs->msr | msr_diff); |
d31626f7 PM |
1148 | } |
1149 | ||
2d19630e | 1150 | #else /* !CONFIG_PPC_TRANSACTIONAL_MEM */ |
fb09692e | 1151 | #define tm_recheckpoint_new_task(new) |
dc310669 | 1152 | #define __switch_to_tm(prev, new) |
2d19630e | 1153 | void tm_reclaim_current(uint8_t cause) {} |
fb09692e | 1154 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
9422de3e | 1155 | |
152d523e AB |
1156 | static inline void save_sprs(struct thread_struct *t) |
1157 | { | |
1158 | #ifdef CONFIG_ALTIVEC | |
01d7c2a2 | 1159 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) |
152d523e AB |
1160 | t->vrsave = mfspr(SPRN_VRSAVE); |
1161 | #endif | |
359c2ca7 CL |
1162 | #ifdef CONFIG_SPE |
1163 | if (cpu_has_feature(CPU_FTR_SPE)) | |
1164 | t->spefscr = mfspr(SPRN_SPEFSCR); | |
1165 | #endif | |
152d523e AB |
1166 | #ifdef CONFIG_PPC_BOOK3S_64 |
1167 | if (cpu_has_feature(CPU_FTR_DSCR)) | |
1168 | t->dscr = mfspr(SPRN_DSCR); | |
1169 | ||
1170 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
1171 | t->bescr = mfspr(SPRN_BESCR); | |
1172 | t->ebbhr = mfspr(SPRN_EBBHR); | |
1173 | t->ebbrr = mfspr(SPRN_EBBRR); | |
1174 | ||
1175 | t->fscr = mfspr(SPRN_FSCR); | |
1176 | ||
1177 | /* | |
1178 | * Note that the TAR is not available for use in the kernel. | |
1179 | * (To provide this, the TAR should be backed up/restored on | |
1180 | * exception entry/exit instead, and be in pt_regs. FIXME, | |
1181 | * this should be in pt_regs anyway (for debug).) | |
1182 | */ | |
1183 | t->tar = mfspr(SPRN_TAR); | |
1184 | } | |
1185 | #endif | |
1186 | } | |
1187 | ||
34e119c9 NP |
1188 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
1189 | void kvmppc_save_user_regs(void) | |
1190 | { | |
1191 | unsigned long usermsr; | |
1192 | ||
1193 | if (!current->thread.regs) | |
1194 | return; | |
1195 | ||
1196 | usermsr = current->thread.regs->msr; | |
1197 | ||
1198 | if (usermsr & MSR_FP) | |
1199 | save_fpu(current); | |
1200 | ||
1201 | if (usermsr & MSR_VEC) | |
1202 | save_altivec(current); | |
1203 | ||
1204 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1205 | if (usermsr & MSR_TM) { | |
1206 | current->thread.tm_tfhar = mfspr(SPRN_TFHAR); | |
1207 | current->thread.tm_tfiar = mfspr(SPRN_TFIAR); | |
1208 | current->thread.tm_texasr = mfspr(SPRN_TEXASR); | |
1209 | current->thread.regs->msr &= ~MSR_TM; | |
1210 | } | |
1211 | #endif | |
1212 | } | |
1213 | EXPORT_SYMBOL_GPL(kvmppc_save_user_regs); | |
5236756d NP |
1214 | |
1215 | void kvmppc_save_current_sprs(void) | |
1216 | { | |
1217 | save_sprs(¤t->thread); | |
1218 | } | |
1219 | EXPORT_SYMBOL_GPL(kvmppc_save_current_sprs); | |
34e119c9 NP |
1220 | #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */ |
1221 | ||
152d523e AB |
1222 | static inline void restore_sprs(struct thread_struct *old_thread, |
1223 | struct thread_struct *new_thread) | |
1224 | { | |
1225 | #ifdef CONFIG_ALTIVEC | |
1226 | if (cpu_has_feature(CPU_FTR_ALTIVEC) && | |
1227 | old_thread->vrsave != new_thread->vrsave) | |
1228 | mtspr(SPRN_VRSAVE, new_thread->vrsave); | |
1229 | #endif | |
359c2ca7 CL |
1230 | #ifdef CONFIG_SPE |
1231 | if (cpu_has_feature(CPU_FTR_SPE) && | |
1232 | old_thread->spefscr != new_thread->spefscr) | |
1233 | mtspr(SPRN_SPEFSCR, new_thread->spefscr); | |
1234 | #endif | |
152d523e AB |
1235 | #ifdef CONFIG_PPC_BOOK3S_64 |
1236 | if (cpu_has_feature(CPU_FTR_DSCR)) { | |
1237 | u64 dscr = get_paca()->dscr_default; | |
b57bd2de | 1238 | if (new_thread->dscr_inherit) |
152d523e | 1239 | dscr = new_thread->dscr; |
152d523e AB |
1240 | |
1241 | if (old_thread->dscr != dscr) | |
1242 | mtspr(SPRN_DSCR, dscr); | |
152d523e AB |
1243 | } |
1244 | ||
1245 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
1246 | if (old_thread->bescr != new_thread->bescr) | |
1247 | mtspr(SPRN_BESCR, new_thread->bescr); | |
1248 | if (old_thread->ebbhr != new_thread->ebbhr) | |
1249 | mtspr(SPRN_EBBHR, new_thread->ebbhr); | |
1250 | if (old_thread->ebbrr != new_thread->ebbrr) | |
1251 | mtspr(SPRN_EBBRR, new_thread->ebbrr); | |
1252 | ||
b57bd2de MN |
1253 | if (old_thread->fscr != new_thread->fscr) |
1254 | mtspr(SPRN_FSCR, new_thread->fscr); | |
1255 | ||
152d523e AB |
1256 | if (old_thread->tar != new_thread->tar) |
1257 | mtspr(SPRN_TAR, new_thread->tar); | |
1258 | } | |
ec233ede | 1259 | |
3449f191 | 1260 | if (cpu_has_feature(CPU_FTR_P9_TIDR) && |
ec233ede SB |
1261 | old_thread->tidr != new_thread->tidr) |
1262 | mtspr(SPRN_TIDR, new_thread->tidr); | |
152d523e | 1263 | #endif |
06bb53b3 | 1264 | |
152d523e AB |
1265 | } |
1266 | ||
14cf11af PM |
1267 | struct task_struct *__switch_to(struct task_struct *prev, |
1268 | struct task_struct *new) | |
1269 | { | |
1270 | struct thread_struct *new_thread, *old_thread; | |
14cf11af | 1271 | struct task_struct *last; |
387e220a | 1272 | #ifdef CONFIG_PPC_64S_HASH_MMU |
d6bf29b4 PZ |
1273 | struct ppc64_tlb_batch *batch; |
1274 | #endif | |
14cf11af | 1275 | |
152d523e AB |
1276 | new_thread = &new->thread; |
1277 | old_thread = ¤t->thread; | |
1278 | ||
7ba5fef7 MN |
1279 | WARN_ON(!irqs_disabled()); |
1280 | ||
387e220a | 1281 | #ifdef CONFIG_PPC_64S_HASH_MMU |
69111bac | 1282 | batch = this_cpu_ptr(&ppc64_tlb_batch); |
d6bf29b4 PZ |
1283 | if (batch->active) { |
1284 | current_thread_info()->local_flags |= _TLF_LAZY_MMU; | |
1285 | if (batch->index) | |
1286 | __flush_tlb_pending(batch); | |
1287 | batch->active = 0; | |
1288 | } | |
f35d2f24 NP |
1289 | |
1290 | /* | |
1291 | * On POWER9 the copy-paste buffer can only paste into | |
1292 | * foreign real addresses, so unprivileged processes can not | |
1293 | * see the data or use it in any way unless they have | |
1294 | * foreign real mappings. If the new process has the foreign | |
1295 | * real address mappings, we must issue a cp_abort to clear | |
1296 | * any state and prevent snooping, corruption or a covert | |
1297 | * channel. ISA v3.1 supports paste into local memory. | |
1298 | */ | |
1299 | if (new->mm && (cpu_has_feature(CPU_FTR_ARCH_31) || | |
1300 | atomic_read(&new->mm->context.vas_windows))) | |
1301 | asm volatile(PPC_CP_ABORT); | |
4e003747 | 1302 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
06d67d54 | 1303 | |
f3d885cc AB |
1304 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
1305 | switch_booke_debug_regs(&new->thread.debug); | |
1306 | #else | |
1307 | /* | |
1308 | * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would | |
1309 | * schedule DABR | |
1310 | */ | |
1311 | #ifndef CONFIG_HAVE_HW_BREAKPOINT | |
303e6a9d | 1312 | switch_hw_breakpoint(new); |
f3d885cc AB |
1313 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
1314 | #endif | |
1315 | ||
1316 | /* | |
1317 | * We need to save SPRs before treclaim/trecheckpoint as these will | |
1318 | * change a number of them. | |
1319 | */ | |
1320 | save_sprs(&prev->thread); | |
1321 | ||
f3d885cc AB |
1322 | /* Save FPU, Altivec, VSX and SPE state */ |
1323 | giveup_all(prev); | |
1324 | ||
dc310669 CB |
1325 | __switch_to_tm(prev, new); |
1326 | ||
e4c0fc5f NP |
1327 | if (!radix_enabled()) { |
1328 | /* | |
1329 | * We can't take a PMU exception inside _switch() since there | |
1330 | * is a window where the kernel stack SLB and the kernel stack | |
1331 | * are out of sync. Hard disable here. | |
1332 | */ | |
1333 | hard_irq_disable(); | |
1334 | } | |
bc2a9408 | 1335 | |
20dbe670 | 1336 | /* |
59dc5bfc NP |
1337 | * Call restore_sprs() and set_return_regs_changed() before calling |
1338 | * _switch(). If we move it after _switch() then we miss out on calling | |
1339 | * it for new tasks. The reason for this is we manually create a stack | |
1340 | * frame for new tasks that directly returns through ret_from_fork() or | |
20dbe670 AB |
1341 | * ret_from_kernel_thread(). See copy_thread() for details. |
1342 | */ | |
f3d885cc AB |
1343 | restore_sprs(old_thread, new_thread); |
1344 | ||
59dc5bfc NP |
1345 | set_return_regs_changed(); /* _switch changes stack (and regs) */ |
1346 | ||
42e03bc5 CL |
1347 | if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64)) |
1348 | kuap_assert_locked(); | |
1349 | ||
20dbe670 AB |
1350 | last = _switch(old_thread, new_thread); |
1351 | ||
f35d2f24 NP |
1352 | /* |
1353 | * Nothing after _switch will be run for newly created tasks, | |
1354 | * because they switch directly to ret_from_fork/ret_from_kernel_thread | |
1355 | * etc. Code added here should have a comment explaining why that is | |
1356 | * okay. | |
1357 | */ | |
1358 | ||
4e003747 | 1359 | #ifdef CONFIG_PPC_BOOK3S_64 |
387e220a | 1360 | #ifdef CONFIG_PPC_64S_HASH_MMU |
f35d2f24 NP |
1361 | /* |
1362 | * This applies to a process that was context switched while inside | |
1363 | * arch_enter_lazy_mmu_mode(), to re-activate the batch that was | |
1364 | * deactivated above, before _switch(). This will never be the case | |
1365 | * for new tasks. | |
1366 | */ | |
d6bf29b4 PZ |
1367 | if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { |
1368 | current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; | |
69111bac | 1369 | batch = this_cpu_ptr(&ppc64_tlb_batch); |
d6bf29b4 PZ |
1370 | batch->active = 1; |
1371 | } | |
387e220a | 1372 | #endif |
70fe3d98 | 1373 | |
f35d2f24 NP |
1374 | /* |
1375 | * Math facilities are masked out of the child MSR in copy_thread. | |
1376 | * A new task does not need to restore_math because it will | |
1377 | * demand fault them. | |
1378 | */ | |
1379 | if (current->thread.regs) | |
05b98791 | 1380 | restore_math(current->thread.regs); |
4e003747 | 1381 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
d6bf29b4 | 1382 | |
14cf11af PM |
1383 | return last; |
1384 | } | |
1385 | ||
df13102f | 1386 | #define NR_INSN_TO_PRINT 16 |
06d67d54 | 1387 | |
06d67d54 PM |
1388 | static void show_instructions(struct pt_regs *regs) |
1389 | { | |
1390 | int i; | |
a6e2c226 | 1391 | unsigned long nip = regs->nip; |
df13102f | 1392 | unsigned long pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int)); |
06d67d54 | 1393 | |
d90bb7b4 | 1394 | printk("Code: "); |
06d67d54 | 1395 | |
a6e2c226 AK |
1396 | /* |
1397 | * If we were executing with the MMU off for instructions, adjust pc | |
1398 | * rather than printing XXXXXXXX. | |
1399 | */ | |
1400 | if (!IS_ENABLED(CONFIG_BOOKE) && !(regs->msr & MSR_IR)) { | |
1401 | pc = (unsigned long)phys_to_virt(pc); | |
1402 | nip = (unsigned long)phys_to_virt(regs->nip); | |
1403 | } | |
1404 | ||
df13102f | 1405 | for (i = 0; i < NR_INSN_TO_PRINT; i++) { |
06d67d54 PM |
1406 | int instr; |
1407 | ||
00ae36de | 1408 | if (!__kernel_text_address(pc) || |
25f12ae4 | 1409 | get_kernel_nofault(instr, (const void *)pc)) { |
2ffd04de | 1410 | pr_cont("XXXXXXXX "); |
06d67d54 | 1411 | } else { |
a6e2c226 | 1412 | if (nip == pc) |
2ffd04de | 1413 | pr_cont("<%08x> ", instr); |
06d67d54 | 1414 | else |
2ffd04de | 1415 | pr_cont("%08x ", instr); |
06d67d54 PM |
1416 | } |
1417 | ||
1418 | pc += sizeof(int); | |
1419 | } | |
1420 | ||
2ffd04de | 1421 | pr_cont("\n"); |
06d67d54 PM |
1422 | } |
1423 | ||
88b0fe17 MOA |
1424 | void show_user_instructions(struct pt_regs *regs) |
1425 | { | |
1426 | unsigned long pc; | |
df13102f | 1427 | int n = NR_INSN_TO_PRINT; |
fb2d9505 CL |
1428 | struct seq_buf s; |
1429 | char buf[96]; /* enough for 8 times 9 + 2 chars */ | |
88b0fe17 | 1430 | |
df13102f | 1431 | pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int)); |
88b0fe17 | 1432 | |
fb2d9505 | 1433 | seq_buf_init(&s, buf, sizeof(buf)); |
88b0fe17 | 1434 | |
fb2d9505 CL |
1435 | while (n) { |
1436 | int i; | |
88b0fe17 | 1437 | |
fb2d9505 | 1438 | seq_buf_clear(&s); |
88b0fe17 | 1439 | |
fb2d9505 CL |
1440 | for (i = 0; i < 8 && n; i++, n--, pc += sizeof(int)) { |
1441 | int instr; | |
1442 | ||
c0ee37e8 CH |
1443 | if (copy_from_user_nofault(&instr, (void __user *)pc, |
1444 | sizeof(instr))) { | |
fb2d9505 CL |
1445 | seq_buf_printf(&s, "XXXXXXXX "); |
1446 | continue; | |
1447 | } | |
1448 | seq_buf_printf(&s, regs->nip == pc ? "<%08x> " : "%08x ", instr); | |
88b0fe17 MOA |
1449 | } |
1450 | ||
fb2d9505 CL |
1451 | if (!seq_buf_has_overflowed(&s)) |
1452 | pr_info("%s[%d]: code: %s\n", current->comm, | |
1453 | current->pid, s.buffer); | |
88b0fe17 | 1454 | } |
88b0fe17 MOA |
1455 | } |
1456 | ||
801c0b2c | 1457 | struct regbit { |
06d67d54 PM |
1458 | unsigned long bit; |
1459 | const char *name; | |
801c0b2c MN |
1460 | }; |
1461 | ||
1462 | static struct regbit msr_bits[] = { | |
3bfd0c9c AB |
1463 | #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) |
1464 | {MSR_SF, "SF"}, | |
1465 | {MSR_HV, "HV"}, | |
1466 | #endif | |
1467 | {MSR_VEC, "VEC"}, | |
1468 | {MSR_VSX, "VSX"}, | |
1469 | #ifdef CONFIG_BOOKE | |
1470 | {MSR_CE, "CE"}, | |
1471 | #endif | |
06d67d54 PM |
1472 | {MSR_EE, "EE"}, |
1473 | {MSR_PR, "PR"}, | |
1474 | {MSR_FP, "FP"}, | |
1475 | {MSR_ME, "ME"}, | |
3bfd0c9c | 1476 | #ifdef CONFIG_BOOKE |
1b98326b | 1477 | {MSR_DE, "DE"}, |
3bfd0c9c AB |
1478 | #else |
1479 | {MSR_SE, "SE"}, | |
1480 | {MSR_BE, "BE"}, | |
1481 | #endif | |
06d67d54 PM |
1482 | {MSR_IR, "IR"}, |
1483 | {MSR_DR, "DR"}, | |
3bfd0c9c AB |
1484 | {MSR_PMM, "PMM"}, |
1485 | #ifndef CONFIG_BOOKE | |
1486 | {MSR_RI, "RI"}, | |
1487 | {MSR_LE, "LE"}, | |
1488 | #endif | |
06d67d54 PM |
1489 | {0, NULL} |
1490 | }; | |
1491 | ||
801c0b2c | 1492 | static void print_bits(unsigned long val, struct regbit *bits, const char *sep) |
06d67d54 | 1493 | { |
801c0b2c | 1494 | const char *s = ""; |
06d67d54 | 1495 | |
06d67d54 PM |
1496 | for (; bits->bit; ++bits) |
1497 | if (val & bits->bit) { | |
db5ba5ae | 1498 | pr_cont("%s%s", s, bits->name); |
801c0b2c | 1499 | s = sep; |
06d67d54 | 1500 | } |
801c0b2c MN |
1501 | } |
1502 | ||
1503 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1504 | static struct regbit msr_tm_bits[] = { | |
1505 | {MSR_TS_T, "T"}, | |
1506 | {MSR_TS_S, "S"}, | |
1507 | {MSR_TM, "E"}, | |
1508 | {0, NULL} | |
1509 | }; | |
1510 | ||
1511 | static void print_tm_bits(unsigned long val) | |
1512 | { | |
1513 | /* | |
1514 | * This only prints something if at least one of the TM bit is set. | |
1515 | * Inside the TM[], the output means: | |
1516 | * E: Enabled (bit 32) | |
1517 | * S: Suspended (bit 33) | |
1518 | * T: Transactional (bit 34) | |
1519 | */ | |
1520 | if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { | |
db5ba5ae | 1521 | pr_cont(",TM["); |
801c0b2c | 1522 | print_bits(val, msr_tm_bits, ""); |
db5ba5ae | 1523 | pr_cont("]"); |
801c0b2c MN |
1524 | } |
1525 | } | |
1526 | #else | |
1527 | static void print_tm_bits(unsigned long val) {} | |
1528 | #endif | |
1529 | ||
1530 | static void print_msr_bits(unsigned long val) | |
1531 | { | |
db5ba5ae | 1532 | pr_cont("<"); |
801c0b2c MN |
1533 | print_bits(val, msr_bits, ","); |
1534 | print_tm_bits(val); | |
db5ba5ae | 1535 | pr_cont(">"); |
06d67d54 PM |
1536 | } |
1537 | ||
1538 | #ifdef CONFIG_PPC64 | |
f6f7dde3 | 1539 | #define REG "%016lx" |
06d67d54 | 1540 | #define REGS_PER_LINE 4 |
06d67d54 | 1541 | #else |
f6f7dde3 | 1542 | #define REG "%08lx" |
06d67d54 | 1543 | #define REGS_PER_LINE 8 |
06d67d54 PM |
1544 | #endif |
1545 | ||
bf13718b | 1546 | static void __show_regs(struct pt_regs *regs) |
14cf11af PM |
1547 | { |
1548 | int i, trap; | |
1549 | ||
a6036100 | 1550 | printk("NIP: "REG" LR: "REG" CTR: "REG"\n", |
06d67d54 | 1551 | regs->nip, regs->link, regs->ctr); |
182dc9c7 | 1552 | printk("REGS: %px TRAP: %04lx %s (%s)\n", |
96b644bd | 1553 | regs, regs->trap, print_tainted(), init_utsname()->release); |
a6036100 | 1554 | printk("MSR: "REG" ", regs->msr); |
801c0b2c | 1555 | print_msr_bits(regs->msr); |
f6fc73fb | 1556 | pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); |
14cf11af | 1557 | trap = TRAP(regs); |
912237ea | 1558 | if (!trap_is_syscall(regs) && cpu_has_feature(CPU_FTR_CFAR)) |
7dae865f | 1559 | pr_cont("CFAR: "REG" ", regs->orig_gpr3); |
7153d4bf XS |
1560 | if (trap == INTERRUPT_MACHINE_CHECK || |
1561 | trap == INTERRUPT_DATA_STORAGE || | |
1562 | trap == INTERRUPT_ALIGNMENT) { | |
2ec42996 | 1563 | if (IS_ENABLED(CONFIG_4xx) || IS_ENABLED(CONFIG_BOOKE)) |
4872cbd0 | 1564 | pr_cont("DEAR: "REG" ESR: "REG" ", regs->dear, regs->esr); |
2ec42996 CL |
1565 | else |
1566 | pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); | |
1567 | } | |
1568 | ||
9db8bcfd | 1569 | #ifdef CONFIG_PPC64 |
3130a7bb | 1570 | pr_cont("IRQMASK: %lx ", regs->softe); |
9db8bcfd AB |
1571 | #endif |
1572 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
6d888d1a | 1573 | if (MSR_TM_ACTIVE(regs->msr)) |
7dae865f | 1574 | pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); |
14170789 | 1575 | #endif |
14cf11af PM |
1576 | |
1577 | for (i = 0; i < 32; i++) { | |
06d67d54 | 1578 | if ((i % REGS_PER_LINE) == 0) |
7dae865f ME |
1579 | pr_cont("\nGPR%02d: ", i); |
1580 | pr_cont(REG " ", regs->gpr[i]); | |
14cf11af | 1581 | } |
7dae865f | 1582 | pr_cont("\n"); |
14cf11af PM |
1583 | /* |
1584 | * Lookup NIP late so we have the best change of getting the | |
1585 | * above info out without failing | |
1586 | */ | |
8f020c7c CL |
1587 | if (IS_ENABLED(CONFIG_KALLSYMS)) { |
1588 | printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); | |
1589 | printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); | |
1590 | } | |
bf13718b NP |
1591 | } |
1592 | ||
1593 | void show_regs(struct pt_regs *regs) | |
1594 | { | |
1595 | show_regs_print_info(KERN_DEFAULT); | |
1596 | __show_regs(regs); | |
9cb8f069 | 1597 | show_stack(current, (unsigned long *) regs->gpr[1], KERN_DEFAULT); |
06d67d54 PM |
1598 | if (!user_mode(regs)) |
1599 | show_instructions(regs); | |
14cf11af PM |
1600 | } |
1601 | ||
14cf11af PM |
1602 | void flush_thread(void) |
1603 | { | |
e0780b72 | 1604 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
5aae8a53 | 1605 | flush_ptrace_hw_breakpoint(current); |
e0780b72 | 1606 | #else /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 1607 | set_debug_reg_defaults(¤t->thread); |
e0780b72 | 1608 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
14cf11af PM |
1609 | } |
1610 | ||
425d3314 NP |
1611 | void arch_setup_new_exec(void) |
1612 | { | |
d7df77e8 AK |
1613 | |
1614 | #ifdef CONFIG_PPC_BOOK3S_64 | |
1615 | if (!radix_enabled()) | |
1616 | hash__setup_new_exec(); | |
425d3314 | 1617 | #endif |
d7df77e8 AK |
1618 | /* |
1619 | * If we exec out of a kernel thread then thread.regs will not be | |
1620 | * set. Do it now. | |
1621 | */ | |
1622 | if (!current->thread.regs) { | |
1623 | struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; | |
1624 | current->thread.regs = regs - 1; | |
1625 | } | |
d5fa30e6 AK |
1626 | |
1627 | #ifdef CONFIG_PPC_MEM_KEYS | |
1628 | current->thread.regs->amr = default_amr; | |
1629 | current->thread.regs->iamr = default_iamr; | |
1630 | #endif | |
d7df77e8 | 1631 | } |
425d3314 | 1632 | |
ec233ede | 1633 | #ifdef CONFIG_PPC64 |
71cc64a8 AS |
1634 | /** |
1635 | * Assign a TIDR (thread ID) for task @t and set it in the thread | |
1636 | * structure. For now, we only support setting TIDR for 'current' task. | |
ec233ede | 1637 | * |
71cc64a8 AS |
1638 | * Since the TID value is a truncated form of it PID, it is possible |
1639 | * (but unlikely) for 2 threads to have the same TID. In the unlikely event | |
1640 | * that 2 threads share the same TID and are waiting, one of the following | |
1641 | * cases will happen: | |
ec233ede | 1642 | * |
71cc64a8 AS |
1643 | * 1. The correct thread is running, the wrong thread is not |
1644 | * In this situation, the correct thread is woken and proceeds to pass it's | |
1645 | * condition check. | |
ec233ede | 1646 | * |
71cc64a8 AS |
1647 | * 2. Neither threads are running |
1648 | * In this situation, neither thread will be woken. When scheduled, the waiting | |
1649 | * threads will execute either a wait, which will return immediately, followed | |
1650 | * by a condition check, which will pass for the correct thread and fail | |
1651 | * for the wrong thread, or they will execute the condition check immediately. | |
ec233ede | 1652 | * |
71cc64a8 AS |
1653 | * 3. The wrong thread is running, the correct thread is not |
1654 | * The wrong thread will be woken, but will fail it's condition check and | |
1655 | * re-execute wait. The correct thread, when scheduled, will execute either | |
1656 | * it's condition check (which will pass), or wait, which returns immediately | |
1657 | * when called the first time after the thread is scheduled, followed by it's | |
1658 | * condition check (which will pass). | |
ec233ede | 1659 | * |
71cc64a8 AS |
1660 | * 4. Both threads are running |
1661 | * Both threads will be woken. The wrong thread will fail it's condition check | |
1662 | * and execute another wait, while the correct thread will pass it's condition | |
1663 | * check. | |
1664 | * | |
1665 | * @t: the task to set the thread ID for | |
ec233ede SB |
1666 | */ |
1667 | int set_thread_tidr(struct task_struct *t) | |
1668 | { | |
3449f191 | 1669 | if (!cpu_has_feature(CPU_FTR_P9_TIDR)) |
ec233ede SB |
1670 | return -EINVAL; |
1671 | ||
1672 | if (t != current) | |
1673 | return -EINVAL; | |
1674 | ||
7e4d4233 VJ |
1675 | if (t->thread.tidr) |
1676 | return 0; | |
1677 | ||
71cc64a8 | 1678 | t->thread.tidr = (u16)task_pid_nr(t); |
ec233ede SB |
1679 | mtspr(SPRN_TIDR, t->thread.tidr); |
1680 | ||
1681 | return 0; | |
1682 | } | |
b1db5513 | 1683 | EXPORT_SYMBOL_GPL(set_thread_tidr); |
ec233ede SB |
1684 | |
1685 | #endif /* CONFIG_PPC64 */ | |
1686 | ||
14cf11af | 1687 | /* |
55ccf3fe SS |
1688 | * this gets called so that we can store coprocessor state into memory and |
1689 | * copy the current task into the new thread. | |
14cf11af | 1690 | */ |
55ccf3fe | 1691 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
14cf11af | 1692 | { |
579e633e | 1693 | flush_all_to_thread(src); |
621b5060 MN |
1694 | /* |
1695 | * Flush TM state out so we can copy it. __switch_to_tm() does this | |
1696 | * flush but it removes the checkpointed state from the current CPU and | |
1697 | * transitions the CPU out of TM mode. Hence we need to call | |
1698 | * tm_recheckpoint_new_task() (on the same task) to restore the | |
1699 | * checkpointed state back and the TM mode. | |
5d176f75 CB |
1700 | * |
1701 | * Can't pass dst because it isn't ready. Doesn't matter, passing | |
1702 | * dst is only important for __switch_to() | |
621b5060 | 1703 | */ |
dc310669 | 1704 | __switch_to_tm(src, src); |
330a1eb7 | 1705 | |
55ccf3fe | 1706 | *dst = *src; |
330a1eb7 ME |
1707 | |
1708 | clear_task_ebb(dst); | |
1709 | ||
55ccf3fe | 1710 | return 0; |
14cf11af PM |
1711 | } |
1712 | ||
cec15488 ME |
1713 | static void setup_ksp_vsid(struct task_struct *p, unsigned long sp) |
1714 | { | |
387e220a | 1715 | #ifdef CONFIG_PPC_64S_HASH_MMU |
cec15488 ME |
1716 | unsigned long sp_vsid; |
1717 | unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; | |
1718 | ||
caca285e AK |
1719 | if (radix_enabled()) |
1720 | return; | |
1721 | ||
cec15488 ME |
1722 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) |
1723 | sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) | |
1724 | << SLB_VSID_SHIFT_1T; | |
1725 | else | |
1726 | sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) | |
1727 | << SLB_VSID_SHIFT; | |
1728 | sp_vsid |= SLB_VSID_KERNEL | llp; | |
1729 | p->thread.ksp_vsid = sp_vsid; | |
1730 | #endif | |
1731 | } | |
1732 | ||
14cf11af PM |
1733 | /* |
1734 | * Copy a thread.. | |
1735 | */ | |
efcac658 | 1736 | |
6eca8933 AD |
1737 | /* |
1738 | * Copy architecture-specific thread state | |
1739 | */ | |
c5febea0 | 1740 | int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) |
14cf11af | 1741 | { |
c5febea0 EB |
1742 | unsigned long clone_flags = args->flags; |
1743 | unsigned long usp = args->stack; | |
c5febea0 | 1744 | unsigned long tls = args->tls; |
14cf11af PM |
1745 | struct pt_regs *childregs, *kregs; |
1746 | extern void ret_from_fork(void); | |
7fa95f9a | 1747 | extern void ret_from_fork_scv(void); |
58254e10 AV |
1748 | extern void ret_from_kernel_thread(void); |
1749 | void (*f)(void); | |
0cec6fd1 | 1750 | unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; |
5d31a96e | 1751 | struct thread_info *ti = task_thread_info(p); |
6b424efa RB |
1752 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1753 | int i; | |
1754 | #endif | |
5d31a96e | 1755 | |
ed1cd6de | 1756 | klp_init_thread_info(p); |
14cf11af | 1757 | |
bc067736 | 1758 | /* Create initial stack frame. */ |
1223e5a2 | 1759 | sp -= STACK_USER_INT_FRAME_SIZE; |
6895dfc0 | 1760 | *(unsigned long *)(sp + STACK_INT_FRAME_MARKER) = STACK_FRAME_REGS_MARKER; |
bc067736 | 1761 | |
14cf11af | 1762 | /* Copy registers */ |
1223e5a2 | 1763 | childregs = (struct pt_regs *)(sp + STACK_INT_FRAME_REGS); |
5bd2e97c | 1764 | if (unlikely(args->fn)) { |
6eca8933 | 1765 | /* kernel thread */ |
6895dfc0 | 1766 | ((unsigned long *)sp)[0] = 0; |
58254e10 | 1767 | memset(childregs, 0, sizeof(struct pt_regs)); |
1223e5a2 | 1768 | childregs->gpr[1] = sp + STACK_USER_INT_FRAME_SIZE; |
7cedd601 | 1769 | /* function */ |
5bd2e97c EB |
1770 | if (args->fn) |
1771 | childregs->gpr[14] = ppc_function_entry((void *)args->fn); | |
58254e10 | 1772 | #ifdef CONFIG_PPC64 |
b5e2fc1c | 1773 | clear_tsk_thread_flag(p, TIF_32BIT); |
c2e480ba | 1774 | childregs->softe = IRQS_ENABLED; |
06d67d54 | 1775 | #endif |
5bd2e97c | 1776 | childregs->gpr[15] = (unsigned long)args->fn_arg; |
14cf11af | 1777 | p->thread.regs = NULL; /* no user register state */ |
138d1ce8 | 1778 | ti->flags |= _TIF_RESTOREALL; |
58254e10 | 1779 | f = ret_from_kernel_thread; |
14cf11af | 1780 | } else { |
6eca8933 | 1781 | /* user thread */ |
afa86fc4 | 1782 | struct pt_regs *regs = current_pt_regs(); |
58254e10 | 1783 | *childregs = *regs; |
ea516b11 AV |
1784 | if (usp) |
1785 | childregs->gpr[1] = usp; | |
6895dfc0 | 1786 | ((unsigned long *)sp)[0] = childregs->gpr[1]; |
14cf11af | 1787 | p->thread.regs = childregs; |
7fa95f9a NP |
1788 | /* 64s sets this in ret_from_fork */ |
1789 | if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64)) | |
1790 | childregs->gpr[3] = 0; /* Result from fork() */ | |
06d67d54 | 1791 | if (clone_flags & CLONE_SETTLS) { |
9904b005 | 1792 | if (!is_32bit_task()) |
facd04a9 | 1793 | childregs->gpr[13] = tls; |
06d67d54 | 1794 | else |
facd04a9 | 1795 | childregs->gpr[2] = tls; |
06d67d54 | 1796 | } |
58254e10 | 1797 | |
7fa95f9a NP |
1798 | if (trap_is_scv(regs)) |
1799 | f = ret_from_fork_scv; | |
1800 | else | |
1801 | f = ret_from_fork; | |
14cf11af | 1802 | } |
d272f667 | 1803 | childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX); |
14cf11af PM |
1804 | |
1805 | /* | |
1806 | * The way this works is that at some point in the future | |
1807 | * some task will call _switch to switch to the new task. | |
1808 | * That will pop off the stack frame created below and start | |
1809 | * the new task running at ret_from_fork. The new task will | |
1810 | * do some house keeping and then return from the fork or clone | |
1811 | * system call, using the stack frame created above. | |
1812 | */ | |
edbd0387 | 1813 | ((unsigned long *)sp)[STACK_FRAME_LR_SAVE] = (unsigned long)f; |
6f291a03 | 1814 | sp -= STACK_SWITCH_FRAME_SIZE; |
edbd0387 | 1815 | ((unsigned long *)sp)[0] = sp + STACK_SWITCH_FRAME_SIZE; |
6f291a03 | 1816 | kregs = (struct pt_regs *)(sp + STACK_SWITCH_FRAME_REGS); |
14cf11af | 1817 | p->thread.ksp = sp; |
6f291a03 | 1818 | |
28d170ab | 1819 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
6b424efa RB |
1820 | for (i = 0; i < nr_wp_slots(); i++) |
1821 | p->thread.ptrace_bps[i] = NULL; | |
28d170ab ON |
1822 | #endif |
1823 | ||
b6254ced | 1824 | #ifdef CONFIG_PPC_FPU_REGS |
18461960 | 1825 | p->thread.fp_save_area = NULL; |
b6254ced | 1826 | #endif |
18461960 PM |
1827 | #ifdef CONFIG_ALTIVEC |
1828 | p->thread.vr_save_area = NULL; | |
1829 | #endif | |
16132529 CL |
1830 | #if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP) |
1831 | p->thread.kuap = KUAP_NONE; | |
1832 | #endif | |
43afcf8f CL |
1833 | #if defined(CONFIG_BOOKE_OR_40x) && defined(CONFIG_PPC_KUAP) |
1834 | p->thread.pid = MMU_NO_CONTEXT; | |
1835 | #endif | |
18461960 | 1836 | |
cec15488 ME |
1837 | setup_ksp_vsid(p, sp); |
1838 | ||
efcac658 AK |
1839 | #ifdef CONFIG_PPC64 |
1840 | if (cpu_has_feature(CPU_FTR_DSCR)) { | |
1021cb26 | 1841 | p->thread.dscr_inherit = current->thread.dscr_inherit; |
db1231dc | 1842 | p->thread.dscr = mfspr(SPRN_DSCR); |
efcac658 | 1843 | } |
92779245 | 1844 | if (cpu_has_feature(CPU_FTR_HAS_PPR)) |
4c2de74c | 1845 | childregs->ppr = DEFAULT_PPR; |
ec233ede SB |
1846 | |
1847 | p->thread.tidr = 0; | |
f643fcab AK |
1848 | #endif |
1849 | /* | |
1850 | * Run with the current AMR value of the kernel | |
1851 | */ | |
1852 | #ifdef CONFIG_PPC_PKEY | |
1853 | if (mmu_has_feature(MMU_FTR_BOOK3S_KUAP)) | |
1854 | kregs->amr = AMR_KUAP_BLOCKED; | |
1855 | ||
1856 | if (mmu_has_feature(MMU_FTR_BOOK3S_KUEP)) | |
1857 | kregs->iamr = AMR_KUEP_BLOCKED; | |
efcac658 | 1858 | #endif |
7cedd601 | 1859 | kregs->nip = ppc_function_entry(f); |
14cf11af PM |
1860 | return 0; |
1861 | } | |
1862 | ||
5434ae74 NP |
1863 | void preload_new_slb_context(unsigned long start, unsigned long sp); |
1864 | ||
14cf11af PM |
1865 | /* |
1866 | * Set up a thread for executing a new program | |
1867 | */ | |
06d67d54 | 1868 | void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) |
14cf11af | 1869 | { |
90eac727 ME |
1870 | #ifdef CONFIG_PPC64 |
1871 | unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ | |
5434ae74 | 1872 | |
bfac2799 | 1873 | if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && !radix_enabled()) |
f89bd8ba | 1874 | preload_new_slb_context(start, sp); |
90eac727 ME |
1875 | #endif |
1876 | ||
8e96a87c CB |
1877 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1878 | /* | |
1879 | * Clear any transactional state, we're exec()ing. The cause is | |
1880 | * not important as there will never be a recheckpoint so it's not | |
1881 | * user visible. | |
1882 | */ | |
1883 | if (MSR_TM_SUSPENDED(mfmsr())) | |
1884 | tm_reclaim_current(0); | |
1885 | #endif | |
1886 | ||
ec6d0dde | 1887 | memset(®s->gpr[1], 0, sizeof(regs->gpr) - sizeof(regs->gpr[0])); |
14cf11af PM |
1888 | regs->ctr = 0; |
1889 | regs->link = 0; | |
1890 | regs->xer = 0; | |
1891 | regs->ccr = 0; | |
14cf11af | 1892 | regs->gpr[1] = sp; |
06d67d54 PM |
1893 | |
1894 | #ifdef CONFIG_PPC32 | |
1895 | regs->mq = 0; | |
1896 | regs->nip = start; | |
14cf11af | 1897 | regs->msr = MSR_USER; |
06d67d54 | 1898 | #else |
9904b005 | 1899 | if (!is_32bit_task()) { |
94af3abf | 1900 | unsigned long entry; |
06d67d54 | 1901 | |
94af3abf RR |
1902 | if (is_elf2_task()) { |
1903 | /* Look ma, no function descriptors! */ | |
1904 | entry = start; | |
06d67d54 | 1905 | |
94af3abf RR |
1906 | /* |
1907 | * Ulrich says: | |
1908 | * The latest iteration of the ABI requires that when | |
1909 | * calling a function (at its global entry point), | |
1910 | * the caller must ensure r12 holds the entry point | |
1911 | * address (so that the function can quickly | |
1912 | * establish addressability). | |
1913 | */ | |
1914 | regs->gpr[12] = start; | |
1915 | /* Make sure that's restored on entry to userspace. */ | |
1916 | set_thread_flag(TIF_RESTOREALL); | |
1917 | } else { | |
1918 | unsigned long toc; | |
1919 | ||
1920 | /* start is a relocated pointer to the function | |
1921 | * descriptor for the elf _start routine. The first | |
1922 | * entry in the function descriptor is the entry | |
1923 | * address of _start and the second entry is the TOC | |
1924 | * value we need to use. | |
1925 | */ | |
1926 | __get_user(entry, (unsigned long __user *)start); | |
1927 | __get_user(toc, (unsigned long __user *)start+1); | |
1928 | ||
1929 | /* Check whether the e_entry function descriptor entries | |
1930 | * need to be relocated before we can use them. | |
1931 | */ | |
1932 | if (load_addr != 0) { | |
1933 | entry += load_addr; | |
1934 | toc += load_addr; | |
1935 | } | |
1936 | regs->gpr[2] = toc; | |
06d67d54 | 1937 | } |
59dc5bfc NP |
1938 | regs_set_return_ip(regs, entry); |
1939 | regs_set_return_msr(regs, MSR_USER64); | |
d4bf9a78 | 1940 | } else { |
d4bf9a78 | 1941 | regs->gpr[2] = 0; |
59dc5bfc NP |
1942 | regs_set_return_ip(regs, start); |
1943 | regs_set_return_msr(regs, MSR_USER32); | |
06d67d54 | 1944 | } |
59dc5bfc | 1945 | |
06d67d54 | 1946 | #endif |
ce48b210 MN |
1947 | #ifdef CONFIG_VSX |
1948 | current->thread.used_vsr = 0; | |
1949 | #endif | |
5434ae74 | 1950 | current->thread.load_slb = 0; |
1195892c | 1951 | current->thread.load_fp = 0; |
b6254ced | 1952 | #ifdef CONFIG_PPC_FPU_REGS |
de79f7b9 | 1953 | memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); |
18461960 | 1954 | current->thread.fp_save_area = NULL; |
b6254ced | 1955 | #endif |
14cf11af | 1956 | #ifdef CONFIG_ALTIVEC |
de79f7b9 PM |
1957 | memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); |
1958 | current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ | |
18461960 | 1959 | current->thread.vr_save_area = NULL; |
14cf11af PM |
1960 | current->thread.vrsave = 0; |
1961 | current->thread.used_vr = 0; | |
1195892c | 1962 | current->thread.load_vec = 0; |
14cf11af PM |
1963 | #endif /* CONFIG_ALTIVEC */ |
1964 | #ifdef CONFIG_SPE | |
1965 | memset(current->thread.evr, 0, sizeof(current->thread.evr)); | |
1966 | current->thread.acc = 0; | |
1967 | current->thread.spefscr = 0; | |
1968 | current->thread.used_spe = 0; | |
1969 | #endif /* CONFIG_SPE */ | |
bc2a9408 | 1970 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
bc2a9408 MN |
1971 | current->thread.tm_tfhar = 0; |
1972 | current->thread.tm_texasr = 0; | |
1973 | current->thread.tm_tfiar = 0; | |
7f22ced4 | 1974 | current->thread.load_tm = 0; |
bc2a9408 | 1975 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
14cf11af | 1976 | } |
e1802b06 | 1977 | EXPORT_SYMBOL(start_thread); |
14cf11af PM |
1978 | |
1979 | #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ | |
1980 | | PR_FP_EXC_RES | PR_FP_EXC_INV) | |
1981 | ||
1982 | int set_fpexc_mode(struct task_struct *tsk, unsigned int val) | |
1983 | { | |
1984 | struct pt_regs *regs = tsk->thread.regs; | |
1985 | ||
1986 | /* This is a bit hairy. If we are an SPE enabled processor | |
1987 | * (have embedded fp) we store the IEEE exception enable flags in | |
1988 | * fpexc_mode. fpexc_mode is also used for setting FP exception | |
1989 | * mode (asyn, precise, disabled) for 'Classic' FP. */ | |
1990 | if (val & PR_FP_EXC_SW_ENABLE) { | |
5e14d21e | 1991 | if (cpu_has_feature(CPU_FTR_SPE)) { |
640e9225 JM |
1992 | /* |
1993 | * When the sticky exception bits are set | |
1994 | * directly by userspace, it must call prctl | |
1995 | * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE | |
1996 | * in the existing prctl settings) or | |
1997 | * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in | |
1998 | * the bits being set). <fenv.h> functions | |
1999 | * saving and restoring the whole | |
2000 | * floating-point environment need to do so | |
2001 | * anyway to restore the prctl settings from | |
2002 | * the saved environment. | |
2003 | */ | |
532ed190 | 2004 | #ifdef CONFIG_SPE |
640e9225 | 2005 | tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); |
5e14d21e KG |
2006 | tsk->thread.fpexc_mode = val & |
2007 | (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); | |
532ed190 | 2008 | #endif |
5e14d21e KG |
2009 | return 0; |
2010 | } else { | |
2011 | return -EINVAL; | |
2012 | } | |
14cf11af | 2013 | } |
06d67d54 PM |
2014 | |
2015 | /* on a CONFIG_SPE this does not hurt us. The bits that | |
2016 | * __pack_fe01 use do not overlap with bits used for | |
2017 | * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits | |
2018 | * on CONFIG_SPE implementations are reserved so writing to | |
2019 | * them does not change anything */ | |
2020 | if (val > PR_FP_EXC_PRECISE) | |
2021 | return -EINVAL; | |
2022 | tsk->thread.fpexc_mode = __pack_fe01(val); | |
59dc5bfc NP |
2023 | if (regs != NULL && (regs->msr & MSR_FP) != 0) { |
2024 | regs_set_return_msr(regs, (regs->msr & ~(MSR_FE0|MSR_FE1)) | |
2025 | | tsk->thread.fpexc_mode); | |
2026 | } | |
14cf11af PM |
2027 | return 0; |
2028 | } | |
2029 | ||
2030 | int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) | |
2031 | { | |
d208e13c | 2032 | unsigned int val = 0; |
14cf11af | 2033 | |
532ed190 | 2034 | if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) { |
640e9225 JM |
2035 | if (cpu_has_feature(CPU_FTR_SPE)) { |
2036 | /* | |
2037 | * When the sticky exception bits are set | |
2038 | * directly by userspace, it must call prctl | |
2039 | * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE | |
2040 | * in the existing prctl settings) or | |
2041 | * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in | |
2042 | * the bits being set). <fenv.h> functions | |
2043 | * saving and restoring the whole | |
2044 | * floating-point environment need to do so | |
2045 | * anyway to restore the prctl settings from | |
2046 | * the saved environment. | |
2047 | */ | |
532ed190 | 2048 | #ifdef CONFIG_SPE |
640e9225 | 2049 | tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); |
5e14d21e | 2050 | val = tsk->thread.fpexc_mode; |
532ed190 | 2051 | #endif |
640e9225 | 2052 | } else |
5e14d21e | 2053 | return -EINVAL; |
532ed190 | 2054 | } else { |
14cf11af | 2055 | val = __unpack_fe01(tsk->thread.fpexc_mode); |
532ed190 | 2056 | } |
14cf11af PM |
2057 | return put_user(val, (unsigned int __user *) adr); |
2058 | } | |
2059 | ||
fab5db97 PM |
2060 | int set_endian(struct task_struct *tsk, unsigned int val) |
2061 | { | |
2062 | struct pt_regs *regs = tsk->thread.regs; | |
2063 | ||
2064 | if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || | |
2065 | (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) | |
2066 | return -EINVAL; | |
2067 | ||
2068 | if (regs == NULL) | |
2069 | return -EINVAL; | |
2070 | ||
2071 | if (val == PR_ENDIAN_BIG) | |
59dc5bfc | 2072 | regs_set_return_msr(regs, regs->msr & ~MSR_LE); |
fab5db97 | 2073 | else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) |
59dc5bfc | 2074 | regs_set_return_msr(regs, regs->msr | MSR_LE); |
fab5db97 PM |
2075 | else |
2076 | return -EINVAL; | |
2077 | ||
2078 | return 0; | |
2079 | } | |
2080 | ||
2081 | int get_endian(struct task_struct *tsk, unsigned long adr) | |
2082 | { | |
2083 | struct pt_regs *regs = tsk->thread.regs; | |
2084 | unsigned int val; | |
2085 | ||
2086 | if (!cpu_has_feature(CPU_FTR_PPC_LE) && | |
2087 | !cpu_has_feature(CPU_FTR_REAL_LE)) | |
2088 | return -EINVAL; | |
2089 | ||
2090 | if (regs == NULL) | |
2091 | return -EINVAL; | |
2092 | ||
2093 | if (regs->msr & MSR_LE) { | |
2094 | if (cpu_has_feature(CPU_FTR_REAL_LE)) | |
2095 | val = PR_ENDIAN_LITTLE; | |
2096 | else | |
2097 | val = PR_ENDIAN_PPC_LITTLE; | |
2098 | } else | |
2099 | val = PR_ENDIAN_BIG; | |
2100 | ||
2101 | return put_user(val, (unsigned int __user *)adr); | |
2102 | } | |
2103 | ||
e9370ae1 PM |
2104 | int set_unalign_ctl(struct task_struct *tsk, unsigned int val) |
2105 | { | |
2106 | tsk->thread.align_ctl = val; | |
2107 | return 0; | |
2108 | } | |
2109 | ||
2110 | int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) | |
2111 | { | |
2112 | return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); | |
2113 | } | |
2114 | ||
bb72c481 PM |
2115 | static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, |
2116 | unsigned long nbytes) | |
2117 | { | |
2118 | unsigned long stack_page; | |
2119 | unsigned long cpu = task_cpu(p); | |
2120 | ||
a7916a1d CL |
2121 | stack_page = (unsigned long)hardirq_ctx[cpu]; |
2122 | if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) | |
2123 | return 1; | |
2124 | ||
2125 | stack_page = (unsigned long)softirq_ctx[cpu]; | |
2126 | if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) | |
2127 | return 1; | |
2128 | ||
bb72c481 PM |
2129 | return 0; |
2130 | } | |
2131 | ||
a2e36683 NP |
2132 | static inline int valid_emergency_stack(unsigned long sp, struct task_struct *p, |
2133 | unsigned long nbytes) | |
2134 | { | |
2135 | #ifdef CONFIG_PPC64 | |
2136 | unsigned long stack_page; | |
2137 | unsigned long cpu = task_cpu(p); | |
2138 | ||
0ecf6a9e ME |
2139 | if (!paca_ptrs) |
2140 | return 0; | |
2141 | ||
a2e36683 NP |
2142 | stack_page = (unsigned long)paca_ptrs[cpu]->emergency_sp - THREAD_SIZE; |
2143 | if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) | |
2144 | return 1; | |
2145 | ||
2146 | # ifdef CONFIG_PPC_BOOK3S_64 | |
2147 | stack_page = (unsigned long)paca_ptrs[cpu]->nmi_emergency_sp - THREAD_SIZE; | |
2148 | if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) | |
2149 | return 1; | |
2150 | ||
2151 | stack_page = (unsigned long)paca_ptrs[cpu]->mc_emergency_sp - THREAD_SIZE; | |
2152 | if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) | |
2153 | return 1; | |
2154 | # endif | |
2155 | #endif | |
2156 | ||
2157 | return 0; | |
2158 | } | |
2159 | ||
4cefb0f6 NP |
2160 | /* |
2161 | * validate the stack frame of a particular minimum size, used for when we are | |
2162 | * looking at a certain object in the stack beyond the minimum. | |
2163 | */ | |
2164 | int validate_sp_size(unsigned long sp, struct task_struct *p, | |
2165 | unsigned long nbytes) | |
14cf11af | 2166 | { |
0cec6fd1 | 2167 | unsigned long stack_page = (unsigned long)task_stack_page(p); |
14cf11af | 2168 | |
a7916a1d CL |
2169 | if (sp < THREAD_SIZE) |
2170 | return 0; | |
2171 | ||
2172 | if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) | |
14cf11af PM |
2173 | return 1; |
2174 | ||
a2e36683 NP |
2175 | if (valid_irq_stack(sp, p, nbytes)) |
2176 | return 1; | |
2177 | ||
2178 | return valid_emergency_stack(sp, p, nbytes); | |
14cf11af PM |
2179 | } |
2180 | ||
4cefb0f6 NP |
2181 | int validate_sp(unsigned long sp, struct task_struct *p) |
2182 | { | |
90f1b431 | 2183 | return validate_sp_size(sp, p, STACK_FRAME_MIN_SIZE); |
4cefb0f6 | 2184 | } |
2f25194d | 2185 | |
42a20f86 | 2186 | static unsigned long ___get_wchan(struct task_struct *p) |
14cf11af PM |
2187 | { |
2188 | unsigned long ip, sp; | |
2189 | int count = 0; | |
2190 | ||
14cf11af | 2191 | sp = p->thread.ksp; |
4cefb0f6 | 2192 | if (!validate_sp(sp, p)) |
14cf11af PM |
2193 | return 0; |
2194 | ||
2195 | do { | |
a1b29ba2 | 2196 | sp = READ_ONCE_NOCHECK(*(unsigned long *)sp); |
4cefb0f6 | 2197 | if (!validate_sp(sp, p) || task_is_running(p)) |
14cf11af PM |
2198 | return 0; |
2199 | if (count > 0) { | |
a1b29ba2 | 2200 | ip = READ_ONCE_NOCHECK(((unsigned long *)sp)[STACK_FRAME_LR_SAVE]); |
14cf11af PM |
2201 | if (!in_sched_functions(ip)) |
2202 | return ip; | |
2203 | } | |
2204 | } while (count++ < 16); | |
2205 | return 0; | |
2206 | } | |
06d67d54 | 2207 | |
42a20f86 | 2208 | unsigned long __get_wchan(struct task_struct *p) |
018cce33 CL |
2209 | { |
2210 | unsigned long ret; | |
2211 | ||
2212 | if (!try_get_task_stack(p)) | |
2213 | return 0; | |
2214 | ||
42a20f86 | 2215 | ret = ___get_wchan(p); |
018cce33 CL |
2216 | |
2217 | put_task_stack(p); | |
2218 | ||
2219 | return ret; | |
2220 | } | |
2221 | ||
c4d04be1 | 2222 | static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; |
06d67d54 | 2223 | |
b112fb91 DA |
2224 | void __no_sanitize_address show_stack(struct task_struct *tsk, |
2225 | unsigned long *stack, | |
2226 | const char *loglvl) | |
06d67d54 PM |
2227 | { |
2228 | unsigned long sp, ip, lr, newsp; | |
2229 | int count = 0; | |
2230 | int firstframe = 1; | |
7c1bb6bb NR |
2231 | unsigned long ret_addr; |
2232 | int ftrace_idx = 0; | |
06d67d54 | 2233 | |
06d67d54 PM |
2234 | if (tsk == NULL) |
2235 | tsk = current; | |
018cce33 CL |
2236 | |
2237 | if (!try_get_task_stack(tsk)) | |
2238 | return; | |
2239 | ||
2240 | sp = (unsigned long) stack; | |
06d67d54 PM |
2241 | if (sp == 0) { |
2242 | if (tsk == current) | |
3d13e839 | 2243 | sp = current_stack_frame(); |
06d67d54 PM |
2244 | else |
2245 | sp = tsk->thread.ksp; | |
2246 | } | |
2247 | ||
2248 | lr = 0; | |
b9677a8c | 2249 | printk("%sCall Trace:\n", loglvl); |
06d67d54 | 2250 | do { |
4cefb0f6 | 2251 | if (!validate_sp(sp, tsk)) |
018cce33 | 2252 | break; |
06d67d54 PM |
2253 | |
2254 | stack = (unsigned long *) sp; | |
2255 | newsp = stack[0]; | |
ec2b36b9 | 2256 | ip = stack[STACK_FRAME_LR_SAVE]; |
06d67d54 | 2257 | if (!firstframe || ip != lr) { |
b9677a8c DS |
2258 | printk("%s["REG"] ["REG"] %pS", |
2259 | loglvl, sp, ip, (void *)ip); | |
7c1bb6bb NR |
2260 | ret_addr = ftrace_graph_ret_addr(current, |
2261 | &ftrace_idx, ip, stack); | |
2262 | if (ret_addr != ip) | |
2263 | pr_cont(" (%pS)", (void *)ret_addr); | |
06d67d54 | 2264 | if (firstframe) |
9a1f490f ME |
2265 | pr_cont(" (unreliable)"); |
2266 | pr_cont("\n"); | |
06d67d54 PM |
2267 | } |
2268 | firstframe = 0; | |
2269 | ||
2270 | /* | |
2271 | * See if this is an exception frame. | |
c03be0a3 | 2272 | * We look for the "regs" marker in the current frame. |
6f291a03 NP |
2273 | * |
2274 | * STACK_SWITCH_FRAME_SIZE being the smallest frame that | |
2275 | * could hold a pt_regs, if that does not fit then it can't | |
2276 | * have regs. | |
06d67d54 | 2277 | */ |
4cefb0f6 | 2278 | if (validate_sp_size(sp, tsk, STACK_SWITCH_FRAME_SIZE) |
e856e336 | 2279 | && stack[STACK_INT_FRAME_MARKER_LONGS] == STACK_FRAME_REGS_MARKER) { |
06d67d54 | 2280 | struct pt_regs *regs = (struct pt_regs *) |
c03be0a3 | 2281 | (sp + STACK_INT_FRAME_REGS); |
bf13718b | 2282 | |
06d67d54 | 2283 | lr = regs->link; |
bf13718b NP |
2284 | printk("%s--- interrupt: %lx at %pS\n", |
2285 | loglvl, regs->trap, (void *)regs->nip); | |
2286 | __show_regs(regs); | |
2287 | printk("%s--- interrupt: %lx\n", | |
2288 | loglvl, regs->trap); | |
2289 | ||
06d67d54 PM |
2290 | firstframe = 1; |
2291 | } | |
2292 | ||
2293 | sp = newsp; | |
2294 | } while (count++ < kstack_depth_to_print); | |
018cce33 CL |
2295 | |
2296 | put_task_stack(tsk); | |
06d67d54 PM |
2297 | } |
2298 | ||
cb2c9b27 | 2299 | #ifdef CONFIG_PPC64 |
fe1952fc | 2300 | /* Called with hard IRQs off */ |
0e37739b | 2301 | void notrace __ppc64_runlatch_on(void) |
cb2c9b27 | 2302 | { |
fe1952fc | 2303 | struct thread_info *ti = current_thread_info(); |
cb2c9b27 | 2304 | |
d1d0d5ff NP |
2305 | if (cpu_has_feature(CPU_FTR_ARCH_206)) { |
2306 | /* | |
2307 | * Least significant bit (RUN) is the only writable bit of | |
2308 | * the CTRL register, so we can avoid mfspr. 2.06 is not the | |
2309 | * earliest ISA where this is the case, but it's convenient. | |
2310 | */ | |
2311 | mtspr(SPRN_CTRLT, CTRL_RUNLATCH); | |
2312 | } else { | |
2313 | unsigned long ctrl; | |
2314 | ||
2315 | /* | |
2316 | * Some architectures (e.g., Cell) have writable fields other | |
2317 | * than RUN, so do the read-modify-write. | |
2318 | */ | |
2319 | ctrl = mfspr(SPRN_CTRLF); | |
2320 | ctrl |= CTRL_RUNLATCH; | |
2321 | mtspr(SPRN_CTRLT, ctrl); | |
2322 | } | |
cb2c9b27 | 2323 | |
fae2e0fb | 2324 | ti->local_flags |= _TLF_RUNLATCH; |
cb2c9b27 AB |
2325 | } |
2326 | ||
fe1952fc | 2327 | /* Called with hard IRQs off */ |
0e37739b | 2328 | void notrace __ppc64_runlatch_off(void) |
cb2c9b27 | 2329 | { |
fe1952fc | 2330 | struct thread_info *ti = current_thread_info(); |
cb2c9b27 | 2331 | |
fae2e0fb | 2332 | ti->local_flags &= ~_TLF_RUNLATCH; |
cb2c9b27 | 2333 | |
d1d0d5ff NP |
2334 | if (cpu_has_feature(CPU_FTR_ARCH_206)) { |
2335 | mtspr(SPRN_CTRLT, 0); | |
2336 | } else { | |
2337 | unsigned long ctrl; | |
2338 | ||
2339 | ctrl = mfspr(SPRN_CTRLF); | |
2340 | ctrl &= ~CTRL_RUNLATCH; | |
2341 | mtspr(SPRN_CTRLT, ctrl); | |
2342 | } | |
cb2c9b27 | 2343 | } |
fe1952fc | 2344 | #endif /* CONFIG_PPC64 */ |
f6a61680 | 2345 | |
d839088c AB |
2346 | unsigned long arch_align_stack(unsigned long sp) |
2347 | { | |
2348 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
8032bf12 | 2349 | sp -= get_random_u32_below(PAGE_SIZE); |
d839088c AB |
2350 | return sp & ~0xf; |
2351 | } |