Commit | Line | Data |
---|---|---|
14cf11af | 1 | /* |
14cf11af PM |
2 | * Derived from "arch/i386/kernel/process.c" |
3 | * Copyright (C) 1995 Linus Torvalds | |
4 | * | |
5 | * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and | |
6 | * Paul Mackerras (paulus@cs.anu.edu.au) | |
7 | * | |
8 | * PowerPC version | |
9 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | */ | |
16 | ||
14cf11af PM |
17 | #include <linux/errno.h> |
18 | #include <linux/sched.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/smp.h> | |
14cf11af PM |
22 | #include <linux/stddef.h> |
23 | #include <linux/unistd.h> | |
24 | #include <linux/ptrace.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/user.h> | |
27 | #include <linux/elf.h> | |
14cf11af PM |
28 | #include <linux/prctl.h> |
29 | #include <linux/init_task.h> | |
4b16f8e2 | 30 | #include <linux/export.h> |
14cf11af PM |
31 | #include <linux/kallsyms.h> |
32 | #include <linux/mqueue.h> | |
33 | #include <linux/hardirq.h> | |
06d67d54 | 34 | #include <linux/utsname.h> |
6794c782 | 35 | #include <linux/ftrace.h> |
79741dd3 | 36 | #include <linux/kernel_stat.h> |
d839088c AB |
37 | #include <linux/personality.h> |
38 | #include <linux/random.h> | |
5aae8a53 | 39 | #include <linux/hw_breakpoint.h> |
7b051f66 | 40 | #include <linux/uaccess.h> |
7f92bc56 | 41 | #include <linux/elf-randomize.h> |
14cf11af PM |
42 | |
43 | #include <asm/pgtable.h> | |
14cf11af PM |
44 | #include <asm/io.h> |
45 | #include <asm/processor.h> | |
46 | #include <asm/mmu.h> | |
47 | #include <asm/prom.h> | |
76032de8 | 48 | #include <asm/machdep.h> |
c6622f63 | 49 | #include <asm/time.h> |
ae3a197e | 50 | #include <asm/runlatch.h> |
a7f31841 | 51 | #include <asm/syscalls.h> |
ae3a197e | 52 | #include <asm/switch_to.h> |
fb09692e | 53 | #include <asm/tm.h> |
ae3a197e | 54 | #include <asm/debug.h> |
06d67d54 PM |
55 | #ifdef CONFIG_PPC64 |
56 | #include <asm/firmware.h> | |
06d67d54 | 57 | #endif |
7cedd601 | 58 | #include <asm/code-patching.h> |
7f92bc56 | 59 | #include <asm/exec.h> |
5d31a96e | 60 | #include <asm/livepatch.h> |
b92a226e | 61 | #include <asm/cpu_has_feature.h> |
0545d543 | 62 | #include <asm/asm-prototypes.h> |
5d31a96e | 63 | |
d6a61bfc LM |
64 | #include <linux/kprobes.h> |
65 | #include <linux/kdebug.h> | |
14cf11af | 66 | |
8b3c34cf MN |
67 | /* Transactional Memory debug */ |
68 | #ifdef TM_DEBUG_SW | |
69 | #define TM_DEBUG(x...) printk(KERN_INFO x) | |
70 | #else | |
71 | #define TM_DEBUG(x...) do { } while(0) | |
72 | #endif | |
73 | ||
14cf11af PM |
74 | extern unsigned long _get_SP(void); |
75 | ||
d31626f7 | 76 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
b86fd2bd | 77 | static void check_if_tm_restore_required(struct task_struct *tsk) |
d31626f7 PM |
78 | { |
79 | /* | |
80 | * If we are saving the current thread's registers, and the | |
81 | * thread is in a transactional state, set the TIF_RESTORE_TM | |
82 | * bit so that we know to restore the registers before | |
83 | * returning to userspace. | |
84 | */ | |
85 | if (tsk == current && tsk->thread.regs && | |
86 | MSR_TM_ACTIVE(tsk->thread.regs->msr) && | |
87 | !test_thread_flag(TIF_RESTORE_TM)) { | |
829023df | 88 | tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; |
d31626f7 PM |
89 | set_thread_flag(TIF_RESTORE_TM); |
90 | } | |
d31626f7 | 91 | } |
dc16b553 CB |
92 | |
93 | static inline bool msr_tm_active(unsigned long msr) | |
94 | { | |
95 | return MSR_TM_ACTIVE(msr); | |
96 | } | |
d31626f7 | 97 | #else |
dc16b553 | 98 | static inline bool msr_tm_active(unsigned long msr) { return false; } |
b86fd2bd | 99 | static inline void check_if_tm_restore_required(struct task_struct *tsk) { } |
d31626f7 PM |
100 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
101 | ||
3eb5d588 AB |
102 | bool strict_msr_control; |
103 | EXPORT_SYMBOL(strict_msr_control); | |
104 | ||
105 | static int __init enable_strict_msr_control(char *str) | |
106 | { | |
107 | strict_msr_control = true; | |
108 | pr_info("Enabling strict facility control\n"); | |
109 | ||
110 | return 0; | |
111 | } | |
112 | early_param("ppc_strict_facility_enable", enable_strict_msr_control); | |
113 | ||
3cee070a | 114 | unsigned long msr_check_and_set(unsigned long bits) |
98da581e | 115 | { |
a0e72cf1 AB |
116 | unsigned long oldmsr = mfmsr(); |
117 | unsigned long newmsr; | |
98da581e | 118 | |
a0e72cf1 | 119 | newmsr = oldmsr | bits; |
98da581e | 120 | |
98da581e | 121 | #ifdef CONFIG_VSX |
a0e72cf1 | 122 | if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) |
98da581e AB |
123 | newmsr |= MSR_VSX; |
124 | #endif | |
a0e72cf1 | 125 | |
98da581e AB |
126 | if (oldmsr != newmsr) |
127 | mtmsr_isync(newmsr); | |
3cee070a CB |
128 | |
129 | return newmsr; | |
a0e72cf1 | 130 | } |
98da581e | 131 | |
3eb5d588 | 132 | void __msr_check_and_clear(unsigned long bits) |
a0e72cf1 AB |
133 | { |
134 | unsigned long oldmsr = mfmsr(); | |
135 | unsigned long newmsr; | |
136 | ||
137 | newmsr = oldmsr & ~bits; | |
138 | ||
139 | #ifdef CONFIG_VSX | |
140 | if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) | |
141 | newmsr &= ~MSR_VSX; | |
142 | #endif | |
143 | ||
144 | if (oldmsr != newmsr) | |
145 | mtmsr_isync(newmsr); | |
146 | } | |
3eb5d588 | 147 | EXPORT_SYMBOL(__msr_check_and_clear); |
a0e72cf1 AB |
148 | |
149 | #ifdef CONFIG_PPC_FPU | |
8792468d CB |
150 | void __giveup_fpu(struct task_struct *tsk) |
151 | { | |
8eb98037 AB |
152 | unsigned long msr; |
153 | ||
8792468d | 154 | save_fpu(tsk); |
8eb98037 AB |
155 | msr = tsk->thread.regs->msr; |
156 | msr &= ~MSR_FP; | |
8792468d CB |
157 | #ifdef CONFIG_VSX |
158 | if (cpu_has_feature(CPU_FTR_VSX)) | |
8eb98037 | 159 | msr &= ~MSR_VSX; |
8792468d | 160 | #endif |
8eb98037 | 161 | tsk->thread.regs->msr = msr; |
8792468d CB |
162 | } |
163 | ||
a0e72cf1 AB |
164 | void giveup_fpu(struct task_struct *tsk) |
165 | { | |
166 | check_if_tm_restore_required(tsk); | |
167 | ||
168 | msr_check_and_set(MSR_FP); | |
98da581e | 169 | __giveup_fpu(tsk); |
a0e72cf1 | 170 | msr_check_and_clear(MSR_FP); |
98da581e AB |
171 | } |
172 | EXPORT_SYMBOL(giveup_fpu); | |
173 | ||
14cf11af PM |
174 | /* |
175 | * Make sure the floating-point register state in the | |
176 | * the thread_struct is up to date for task tsk. | |
177 | */ | |
178 | void flush_fp_to_thread(struct task_struct *tsk) | |
179 | { | |
180 | if (tsk->thread.regs) { | |
181 | /* | |
182 | * We need to disable preemption here because if we didn't, | |
183 | * another process could get scheduled after the regs->msr | |
184 | * test but before we have finished saving the FP registers | |
185 | * to the thread_struct. That process could take over the | |
186 | * FPU, and then when we get scheduled again we would store | |
187 | * bogus values for the remaining FP registers. | |
188 | */ | |
189 | preempt_disable(); | |
190 | if (tsk->thread.regs->msr & MSR_FP) { | |
14cf11af PM |
191 | /* |
192 | * This should only ever be called for current or | |
193 | * for a stopped child process. Since we save away | |
af1bbc3d | 194 | * the FP register state on context switch, |
14cf11af PM |
195 | * there is something wrong if a stopped child appears |
196 | * to still have its FP state in the CPU registers. | |
197 | */ | |
198 | BUG_ON(tsk != current); | |
b86fd2bd | 199 | giveup_fpu(tsk); |
14cf11af PM |
200 | } |
201 | preempt_enable(); | |
202 | } | |
203 | } | |
de56a948 | 204 | EXPORT_SYMBOL_GPL(flush_fp_to_thread); |
14cf11af PM |
205 | |
206 | void enable_kernel_fp(void) | |
207 | { | |
e909fb83 CB |
208 | unsigned long cpumsr; |
209 | ||
14cf11af PM |
210 | WARN_ON(preemptible()); |
211 | ||
e909fb83 | 212 | cpumsr = msr_check_and_set(MSR_FP); |
611b0e5c | 213 | |
d64d02ce AB |
214 | if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { |
215 | check_if_tm_restore_required(current); | |
e909fb83 CB |
216 | /* |
217 | * If a thread has already been reclaimed then the | |
218 | * checkpointed registers are on the CPU but have definitely | |
219 | * been saved by the reclaim code. Don't need to and *cannot* | |
220 | * giveup as this would save to the 'live' structure not the | |
221 | * checkpointed structure. | |
222 | */ | |
223 | if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr)) | |
224 | return; | |
a0e72cf1 | 225 | __giveup_fpu(current); |
d64d02ce | 226 | } |
14cf11af PM |
227 | } |
228 | EXPORT_SYMBOL(enable_kernel_fp); | |
70fe3d98 CB |
229 | |
230 | static int restore_fp(struct task_struct *tsk) { | |
dc16b553 | 231 | if (tsk->thread.load_fp || msr_tm_active(tsk->thread.regs->msr)) { |
70fe3d98 CB |
232 | load_fp_state(¤t->thread.fp_state); |
233 | current->thread.load_fp++; | |
234 | return 1; | |
235 | } | |
236 | return 0; | |
237 | } | |
238 | #else | |
239 | static int restore_fp(struct task_struct *tsk) { return 0; } | |
d1e1cf2e | 240 | #endif /* CONFIG_PPC_FPU */ |
14cf11af | 241 | |
14cf11af | 242 | #ifdef CONFIG_ALTIVEC |
70fe3d98 CB |
243 | #define loadvec(thr) ((thr).load_vec) |
244 | ||
6f515d84 CB |
245 | static void __giveup_altivec(struct task_struct *tsk) |
246 | { | |
8eb98037 AB |
247 | unsigned long msr; |
248 | ||
6f515d84 | 249 | save_altivec(tsk); |
8eb98037 AB |
250 | msr = tsk->thread.regs->msr; |
251 | msr &= ~MSR_VEC; | |
6f515d84 CB |
252 | #ifdef CONFIG_VSX |
253 | if (cpu_has_feature(CPU_FTR_VSX)) | |
8eb98037 | 254 | msr &= ~MSR_VSX; |
6f515d84 | 255 | #endif |
8eb98037 | 256 | tsk->thread.regs->msr = msr; |
6f515d84 CB |
257 | } |
258 | ||
98da581e AB |
259 | void giveup_altivec(struct task_struct *tsk) |
260 | { | |
98da581e AB |
261 | check_if_tm_restore_required(tsk); |
262 | ||
a0e72cf1 | 263 | msr_check_and_set(MSR_VEC); |
98da581e | 264 | __giveup_altivec(tsk); |
a0e72cf1 | 265 | msr_check_and_clear(MSR_VEC); |
98da581e AB |
266 | } |
267 | EXPORT_SYMBOL(giveup_altivec); | |
268 | ||
14cf11af PM |
269 | void enable_kernel_altivec(void) |
270 | { | |
e909fb83 CB |
271 | unsigned long cpumsr; |
272 | ||
14cf11af PM |
273 | WARN_ON(preemptible()); |
274 | ||
e909fb83 | 275 | cpumsr = msr_check_and_set(MSR_VEC); |
611b0e5c | 276 | |
d64d02ce AB |
277 | if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { |
278 | check_if_tm_restore_required(current); | |
e909fb83 CB |
279 | /* |
280 | * If a thread has already been reclaimed then the | |
281 | * checkpointed registers are on the CPU but have definitely | |
282 | * been saved by the reclaim code. Don't need to and *cannot* | |
283 | * giveup as this would save to the 'live' structure not the | |
284 | * checkpointed structure. | |
285 | */ | |
286 | if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr)) | |
287 | return; | |
a0e72cf1 | 288 | __giveup_altivec(current); |
d64d02ce | 289 | } |
14cf11af PM |
290 | } |
291 | EXPORT_SYMBOL(enable_kernel_altivec); | |
292 | ||
293 | /* | |
294 | * Make sure the VMX/Altivec register state in the | |
295 | * the thread_struct is up to date for task tsk. | |
296 | */ | |
297 | void flush_altivec_to_thread(struct task_struct *tsk) | |
298 | { | |
299 | if (tsk->thread.regs) { | |
300 | preempt_disable(); | |
301 | if (tsk->thread.regs->msr & MSR_VEC) { | |
14cf11af | 302 | BUG_ON(tsk != current); |
b86fd2bd | 303 | giveup_altivec(tsk); |
14cf11af PM |
304 | } |
305 | preempt_enable(); | |
306 | } | |
307 | } | |
de56a948 | 308 | EXPORT_SYMBOL_GPL(flush_altivec_to_thread); |
70fe3d98 CB |
309 | |
310 | static int restore_altivec(struct task_struct *tsk) | |
311 | { | |
dc16b553 CB |
312 | if (cpu_has_feature(CPU_FTR_ALTIVEC) && |
313 | (tsk->thread.load_vec || msr_tm_active(tsk->thread.regs->msr))) { | |
70fe3d98 CB |
314 | load_vr_state(&tsk->thread.vr_state); |
315 | tsk->thread.used_vr = 1; | |
316 | tsk->thread.load_vec++; | |
317 | ||
318 | return 1; | |
319 | } | |
320 | return 0; | |
321 | } | |
322 | #else | |
323 | #define loadvec(thr) 0 | |
324 | static inline int restore_altivec(struct task_struct *tsk) { return 0; } | |
14cf11af PM |
325 | #endif /* CONFIG_ALTIVEC */ |
326 | ||
ce48b210 | 327 | #ifdef CONFIG_VSX |
bf6a4d5b | 328 | static void __giveup_vsx(struct task_struct *tsk) |
a7d623d4 | 329 | { |
a7d623d4 AB |
330 | if (tsk->thread.regs->msr & MSR_FP) |
331 | __giveup_fpu(tsk); | |
332 | if (tsk->thread.regs->msr & MSR_VEC) | |
333 | __giveup_altivec(tsk); | |
bf6a4d5b CB |
334 | tsk->thread.regs->msr &= ~MSR_VSX; |
335 | } | |
336 | ||
337 | static void giveup_vsx(struct task_struct *tsk) | |
338 | { | |
339 | check_if_tm_restore_required(tsk); | |
340 | ||
341 | msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); | |
a7d623d4 | 342 | __giveup_vsx(tsk); |
a0e72cf1 | 343 | msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); |
a7d623d4 | 344 | } |
bf6a4d5b CB |
345 | |
346 | static void save_vsx(struct task_struct *tsk) | |
347 | { | |
348 | if (tsk->thread.regs->msr & MSR_FP) | |
349 | save_fpu(tsk); | |
350 | if (tsk->thread.regs->msr & MSR_VEC) | |
351 | save_altivec(tsk); | |
352 | } | |
a7d623d4 | 353 | |
ce48b210 MN |
354 | void enable_kernel_vsx(void) |
355 | { | |
e909fb83 CB |
356 | unsigned long cpumsr; |
357 | ||
ce48b210 MN |
358 | WARN_ON(preemptible()); |
359 | ||
e909fb83 | 360 | cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); |
611b0e5c | 361 | |
a0e72cf1 | 362 | if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) { |
d64d02ce | 363 | check_if_tm_restore_required(current); |
e909fb83 CB |
364 | /* |
365 | * If a thread has already been reclaimed then the | |
366 | * checkpointed registers are on the CPU but have definitely | |
367 | * been saved by the reclaim code. Don't need to and *cannot* | |
368 | * giveup as this would save to the 'live' structure not the | |
369 | * checkpointed structure. | |
370 | */ | |
371 | if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr)) | |
372 | return; | |
a0e72cf1 AB |
373 | if (current->thread.regs->msr & MSR_FP) |
374 | __giveup_fpu(current); | |
375 | if (current->thread.regs->msr & MSR_VEC) | |
376 | __giveup_altivec(current); | |
377 | __giveup_vsx(current); | |
611b0e5c | 378 | } |
ce48b210 MN |
379 | } |
380 | EXPORT_SYMBOL(enable_kernel_vsx); | |
ce48b210 MN |
381 | |
382 | void flush_vsx_to_thread(struct task_struct *tsk) | |
383 | { | |
384 | if (tsk->thread.regs) { | |
385 | preempt_disable(); | |
386 | if (tsk->thread.regs->msr & MSR_VSX) { | |
ce48b210 | 387 | BUG_ON(tsk != current); |
ce48b210 MN |
388 | giveup_vsx(tsk); |
389 | } | |
390 | preempt_enable(); | |
391 | } | |
392 | } | |
de56a948 | 393 | EXPORT_SYMBOL_GPL(flush_vsx_to_thread); |
70fe3d98 CB |
394 | |
395 | static int restore_vsx(struct task_struct *tsk) | |
396 | { | |
397 | if (cpu_has_feature(CPU_FTR_VSX)) { | |
398 | tsk->thread.used_vsr = 1; | |
399 | return 1; | |
400 | } | |
401 | ||
402 | return 0; | |
403 | } | |
404 | #else | |
405 | static inline int restore_vsx(struct task_struct *tsk) { return 0; } | |
bf6a4d5b | 406 | static inline void save_vsx(struct task_struct *tsk) { } |
ce48b210 MN |
407 | #endif /* CONFIG_VSX */ |
408 | ||
14cf11af | 409 | #ifdef CONFIG_SPE |
98da581e AB |
410 | void giveup_spe(struct task_struct *tsk) |
411 | { | |
98da581e AB |
412 | check_if_tm_restore_required(tsk); |
413 | ||
a0e72cf1 | 414 | msr_check_and_set(MSR_SPE); |
98da581e | 415 | __giveup_spe(tsk); |
a0e72cf1 | 416 | msr_check_and_clear(MSR_SPE); |
98da581e AB |
417 | } |
418 | EXPORT_SYMBOL(giveup_spe); | |
14cf11af PM |
419 | |
420 | void enable_kernel_spe(void) | |
421 | { | |
422 | WARN_ON(preemptible()); | |
423 | ||
a0e72cf1 | 424 | msr_check_and_set(MSR_SPE); |
611b0e5c | 425 | |
d64d02ce AB |
426 | if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { |
427 | check_if_tm_restore_required(current); | |
a0e72cf1 | 428 | __giveup_spe(current); |
d64d02ce | 429 | } |
14cf11af PM |
430 | } |
431 | EXPORT_SYMBOL(enable_kernel_spe); | |
432 | ||
433 | void flush_spe_to_thread(struct task_struct *tsk) | |
434 | { | |
435 | if (tsk->thread.regs) { | |
436 | preempt_disable(); | |
437 | if (tsk->thread.regs->msr & MSR_SPE) { | |
14cf11af | 438 | BUG_ON(tsk != current); |
685659ee | 439 | tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); |
0ee6c15e | 440 | giveup_spe(tsk); |
14cf11af PM |
441 | } |
442 | preempt_enable(); | |
443 | } | |
444 | } | |
14cf11af PM |
445 | #endif /* CONFIG_SPE */ |
446 | ||
c2085059 AB |
447 | static unsigned long msr_all_available; |
448 | ||
449 | static int __init init_msr_all_available(void) | |
450 | { | |
451 | #ifdef CONFIG_PPC_FPU | |
452 | msr_all_available |= MSR_FP; | |
453 | #endif | |
454 | #ifdef CONFIG_ALTIVEC | |
455 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) | |
456 | msr_all_available |= MSR_VEC; | |
457 | #endif | |
458 | #ifdef CONFIG_VSX | |
459 | if (cpu_has_feature(CPU_FTR_VSX)) | |
460 | msr_all_available |= MSR_VSX; | |
461 | #endif | |
462 | #ifdef CONFIG_SPE | |
463 | if (cpu_has_feature(CPU_FTR_SPE)) | |
464 | msr_all_available |= MSR_SPE; | |
465 | #endif | |
466 | ||
467 | return 0; | |
468 | } | |
469 | early_initcall(init_msr_all_available); | |
470 | ||
471 | void giveup_all(struct task_struct *tsk) | |
472 | { | |
473 | unsigned long usermsr; | |
474 | ||
475 | if (!tsk->thread.regs) | |
476 | return; | |
477 | ||
478 | usermsr = tsk->thread.regs->msr; | |
479 | ||
480 | if ((usermsr & msr_all_available) == 0) | |
481 | return; | |
482 | ||
483 | msr_check_and_set(msr_all_available); | |
b0f16b46 | 484 | check_if_tm_restore_required(tsk); |
c2085059 AB |
485 | |
486 | #ifdef CONFIG_PPC_FPU | |
487 | if (usermsr & MSR_FP) | |
488 | __giveup_fpu(tsk); | |
489 | #endif | |
490 | #ifdef CONFIG_ALTIVEC | |
491 | if (usermsr & MSR_VEC) | |
492 | __giveup_altivec(tsk); | |
493 | #endif | |
494 | #ifdef CONFIG_VSX | |
495 | if (usermsr & MSR_VSX) | |
496 | __giveup_vsx(tsk); | |
497 | #endif | |
498 | #ifdef CONFIG_SPE | |
499 | if (usermsr & MSR_SPE) | |
500 | __giveup_spe(tsk); | |
501 | #endif | |
502 | ||
503 | msr_check_and_clear(msr_all_available); | |
504 | } | |
505 | EXPORT_SYMBOL(giveup_all); | |
506 | ||
70fe3d98 CB |
507 | void restore_math(struct pt_regs *regs) |
508 | { | |
509 | unsigned long msr; | |
510 | ||
dc16b553 CB |
511 | if (!msr_tm_active(regs->msr) && |
512 | !current->thread.load_fp && !loadvec(current->thread)) | |
70fe3d98 CB |
513 | return; |
514 | ||
515 | msr = regs->msr; | |
516 | msr_check_and_set(msr_all_available); | |
517 | ||
518 | /* | |
519 | * Only reload if the bit is not set in the user MSR, the bit BEING set | |
520 | * indicates that the registers are hot | |
521 | */ | |
522 | if ((!(msr & MSR_FP)) && restore_fp(current)) | |
523 | msr |= MSR_FP | current->thread.fpexc_mode; | |
524 | ||
525 | if ((!(msr & MSR_VEC)) && restore_altivec(current)) | |
526 | msr |= MSR_VEC; | |
527 | ||
528 | if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) && | |
529 | restore_vsx(current)) { | |
530 | msr |= MSR_VSX; | |
531 | } | |
532 | ||
533 | msr_check_and_clear(msr_all_available); | |
534 | ||
535 | regs->msr = msr; | |
536 | } | |
537 | ||
de2a20aa CB |
538 | void save_all(struct task_struct *tsk) |
539 | { | |
540 | unsigned long usermsr; | |
541 | ||
542 | if (!tsk->thread.regs) | |
543 | return; | |
544 | ||
545 | usermsr = tsk->thread.regs->msr; | |
546 | ||
547 | if ((usermsr & msr_all_available) == 0) | |
548 | return; | |
549 | ||
550 | msr_check_and_set(msr_all_available); | |
551 | ||
bf6a4d5b CB |
552 | /* |
553 | * Saving the way the register space is in hardware, save_vsx boils | |
554 | * down to a save_fpu() and save_altivec() | |
555 | */ | |
556 | if (usermsr & MSR_VSX) { | |
557 | save_vsx(tsk); | |
558 | } else { | |
559 | if (usermsr & MSR_FP) | |
560 | save_fpu(tsk); | |
561 | ||
562 | if (usermsr & MSR_VEC) | |
563 | save_altivec(tsk); | |
564 | } | |
de2a20aa CB |
565 | |
566 | if (usermsr & MSR_SPE) | |
567 | __giveup_spe(tsk); | |
568 | ||
569 | msr_check_and_clear(msr_all_available); | |
570 | } | |
571 | ||
579e633e AB |
572 | void flush_all_to_thread(struct task_struct *tsk) |
573 | { | |
574 | if (tsk->thread.regs) { | |
575 | preempt_disable(); | |
576 | BUG_ON(tsk != current); | |
de2a20aa | 577 | save_all(tsk); |
579e633e AB |
578 | |
579 | #ifdef CONFIG_SPE | |
580 | if (tsk->thread.regs->msr & MSR_SPE) | |
581 | tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); | |
582 | #endif | |
583 | ||
584 | preempt_enable(); | |
585 | } | |
586 | } | |
587 | EXPORT_SYMBOL(flush_all_to_thread); | |
588 | ||
3bffb652 DK |
589 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
590 | void do_send_trap(struct pt_regs *regs, unsigned long address, | |
591 | unsigned long error_code, int signal_code, int breakpt) | |
592 | { | |
593 | siginfo_t info; | |
594 | ||
41ab5266 | 595 | current->thread.trap_nr = signal_code; |
3bffb652 DK |
596 | if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, |
597 | 11, SIGSEGV) == NOTIFY_STOP) | |
598 | return; | |
599 | ||
600 | /* Deliver the signal to userspace */ | |
601 | info.si_signo = SIGTRAP; | |
602 | info.si_errno = breakpt; /* breakpoint or watchpoint id */ | |
603 | info.si_code = signal_code; | |
604 | info.si_addr = (void __user *)address; | |
605 | force_sig_info(SIGTRAP, &info, current); | |
606 | } | |
607 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ | |
9422de3e | 608 | void do_break (struct pt_regs *regs, unsigned long address, |
d6a61bfc LM |
609 | unsigned long error_code) |
610 | { | |
611 | siginfo_t info; | |
612 | ||
41ab5266 | 613 | current->thread.trap_nr = TRAP_HWBKPT; |
d6a61bfc LM |
614 | if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, |
615 | 11, SIGSEGV) == NOTIFY_STOP) | |
616 | return; | |
617 | ||
9422de3e | 618 | if (debugger_break_match(regs)) |
d6a61bfc LM |
619 | return; |
620 | ||
9422de3e MN |
621 | /* Clear the breakpoint */ |
622 | hw_breakpoint_disable(); | |
d6a61bfc LM |
623 | |
624 | /* Deliver the signal to userspace */ | |
625 | info.si_signo = SIGTRAP; | |
626 | info.si_errno = 0; | |
627 | info.si_code = TRAP_HWBKPT; | |
628 | info.si_addr = (void __user *)address; | |
629 | force_sig_info(SIGTRAP, &info, current); | |
630 | } | |
3bffb652 | 631 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
d6a61bfc | 632 | |
9422de3e | 633 | static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); |
a2ceff5e | 634 | |
3bffb652 DK |
635 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
636 | /* | |
637 | * Set the debug registers back to their default "safe" values. | |
638 | */ | |
639 | static void set_debug_reg_defaults(struct thread_struct *thread) | |
640 | { | |
51ae8d4a | 641 | thread->debug.iac1 = thread->debug.iac2 = 0; |
3bffb652 | 642 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
51ae8d4a | 643 | thread->debug.iac3 = thread->debug.iac4 = 0; |
3bffb652 | 644 | #endif |
51ae8d4a | 645 | thread->debug.dac1 = thread->debug.dac2 = 0; |
3bffb652 | 646 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
51ae8d4a | 647 | thread->debug.dvc1 = thread->debug.dvc2 = 0; |
3bffb652 | 648 | #endif |
51ae8d4a | 649 | thread->debug.dbcr0 = 0; |
3bffb652 DK |
650 | #ifdef CONFIG_BOOKE |
651 | /* | |
652 | * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) | |
653 | */ | |
51ae8d4a | 654 | thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | |
3bffb652 DK |
655 | DBCR1_IAC3US | DBCR1_IAC4US; |
656 | /* | |
657 | * Force Data Address Compare User/Supervisor bits to be User-only | |
658 | * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. | |
659 | */ | |
51ae8d4a | 660 | thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; |
3bffb652 | 661 | #else |
51ae8d4a | 662 | thread->debug.dbcr1 = 0; |
3bffb652 DK |
663 | #endif |
664 | } | |
665 | ||
f5f97210 | 666 | static void prime_debug_regs(struct debug_reg *debug) |
3bffb652 | 667 | { |
6cecf76b SW |
668 | /* |
669 | * We could have inherited MSR_DE from userspace, since | |
670 | * it doesn't get cleared on exception entry. Make sure | |
671 | * MSR_DE is clear before we enable any debug events. | |
672 | */ | |
673 | mtmsr(mfmsr() & ~MSR_DE); | |
674 | ||
f5f97210 SW |
675 | mtspr(SPRN_IAC1, debug->iac1); |
676 | mtspr(SPRN_IAC2, debug->iac2); | |
3bffb652 | 677 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
f5f97210 SW |
678 | mtspr(SPRN_IAC3, debug->iac3); |
679 | mtspr(SPRN_IAC4, debug->iac4); | |
3bffb652 | 680 | #endif |
f5f97210 SW |
681 | mtspr(SPRN_DAC1, debug->dac1); |
682 | mtspr(SPRN_DAC2, debug->dac2); | |
3bffb652 | 683 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
f5f97210 SW |
684 | mtspr(SPRN_DVC1, debug->dvc1); |
685 | mtspr(SPRN_DVC2, debug->dvc2); | |
3bffb652 | 686 | #endif |
f5f97210 SW |
687 | mtspr(SPRN_DBCR0, debug->dbcr0); |
688 | mtspr(SPRN_DBCR1, debug->dbcr1); | |
3bffb652 | 689 | #ifdef CONFIG_BOOKE |
f5f97210 | 690 | mtspr(SPRN_DBCR2, debug->dbcr2); |
3bffb652 DK |
691 | #endif |
692 | } | |
693 | /* | |
694 | * Unless neither the old or new thread are making use of the | |
695 | * debug registers, set the debug registers from the values | |
696 | * stored in the new thread. | |
697 | */ | |
f5f97210 | 698 | void switch_booke_debug_regs(struct debug_reg *new_debug) |
3bffb652 | 699 | { |
51ae8d4a | 700 | if ((current->thread.debug.dbcr0 & DBCR0_IDM) |
f5f97210 SW |
701 | || (new_debug->dbcr0 & DBCR0_IDM)) |
702 | prime_debug_regs(new_debug); | |
3bffb652 | 703 | } |
3743c9b8 | 704 | EXPORT_SYMBOL_GPL(switch_booke_debug_regs); |
3bffb652 | 705 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ |
e0780b72 | 706 | #ifndef CONFIG_HAVE_HW_BREAKPOINT |
3bffb652 DK |
707 | static void set_debug_reg_defaults(struct thread_struct *thread) |
708 | { | |
9422de3e MN |
709 | thread->hw_brk.address = 0; |
710 | thread->hw_brk.type = 0; | |
b9818c33 | 711 | set_breakpoint(&thread->hw_brk); |
3bffb652 | 712 | } |
e0780b72 | 713 | #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 DK |
714 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
715 | ||
172ae2e7 | 716 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
9422de3e MN |
717 | static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) |
718 | { | |
d6a61bfc | 719 | mtspr(SPRN_DAC1, dabr); |
221c185d DK |
720 | #ifdef CONFIG_PPC_47x |
721 | isync(); | |
722 | #endif | |
9422de3e MN |
723 | return 0; |
724 | } | |
c6c9eace | 725 | #elif defined(CONFIG_PPC_BOOK3S) |
9422de3e MN |
726 | static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) |
727 | { | |
c6c9eace | 728 | mtspr(SPRN_DABR, dabr); |
82a9f16a MN |
729 | if (cpu_has_feature(CPU_FTR_DABRX)) |
730 | mtspr(SPRN_DABRX, dabrx); | |
cab0af98 | 731 | return 0; |
14cf11af | 732 | } |
9422de3e MN |
733 | #else |
734 | static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) | |
735 | { | |
736 | return -EINVAL; | |
737 | } | |
738 | #endif | |
739 | ||
740 | static inline int set_dabr(struct arch_hw_breakpoint *brk) | |
741 | { | |
742 | unsigned long dabr, dabrx; | |
743 | ||
744 | dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); | |
745 | dabrx = ((brk->type >> 3) & 0x7); | |
746 | ||
747 | if (ppc_md.set_dabr) | |
748 | return ppc_md.set_dabr(dabr, dabrx); | |
749 | ||
750 | return __set_dabr(dabr, dabrx); | |
751 | } | |
752 | ||
bf99de36 MN |
753 | static inline int set_dawr(struct arch_hw_breakpoint *brk) |
754 | { | |
05d694ea | 755 | unsigned long dawr, dawrx, mrd; |
bf99de36 MN |
756 | |
757 | dawr = brk->address; | |
758 | ||
759 | dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \ | |
760 | << (63 - 58); //* read/write bits */ | |
761 | dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \ | |
762 | << (63 - 59); //* translate */ | |
763 | dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \ | |
764 | >> 3; //* PRIM bits */ | |
05d694ea MN |
765 | /* dawr length is stored in field MDR bits 48:53. Matches range in |
766 | doublewords (64 bits) baised by -1 eg. 0b000000=1DW and | |
767 | 0b111111=64DW. | |
768 | brk->len is in bytes. | |
769 | This aligns up to double word size, shifts and does the bias. | |
770 | */ | |
771 | mrd = ((brk->len + 7) >> 3) - 1; | |
772 | dawrx |= (mrd & 0x3f) << (63 - 53); | |
bf99de36 MN |
773 | |
774 | if (ppc_md.set_dawr) | |
775 | return ppc_md.set_dawr(dawr, dawrx); | |
776 | mtspr(SPRN_DAWR, dawr); | |
777 | mtspr(SPRN_DAWRX, dawrx); | |
778 | return 0; | |
779 | } | |
780 | ||
21f58507 | 781 | void __set_breakpoint(struct arch_hw_breakpoint *brk) |
9422de3e | 782 | { |
69111bac | 783 | memcpy(this_cpu_ptr(¤t_brk), brk, sizeof(*brk)); |
9422de3e | 784 | |
bf99de36 | 785 | if (cpu_has_feature(CPU_FTR_DAWR)) |
04c32a51 PG |
786 | set_dawr(brk); |
787 | else | |
788 | set_dabr(brk); | |
9422de3e | 789 | } |
14cf11af | 790 | |
21f58507 PG |
791 | void set_breakpoint(struct arch_hw_breakpoint *brk) |
792 | { | |
793 | preempt_disable(); | |
794 | __set_breakpoint(brk); | |
795 | preempt_enable(); | |
796 | } | |
797 | ||
06d67d54 PM |
798 | #ifdef CONFIG_PPC64 |
799 | DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array); | |
06d67d54 | 800 | #endif |
14cf11af | 801 | |
9422de3e MN |
802 | static inline bool hw_brk_match(struct arch_hw_breakpoint *a, |
803 | struct arch_hw_breakpoint *b) | |
804 | { | |
805 | if (a->address != b->address) | |
806 | return false; | |
807 | if (a->type != b->type) | |
808 | return false; | |
809 | if (a->len != b->len) | |
810 | return false; | |
811 | return true; | |
812 | } | |
d31626f7 | 813 | |
fb09692e | 814 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
5d176f75 CB |
815 | |
816 | static inline bool tm_enabled(struct task_struct *tsk) | |
817 | { | |
818 | return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM); | |
819 | } | |
820 | ||
d31626f7 PM |
821 | static void tm_reclaim_thread(struct thread_struct *thr, |
822 | struct thread_info *ti, uint8_t cause) | |
823 | { | |
7f821fc9 MN |
824 | /* |
825 | * Use the current MSR TM suspended bit to track if we have | |
826 | * checkpointed state outstanding. | |
827 | * On signal delivery, we'd normally reclaim the checkpointed | |
828 | * state to obtain stack pointer (see:get_tm_stackpointer()). | |
829 | * This will then directly return to userspace without going | |
830 | * through __switch_to(). However, if the stack frame is bad, | |
831 | * we need to exit this thread which calls __switch_to() which | |
832 | * will again attempt to reclaim the already saved tm state. | |
833 | * Hence we need to check that we've not already reclaimed | |
834 | * this state. | |
835 | * We do this using the current MSR, rather tracking it in | |
836 | * some specific thread_struct bit, as it has the additional | |
027dfac6 | 837 | * benefit of checking for a potential TM bad thing exception. |
7f821fc9 MN |
838 | */ |
839 | if (!MSR_TM_SUSPENDED(mfmsr())) | |
840 | return; | |
841 | ||
dc310669 | 842 | giveup_all(container_of(thr, struct task_struct, thread)); |
d31626f7 | 843 | |
dc310669 | 844 | tm_reclaim(thr, thr->ckpt_regs.msr, cause); |
d31626f7 PM |
845 | } |
846 | ||
847 | void tm_reclaim_current(uint8_t cause) | |
848 | { | |
849 | tm_enable(); | |
850 | tm_reclaim_thread(¤t->thread, current_thread_info(), cause); | |
851 | } | |
852 | ||
fb09692e MN |
853 | static inline void tm_reclaim_task(struct task_struct *tsk) |
854 | { | |
855 | /* We have to work out if we're switching from/to a task that's in the | |
856 | * middle of a transaction. | |
857 | * | |
858 | * In switching we need to maintain a 2nd register state as | |
859 | * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the | |
000ec280 CB |
860 | * checkpointed (tbegin) state in ckpt_regs, ckfp_state and |
861 | * ckvr_state | |
fb09692e MN |
862 | * |
863 | * We also context switch (save) TFHAR/TEXASR/TFIAR in here. | |
864 | */ | |
865 | struct thread_struct *thr = &tsk->thread; | |
866 | ||
867 | if (!thr->regs) | |
868 | return; | |
869 | ||
870 | if (!MSR_TM_ACTIVE(thr->regs->msr)) | |
871 | goto out_and_saveregs; | |
872 | ||
fb09692e MN |
873 | TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " |
874 | "ccr=%lx, msr=%lx, trap=%lx)\n", | |
875 | tsk->pid, thr->regs->nip, | |
876 | thr->regs->ccr, thr->regs->msr, | |
877 | thr->regs->trap); | |
878 | ||
d31626f7 | 879 | tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED); |
fb09692e MN |
880 | |
881 | TM_DEBUG("--- tm_reclaim on pid %d complete\n", | |
882 | tsk->pid); | |
883 | ||
884 | out_and_saveregs: | |
885 | /* Always save the regs here, even if a transaction's not active. | |
886 | * This context-switches a thread's TM info SPRs. We do it here to | |
887 | * be consistent with the restore path (in recheckpoint) which | |
888 | * cannot happen later in _switch(). | |
889 | */ | |
890 | tm_save_sprs(thr); | |
891 | } | |
892 | ||
e6b8fd02 MN |
893 | extern void __tm_recheckpoint(struct thread_struct *thread, |
894 | unsigned long orig_msr); | |
895 | ||
896 | void tm_recheckpoint(struct thread_struct *thread, | |
897 | unsigned long orig_msr) | |
898 | { | |
899 | unsigned long flags; | |
900 | ||
5d176f75 CB |
901 | if (!(thread->regs->msr & MSR_TM)) |
902 | return; | |
903 | ||
e6b8fd02 MN |
904 | /* We really can't be interrupted here as the TEXASR registers can't |
905 | * change and later in the trecheckpoint code, we have a userspace R1. | |
906 | * So let's hard disable over this region. | |
907 | */ | |
908 | local_irq_save(flags); | |
909 | hard_irq_disable(); | |
910 | ||
911 | /* The TM SPRs are restored here, so that TEXASR.FS can be set | |
912 | * before the trecheckpoint and no explosion occurs. | |
913 | */ | |
914 | tm_restore_sprs(thread); | |
915 | ||
916 | __tm_recheckpoint(thread, orig_msr); | |
917 | ||
918 | local_irq_restore(flags); | |
919 | } | |
920 | ||
bc2a9408 | 921 | static inline void tm_recheckpoint_new_task(struct task_struct *new) |
fb09692e MN |
922 | { |
923 | unsigned long msr; | |
924 | ||
925 | if (!cpu_has_feature(CPU_FTR_TM)) | |
926 | return; | |
927 | ||
928 | /* Recheckpoint the registers of the thread we're about to switch to. | |
929 | * | |
930 | * If the task was using FP, we non-lazily reload both the original and | |
931 | * the speculative FP register states. This is because the kernel | |
932 | * doesn't see if/when a TM rollback occurs, so if we take an FP | |
dc310669 | 933 | * unavailable later, we are unable to determine which set of FP regs |
fb09692e MN |
934 | * need to be restored. |
935 | */ | |
5d176f75 | 936 | if (!tm_enabled(new)) |
fb09692e MN |
937 | return; |
938 | ||
e6b8fd02 MN |
939 | if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ |
940 | tm_restore_sprs(&new->thread); | |
fb09692e | 941 | return; |
e6b8fd02 | 942 | } |
829023df | 943 | msr = new->thread.ckpt_regs.msr; |
fb09692e MN |
944 | /* Recheckpoint to restore original checkpointed register state. */ |
945 | TM_DEBUG("*** tm_recheckpoint of pid %d " | |
946 | "(new->msr 0x%lx, new->origmsr 0x%lx)\n", | |
947 | new->pid, new->thread.regs->msr, msr); | |
948 | ||
fb09692e MN |
949 | tm_recheckpoint(&new->thread, msr); |
950 | ||
dc310669 CB |
951 | /* |
952 | * The checkpointed state has been restored but the live state has | |
953 | * not, ensure all the math functionality is turned off to trigger | |
954 | * restore_math() to reload. | |
955 | */ | |
956 | new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX); | |
fb09692e MN |
957 | |
958 | TM_DEBUG("*** tm_recheckpoint of pid %d complete " | |
959 | "(kernel msr 0x%lx)\n", | |
960 | new->pid, mfmsr()); | |
961 | } | |
962 | ||
dc310669 CB |
963 | static inline void __switch_to_tm(struct task_struct *prev, |
964 | struct task_struct *new) | |
fb09692e MN |
965 | { |
966 | if (cpu_has_feature(CPU_FTR_TM)) { | |
5d176f75 CB |
967 | if (tm_enabled(prev) || tm_enabled(new)) |
968 | tm_enable(); | |
969 | ||
970 | if (tm_enabled(prev)) { | |
971 | prev->thread.load_tm++; | |
972 | tm_reclaim_task(prev); | |
973 | if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0) | |
974 | prev->thread.regs->msr &= ~MSR_TM; | |
975 | } | |
976 | ||
dc310669 | 977 | tm_recheckpoint_new_task(new); |
fb09692e MN |
978 | } |
979 | } | |
d31626f7 PM |
980 | |
981 | /* | |
982 | * This is called if we are on the way out to userspace and the | |
983 | * TIF_RESTORE_TM flag is set. It checks if we need to reload | |
984 | * FP and/or vector state and does so if necessary. | |
985 | * If userspace is inside a transaction (whether active or | |
986 | * suspended) and FP/VMX/VSX instructions have ever been enabled | |
987 | * inside that transaction, then we have to keep them enabled | |
988 | * and keep the FP/VMX/VSX state loaded while ever the transaction | |
989 | * continues. The reason is that if we didn't, and subsequently | |
990 | * got a FP/VMX/VSX unavailable interrupt inside a transaction, | |
991 | * we don't know whether it's the same transaction, and thus we | |
992 | * don't know which of the checkpointed state and the transactional | |
993 | * state to use. | |
994 | */ | |
995 | void restore_tm_state(struct pt_regs *regs) | |
996 | { | |
997 | unsigned long msr_diff; | |
998 | ||
dc310669 CB |
999 | /* |
1000 | * This is the only moment we should clear TIF_RESTORE_TM as | |
1001 | * it is here that ckpt_regs.msr and pt_regs.msr become the same | |
1002 | * again, anything else could lead to an incorrect ckpt_msr being | |
1003 | * saved and therefore incorrect signal contexts. | |
1004 | */ | |
d31626f7 PM |
1005 | clear_thread_flag(TIF_RESTORE_TM); |
1006 | if (!MSR_TM_ACTIVE(regs->msr)) | |
1007 | return; | |
1008 | ||
829023df | 1009 | msr_diff = current->thread.ckpt_regs.msr & ~regs->msr; |
d31626f7 | 1010 | msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; |
70fe3d98 | 1011 | |
dc16b553 CB |
1012 | /* Ensure that restore_math() will restore */ |
1013 | if (msr_diff & MSR_FP) | |
1014 | current->thread.load_fp = 1; | |
39715bf9 | 1015 | #ifdef CONFIG_ALTIVEC |
dc16b553 CB |
1016 | if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC) |
1017 | current->thread.load_vec = 1; | |
1018 | #endif | |
70fe3d98 CB |
1019 | restore_math(regs); |
1020 | ||
d31626f7 PM |
1021 | regs->msr |= msr_diff; |
1022 | } | |
1023 | ||
fb09692e MN |
1024 | #else |
1025 | #define tm_recheckpoint_new_task(new) | |
dc310669 | 1026 | #define __switch_to_tm(prev, new) |
fb09692e | 1027 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
9422de3e | 1028 | |
152d523e AB |
1029 | static inline void save_sprs(struct thread_struct *t) |
1030 | { | |
1031 | #ifdef CONFIG_ALTIVEC | |
01d7c2a2 | 1032 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) |
152d523e AB |
1033 | t->vrsave = mfspr(SPRN_VRSAVE); |
1034 | #endif | |
1035 | #ifdef CONFIG_PPC_BOOK3S_64 | |
1036 | if (cpu_has_feature(CPU_FTR_DSCR)) | |
1037 | t->dscr = mfspr(SPRN_DSCR); | |
1038 | ||
1039 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
1040 | t->bescr = mfspr(SPRN_BESCR); | |
1041 | t->ebbhr = mfspr(SPRN_EBBHR); | |
1042 | t->ebbrr = mfspr(SPRN_EBBRR); | |
1043 | ||
1044 | t->fscr = mfspr(SPRN_FSCR); | |
1045 | ||
1046 | /* | |
1047 | * Note that the TAR is not available for use in the kernel. | |
1048 | * (To provide this, the TAR should be backed up/restored on | |
1049 | * exception entry/exit instead, and be in pt_regs. FIXME, | |
1050 | * this should be in pt_regs anyway (for debug).) | |
1051 | */ | |
1052 | t->tar = mfspr(SPRN_TAR); | |
1053 | } | |
bd3ea317 JM |
1054 | |
1055 | if (cpu_has_feature(CPU_FTR_ARCH_300)) { | |
1056 | /* Conditionally save Load Monitor registers, if enabled */ | |
1057 | if (t->fscr & FSCR_LM) { | |
1058 | t->lmrr = mfspr(SPRN_LMRR); | |
1059 | t->lmser = mfspr(SPRN_LMSER); | |
1060 | } | |
1061 | } | |
152d523e AB |
1062 | #endif |
1063 | } | |
1064 | ||
1065 | static inline void restore_sprs(struct thread_struct *old_thread, | |
1066 | struct thread_struct *new_thread) | |
1067 | { | |
1068 | #ifdef CONFIG_ALTIVEC | |
1069 | if (cpu_has_feature(CPU_FTR_ALTIVEC) && | |
1070 | old_thread->vrsave != new_thread->vrsave) | |
1071 | mtspr(SPRN_VRSAVE, new_thread->vrsave); | |
1072 | #endif | |
1073 | #ifdef CONFIG_PPC_BOOK3S_64 | |
1074 | if (cpu_has_feature(CPU_FTR_DSCR)) { | |
1075 | u64 dscr = get_paca()->dscr_default; | |
b57bd2de | 1076 | if (new_thread->dscr_inherit) |
152d523e | 1077 | dscr = new_thread->dscr; |
152d523e AB |
1078 | |
1079 | if (old_thread->dscr != dscr) | |
1080 | mtspr(SPRN_DSCR, dscr); | |
152d523e AB |
1081 | } |
1082 | ||
1083 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
1084 | if (old_thread->bescr != new_thread->bescr) | |
1085 | mtspr(SPRN_BESCR, new_thread->bescr); | |
1086 | if (old_thread->ebbhr != new_thread->ebbhr) | |
1087 | mtspr(SPRN_EBBHR, new_thread->ebbhr); | |
1088 | if (old_thread->ebbrr != new_thread->ebbrr) | |
1089 | mtspr(SPRN_EBBRR, new_thread->ebbrr); | |
1090 | ||
b57bd2de MN |
1091 | if (old_thread->fscr != new_thread->fscr) |
1092 | mtspr(SPRN_FSCR, new_thread->fscr); | |
1093 | ||
152d523e AB |
1094 | if (old_thread->tar != new_thread->tar) |
1095 | mtspr(SPRN_TAR, new_thread->tar); | |
1096 | } | |
bd3ea317 JM |
1097 | |
1098 | if (cpu_has_feature(CPU_FTR_ARCH_300)) { | |
1099 | /* Conditionally restore Load Monitor registers, if enabled */ | |
1100 | if (new_thread->fscr & FSCR_LM) { | |
1101 | if (old_thread->lmrr != new_thread->lmrr) | |
1102 | mtspr(SPRN_LMRR, new_thread->lmrr); | |
1103 | if (old_thread->lmser != new_thread->lmser) | |
1104 | mtspr(SPRN_LMSER, new_thread->lmser); | |
1105 | } | |
1106 | } | |
152d523e AB |
1107 | #endif |
1108 | } | |
1109 | ||
14cf11af PM |
1110 | struct task_struct *__switch_to(struct task_struct *prev, |
1111 | struct task_struct *new) | |
1112 | { | |
1113 | struct thread_struct *new_thread, *old_thread; | |
14cf11af | 1114 | struct task_struct *last; |
d6bf29b4 PZ |
1115 | #ifdef CONFIG_PPC_BOOK3S_64 |
1116 | struct ppc64_tlb_batch *batch; | |
1117 | #endif | |
14cf11af | 1118 | |
152d523e AB |
1119 | new_thread = &new->thread; |
1120 | old_thread = ¤t->thread; | |
1121 | ||
7ba5fef7 MN |
1122 | WARN_ON(!irqs_disabled()); |
1123 | ||
06d67d54 PM |
1124 | #ifdef CONFIG_PPC64 |
1125 | /* | |
1126 | * Collect processor utilization data per process | |
1127 | */ | |
1128 | if (firmware_has_feature(FW_FEATURE_SPLPAR)) { | |
69111bac | 1129 | struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array); |
06d67d54 PM |
1130 | long unsigned start_tb, current_tb; |
1131 | start_tb = old_thread->start_tb; | |
1132 | cu->current_tb = current_tb = mfspr(SPRN_PURR); | |
1133 | old_thread->accum_tb += (current_tb - start_tb); | |
1134 | new_thread->start_tb = current_tb; | |
1135 | } | |
d6bf29b4 PZ |
1136 | #endif /* CONFIG_PPC64 */ |
1137 | ||
caca285e | 1138 | #ifdef CONFIG_PPC_STD_MMU_64 |
69111bac | 1139 | batch = this_cpu_ptr(&ppc64_tlb_batch); |
d6bf29b4 PZ |
1140 | if (batch->active) { |
1141 | current_thread_info()->local_flags |= _TLF_LAZY_MMU; | |
1142 | if (batch->index) | |
1143 | __flush_tlb_pending(batch); | |
1144 | batch->active = 0; | |
1145 | } | |
caca285e | 1146 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
06d67d54 | 1147 | |
f3d885cc AB |
1148 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
1149 | switch_booke_debug_regs(&new->thread.debug); | |
1150 | #else | |
1151 | /* | |
1152 | * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would | |
1153 | * schedule DABR | |
1154 | */ | |
1155 | #ifndef CONFIG_HAVE_HW_BREAKPOINT | |
1156 | if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk), &new->thread.hw_brk))) | |
1157 | __set_breakpoint(&new->thread.hw_brk); | |
1158 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
1159 | #endif | |
1160 | ||
1161 | /* | |
1162 | * We need to save SPRs before treclaim/trecheckpoint as these will | |
1163 | * change a number of them. | |
1164 | */ | |
1165 | save_sprs(&prev->thread); | |
1166 | ||
f3d885cc AB |
1167 | /* Save FPU, Altivec, VSX and SPE state */ |
1168 | giveup_all(prev); | |
1169 | ||
dc310669 CB |
1170 | __switch_to_tm(prev, new); |
1171 | ||
44387e9f AB |
1172 | /* |
1173 | * We can't take a PMU exception inside _switch() since there is a | |
1174 | * window where the kernel stack SLB and the kernel stack are out | |
1175 | * of sync. Hard disable here. | |
1176 | */ | |
1177 | hard_irq_disable(); | |
bc2a9408 | 1178 | |
20dbe670 AB |
1179 | /* |
1180 | * Call restore_sprs() before calling _switch(). If we move it after | |
1181 | * _switch() then we miss out on calling it for new tasks. The reason | |
1182 | * for this is we manually create a stack frame for new tasks that | |
1183 | * directly returns through ret_from_fork() or | |
1184 | * ret_from_kernel_thread(). See copy_thread() for details. | |
1185 | */ | |
f3d885cc AB |
1186 | restore_sprs(old_thread, new_thread); |
1187 | ||
20dbe670 AB |
1188 | last = _switch(old_thread, new_thread); |
1189 | ||
caca285e | 1190 | #ifdef CONFIG_PPC_STD_MMU_64 |
d6bf29b4 PZ |
1191 | if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { |
1192 | current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; | |
69111bac | 1193 | batch = this_cpu_ptr(&ppc64_tlb_batch); |
d6bf29b4 PZ |
1194 | batch->active = 1; |
1195 | } | |
70fe3d98 CB |
1196 | |
1197 | if (current_thread_info()->task->thread.regs) | |
1198 | restore_math(current_thread_info()->task->thread.regs); | |
caca285e | 1199 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
d6bf29b4 | 1200 | |
14cf11af PM |
1201 | return last; |
1202 | } | |
1203 | ||
06d67d54 PM |
1204 | static int instructions_to_print = 16; |
1205 | ||
06d67d54 PM |
1206 | static void show_instructions(struct pt_regs *regs) |
1207 | { | |
1208 | int i; | |
1209 | unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 * | |
1210 | sizeof(int)); | |
1211 | ||
1212 | printk("Instruction dump:"); | |
1213 | ||
1214 | for (i = 0; i < instructions_to_print; i++) { | |
1215 | int instr; | |
1216 | ||
1217 | if (!(i % 8)) | |
1218 | printk("\n"); | |
1219 | ||
0de2d820 SW |
1220 | #if !defined(CONFIG_BOOKE) |
1221 | /* If executing with the IMMU off, adjust pc rather | |
1222 | * than print XXXXXXXX. | |
1223 | */ | |
1224 | if (!(regs->msr & MSR_IR)) | |
1225 | pc = (unsigned long)phys_to_virt(pc); | |
1226 | #endif | |
1227 | ||
00ae36de | 1228 | if (!__kernel_text_address(pc) || |
7b051f66 | 1229 | probe_kernel_address((unsigned int __user *)pc, instr)) { |
40c8cefa | 1230 | printk(KERN_CONT "XXXXXXXX "); |
06d67d54 PM |
1231 | } else { |
1232 | if (regs->nip == pc) | |
40c8cefa | 1233 | printk(KERN_CONT "<%08x> ", instr); |
06d67d54 | 1234 | else |
40c8cefa | 1235 | printk(KERN_CONT "%08x ", instr); |
06d67d54 PM |
1236 | } |
1237 | ||
1238 | pc += sizeof(int); | |
1239 | } | |
1240 | ||
1241 | printk("\n"); | |
1242 | } | |
1243 | ||
801c0b2c | 1244 | struct regbit { |
06d67d54 PM |
1245 | unsigned long bit; |
1246 | const char *name; | |
801c0b2c MN |
1247 | }; |
1248 | ||
1249 | static struct regbit msr_bits[] = { | |
3bfd0c9c AB |
1250 | #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) |
1251 | {MSR_SF, "SF"}, | |
1252 | {MSR_HV, "HV"}, | |
1253 | #endif | |
1254 | {MSR_VEC, "VEC"}, | |
1255 | {MSR_VSX, "VSX"}, | |
1256 | #ifdef CONFIG_BOOKE | |
1257 | {MSR_CE, "CE"}, | |
1258 | #endif | |
06d67d54 PM |
1259 | {MSR_EE, "EE"}, |
1260 | {MSR_PR, "PR"}, | |
1261 | {MSR_FP, "FP"}, | |
1262 | {MSR_ME, "ME"}, | |
3bfd0c9c | 1263 | #ifdef CONFIG_BOOKE |
1b98326b | 1264 | {MSR_DE, "DE"}, |
3bfd0c9c AB |
1265 | #else |
1266 | {MSR_SE, "SE"}, | |
1267 | {MSR_BE, "BE"}, | |
1268 | #endif | |
06d67d54 PM |
1269 | {MSR_IR, "IR"}, |
1270 | {MSR_DR, "DR"}, | |
3bfd0c9c AB |
1271 | {MSR_PMM, "PMM"}, |
1272 | #ifndef CONFIG_BOOKE | |
1273 | {MSR_RI, "RI"}, | |
1274 | {MSR_LE, "LE"}, | |
1275 | #endif | |
06d67d54 PM |
1276 | {0, NULL} |
1277 | }; | |
1278 | ||
801c0b2c | 1279 | static void print_bits(unsigned long val, struct regbit *bits, const char *sep) |
06d67d54 | 1280 | { |
801c0b2c | 1281 | const char *s = ""; |
06d67d54 | 1282 | |
06d67d54 PM |
1283 | for (; bits->bit; ++bits) |
1284 | if (val & bits->bit) { | |
801c0b2c MN |
1285 | printk("%s%s", s, bits->name); |
1286 | s = sep; | |
06d67d54 | 1287 | } |
801c0b2c MN |
1288 | } |
1289 | ||
1290 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1291 | static struct regbit msr_tm_bits[] = { | |
1292 | {MSR_TS_T, "T"}, | |
1293 | {MSR_TS_S, "S"}, | |
1294 | {MSR_TM, "E"}, | |
1295 | {0, NULL} | |
1296 | }; | |
1297 | ||
1298 | static void print_tm_bits(unsigned long val) | |
1299 | { | |
1300 | /* | |
1301 | * This only prints something if at least one of the TM bit is set. | |
1302 | * Inside the TM[], the output means: | |
1303 | * E: Enabled (bit 32) | |
1304 | * S: Suspended (bit 33) | |
1305 | * T: Transactional (bit 34) | |
1306 | */ | |
1307 | if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { | |
1308 | printk(",TM["); | |
1309 | print_bits(val, msr_tm_bits, ""); | |
1310 | printk("]"); | |
1311 | } | |
1312 | } | |
1313 | #else | |
1314 | static void print_tm_bits(unsigned long val) {} | |
1315 | #endif | |
1316 | ||
1317 | static void print_msr_bits(unsigned long val) | |
1318 | { | |
1319 | printk("<"); | |
1320 | print_bits(val, msr_bits, ","); | |
1321 | print_tm_bits(val); | |
06d67d54 PM |
1322 | printk(">"); |
1323 | } | |
1324 | ||
1325 | #ifdef CONFIG_PPC64 | |
f6f7dde3 | 1326 | #define REG "%016lx" |
06d67d54 PM |
1327 | #define REGS_PER_LINE 4 |
1328 | #define LAST_VOLATILE 13 | |
1329 | #else | |
f6f7dde3 | 1330 | #define REG "%08lx" |
06d67d54 PM |
1331 | #define REGS_PER_LINE 8 |
1332 | #define LAST_VOLATILE 12 | |
1333 | #endif | |
1334 | ||
14cf11af PM |
1335 | void show_regs(struct pt_regs * regs) |
1336 | { | |
1337 | int i, trap; | |
1338 | ||
a43cb95d TH |
1339 | show_regs_print_info(KERN_DEFAULT); |
1340 | ||
06d67d54 PM |
1341 | printk("NIP: "REG" LR: "REG" CTR: "REG"\n", |
1342 | regs->nip, regs->link, regs->ctr); | |
1343 | printk("REGS: %p TRAP: %04lx %s (%s)\n", | |
96b644bd | 1344 | regs, regs->trap, print_tainted(), init_utsname()->release); |
06d67d54 | 1345 | printk("MSR: "REG" ", regs->msr); |
801c0b2c | 1346 | print_msr_bits(regs->msr); |
f6f7dde3 | 1347 | printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); |
14cf11af | 1348 | trap = TRAP(regs); |
5115a026 | 1349 | if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) |
9db8bcfd | 1350 | printk("CFAR: "REG" ", regs->orig_gpr3); |
c5400649 | 1351 | if (trap == 0x200 || trap == 0x300 || trap == 0x600) |
ba28c9aa | 1352 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) |
9db8bcfd | 1353 | printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); |
14170789 | 1354 | #else |
9db8bcfd AB |
1355 | printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); |
1356 | #endif | |
1357 | #ifdef CONFIG_PPC64 | |
1358 | printk("SOFTE: %ld ", regs->softe); | |
1359 | #endif | |
1360 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
6d888d1a AB |
1361 | if (MSR_TM_ACTIVE(regs->msr)) |
1362 | printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); | |
14170789 | 1363 | #endif |
14cf11af PM |
1364 | |
1365 | for (i = 0; i < 32; i++) { | |
06d67d54 | 1366 | if ((i % REGS_PER_LINE) == 0) |
a2367194 | 1367 | printk("\nGPR%02d: ", i); |
06d67d54 PM |
1368 | printk(REG " ", regs->gpr[i]); |
1369 | if (i == LAST_VOLATILE && !FULL_REGS(regs)) | |
14cf11af PM |
1370 | break; |
1371 | } | |
1372 | printk("\n"); | |
1373 | #ifdef CONFIG_KALLSYMS | |
1374 | /* | |
1375 | * Lookup NIP late so we have the best change of getting the | |
1376 | * above info out without failing | |
1377 | */ | |
058c78f4 BH |
1378 | printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); |
1379 | printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); | |
afc07701 | 1380 | #endif |
14cf11af | 1381 | show_stack(current, (unsigned long *) regs->gpr[1]); |
06d67d54 PM |
1382 | if (!user_mode(regs)) |
1383 | show_instructions(regs); | |
14cf11af PM |
1384 | } |
1385 | ||
14cf11af PM |
1386 | void flush_thread(void) |
1387 | { | |
e0780b72 | 1388 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
5aae8a53 | 1389 | flush_ptrace_hw_breakpoint(current); |
e0780b72 | 1390 | #else /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 1391 | set_debug_reg_defaults(¤t->thread); |
e0780b72 | 1392 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
14cf11af PM |
1393 | } |
1394 | ||
1395 | void | |
1396 | release_thread(struct task_struct *t) | |
1397 | { | |
1398 | } | |
1399 | ||
1400 | /* | |
55ccf3fe SS |
1401 | * this gets called so that we can store coprocessor state into memory and |
1402 | * copy the current task into the new thread. | |
14cf11af | 1403 | */ |
55ccf3fe | 1404 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
14cf11af | 1405 | { |
579e633e | 1406 | flush_all_to_thread(src); |
621b5060 MN |
1407 | /* |
1408 | * Flush TM state out so we can copy it. __switch_to_tm() does this | |
1409 | * flush but it removes the checkpointed state from the current CPU and | |
1410 | * transitions the CPU out of TM mode. Hence we need to call | |
1411 | * tm_recheckpoint_new_task() (on the same task) to restore the | |
1412 | * checkpointed state back and the TM mode. | |
5d176f75 CB |
1413 | * |
1414 | * Can't pass dst because it isn't ready. Doesn't matter, passing | |
1415 | * dst is only important for __switch_to() | |
621b5060 | 1416 | */ |
dc310669 | 1417 | __switch_to_tm(src, src); |
330a1eb7 | 1418 | |
55ccf3fe | 1419 | *dst = *src; |
330a1eb7 ME |
1420 | |
1421 | clear_task_ebb(dst); | |
1422 | ||
55ccf3fe | 1423 | return 0; |
14cf11af PM |
1424 | } |
1425 | ||
cec15488 ME |
1426 | static void setup_ksp_vsid(struct task_struct *p, unsigned long sp) |
1427 | { | |
1428 | #ifdef CONFIG_PPC_STD_MMU_64 | |
1429 | unsigned long sp_vsid; | |
1430 | unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; | |
1431 | ||
caca285e AK |
1432 | if (radix_enabled()) |
1433 | return; | |
1434 | ||
cec15488 ME |
1435 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) |
1436 | sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) | |
1437 | << SLB_VSID_SHIFT_1T; | |
1438 | else | |
1439 | sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) | |
1440 | << SLB_VSID_SHIFT; | |
1441 | sp_vsid |= SLB_VSID_KERNEL | llp; | |
1442 | p->thread.ksp_vsid = sp_vsid; | |
1443 | #endif | |
1444 | } | |
1445 | ||
14cf11af PM |
1446 | /* |
1447 | * Copy a thread.. | |
1448 | */ | |
efcac658 | 1449 | |
6eca8933 AD |
1450 | /* |
1451 | * Copy architecture-specific thread state | |
1452 | */ | |
6f2c55b8 | 1453 | int copy_thread(unsigned long clone_flags, unsigned long usp, |
6eca8933 | 1454 | unsigned long kthread_arg, struct task_struct *p) |
14cf11af PM |
1455 | { |
1456 | struct pt_regs *childregs, *kregs; | |
1457 | extern void ret_from_fork(void); | |
58254e10 AV |
1458 | extern void ret_from_kernel_thread(void); |
1459 | void (*f)(void); | |
0cec6fd1 | 1460 | unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; |
5d31a96e ME |
1461 | struct thread_info *ti = task_thread_info(p); |
1462 | ||
1463 | klp_init_thread_info(ti); | |
14cf11af | 1464 | |
14cf11af PM |
1465 | /* Copy registers */ |
1466 | sp -= sizeof(struct pt_regs); | |
1467 | childregs = (struct pt_regs *) sp; | |
ab75819d | 1468 | if (unlikely(p->flags & PF_KTHREAD)) { |
6eca8933 | 1469 | /* kernel thread */ |
58254e10 | 1470 | memset(childregs, 0, sizeof(struct pt_regs)); |
14cf11af | 1471 | childregs->gpr[1] = sp + sizeof(struct pt_regs); |
7cedd601 AB |
1472 | /* function */ |
1473 | if (usp) | |
1474 | childregs->gpr[14] = ppc_function_entry((void *)usp); | |
58254e10 | 1475 | #ifdef CONFIG_PPC64 |
b5e2fc1c | 1476 | clear_tsk_thread_flag(p, TIF_32BIT); |
138d1ce8 | 1477 | childregs->softe = 1; |
06d67d54 | 1478 | #endif |
6eca8933 | 1479 | childregs->gpr[15] = kthread_arg; |
14cf11af | 1480 | p->thread.regs = NULL; /* no user register state */ |
138d1ce8 | 1481 | ti->flags |= _TIF_RESTOREALL; |
58254e10 | 1482 | f = ret_from_kernel_thread; |
14cf11af | 1483 | } else { |
6eca8933 | 1484 | /* user thread */ |
afa86fc4 | 1485 | struct pt_regs *regs = current_pt_regs(); |
58254e10 AV |
1486 | CHECK_FULL_REGS(regs); |
1487 | *childregs = *regs; | |
ea516b11 AV |
1488 | if (usp) |
1489 | childregs->gpr[1] = usp; | |
14cf11af | 1490 | p->thread.regs = childregs; |
58254e10 | 1491 | childregs->gpr[3] = 0; /* Result from fork() */ |
06d67d54 PM |
1492 | if (clone_flags & CLONE_SETTLS) { |
1493 | #ifdef CONFIG_PPC64 | |
9904b005 | 1494 | if (!is_32bit_task()) |
06d67d54 PM |
1495 | childregs->gpr[13] = childregs->gpr[6]; |
1496 | else | |
1497 | #endif | |
1498 | childregs->gpr[2] = childregs->gpr[6]; | |
1499 | } | |
58254e10 AV |
1500 | |
1501 | f = ret_from_fork; | |
14cf11af | 1502 | } |
d272f667 | 1503 | childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX); |
14cf11af | 1504 | sp -= STACK_FRAME_OVERHEAD; |
14cf11af PM |
1505 | |
1506 | /* | |
1507 | * The way this works is that at some point in the future | |
1508 | * some task will call _switch to switch to the new task. | |
1509 | * That will pop off the stack frame created below and start | |
1510 | * the new task running at ret_from_fork. The new task will | |
1511 | * do some house keeping and then return from the fork or clone | |
1512 | * system call, using the stack frame created above. | |
1513 | */ | |
af945cf4 | 1514 | ((unsigned long *)sp)[0] = 0; |
14cf11af PM |
1515 | sp -= sizeof(struct pt_regs); |
1516 | kregs = (struct pt_regs *) sp; | |
1517 | sp -= STACK_FRAME_OVERHEAD; | |
1518 | p->thread.ksp = sp; | |
cbc9565e | 1519 | #ifdef CONFIG_PPC32 |
85218827 KG |
1520 | p->thread.ksp_limit = (unsigned long)task_stack_page(p) + |
1521 | _ALIGN_UP(sizeof(struct thread_info), 16); | |
cbc9565e | 1522 | #endif |
28d170ab ON |
1523 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1524 | p->thread.ptrace_bps[0] = NULL; | |
1525 | #endif | |
1526 | ||
18461960 PM |
1527 | p->thread.fp_save_area = NULL; |
1528 | #ifdef CONFIG_ALTIVEC | |
1529 | p->thread.vr_save_area = NULL; | |
1530 | #endif | |
1531 | ||
cec15488 ME |
1532 | setup_ksp_vsid(p, sp); |
1533 | ||
efcac658 AK |
1534 | #ifdef CONFIG_PPC64 |
1535 | if (cpu_has_feature(CPU_FTR_DSCR)) { | |
1021cb26 | 1536 | p->thread.dscr_inherit = current->thread.dscr_inherit; |
db1231dc | 1537 | p->thread.dscr = mfspr(SPRN_DSCR); |
efcac658 | 1538 | } |
92779245 HM |
1539 | if (cpu_has_feature(CPU_FTR_HAS_PPR)) |
1540 | p->thread.ppr = INIT_PPR; | |
efcac658 | 1541 | #endif |
7cedd601 | 1542 | kregs->nip = ppc_function_entry(f); |
14cf11af PM |
1543 | return 0; |
1544 | } | |
1545 | ||
1546 | /* | |
1547 | * Set up a thread for executing a new program | |
1548 | */ | |
06d67d54 | 1549 | void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) |
14cf11af | 1550 | { |
90eac727 ME |
1551 | #ifdef CONFIG_PPC64 |
1552 | unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ | |
1553 | #endif | |
1554 | ||
06d67d54 PM |
1555 | /* |
1556 | * If we exec out of a kernel thread then thread.regs will not be | |
1557 | * set. Do it now. | |
1558 | */ | |
1559 | if (!current->thread.regs) { | |
0cec6fd1 AV |
1560 | struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; |
1561 | current->thread.regs = regs - 1; | |
06d67d54 PM |
1562 | } |
1563 | ||
8e96a87c CB |
1564 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1565 | /* | |
1566 | * Clear any transactional state, we're exec()ing. The cause is | |
1567 | * not important as there will never be a recheckpoint so it's not | |
1568 | * user visible. | |
1569 | */ | |
1570 | if (MSR_TM_SUSPENDED(mfmsr())) | |
1571 | tm_reclaim_current(0); | |
1572 | #endif | |
1573 | ||
14cf11af PM |
1574 | memset(regs->gpr, 0, sizeof(regs->gpr)); |
1575 | regs->ctr = 0; | |
1576 | regs->link = 0; | |
1577 | regs->xer = 0; | |
1578 | regs->ccr = 0; | |
14cf11af | 1579 | regs->gpr[1] = sp; |
06d67d54 | 1580 | |
474f8196 RM |
1581 | /* |
1582 | * We have just cleared all the nonvolatile GPRs, so make | |
1583 | * FULL_REGS(regs) return true. This is necessary to allow | |
1584 | * ptrace to examine the thread immediately after exec. | |
1585 | */ | |
1586 | regs->trap &= ~1UL; | |
1587 | ||
06d67d54 PM |
1588 | #ifdef CONFIG_PPC32 |
1589 | regs->mq = 0; | |
1590 | regs->nip = start; | |
14cf11af | 1591 | regs->msr = MSR_USER; |
06d67d54 | 1592 | #else |
9904b005 | 1593 | if (!is_32bit_task()) { |
94af3abf | 1594 | unsigned long entry; |
06d67d54 | 1595 | |
94af3abf RR |
1596 | if (is_elf2_task()) { |
1597 | /* Look ma, no function descriptors! */ | |
1598 | entry = start; | |
06d67d54 | 1599 | |
94af3abf RR |
1600 | /* |
1601 | * Ulrich says: | |
1602 | * The latest iteration of the ABI requires that when | |
1603 | * calling a function (at its global entry point), | |
1604 | * the caller must ensure r12 holds the entry point | |
1605 | * address (so that the function can quickly | |
1606 | * establish addressability). | |
1607 | */ | |
1608 | regs->gpr[12] = start; | |
1609 | /* Make sure that's restored on entry to userspace. */ | |
1610 | set_thread_flag(TIF_RESTOREALL); | |
1611 | } else { | |
1612 | unsigned long toc; | |
1613 | ||
1614 | /* start is a relocated pointer to the function | |
1615 | * descriptor for the elf _start routine. The first | |
1616 | * entry in the function descriptor is the entry | |
1617 | * address of _start and the second entry is the TOC | |
1618 | * value we need to use. | |
1619 | */ | |
1620 | __get_user(entry, (unsigned long __user *)start); | |
1621 | __get_user(toc, (unsigned long __user *)start+1); | |
1622 | ||
1623 | /* Check whether the e_entry function descriptor entries | |
1624 | * need to be relocated before we can use them. | |
1625 | */ | |
1626 | if (load_addr != 0) { | |
1627 | entry += load_addr; | |
1628 | toc += load_addr; | |
1629 | } | |
1630 | regs->gpr[2] = toc; | |
06d67d54 PM |
1631 | } |
1632 | regs->nip = entry; | |
06d67d54 | 1633 | regs->msr = MSR_USER64; |
d4bf9a78 SR |
1634 | } else { |
1635 | regs->nip = start; | |
1636 | regs->gpr[2] = 0; | |
1637 | regs->msr = MSR_USER32; | |
06d67d54 PM |
1638 | } |
1639 | #endif | |
ce48b210 MN |
1640 | #ifdef CONFIG_VSX |
1641 | current->thread.used_vsr = 0; | |
1642 | #endif | |
de79f7b9 | 1643 | memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); |
18461960 | 1644 | current->thread.fp_save_area = NULL; |
14cf11af | 1645 | #ifdef CONFIG_ALTIVEC |
de79f7b9 PM |
1646 | memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); |
1647 | current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ | |
18461960 | 1648 | current->thread.vr_save_area = NULL; |
14cf11af PM |
1649 | current->thread.vrsave = 0; |
1650 | current->thread.used_vr = 0; | |
1651 | #endif /* CONFIG_ALTIVEC */ | |
1652 | #ifdef CONFIG_SPE | |
1653 | memset(current->thread.evr, 0, sizeof(current->thread.evr)); | |
1654 | current->thread.acc = 0; | |
1655 | current->thread.spefscr = 0; | |
1656 | current->thread.used_spe = 0; | |
1657 | #endif /* CONFIG_SPE */ | |
bc2a9408 | 1658 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
bc2a9408 MN |
1659 | current->thread.tm_tfhar = 0; |
1660 | current->thread.tm_texasr = 0; | |
1661 | current->thread.tm_tfiar = 0; | |
1662 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ | |
14cf11af | 1663 | } |
e1802b06 | 1664 | EXPORT_SYMBOL(start_thread); |
14cf11af PM |
1665 | |
1666 | #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ | |
1667 | | PR_FP_EXC_RES | PR_FP_EXC_INV) | |
1668 | ||
1669 | int set_fpexc_mode(struct task_struct *tsk, unsigned int val) | |
1670 | { | |
1671 | struct pt_regs *regs = tsk->thread.regs; | |
1672 | ||
1673 | /* This is a bit hairy. If we are an SPE enabled processor | |
1674 | * (have embedded fp) we store the IEEE exception enable flags in | |
1675 | * fpexc_mode. fpexc_mode is also used for setting FP exception | |
1676 | * mode (asyn, precise, disabled) for 'Classic' FP. */ | |
1677 | if (val & PR_FP_EXC_SW_ENABLE) { | |
1678 | #ifdef CONFIG_SPE | |
5e14d21e | 1679 | if (cpu_has_feature(CPU_FTR_SPE)) { |
640e9225 JM |
1680 | /* |
1681 | * When the sticky exception bits are set | |
1682 | * directly by userspace, it must call prctl | |
1683 | * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE | |
1684 | * in the existing prctl settings) or | |
1685 | * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in | |
1686 | * the bits being set). <fenv.h> functions | |
1687 | * saving and restoring the whole | |
1688 | * floating-point environment need to do so | |
1689 | * anyway to restore the prctl settings from | |
1690 | * the saved environment. | |
1691 | */ | |
1692 | tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); | |
5e14d21e KG |
1693 | tsk->thread.fpexc_mode = val & |
1694 | (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); | |
1695 | return 0; | |
1696 | } else { | |
1697 | return -EINVAL; | |
1698 | } | |
14cf11af PM |
1699 | #else |
1700 | return -EINVAL; | |
1701 | #endif | |
14cf11af | 1702 | } |
06d67d54 PM |
1703 | |
1704 | /* on a CONFIG_SPE this does not hurt us. The bits that | |
1705 | * __pack_fe01 use do not overlap with bits used for | |
1706 | * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits | |
1707 | * on CONFIG_SPE implementations are reserved so writing to | |
1708 | * them does not change anything */ | |
1709 | if (val > PR_FP_EXC_PRECISE) | |
1710 | return -EINVAL; | |
1711 | tsk->thread.fpexc_mode = __pack_fe01(val); | |
1712 | if (regs != NULL && (regs->msr & MSR_FP) != 0) | |
1713 | regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) | |
1714 | | tsk->thread.fpexc_mode; | |
14cf11af PM |
1715 | return 0; |
1716 | } | |
1717 | ||
1718 | int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) | |
1719 | { | |
1720 | unsigned int val; | |
1721 | ||
1722 | if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) | |
1723 | #ifdef CONFIG_SPE | |
640e9225 JM |
1724 | if (cpu_has_feature(CPU_FTR_SPE)) { |
1725 | /* | |
1726 | * When the sticky exception bits are set | |
1727 | * directly by userspace, it must call prctl | |
1728 | * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE | |
1729 | * in the existing prctl settings) or | |
1730 | * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in | |
1731 | * the bits being set). <fenv.h> functions | |
1732 | * saving and restoring the whole | |
1733 | * floating-point environment need to do so | |
1734 | * anyway to restore the prctl settings from | |
1735 | * the saved environment. | |
1736 | */ | |
1737 | tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); | |
5e14d21e | 1738 | val = tsk->thread.fpexc_mode; |
640e9225 | 1739 | } else |
5e14d21e | 1740 | return -EINVAL; |
14cf11af PM |
1741 | #else |
1742 | return -EINVAL; | |
1743 | #endif | |
1744 | else | |
1745 | val = __unpack_fe01(tsk->thread.fpexc_mode); | |
1746 | return put_user(val, (unsigned int __user *) adr); | |
1747 | } | |
1748 | ||
fab5db97 PM |
1749 | int set_endian(struct task_struct *tsk, unsigned int val) |
1750 | { | |
1751 | struct pt_regs *regs = tsk->thread.regs; | |
1752 | ||
1753 | if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || | |
1754 | (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) | |
1755 | return -EINVAL; | |
1756 | ||
1757 | if (regs == NULL) | |
1758 | return -EINVAL; | |
1759 | ||
1760 | if (val == PR_ENDIAN_BIG) | |
1761 | regs->msr &= ~MSR_LE; | |
1762 | else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) | |
1763 | regs->msr |= MSR_LE; | |
1764 | else | |
1765 | return -EINVAL; | |
1766 | ||
1767 | return 0; | |
1768 | } | |
1769 | ||
1770 | int get_endian(struct task_struct *tsk, unsigned long adr) | |
1771 | { | |
1772 | struct pt_regs *regs = tsk->thread.regs; | |
1773 | unsigned int val; | |
1774 | ||
1775 | if (!cpu_has_feature(CPU_FTR_PPC_LE) && | |
1776 | !cpu_has_feature(CPU_FTR_REAL_LE)) | |
1777 | return -EINVAL; | |
1778 | ||
1779 | if (regs == NULL) | |
1780 | return -EINVAL; | |
1781 | ||
1782 | if (regs->msr & MSR_LE) { | |
1783 | if (cpu_has_feature(CPU_FTR_REAL_LE)) | |
1784 | val = PR_ENDIAN_LITTLE; | |
1785 | else | |
1786 | val = PR_ENDIAN_PPC_LITTLE; | |
1787 | } else | |
1788 | val = PR_ENDIAN_BIG; | |
1789 | ||
1790 | return put_user(val, (unsigned int __user *)adr); | |
1791 | } | |
1792 | ||
e9370ae1 PM |
1793 | int set_unalign_ctl(struct task_struct *tsk, unsigned int val) |
1794 | { | |
1795 | tsk->thread.align_ctl = val; | |
1796 | return 0; | |
1797 | } | |
1798 | ||
1799 | int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) | |
1800 | { | |
1801 | return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); | |
1802 | } | |
1803 | ||
bb72c481 PM |
1804 | static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, |
1805 | unsigned long nbytes) | |
1806 | { | |
1807 | unsigned long stack_page; | |
1808 | unsigned long cpu = task_cpu(p); | |
1809 | ||
1810 | /* | |
1811 | * Avoid crashing if the stack has overflowed and corrupted | |
1812 | * task_cpu(p), which is in the thread_info struct. | |
1813 | */ | |
1814 | if (cpu < NR_CPUS && cpu_possible(cpu)) { | |
1815 | stack_page = (unsigned long) hardirq_ctx[cpu]; | |
1816 | if (sp >= stack_page + sizeof(struct thread_struct) | |
1817 | && sp <= stack_page + THREAD_SIZE - nbytes) | |
1818 | return 1; | |
1819 | ||
1820 | stack_page = (unsigned long) softirq_ctx[cpu]; | |
1821 | if (sp >= stack_page + sizeof(struct thread_struct) | |
1822 | && sp <= stack_page + THREAD_SIZE - nbytes) | |
1823 | return 1; | |
1824 | } | |
1825 | return 0; | |
1826 | } | |
1827 | ||
2f25194d | 1828 | int validate_sp(unsigned long sp, struct task_struct *p, |
14cf11af PM |
1829 | unsigned long nbytes) |
1830 | { | |
0cec6fd1 | 1831 | unsigned long stack_page = (unsigned long)task_stack_page(p); |
14cf11af PM |
1832 | |
1833 | if (sp >= stack_page + sizeof(struct thread_struct) | |
1834 | && sp <= stack_page + THREAD_SIZE - nbytes) | |
1835 | return 1; | |
1836 | ||
bb72c481 | 1837 | return valid_irq_stack(sp, p, nbytes); |
14cf11af PM |
1838 | } |
1839 | ||
2f25194d AB |
1840 | EXPORT_SYMBOL(validate_sp); |
1841 | ||
14cf11af PM |
1842 | unsigned long get_wchan(struct task_struct *p) |
1843 | { | |
1844 | unsigned long ip, sp; | |
1845 | int count = 0; | |
1846 | ||
1847 | if (!p || p == current || p->state == TASK_RUNNING) | |
1848 | return 0; | |
1849 | ||
1850 | sp = p->thread.ksp; | |
ec2b36b9 | 1851 | if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) |
14cf11af PM |
1852 | return 0; |
1853 | ||
1854 | do { | |
1855 | sp = *(unsigned long *)sp; | |
ec2b36b9 | 1856 | if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) |
14cf11af PM |
1857 | return 0; |
1858 | if (count > 0) { | |
ec2b36b9 | 1859 | ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; |
14cf11af PM |
1860 | if (!in_sched_functions(ip)) |
1861 | return ip; | |
1862 | } | |
1863 | } while (count++ < 16); | |
1864 | return 0; | |
1865 | } | |
06d67d54 | 1866 | |
c4d04be1 | 1867 | static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; |
06d67d54 PM |
1868 | |
1869 | void show_stack(struct task_struct *tsk, unsigned long *stack) | |
1870 | { | |
1871 | unsigned long sp, ip, lr, newsp; | |
1872 | int count = 0; | |
1873 | int firstframe = 1; | |
6794c782 SR |
1874 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
1875 | int curr_frame = current->curr_ret_stack; | |
1876 | extern void return_to_handler(void); | |
9135c3cc | 1877 | unsigned long rth = (unsigned long)return_to_handler; |
6794c782 | 1878 | #endif |
06d67d54 PM |
1879 | |
1880 | sp = (unsigned long) stack; | |
1881 | if (tsk == NULL) | |
1882 | tsk = current; | |
1883 | if (sp == 0) { | |
1884 | if (tsk == current) | |
acf620ec | 1885 | sp = current_stack_pointer(); |
06d67d54 PM |
1886 | else |
1887 | sp = tsk->thread.ksp; | |
1888 | } | |
1889 | ||
1890 | lr = 0; | |
1891 | printk("Call Trace:\n"); | |
1892 | do { | |
ec2b36b9 | 1893 | if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) |
06d67d54 PM |
1894 | return; |
1895 | ||
1896 | stack = (unsigned long *) sp; | |
1897 | newsp = stack[0]; | |
ec2b36b9 | 1898 | ip = stack[STACK_FRAME_LR_SAVE]; |
06d67d54 | 1899 | if (!firstframe || ip != lr) { |
058c78f4 | 1900 | printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); |
6794c782 | 1901 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
7d56c65a | 1902 | if ((ip == rth) && curr_frame >= 0) { |
6794c782 SR |
1903 | printk(" (%pS)", |
1904 | (void *)current->ret_stack[curr_frame].ret); | |
1905 | curr_frame--; | |
1906 | } | |
1907 | #endif | |
06d67d54 PM |
1908 | if (firstframe) |
1909 | printk(" (unreliable)"); | |
1910 | printk("\n"); | |
1911 | } | |
1912 | firstframe = 0; | |
1913 | ||
1914 | /* | |
1915 | * See if this is an exception frame. | |
1916 | * We look for the "regshere" marker in the current frame. | |
1917 | */ | |
ec2b36b9 BH |
1918 | if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) |
1919 | && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { | |
06d67d54 PM |
1920 | struct pt_regs *regs = (struct pt_regs *) |
1921 | (sp + STACK_FRAME_OVERHEAD); | |
06d67d54 | 1922 | lr = regs->link; |
9be9be2e | 1923 | printk("--- interrupt: %lx at %pS\n LR = %pS\n", |
058c78f4 | 1924 | regs->trap, (void *)regs->nip, (void *)lr); |
06d67d54 PM |
1925 | firstframe = 1; |
1926 | } | |
1927 | ||
1928 | sp = newsp; | |
1929 | } while (count++ < kstack_depth_to_print); | |
1930 | } | |
1931 | ||
cb2c9b27 | 1932 | #ifdef CONFIG_PPC64 |
fe1952fc | 1933 | /* Called with hard IRQs off */ |
0e37739b | 1934 | void notrace __ppc64_runlatch_on(void) |
cb2c9b27 | 1935 | { |
fe1952fc | 1936 | struct thread_info *ti = current_thread_info(); |
cb2c9b27 AB |
1937 | unsigned long ctrl; |
1938 | ||
fe1952fc BH |
1939 | ctrl = mfspr(SPRN_CTRLF); |
1940 | ctrl |= CTRL_RUNLATCH; | |
1941 | mtspr(SPRN_CTRLT, ctrl); | |
cb2c9b27 | 1942 | |
fae2e0fb | 1943 | ti->local_flags |= _TLF_RUNLATCH; |
cb2c9b27 AB |
1944 | } |
1945 | ||
fe1952fc | 1946 | /* Called with hard IRQs off */ |
0e37739b | 1947 | void notrace __ppc64_runlatch_off(void) |
cb2c9b27 | 1948 | { |
fe1952fc | 1949 | struct thread_info *ti = current_thread_info(); |
cb2c9b27 AB |
1950 | unsigned long ctrl; |
1951 | ||
fae2e0fb | 1952 | ti->local_flags &= ~_TLF_RUNLATCH; |
cb2c9b27 | 1953 | |
4138d653 AB |
1954 | ctrl = mfspr(SPRN_CTRLF); |
1955 | ctrl &= ~CTRL_RUNLATCH; | |
1956 | mtspr(SPRN_CTRLT, ctrl); | |
cb2c9b27 | 1957 | } |
fe1952fc | 1958 | #endif /* CONFIG_PPC64 */ |
f6a61680 | 1959 | |
d839088c AB |
1960 | unsigned long arch_align_stack(unsigned long sp) |
1961 | { | |
1962 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
1963 | sp -= get_random_int() & ~PAGE_MASK; | |
1964 | return sp & ~0xf; | |
1965 | } | |
912f9ee2 AB |
1966 | |
1967 | static inline unsigned long brk_rnd(void) | |
1968 | { | |
1969 | unsigned long rnd = 0; | |
1970 | ||
1971 | /* 8MB for 32bit, 1GB for 64bit */ | |
1972 | if (is_32bit_task()) | |
5ef11c35 | 1973 | rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT))); |
912f9ee2 | 1974 | else |
5ef11c35 | 1975 | rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT))); |
912f9ee2 AB |
1976 | |
1977 | return rnd << PAGE_SHIFT; | |
1978 | } | |
1979 | ||
1980 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
1981 | { | |
8bbde7a7 AB |
1982 | unsigned long base = mm->brk; |
1983 | unsigned long ret; | |
1984 | ||
ce7a35c7 | 1985 | #ifdef CONFIG_PPC_STD_MMU_64 |
8bbde7a7 AB |
1986 | /* |
1987 | * If we are using 1TB segments and we are allowed to randomise | |
1988 | * the heap, we can put it above 1TB so it is backed by a 1TB | |
1989 | * segment. Otherwise the heap will be in the bottom 1TB | |
1990 | * which always uses 256MB segments and this may result in a | |
caca285e AK |
1991 | * performance penalty. We don't need to worry about radix. For |
1992 | * radix, mmu_highuser_ssize remains unchanged from 256MB. | |
8bbde7a7 AB |
1993 | */ |
1994 | if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) | |
1995 | base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); | |
1996 | #endif | |
1997 | ||
1998 | ret = PAGE_ALIGN(base + brk_rnd()); | |
912f9ee2 AB |
1999 | |
2000 | if (ret < mm->brk) | |
2001 | return mm->brk; | |
2002 | ||
2003 | return ret; | |
2004 | } | |
501cb16d | 2005 |