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880860e3 PM |
1 | /* |
2 | * Performance counter support for POWER4 (GP) and POWER4+ (GQ) processors. | |
3 | * | |
4 | * Copyright 2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/perf_counter.h> | |
13 | #include <asm/reg.h> | |
14 | ||
15 | /* | |
16 | * Bits in event code for POWER4 | |
17 | */ | |
18 | #define PM_PMC_SH 12 /* PMC number (1-based) for direct events */ | |
19 | #define PM_PMC_MSK 0xf | |
20 | #define PM_UNIT_SH 8 /* TTMMUX number and setting - unit select */ | |
21 | #define PM_UNIT_MSK 0xf | |
22 | #define PM_LOWER_SH 6 | |
23 | #define PM_LOWER_MSK 1 | |
24 | #define PM_LOWER_MSKS 0x40 | |
25 | #define PM_BYTE_SH 4 /* Byte number of event bus to use */ | |
26 | #define PM_BYTE_MSK 3 | |
27 | #define PM_PMCSEL_MSK 7 | |
28 | ||
29 | /* | |
30 | * Unit code values | |
31 | */ | |
32 | #define PM_FPU 1 | |
33 | #define PM_ISU1 2 | |
34 | #define PM_IFU 3 | |
35 | #define PM_IDU0 4 | |
36 | #define PM_ISU1_ALT 6 | |
37 | #define PM_ISU2 7 | |
38 | #define PM_IFU_ALT 8 | |
39 | #define PM_LSU0 9 | |
40 | #define PM_LSU1 0xc | |
41 | #define PM_GPS 0xf | |
42 | ||
43 | /* | |
44 | * Bits in MMCR0 for POWER4 | |
45 | */ | |
46 | #define MMCR0_PMC1SEL_SH 8 | |
47 | #define MMCR0_PMC2SEL_SH 1 | |
48 | #define MMCR_PMCSEL_MSK 0x1f | |
49 | ||
50 | /* | |
51 | * Bits in MMCR1 for POWER4 | |
52 | */ | |
53 | #define MMCR1_TTM0SEL_SH 62 | |
54 | #define MMCR1_TTC0SEL_SH 61 | |
55 | #define MMCR1_TTM1SEL_SH 59 | |
56 | #define MMCR1_TTC1SEL_SH 58 | |
57 | #define MMCR1_TTM2SEL_SH 56 | |
58 | #define MMCR1_TTC2SEL_SH 55 | |
59 | #define MMCR1_TTM3SEL_SH 53 | |
60 | #define MMCR1_TTC3SEL_SH 52 | |
61 | #define MMCR1_TTMSEL_MSK 3 | |
62 | #define MMCR1_TD_CP_DBG0SEL_SH 50 | |
63 | #define MMCR1_TD_CP_DBG1SEL_SH 48 | |
64 | #define MMCR1_TD_CP_DBG2SEL_SH 46 | |
65 | #define MMCR1_TD_CP_DBG3SEL_SH 44 | |
66 | #define MMCR1_DEBUG0SEL_SH 43 | |
67 | #define MMCR1_DEBUG1SEL_SH 42 | |
68 | #define MMCR1_DEBUG2SEL_SH 41 | |
69 | #define MMCR1_DEBUG3SEL_SH 40 | |
70 | #define MMCR1_PMC1_ADDER_SEL_SH 39 | |
71 | #define MMCR1_PMC2_ADDER_SEL_SH 38 | |
72 | #define MMCR1_PMC6_ADDER_SEL_SH 37 | |
73 | #define MMCR1_PMC5_ADDER_SEL_SH 36 | |
74 | #define MMCR1_PMC8_ADDER_SEL_SH 35 | |
75 | #define MMCR1_PMC7_ADDER_SEL_SH 34 | |
76 | #define MMCR1_PMC3_ADDER_SEL_SH 33 | |
77 | #define MMCR1_PMC4_ADDER_SEL_SH 32 | |
78 | #define MMCR1_PMC3SEL_SH 27 | |
79 | #define MMCR1_PMC4SEL_SH 22 | |
80 | #define MMCR1_PMC5SEL_SH 17 | |
81 | #define MMCR1_PMC6SEL_SH 12 | |
82 | #define MMCR1_PMC7SEL_SH 7 | |
83 | #define MMCR1_PMC8SEL_SH 2 /* note bit 0 is in MMCRA for GP */ | |
84 | ||
85 | static short mmcr1_adder_bits[8] = { | |
86 | MMCR1_PMC1_ADDER_SEL_SH, | |
87 | MMCR1_PMC2_ADDER_SEL_SH, | |
88 | MMCR1_PMC3_ADDER_SEL_SH, | |
89 | MMCR1_PMC4_ADDER_SEL_SH, | |
90 | MMCR1_PMC5_ADDER_SEL_SH, | |
91 | MMCR1_PMC6_ADDER_SEL_SH, | |
92 | MMCR1_PMC7_ADDER_SEL_SH, | |
93 | MMCR1_PMC8_ADDER_SEL_SH | |
94 | }; | |
95 | ||
96 | /* | |
97 | * Bits in MMCRA | |
98 | */ | |
99 | #define MMCRA_PMC8SEL0_SH 17 /* PMC8SEL bit 0 for GP */ | |
100 | ||
101 | /* | |
102 | * Layout of constraint bits: | |
103 | * 6666555555555544444444443333333333222222222211111111110000000000 | |
104 | * 3210987654321098765432109876543210987654321098765432109876543210 | |
105 | * |[ >[ >[ >|||[ >[ >< >< >< >< ><><><><><><><><> | |
106 | * | UC1 UC2 UC3 ||| PS1 PS2 B0 B1 B2 B3 P1P2P3P4P5P6P7P8 | |
107 | * \SMPL ||\TTC3SEL | |
108 | * |\TTC_IFU_SEL | |
109 | * \TTM2SEL0 | |
110 | * | |
111 | * SMPL - SAMPLE_ENABLE constraint | |
112 | * 56: SAMPLE_ENABLE value 0x0100_0000_0000_0000 | |
113 | * | |
114 | * UC1 - unit constraint 1: can't have all three of FPU/ISU1/IDU0|ISU2 | |
115 | * 55: UC1 error 0x0080_0000_0000_0000 | |
116 | * 54: FPU events needed 0x0040_0000_0000_0000 | |
117 | * 53: ISU1 events needed 0x0020_0000_0000_0000 | |
118 | * 52: IDU0|ISU2 events needed 0x0010_0000_0000_0000 | |
119 | * | |
120 | * UC2 - unit constraint 2: can't have all three of FPU/IFU/LSU0 | |
121 | * 51: UC2 error 0x0008_0000_0000_0000 | |
122 | * 50: FPU events needed 0x0004_0000_0000_0000 | |
123 | * 49: IFU events needed 0x0002_0000_0000_0000 | |
124 | * 48: LSU0 events needed 0x0001_0000_0000_0000 | |
125 | * | |
126 | * UC3 - unit constraint 3: can't have all four of LSU0/IFU/IDU0|ISU2/ISU1 | |
127 | * 47: UC3 error 0x8000_0000_0000 | |
128 | * 46: LSU0 events needed 0x4000_0000_0000 | |
129 | * 45: IFU events needed 0x2000_0000_0000 | |
130 | * 44: IDU0|ISU2 events needed 0x1000_0000_0000 | |
131 | * 43: ISU1 events needed 0x0800_0000_0000 | |
132 | * | |
133 | * TTM2SEL0 | |
134 | * 42: 0 = IDU0 events needed | |
135 | * 1 = ISU2 events needed 0x0400_0000_0000 | |
136 | * | |
137 | * TTC_IFU_SEL | |
138 | * 41: 0 = IFU.U events needed | |
139 | * 1 = IFU.L events needed 0x0200_0000_0000 | |
140 | * | |
141 | * TTC3SEL | |
142 | * 40: 0 = LSU1.U events needed | |
143 | * 1 = LSU1.L events needed 0x0100_0000_0000 | |
144 | * | |
145 | * PS1 | |
146 | * 39: PS1 error 0x0080_0000_0000 | |
147 | * 36-38: count of events needing PMC1/2/5/6 0x0070_0000_0000 | |
148 | * | |
149 | * PS2 | |
150 | * 35: PS2 error 0x0008_0000_0000 | |
151 | * 32-34: count of events needing PMC3/4/7/8 0x0007_0000_0000 | |
152 | * | |
153 | * B0 | |
154 | * 28-31: Byte 0 event source 0xf000_0000 | |
155 | * 1 = FPU | |
156 | * 2 = ISU1 | |
157 | * 3 = IFU | |
158 | * 4 = IDU0 | |
159 | * 7 = ISU2 | |
160 | * 9 = LSU0 | |
161 | * c = LSU1 | |
162 | * f = GPS | |
163 | * | |
164 | * B1, B2, B3 | |
165 | * 24-27, 20-23, 16-19: Byte 1, 2, 3 event sources | |
166 | * | |
167 | * P8 | |
168 | * 15: P8 error 0x8000 | |
169 | * 14-15: Count of events needing PMC8 | |
170 | * | |
171 | * P1..P7 | |
172 | * 0-13: Count of events needing PMC1..PMC7 | |
173 | * | |
174 | * Note: this doesn't allow events using IFU.U to be combined with events | |
175 | * using IFU.L, though that is feasible (using TTM0 and TTM2). However | |
176 | * there are no listed events for IFU.L (they are debug events not | |
177 | * verified for performance monitoring) so this shouldn't cause a | |
178 | * problem. | |
179 | */ | |
180 | ||
181 | static struct unitinfo { | |
182 | u64 value, mask; | |
183 | int unit; | |
184 | int lowerbit; | |
185 | } p4_unitinfo[16] = { | |
186 | [PM_FPU] = { 0x44000000000000ull, 0x88000000000000ull, PM_FPU, 0 }, | |
187 | [PM_ISU1] = { 0x20080000000000ull, 0x88000000000000ull, PM_ISU1, 0 }, | |
188 | [PM_ISU1_ALT] = | |
189 | { 0x20080000000000ull, 0x88000000000000ull, PM_ISU1, 0 }, | |
190 | [PM_IFU] = { 0x02200000000000ull, 0x08820000000000ull, PM_IFU, 41 }, | |
191 | [PM_IFU_ALT] = | |
192 | { 0x02200000000000ull, 0x08820000000000ull, PM_IFU, 41 }, | |
193 | [PM_IDU0] = { 0x10100000000000ull, 0x80840000000000ull, PM_IDU0, 1 }, | |
194 | [PM_ISU2] = { 0x10140000000000ull, 0x80840000000000ull, PM_ISU2, 0 }, | |
195 | [PM_LSU0] = { 0x01400000000000ull, 0x08800000000000ull, PM_LSU0, 0 }, | |
196 | [PM_LSU1] = { 0x00000000000000ull, 0x00010000000000ull, PM_LSU1, 40 }, | |
197 | [PM_GPS] = { 0x00000000000000ull, 0x00000000000000ull, PM_GPS, 0 } | |
198 | }; | |
199 | ||
200 | static unsigned char direct_marked_event[8] = { | |
201 | (1<<2) | (1<<3), /* PMC1: PM_MRK_GRP_DISP, PM_MRK_ST_CMPL */ | |
202 | (1<<3) | (1<<5), /* PMC2: PM_THRESH_TIMEO, PM_MRK_BRU_FIN */ | |
203 | (1<<3), /* PMC3: PM_MRK_ST_CMPL_INT */ | |
204 | (1<<4) | (1<<5), /* PMC4: PM_MRK_GRP_CMPL, PM_MRK_CRU_FIN */ | |
205 | (1<<4) | (1<<5), /* PMC5: PM_MRK_GRP_TIMEO */ | |
206 | (1<<3) | (1<<4) | (1<<5), | |
207 | /* PMC6: PM_MRK_ST_GPS, PM_MRK_FXU_FIN, PM_MRK_GRP_ISSUED */ | |
208 | (1<<4) | (1<<5), /* PMC7: PM_MRK_FPU_FIN, PM_MRK_INST_FIN */ | |
209 | (1<<4), /* PMC8: PM_MRK_LSU_FIN */ | |
210 | }; | |
211 | ||
212 | /* | |
213 | * Returns 1 if event counts things relating to marked instructions | |
214 | * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not. | |
215 | */ | |
216 | static int p4_marked_instr_event(unsigned int event) | |
217 | { | |
218 | int pmc, psel, unit, byte, bit; | |
219 | unsigned int mask; | |
220 | ||
221 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | |
222 | psel = event & PM_PMCSEL_MSK; | |
223 | if (pmc) { | |
224 | if (direct_marked_event[pmc - 1] & (1 << psel)) | |
225 | return 1; | |
226 | if (psel == 0) /* add events */ | |
227 | bit = (pmc <= 4)? pmc - 1: 8 - pmc; | |
228 | else if (psel == 6) /* decode events */ | |
229 | bit = 4; | |
230 | else | |
231 | return 0; | |
232 | } else | |
233 | bit = psel; | |
234 | ||
235 | byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; | |
236 | unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; | |
237 | mask = 0; | |
238 | switch (unit) { | |
239 | case PM_LSU1: | |
240 | if (event & PM_LOWER_MSKS) | |
241 | mask = 1 << 28; /* byte 7 bit 4 */ | |
242 | else | |
243 | mask = 6 << 24; /* byte 3 bits 1 and 2 */ | |
244 | break; | |
245 | case PM_LSU0: | |
246 | /* byte 3, bit 3; byte 2 bits 0,2,3,4,5; byte 1 */ | |
247 | mask = 0x083dff00; | |
248 | } | |
249 | return (mask >> (byte * 8 + bit)) & 1; | |
250 | } | |
251 | ||
252 | static int p4_get_constraint(unsigned int event, u64 *maskp, u64 *valp) | |
253 | { | |
254 | int pmc, byte, unit, lower, sh; | |
255 | u64 mask = 0, value = 0; | |
256 | int grp = -1; | |
257 | ||
258 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | |
259 | if (pmc) { | |
260 | if (pmc > 8) | |
261 | return -1; | |
262 | sh = (pmc - 1) * 2; | |
263 | mask |= 2 << sh; | |
264 | value |= 1 << sh; | |
265 | grp = ((pmc - 1) >> 1) & 1; | |
266 | } | |
267 | unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; | |
268 | byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; | |
269 | if (unit) { | |
270 | lower = (event >> PM_LOWER_SH) & PM_LOWER_MSK; | |
271 | ||
272 | /* | |
273 | * Bus events on bytes 0 and 2 can be counted | |
274 | * on PMC1/2/5/6; bytes 1 and 3 on PMC3/4/7/8. | |
275 | */ | |
276 | if (!pmc) | |
277 | grp = byte & 1; | |
278 | ||
279 | if (!p4_unitinfo[unit].unit) | |
280 | return -1; | |
281 | mask |= p4_unitinfo[unit].mask; | |
282 | value |= p4_unitinfo[unit].value; | |
283 | sh = p4_unitinfo[unit].lowerbit; | |
284 | if (sh > 1) | |
285 | value |= (u64)lower << sh; | |
286 | else if (lower != sh) | |
287 | return -1; | |
288 | unit = p4_unitinfo[unit].unit; | |
289 | ||
290 | /* Set byte lane select field */ | |
291 | mask |= 0xfULL << (28 - 4 * byte); | |
292 | value |= (u64)unit << (28 - 4 * byte); | |
293 | } | |
294 | if (grp == 0) { | |
295 | /* increment PMC1/2/5/6 field */ | |
296 | mask |= 0x8000000000ull; | |
297 | value |= 0x1000000000ull; | |
298 | } else { | |
299 | /* increment PMC3/4/7/8 field */ | |
300 | mask |= 0x800000000ull; | |
301 | value |= 0x100000000ull; | |
302 | } | |
303 | ||
304 | /* Marked instruction events need sample_enable set */ | |
305 | if (p4_marked_instr_event(event)) { | |
306 | mask |= 1ull << 56; | |
307 | value |= 1ull << 56; | |
308 | } | |
309 | ||
310 | /* PMCSEL=6 decode events on byte 2 need sample_enable clear */ | |
311 | if (pmc && (event & PM_PMCSEL_MSK) == 6 && byte == 2) | |
312 | mask |= 1ull << 56; | |
313 | ||
314 | *maskp = mask; | |
315 | *valp = value; | |
316 | return 0; | |
317 | } | |
318 | ||
319 | static unsigned int ppc_inst_cmpl[] = { | |
320 | 0x1001, 0x4001, 0x6001, 0x7001, 0x8001 | |
321 | }; | |
322 | ||
323 | static int p4_get_alternatives(unsigned int event, unsigned int alt[]) | |
324 | { | |
325 | int i, j, na; | |
326 | ||
327 | alt[0] = event; | |
328 | na = 1; | |
329 | ||
330 | /* 2 possibilities for PM_GRP_DISP_REJECT */ | |
331 | if (event == 0x8003 || event == 0x0224) { | |
332 | alt[1] = event ^ (0x8003 ^ 0x0224); | |
333 | return 2; | |
334 | } | |
335 | ||
336 | /* 2 possibilities for PM_ST_MISS_L1 */ | |
337 | if (event == 0x0c13 || event == 0x0c23) { | |
338 | alt[1] = event ^ (0x0c13 ^ 0x0c23); | |
339 | return 2; | |
340 | } | |
341 | ||
342 | /* several possibilities for PM_INST_CMPL */ | |
343 | for (i = 0; i < ARRAY_SIZE(ppc_inst_cmpl); ++i) { | |
344 | if (event == ppc_inst_cmpl[i]) { | |
345 | for (j = 0; j < ARRAY_SIZE(ppc_inst_cmpl); ++j) | |
346 | if (j != i) | |
347 | alt[na++] = ppc_inst_cmpl[j]; | |
348 | break; | |
349 | } | |
350 | } | |
351 | ||
352 | return na; | |
353 | } | |
354 | ||
355 | static int p4_compute_mmcr(unsigned int event[], int n_ev, | |
356 | unsigned int hwc[], u64 mmcr[]) | |
357 | { | |
358 | u64 mmcr0 = 0, mmcr1 = 0, mmcra = 0; | |
359 | unsigned int pmc, unit, byte, psel, lower; | |
360 | unsigned int ttm, grp; | |
361 | unsigned int pmc_inuse = 0; | |
362 | unsigned int pmc_grp_use[2]; | |
363 | unsigned char busbyte[4]; | |
364 | unsigned char unituse[16]; | |
365 | unsigned int unitlower = 0; | |
366 | int i; | |
367 | ||
368 | if (n_ev > 8) | |
369 | return -1; | |
370 | ||
371 | /* First pass to count resource use */ | |
372 | pmc_grp_use[0] = pmc_grp_use[1] = 0; | |
373 | memset(busbyte, 0, sizeof(busbyte)); | |
374 | memset(unituse, 0, sizeof(unituse)); | |
375 | for (i = 0; i < n_ev; ++i) { | |
376 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; | |
377 | if (pmc) { | |
378 | if (pmc_inuse & (1 << (pmc - 1))) | |
379 | return -1; | |
380 | pmc_inuse |= 1 << (pmc - 1); | |
381 | /* count 1/2/5/6 vs 3/4/7/8 use */ | |
382 | ++pmc_grp_use[((pmc - 1) >> 1) & 1]; | |
383 | } | |
384 | unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK; | |
385 | byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK; | |
386 | lower = (event[i] >> PM_LOWER_SH) & PM_LOWER_MSK; | |
387 | if (unit) { | |
388 | if (!pmc) | |
389 | ++pmc_grp_use[byte & 1]; | |
390 | if (unit == 6 || unit == 8) | |
391 | /* map alt ISU1/IFU codes: 6->2, 8->3 */ | |
392 | unit = (unit >> 1) - 1; | |
393 | if (busbyte[byte] && busbyte[byte] != unit) | |
394 | return -1; | |
395 | busbyte[byte] = unit; | |
396 | lower <<= unit; | |
397 | if (unituse[unit] && lower != (unitlower & lower)) | |
398 | return -1; | |
399 | unituse[unit] = 1; | |
400 | unitlower |= lower; | |
401 | } | |
402 | } | |
403 | if (pmc_grp_use[0] > 4 || pmc_grp_use[1] > 4) | |
404 | return -1; | |
405 | ||
406 | /* | |
407 | * Assign resources and set multiplexer selects. | |
408 | * | |
409 | * Units 1,2,3 are on TTM0, 4,6,7 on TTM1, 8,10 on TTM2. | |
410 | * Each TTMx can only select one unit, but since | |
411 | * units 2 and 6 are both ISU1, and 3 and 8 are both IFU, | |
412 | * we have some choices. | |
413 | */ | |
414 | if (unituse[2] & (unituse[1] | (unituse[3] & unituse[9]))) { | |
415 | unituse[6] = 1; /* Move 2 to 6 */ | |
416 | unituse[2] = 0; | |
417 | } | |
418 | if (unituse[3] & (unituse[1] | unituse[2])) { | |
419 | unituse[8] = 1; /* Move 3 to 8 */ | |
420 | unituse[3] = 0; | |
421 | unitlower = (unitlower & ~8) | ((unitlower & 8) << 5); | |
422 | } | |
423 | /* Check only one unit per TTMx */ | |
424 | if (unituse[1] + unituse[2] + unituse[3] > 1 || | |
425 | unituse[4] + unituse[6] + unituse[7] > 1 || | |
426 | unituse[8] + unituse[9] > 1 || | |
427 | (unituse[5] | unituse[10] | unituse[11] | | |
428 | unituse[13] | unituse[14])) | |
429 | return -1; | |
430 | ||
431 | /* Set TTMxSEL fields. Note, units 1-3 => TTM0SEL codes 0-2 */ | |
432 | mmcr1 |= (u64)(unituse[3] * 2 + unituse[2]) << MMCR1_TTM0SEL_SH; | |
433 | mmcr1 |= (u64)(unituse[7] * 3 + unituse[6] * 2) << MMCR1_TTM1SEL_SH; | |
434 | mmcr1 |= (u64)unituse[9] << MMCR1_TTM2SEL_SH; | |
435 | ||
436 | /* Set TTCxSEL fields. */ | |
437 | if (unitlower & 0xe) | |
438 | mmcr1 |= 1ull << MMCR1_TTC0SEL_SH; | |
439 | if (unitlower & 0xf0) | |
440 | mmcr1 |= 1ull << MMCR1_TTC1SEL_SH; | |
441 | if (unitlower & 0xf00) | |
442 | mmcr1 |= 1ull << MMCR1_TTC2SEL_SH; | |
443 | if (unitlower & 0x7000) | |
444 | mmcr1 |= 1ull << MMCR1_TTC3SEL_SH; | |
445 | ||
446 | /* Set byte lane select fields. */ | |
447 | for (byte = 0; byte < 4; ++byte) { | |
448 | unit = busbyte[byte]; | |
449 | if (!unit) | |
450 | continue; | |
451 | if (unit == 0xf) { | |
452 | /* special case for GPS */ | |
453 | mmcr1 |= 1ull << (MMCR1_DEBUG0SEL_SH - byte); | |
454 | } else { | |
455 | if (!unituse[unit]) | |
456 | ttm = unit - 1; /* 2->1, 3->2 */ | |
457 | else | |
458 | ttm = unit >> 2; | |
459 | mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2*byte); | |
460 | } | |
461 | } | |
462 | ||
463 | /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */ | |
464 | for (i = 0; i < n_ev; ++i) { | |
465 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; | |
466 | unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK; | |
467 | byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK; | |
468 | psel = event[i] & PM_PMCSEL_MSK; | |
469 | if (!pmc) { | |
470 | /* Bus event or 00xxx direct event (off or cycles) */ | |
471 | if (unit) | |
472 | psel |= 0x10 | ((byte & 2) << 2); | |
473 | for (pmc = 0; pmc < 8; ++pmc) { | |
474 | if (pmc_inuse & (1 << pmc)) | |
475 | continue; | |
476 | grp = (pmc >> 1) & 1; | |
477 | if (unit) { | |
478 | if (grp == (byte & 1)) | |
479 | break; | |
480 | } else if (pmc_grp_use[grp] < 4) { | |
481 | ++pmc_grp_use[grp]; | |
482 | break; | |
483 | } | |
484 | } | |
485 | pmc_inuse |= 1 << pmc; | |
486 | } else { | |
487 | /* Direct event */ | |
488 | --pmc; | |
489 | if (psel == 0 && (byte & 2)) | |
490 | /* add events on higher-numbered bus */ | |
491 | mmcr1 |= 1ull << mmcr1_adder_bits[pmc]; | |
492 | else if (psel == 6 && byte == 3) | |
493 | /* seem to need to set sample_enable here */ | |
494 | mmcra |= MMCRA_SAMPLE_ENABLE; | |
495 | psel |= 8; | |
496 | } | |
497 | if (pmc <= 1) | |
498 | mmcr0 |= psel << (MMCR0_PMC1SEL_SH - 7 * pmc); | |
499 | else | |
500 | mmcr1 |= psel << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2)); | |
501 | if (pmc == 7) /* PMC8 */ | |
502 | mmcra |= (psel & 1) << MMCRA_PMC8SEL0_SH; | |
503 | hwc[i] = pmc; | |
504 | if (p4_marked_instr_event(event[i])) | |
505 | mmcra |= MMCRA_SAMPLE_ENABLE; | |
506 | } | |
507 | ||
508 | if (pmc_inuse & 1) | |
509 | mmcr0 |= MMCR0_PMC1CE; | |
510 | if (pmc_inuse & 0xfe) | |
511 | mmcr0 |= MMCR0_PMCjCE; | |
512 | ||
513 | mmcra |= 0x2000; /* mark only one IOP per PPC instruction */ | |
514 | ||
515 | /* Return MMCRx values */ | |
516 | mmcr[0] = mmcr0; | |
517 | mmcr[1] = mmcr1; | |
518 | mmcr[2] = mmcra; | |
519 | return 0; | |
520 | } | |
521 | ||
522 | static void p4_disable_pmc(unsigned int pmc, u64 mmcr[]) | |
523 | { | |
524 | /* | |
525 | * Setting the PMCxSEL field to 0 disables PMC x. | |
526 | * (Note that pmc is 0-based here, not 1-based.) | |
527 | */ | |
528 | if (pmc <= 1) { | |
529 | mmcr[0] &= ~(0x1fUL << (MMCR0_PMC1SEL_SH - 7 * pmc)); | |
530 | } else { | |
531 | mmcr[1] &= ~(0x1fUL << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2))); | |
532 | if (pmc == 7) | |
533 | mmcr[2] &= ~(1UL << MMCRA_PMC8SEL0_SH); | |
534 | } | |
535 | } | |
536 | ||
537 | static int p4_generic_events[] = { | |
538 | [PERF_COUNT_CPU_CYCLES] = 7, | |
539 | [PERF_COUNT_INSTRUCTIONS] = 0x1001, | |
540 | [PERF_COUNT_CACHE_REFERENCES] = 0x8c10, /* PM_LD_REF_L1 */ | |
541 | [PERF_COUNT_CACHE_MISSES] = 0x3c10, /* PM_LD_MISS_L1 */ | |
542 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x330, /* PM_BR_ISSUED */ | |
543 | [PERF_COUNT_BRANCH_MISSES] = 0x331, /* PM_BR_MPRED_CR */ | |
544 | }; | |
545 | ||
546 | struct power_pmu power4_pmu = { | |
547 | .n_counter = 8, | |
548 | .max_alternatives = 5, | |
549 | .add_fields = 0x0000001100005555ull, | |
550 | .test_adder = 0x0011083300000000ull, | |
551 | .compute_mmcr = p4_compute_mmcr, | |
552 | .get_constraint = p4_get_constraint, | |
553 | .get_alternatives = p4_get_alternatives, | |
554 | .disable_pmc = p4_disable_pmc, | |
555 | .n_generic = ARRAY_SIZE(p4_generic_events), | |
556 | .generic_events = p4_generic_events, | |
557 | }; |