powerpc/32s: Setup the early hash table at all time.
[linux-block.git] / arch / powerpc / kernel / pmc.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 2/*
f7f6f4fe 3 * arch/powerpc/kernel/pmc.c
1da177e4
LT
4 *
5 * Copyright (C) 2004 David Gibson, IBM Corporation.
f7f6f4fe
DG
6 * Includes code formerly from arch/ppc/kernel/perfmon.c:
7 * Author: Andy Fleming
8 * Copyright (c) 2004 Freescale Semiconductor, Inc
1da177e4
LT
9 */
10
1da177e4 11#include <linux/errno.h>
50af5ead 12#include <linux/bug.h>
1da177e4 13#include <linux/spinlock.h>
4b16f8e2 14#include <linux/export.h>
1da177e4
LT
15
16#include <asm/processor.h>
6529c13d 17#include <asm/cputable.h>
1da177e4
LT
18#include <asm/pmc.h>
19
177e9ea4
AB
20#ifndef MMCR0_PMAO
21#define MMCR0_PMAO 0
f7f6f4fe
DG
22#endif
23
1da177e4
LT
24static void dummy_perf(struct pt_regs *regs)
25{
39aef685 26#if defined(CONFIG_FSL_EMB_PERFMON)
1bd2e5ae 27 mtpmr(PMRN_PMGC0, mfpmr(PMRN_PMGC0) & ~PMGC0_PMIE);
d7cceda9 28#elif defined(CONFIG_PPC64) || defined(CONFIG_PPC_BOOK3S_32)
6529c13d 29 if (cur_cpu_spec->pmc_type == PPC_PMC_IBM)
177e9ea4 30 mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~(MMCR0_PMXE|MMCR0_PMAO));
f7f6f4fe 31#else
1bd2e5ae 32 mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~MMCR0_PMXE);
f7f6f4fe 33#endif
1bd2e5ae
OJ
34}
35
1da177e4 36
071c06cb 37static DEFINE_RAW_SPINLOCK(pmc_owner_lock);
1da177e4
LT
38static void *pmc_owner_caller; /* mostly for debugging */
39perf_irq_t perf_irq = dummy_perf;
40
41int reserve_pmc_hardware(perf_irq_t new_perf_irq)
42{
43 int err = 0;
44
071c06cb 45 raw_spin_lock(&pmc_owner_lock);
1da177e4
LT
46
47 if (pmc_owner_caller) {
48 printk(KERN_WARNING "reserve_pmc_hardware: "
49 "PMC hardware busy (reserved by caller %p)\n",
50 pmc_owner_caller);
51 err = -EBUSY;
52 goto out;
53 }
54
55 pmc_owner_caller = __builtin_return_address(0);
dd6c89f6 56 perf_irq = new_perf_irq ? new_perf_irq : dummy_perf;
1da177e4
LT
57
58 out:
071c06cb 59 raw_spin_unlock(&pmc_owner_lock);
1da177e4
LT
60 return err;
61}
62EXPORT_SYMBOL_GPL(reserve_pmc_hardware);
63
64void release_pmc_hardware(void)
65{
071c06cb 66 raw_spin_lock(&pmc_owner_lock);
1da177e4
LT
67
68 WARN_ON(! pmc_owner_caller);
69
70 pmc_owner_caller = NULL;
71 perf_irq = dummy_perf;
72
071c06cb 73 raw_spin_unlock(&pmc_owner_lock);
1da177e4
LT
74}
75EXPORT_SYMBOL_GPL(release_pmc_hardware);
180a3362 76
f7f6f4fe 77#ifdef CONFIG_PPC64
180a3362
ME
78void power4_enable_pmcs(void)
79{
80 unsigned long hid0;
81
b5bbeb23 82 hid0 = mfspr(SPRN_HID0);
180a3362
ME
83 hid0 |= 1UL << (63 - 20);
84
85 /* POWER4 requires the following sequence */
86 asm volatile(
87 "sync\n"
88 "mtspr %1, %0\n"
89 "mfspr %0, %1\n"
90 "mfspr %0, %1\n"
91 "mfspr %0, %1\n"
92 "mfspr %0, %1\n"
93 "mfspr %0, %1\n"
94 "mfspr %0, %1\n"
b5bbeb23 95 "isync" : "=&r" (hid0) : "i" (SPRN_HID0), "0" (hid0):
180a3362
ME
96 "memory");
97}
f7f6f4fe 98#endif /* CONFIG_PPC64 */