[linux-2.6-block.git] / arch / powerpc / kernel / pci_of_scan.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Helper routines to scan the device tree for PCI devices and busses
 *
 * Migrated out of PowerPC architecture pci_64.c file by Grant Likely
 * <grant.likely@secretlab.ca> so that these routines are available for
 * 32 bit also.
 *
 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
 *   Rework, based on alpha PCI code.
 * Copyright (c) 2009 Secret Lab Technologies Ltd.
 */

#include <linux/pci.h>
#include <linux/export.h>
#include <linux/of.h>
#include <asm/pci-bridge.h>

/**
 * get_int_prop - Decode a u32 from a device tree property
 */
static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
{
	const __be32 *prop;
	int len;

	prop = of_get_property(np, name, &len);
	if (prop && len >= 4)
		return of_read_number(prop, 1);
	return def;
}

/**
 * pci_parse_of_flags - Parse the flags cell of a device tree PCI address
 * @addr0: value of 1st cell of a device tree PCI address.
 * @bridge: Set this flag if the address is from a bridge 'ranges' property
 *
 * PCI Bus Binding to IEEE Std 1275-1994
 *
 * Bit#            33222222 22221111 11111100 00000000
 *                 10987654 32109876 54321098 76543210
 * phys.hi cell:   npt000ss bbbbbbbb dddddfff rrrrrrrr
 * phys.mid cell:  hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
 * phys.lo cell:   llllllll llllllll llllllll llllllll
 *
 * where:
 * n        is 0 if the address is relocatable, 1 otherwise
 * p        is 1 if the addressable region is "prefetchable", 0 otherwise
 * t        is 1 if the address is aliased (for non-relocatable I/O),
 *          below 1 MB (for Memory),or below 64 KB (for relocatable I/O).
 * ss       is the space code, denoting the address space:
 *              00 denotes Configuration Space
 *              01 denotes I/O Space
 *              10 denotes 32-bit-address Memory Space
 *              11 denotes 64-bit-address Memory Space
 * bbbbbbbb is the 8-bit Bus Number
 * ddddd    is the 5-bit Device Number
 * fff      is the 3-bit Function Number
 * rrrrrrrr is the 8-bit Register Number
 */
#define OF_PCI_ADDR0_SPACE(ss)		(((ss)&3)<<24)
#define OF_PCI_ADDR0_SPACE_CFG		OF_PCI_ADDR0_SPACE(0)
#define OF_PCI_ADDR0_SPACE_IO		OF_PCI_ADDR0_SPACE(1)
#define OF_PCI_ADDR0_SPACE_MMIO32	OF_PCI_ADDR0_SPACE(2)
#define OF_PCI_ADDR0_SPACE_MMIO64	OF_PCI_ADDR0_SPACE(3)
#define OF_PCI_ADDR0_SPACE_MASK		OF_PCI_ADDR0_SPACE(3)
#define OF_PCI_ADDR0_RELOC		(1UL<<31)
#define OF_PCI_ADDR0_PREFETCH		(1UL<<30)
#define OF_PCI_ADDR0_ALIAS		(1UL<<29)
#define OF_PCI_ADDR0_BUS		0x00FF0000UL
#define OF_PCI_ADDR0_DEV		0x0000F800UL
#define OF_PCI_ADDR0_FN			0x00000700UL
#define OF_PCI_ADDR0_BARREG		0x000000FFUL

unsigned int pci_parse_of_flags(u32 addr0, int bridge)
{
	unsigned int flags = 0, as = addr0 & OF_PCI_ADDR0_SPACE_MASK;

	if (as == OF_PCI_ADDR0_SPACE_MMIO32 || as == OF_PCI_ADDR0_SPACE_MMIO64) {
		flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;

		if (as == OF_PCI_ADDR0_SPACE_MMIO64)
			flags |= PCI_BASE_ADDRESS_MEM_TYPE_64 | IORESOURCE_MEM_64;

		if (addr0 & OF_PCI_ADDR0_ALIAS)
			flags |= PCI_BASE_ADDRESS_MEM_TYPE_1M;

		if (addr0 & OF_PCI_ADDR0_PREFETCH)
			flags |= IORESOURCE_PREFETCH |
				 PCI_BASE_ADDRESS_MEM_PREFETCH;

		/* Note: We don't know whether the ROM has been left enabled
		 * by the firmware or not. We mark it as disabled (ie, we do
		 * not set the IORESOURCE_ROM_ENABLE flag) for now rather than
		 * do a config space read, it will be force-enabled if needed
		 */
		if (!bridge && (addr0 & OF_PCI_ADDR0_BARREG) == PCI_ROM_ADDRESS)
			flags |= IORESOURCE_READONLY;

	} else if (as == OF_PCI_ADDR0_SPACE_IO)
		flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;

	if (flags)
		flags |= IORESOURCE_SIZEALIGN;

	return flags;
}

/**
 * of_pci_parse_addrs - Parse PCI addresses assigned in the device tree node
 * @node: device tree node for the PCI device
 * @dev: pci_dev structure for the device
 *
 * This function parses the 'assigned-addresses' property of a PCI devices'
 * device tree node and writes them into the associated pci_dev structure.
 */
static void of_pci_parse_addrs(struct device_node *node, struct pci_dev *dev)
{
	u64 base, size;
	unsigned int flags;
	struct pci_bus_region region;
	struct resource *res;
	const __be32 *addrs;
	u32 i;
	int proplen;
	bool mark_unset = false;

	addrs = of_get_property(node, "assigned-addresses", &proplen);
	if (!addrs || !proplen) {
		addrs = of_get_property(node, "reg", &proplen);
		if (!addrs || !proplen)
			return;
		mark_unset = true;
	}

	pr_debug("    parse addresses (%d bytes) @ %p\n", proplen, addrs);
	for (; proplen >= 20; proplen -= 20, addrs += 5) {
		flags = pci_parse_of_flags(of_read_number(addrs, 1), 0);
		if (!flags)
			continue;
		base = of_read_number(&addrs[1], 2);
		size = of_read_number(&addrs[3], 2);
		if (!size)
			continue;
		i = of_read_number(addrs, 1) & 0xff;
		pr_debug("  base: %llx, size: %llx, i: %x\n",
			 (unsigned long long)base,
			 (unsigned long long)size, i);

		if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
			res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
		} else if (i == dev->rom_base_reg) {
			res = &dev->resource[PCI_ROM_RESOURCE];
			flags |= IORESOURCE_READONLY;
		} else {
			printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
			continue;
		}
		res->flags = flags;
		if (mark_unset)
			res->flags |= IORESOURCE_UNSET;
		res->name = pci_name(dev);
		region.start = base;
		region.end = base + size - 1;
		pcibios_bus_to_resource(dev->bus, res, &region);
	}
}

/**
 * of_create_pci_dev - Given a device tree node on a pci bus, create a pci_dev
 * @node: device tree node pointer
 * @bus: bus the device is sitting on
 * @devfn: PCI function number, extracted from device tree by caller.
 */
struct pci_dev *of_create_pci_dev(struct device_node *node,
				 struct pci_bus *bus, int devfn)
{
	struct pci_dev *dev;

	dev = pci_alloc_dev(bus);
	if (!dev)
		return NULL;

	pr_debug("    create device, devfn: %x, type: %s\n", devfn,
		 of_node_get_device_type(node));

	dev->dev.of_node = of_node_get(node);
	dev->dev.parent = bus->bridge;
	dev->dev.bus = &pci_bus_type;
	dev->devfn = devfn;
	dev->multifunction = 0;		/* maybe a lie? */
	dev->needs_freset = 0;		/* pcie fundamental reset required */
	set_pcie_port_type(dev);

	pci_dev_assign_slot(dev);
	dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
	dev->device = get_int_prop(node, "device-id", 0xffff);
	dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
	dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);

	dev->cfg_size = pci_cfg_space_size(dev);

	dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
		dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
	dev->class = get_int_prop(node, "class-code", 0);
	dev->revision = get_int_prop(node, "revision-id", 0);

	pr_debug("    class: 0x%x\n", dev->class);
	pr_debug("    revision: 0x%x\n", dev->revision);

	dev->current_state = PCI_UNKNOWN;	/* unknown power state */
	dev->error_state = pci_channel_io_normal;
	dev->dma_mask = 0xffffffff;

	/* Early fixups, before probing the BARs */
	pci_fixup_device(pci_fixup_early, dev);

	if (of_node_is_type(node, "pci") || of_node_is_type(node, "pciex")) {
		/* a PCI-PCI bridge */
		dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
		dev->rom_base_reg = PCI_ROM_ADDRESS1;
		set_pcie_hotplug_bridge(dev);
	} else if (of_node_is_type(node, "cardbus")) {
		dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
	} else {
		dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
		dev->rom_base_reg = PCI_ROM_ADDRESS;
		/* Maybe do a default OF mapping here */
		dev->irq = 0;
	}

	of_pci_parse_addrs(node, dev);

	pr_debug("    adding to system ...\n");

	pci_device_add(dev, bus);

	return dev;
}
EXPORT_SYMBOL(of_create_pci_dev);

/**
 * of_scan_pci_bridge - Set up a PCI bridge and scan for child nodes
 * @dev: pci_dev structure for the bridge
 *
 * of_scan_bus() calls this routine for each PCI bridge that it finds, and
 * this routine in turn call of_scan_bus() recursively to scan for more child
 * devices.
 */
void of_scan_pci_bridge(struct pci_dev *dev)
{
	struct device_node *node = dev->dev.of_node;
	struct pci_bus *bus;
	struct pci_controller *phb;
	const __be32 *busrange, *ranges;
	int len, i, mode;
	struct pci_bus_region region;
	struct resource *res;
	unsigned int flags;
	u64 size;

	pr_debug("of_scan_pci_bridge(%pOF)\n", node);

	/* parse bus-range property */
	busrange = of_get_property(node, "bus-range", &len);
	if (busrange == NULL || len != 8) {
		printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %pOF\n",
		       node);
		return;
	}
	ranges = of_get_property(node, "ranges", &len);
	if (ranges == NULL) {
		printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %pOF\n",
		       node);
		return;
	}

	bus = pci_find_bus(pci_domain_nr(dev->bus),
			   of_read_number(busrange, 1));
	if (!bus) {
		bus = pci_add_new_bus(dev->bus, dev,
				      of_read_number(busrange, 1));
		if (!bus) {
			printk(KERN_ERR "Failed to create pci bus for %pOF\n",
			       node);
			return;
		}
	}

	bus->primary = dev->bus->number;
	pci_bus_insert_busn_res(bus, of_read_number(busrange, 1),
				of_read_number(busrange+1, 1));
	bus->bridge_ctl = 0;

	/* parse ranges property */
	/* PCI #address-cells == 3 and #size-cells == 2 always */
	res = &dev->resource[PCI_BRIDGE_RESOURCES];
	for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
		res->flags = 0;
		bus->resource[i] = res;
		++res;
	}
	i = 1;
	for (; len >= 32; len -= 32, ranges += 8) {
		flags = pci_parse_of_flags(of_read_number(ranges, 1), 1);
		size = of_read_number(&ranges[6], 2);
		if (flags == 0 || size == 0)
			continue;
		if (flags & IORESOURCE_IO) {
			res = bus->resource[0];
			if (res->flags) {
				printk(KERN_ERR "PCI: ignoring extra I/O range"
				       " for bridge %pOF\n", node);
				continue;
			}
		} else {
			if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
				printk(KERN_ERR "PCI: too many memory ranges"
				       " for bridge %pOF\n", node);
				continue;
			}
			res = bus->resource[i];
			++i;
		}
		res->flags = flags;
		region.start = of_read_number(&ranges[1], 2);
		region.end = region.start + size - 1;
		pcibios_bus_to_resource(dev->bus, res, &region);
	}
	sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
		bus->number);
	pr_debug("    bus name: %s\n", bus->name);

	phb = pci_bus_to_host(bus);

	mode = PCI_PROBE_NORMAL;
	if (phb->controller_ops.probe_mode)
		mode = phb->controller_ops.probe_mode(bus);
	pr_debug("    probe mode: %d\n", mode);

	if (mode == PCI_PROBE_DEVTREE)
		of_scan_bus(node, bus);
	else if (mode == PCI_PROBE_NORMAL)
		pci_scan_child_bus(bus);
}
EXPORT_SYMBOL(of_scan_pci_bridge);

static struct pci_dev *of_scan_pci_dev(struct pci_bus *bus,
			    struct device_node *dn)
{
	struct pci_dev *dev = NULL;
	const __be32 *reg;
	int reglen, devfn;
#ifdef CONFIG_EEH
	struct eeh_dev *edev = pdn_to_eeh_dev(PCI_DN(dn));
#endif

	pr_debug("  * %pOF\n", dn);
	if (!of_device_is_available(dn))
		return NULL;

	reg = of_get_property(dn, "reg", &reglen);
	if (reg == NULL || reglen < 20)
		return NULL;
	devfn = (of_read_number(reg, 1) >> 8) & 0xff;

	/* Check if the PCI device is already there */
	dev = pci_get_slot(bus, devfn);
	if (dev) {
		pci_dev_put(dev);
		return dev;
	}

	/* Device removed permanently ? */
#ifdef CONFIG_EEH
	if (edev && (edev->mode & EEH_DEV_REMOVED))
		return NULL;
#endif

	/* create a new pci_dev for this device */
	dev = of_create_pci_dev(dn, bus, devfn);
	if (!dev)
		return NULL;

	pr_debug("  dev header type: %x\n", dev->hdr_type);
	return dev;
}

/**
 * __of_scan_bus - given a PCI bus node, setup bus and scan for child devices
 * @node: device tree node for the PCI bus
 * @bus: pci_bus structure for the PCI bus
 * @rescan_existing: Flag indicating bus has already been set up
 */
static void __of_scan_bus(struct device_node *node, struct pci_bus *bus,
			  int rescan_existing)
{
	struct device_node *child;
	struct pci_dev *dev;

	pr_debug("of_scan_bus(%pOF) bus no %d...\n",
		 node, bus->number);

	/* Scan direct children */
	for_each_child_of_node(node, child) {
		dev = of_scan_pci_dev(bus, child);
		if (!dev)
			continue;
		pr_debug("    dev header type: %x\n", dev->hdr_type);
	}

	/* Apply all fixups necessary. We don't fixup the bus "self"
	 * for an existing bridge that is being rescanned
	 */
	if (!rescan_existing)
		pcibios_setup_bus_self(bus);

	/* Now scan child busses */
	for_each_pci_bridge(dev, bus)
		of_scan_pci_bridge(dev);
}

/**
 * of_scan_bus - given a PCI bus node, setup bus and scan for child devices
 * @node: device tree node for the PCI bus
 * @bus: pci_bus structure for the PCI bus
 */
void of_scan_bus(struct device_node *node, struct pci_bus *bus)
{
	__of_scan_bus(node, bus, 0);
}
EXPORT_SYMBOL_GPL(of_scan_bus);

/**
 * of_rescan_bus - given a PCI bus node, scan for child devices
 * @node: device tree node for the PCI bus
 * @bus: pci_bus structure for the PCI bus
 *
 * Same as of_scan_bus, but for a pci_bus structure that has already been
 * setup.
 */
void of_rescan_bus(struct device_node *node, struct pci_bus *bus)
{
	__of_scan_bus(node, bus, 1);
}
EXPORT_SYMBOL_GPL(of_rescan_bus);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
fbe65447 GL	2	/*
	3	* Helper routines to scan the device tree for PCI devices and busses
	4	*
	5	* Migrated out of PowerPC architecture pci_64.c file by Grant Likely
	6	* <grant.likely@secretlab.ca> so that these routines are available for
	7	* 32 bit also.
	8	*
	9	* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
	10	* Rework, based on alpha PCI code.
	11	* Copyright (c) 2009 Secret Lab Technologies Ltd.
fbe65447 GL	12	*/
	13
	14	#include <linux/pci.h>
66b15db6	15	#include <linux/export.h>
e6f6390a	16	#include <linux/of.h>
fbe65447	17	#include <asm/pci-bridge.h>
fbe65447 GL	18
	19	/**
	20	* get_int_prop - Decode a u32 from a device tree property
	21	*/
	22	static u32 get_int_prop(struct device_node np, const char name, u32 def)
	23	{
a795dc54	24	const __be32 *prop;
fbe65447 GL	25	int len;
	26
	27	prop = of_get_property(np, name, &len);
	28	if (prop && len >= 4)
a795dc54	29	return of_read_number(prop, 1);
fbe65447 GL	30	return def;
	31	}
	32
	33	/**
	34	* pci_parse_of_flags - Parse the flags cell of a device tree PCI address
	35	* @addr0: value of 1st cell of a device tree PCI address.
	36	* @bridge: Set this flag if the address is from a bridge 'ranges' property
bc605cd7 AK	37	*
	38	* PCI Bus Binding to IEEE Std 1275-1994
	39	*
	40	* Bit# 33222222 22221111 11111100 00000000
	41	* 10987654 32109876 54321098 76543210
	42	* phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr
	43	* phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
	44	* phys.lo cell: llllllll llllllll llllllll llllllll
	45	*
	46	* where:
	47	* n is 0 if the address is relocatable, 1 otherwise
	48	* p is 1 if the addressable region is "prefetchable", 0 otherwise
	49	* t is 1 if the address is aliased (for non-relocatable I/O),
	50	* below 1 MB (for Memory),or below 64 KB (for relocatable I/O).
	51	* ss is the space code, denoting the address space:
	52	* 00 denotes Configuration Space
	53	* 01 denotes I/O Space
	54	* 10 denotes 32-bit-address Memory Space
	55	* 11 denotes 64-bit-address Memory Space
	56	* bbbbbbbb is the 8-bit Bus Number
	57	* ddddd is the 5-bit Device Number
	58	* fff is the 3-bit Function Number
	59	* rrrrrrrr is the 8-bit Register Number
fbe65447	60	*/
bc605cd7 AK	61	#define OF_PCI_ADDR0_SPACE(ss) (((ss)&3)<<24)
	62	#define OF_PCI_ADDR0_SPACE_CFG OF_PCI_ADDR0_SPACE(0)
	63	#define OF_PCI_ADDR0_SPACE_IO OF_PCI_ADDR0_SPACE(1)
	64	#define OF_PCI_ADDR0_SPACE_MMIO32 OF_PCI_ADDR0_SPACE(2)
	65	#define OF_PCI_ADDR0_SPACE_MMIO64 OF_PCI_ADDR0_SPACE(3)
	66	#define OF_PCI_ADDR0_SPACE_MASK OF_PCI_ADDR0_SPACE(3)
	67	#define OF_PCI_ADDR0_RELOC (1UL<<31)
	68	#define OF_PCI_ADDR0_PREFETCH (1UL<<30)
	69	#define OF_PCI_ADDR0_ALIAS (1UL<<29)
	70	#define OF_PCI_ADDR0_BUS 0x00FF0000UL
	71	#define OF_PCI_ADDR0_DEV 0x0000F800UL
	72	#define OF_PCI_ADDR0_FN 0x00000700UL
	73	#define OF_PCI_ADDR0_BARREG 0x000000FFUL
	74
fc5f6221	75	unsigned int pci_parse_of_flags(u32 addr0, int bridge)
fbe65447	76	{
bc605cd7	77	unsigned int flags = 0, as = addr0 & OF_PCI_ADDR0_SPACE_MASK;
fbe65447	78
bc605cd7	79	if (as == OF_PCI_ADDR0_SPACE_MMIO32 \|\| as == OF_PCI_ADDR0_SPACE_MMIO64) {
fbe65447	80	flags = IORESOURCE_MEM \| PCI_BASE_ADDRESS_SPACE_MEMORY;
bc605cd7 AK	81
	82	if (as == OF_PCI_ADDR0_SPACE_MMIO64)
	83	flags \|= PCI_BASE_ADDRESS_MEM_TYPE_64 \| IORESOURCE_MEM_64;
	84
	85	if (addr0 & OF_PCI_ADDR0_ALIAS)
	86	flags \|= PCI_BASE_ADDRESS_MEM_TYPE_1M;
	87
	88	if (addr0 & OF_PCI_ADDR0_PREFETCH)
	89	flags \|= IORESOURCE_PREFETCH \|
	90	PCI_BASE_ADDRESS_MEM_PREFETCH;
	91
fbe65447 GL	92	/* Note: We don't know whether the ROM has been left enabled
	93	* by the firmware or not. We mark it as disabled (ie, we do
	94	* not set the IORESOURCE_ROM_ENABLE flag) for now rather than
	95	* do a config space read, it will be force-enabled if needed
	96	*/
bc605cd7	97	if (!bridge && (addr0 & OF_PCI_ADDR0_BARREG) == PCI_ROM_ADDRESS)
fbe65447	98	flags \|= IORESOURCE_READONLY;
bc605cd7 AK	99
bc605cd7 AK	100	} else if (as == OF_PCI_ADDR0_SPACE_IO)
fbe65447	101	flags = IORESOURCE_IO \| PCI_BASE_ADDRESS_SPACE_IO;
bc605cd7	102
fbe65447 GL	103	if (flags)
fbe65447 GL	104	flags \|= IORESOURCE_SIZEALIGN;
bc605cd7	105
fbe65447 GL	106	return flags;
	107	}
	108
	109	/**
	110	* of_pci_parse_addrs - Parse PCI addresses assigned in the device tree node
	111	* @node: device tree node for the PCI device
	112	* @dev: pci_dev structure for the device
	113	*
	114	* This function parses the 'assigned-addresses' property of a PCI devices'
	115	* device tree node and writes them into the associated pci_dev structure.
	116	*/
	117	static void of_pci_parse_addrs(struct device_node node, struct pci_dev dev)
	118	{
	119	u64 base, size;
	120	unsigned int flags;
39aa146a	121	struct pci_bus_region region;
fbe65447	122	struct resource *res;
a795dc54	123	const __be32 *addrs;
fbe65447 GL	124	u32 i;
fbe65447 GL	125	int proplen;
dead1c84	126	bool mark_unset = false;
fbe65447 GL	127
fbe65447 GL	128	addrs = of_get_property(node, "assigned-addresses", &proplen);
dead1c84 AK	129	if (!addrs \|\| !proplen) {
	130	addrs = of_get_property(node, "reg", &proplen);
	131	if (!addrs \|\| !proplen)
	132	return;
	133	mark_unset = true;
	134	}
	135
fbe65447 GL	136	pr_debug(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
fbe65447 GL	137	for (; proplen >= 20; proplen -= 20, addrs += 5) {
a795dc54	138	flags = pci_parse_of_flags(of_read_number(addrs, 1), 0);
fbe65447 GL	139	if (!flags)
	140	continue;
	141	base = of_read_number(&addrs[1], 2);
	142	size = of_read_number(&addrs[3], 2);
	143	if (!size)
	144	continue;
a795dc54	145	i = of_read_number(addrs, 1) & 0xff;
fbe65447 GL	146	pr_debug(" base: %llx, size: %llx, i: %x\n",
	147	(unsigned long long)base,
	148	(unsigned long long)size, i);
	149
	150	if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
	151	res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
	152	} else if (i == dev->rom_base_reg) {
	153	res = &dev->resource[PCI_ROM_RESOURCE];
92b19ff5	154	flags \|= IORESOURCE_READONLY;
fbe65447 GL	155	} else {
	156	printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
	157	continue;
	158	}
fbe65447	159	res->flags = flags;
dead1c84 AK	160	if (mark_unset)
dead1c84 AK	161	res->flags \|= IORESOURCE_UNSET;
fbe65447	162	res->name = pci_name(dev);
39aa146a BH	163	region.start = base;
39aa146a BH	164	region.end = base + size - 1;
fc279850	165	pcibios_bus_to_resource(dev->bus, res, &region);
fbe65447 GL	166	}
	167	}
	168
	169	/**
	170	* of_create_pci_dev - Given a device tree node on a pci bus, create a pci_dev
	171	* @node: device tree node pointer
	172	* @bus: bus the device is sitting on
	173	* @devfn: PCI function number, extracted from device tree by caller.
	174	*/
	175	struct pci_dev of_create_pci_dev(struct device_node node,
	176	struct pci_bus *bus, int devfn)
	177	{
	178	struct pci_dev *dev;
fbe65447	179
8b1fce04	180	dev = pci_alloc_dev(bus);
fbe65447 GL	181	if (!dev)
fbe65447 GL	182	return NULL;
fbe65447	183
e5480bdc RH	184	pr_debug(" create device, devfn: %x, type: %s\n", devfn,
e5480bdc RH	185	of_node_get_device_type(node));
fbe65447	186
b5d937de	187	dev->dev.of_node = of_node_get(node);
fbe65447 GL	188	dev->dev.parent = bus->bridge;
	189	dev->dev.bus = &pci_bus_type;
	190	dev->devfn = devfn;
	191	dev->multifunction = 0; /* maybe a lie? */
4406c56d	192	dev->needs_freset = 0; /* pcie fundamental reset required */
bb209c82	193	set_pcie_port_type(dev);
fbe65447	194
017ffe64	195	pci_dev_assign_slot(dev);
fbe65447 GL	196	dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
	197	dev->device = get_int_prop(node, "device-id", 0xffff);
	198	dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
	199	dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
	200
	201	dev->cfg_size = pci_cfg_space_size(dev);
	202
	203	dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
	204	dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
	205	dev->class = get_int_prop(node, "class-code", 0);
	206	dev->revision = get_int_prop(node, "revision-id", 0);
	207
	208	pr_debug(" class: 0x%x\n", dev->class);
	209	pr_debug(" revision: 0x%x\n", dev->revision);
	210
c2defb5f	211	dev->current_state = PCI_UNKNOWN; /* unknown power state */
fbe65447 GL	212	dev->error_state = pci_channel_io_normal;
	213	dev->dma_mask = 0xffffffff;
	214
94afc008 BH	215	/* Early fixups, before probing the BARs */
	216	pci_fixup_device(pci_fixup_early, dev);
	217
e5480bdc	218	if (of_node_is_type(node, "pci") \|\| of_node_is_type(node, "pciex")) {
fbe65447 GL	219	/* a PCI-PCI bridge */
	220	dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
	221	dev->rom_base_reg = PCI_ROM_ADDRESS1;
bb209c82	222	set_pcie_hotplug_bridge(dev);
e5480bdc	223	} else if (of_node_is_type(node, "cardbus")) {
fbe65447 GL	224	dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
	225	} else {
	226	dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
	227	dev->rom_base_reg = PCI_ROM_ADDRESS;
	228	/* Maybe do a default OF mapping here */
ef24ba70	229	dev->irq = 0;
fbe65447 GL	230	}
	231
	232	of_pci_parse_addrs(node, dev);
	233
	234	pr_debug(" adding to system ...\n");
	235
	236	pci_device_add(dev, bus);
	237
	238	return dev;
	239	}
	240	EXPORT_SYMBOL(of_create_pci_dev);
	241
	242	/**
	243	* of_scan_pci_bridge - Set up a PCI bridge and scan for child nodes
fbe65447 GL	244	* @dev: pci_dev structure for the bridge
	245	*
	246	* of_scan_bus() calls this routine for each PCI bridge that it finds, and
1fd02f66	247	* this routine in turn call of_scan_bus() recursively to scan for more child
fbe65447 GL	248	* devices.
fbe65447 GL	249	*/
cad5cef6	250	void of_scan_pci_bridge(struct pci_dev *dev)
fbe65447	251	{
98d9f30c	252	struct device_node *node = dev->dev.of_node;
fbe65447	253	struct pci_bus *bus;
467efc2e	254	struct pci_controller *phb;
a795dc54	255	const __be32 busrange, ranges;
fbe65447	256	int len, i, mode;
39aa146a	257	struct pci_bus_region region;
fbe65447 GL	258	struct resource *res;
	259	unsigned int flags;
	260	u64 size;
	261
b7c670d6	262	pr_debug("of_scan_pci_bridge(%pOF)\n", node);
fbe65447 GL	263
	264	/* parse bus-range property */
	265	busrange = of_get_property(node, "bus-range", &len);
	266	if (busrange == NULL \|\| len != 8) {
b7c670d6 RH	267	printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %pOF\n",
b7c670d6 RH	268	node);
fbe65447 GL	269	return;
	270	}
	271	ranges = of_get_property(node, "ranges", &len);
	272	if (ranges == NULL) {
b7c670d6 RH	273	printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %pOF\n",
b7c670d6 RH	274	node);
fbe65447 GL	275	return;
	276	}
	277
a795dc54 AB	278	bus = pci_find_bus(pci_domain_nr(dev->bus),
a795dc54 AB	279	of_read_number(busrange, 1));
fbe65447	280	if (!bus) {
a795dc54 AB	281	bus = pci_add_new_bus(dev->bus, dev,
a795dc54 AB	282	of_read_number(busrange, 1));
ab444ec9	283	if (!bus) {
b7c670d6 RH	284	printk(KERN_ERR "Failed to create pci bus for %pOF\n",
b7c670d6 RH	285	node);
ab444ec9 GS	286	return;
ab444ec9 GS	287	}
fbe65447 GL	288	}
	289
	290	bus->primary = dev->bus->number;
a795dc54 AB	291	pci_bus_insert_busn_res(bus, of_read_number(busrange, 1),
a795dc54 AB	292	of_read_number(busrange+1, 1));
fbe65447	293	bus->bridge_ctl = 0;
fbe65447 GL	294
	295	/* parse ranges property */
	296	/* PCI #address-cells == 3 and #size-cells == 2 always */
	297	res = &dev->resource[PCI_BRIDGE_RESOURCES];
	298	for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
	299	res->flags = 0;
	300	bus->resource[i] = res;
	301	++res;
	302	}
	303	i = 1;
	304	for (; len >= 32; len -= 32, ranges += 8) {
a795dc54	305	flags = pci_parse_of_flags(of_read_number(ranges, 1), 1);
fbe65447 GL	306	size = of_read_number(&ranges[6], 2);
	307	if (flags == 0 \|\| size == 0)
	308	continue;
	309	if (flags & IORESOURCE_IO) {
	310	res = bus->resource[0];
	311	if (res->flags) {
	312	printk(KERN_ERR "PCI: ignoring extra I/O range"
b7c670d6	313	" for bridge %pOF\n", node);
fbe65447 GL	314	continue;
	315	}
	316	} else {
	317	if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
	318	printk(KERN_ERR "PCI: too many memory ranges"
b7c670d6	319	" for bridge %pOF\n", node);
fbe65447 GL	320	continue;
	321	}
	322	res = bus->resource[i];
	323	++i;
	324	}
fbe65447	325	res->flags = flags;
39aa146a BH	326	region.start = of_read_number(&ranges[1], 2);
39aa146a BH	327	region.end = region.start + size - 1;
fc279850	328	pcibios_bus_to_resource(dev->bus, res, &region);
fbe65447 GL	329	}
	330	sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
	331	bus->number);
	332	pr_debug(" bus name: %s\n", bus->name);
	333
467efc2e DA	334	phb = pci_bus_to_host(bus);
467efc2e DA	335
fbe65447	336	mode = PCI_PROBE_NORMAL;
467efc2e DA	337	if (phb->controller_ops.probe_mode)
467efc2e DA	338	mode = phb->controller_ops.probe_mode(bus);
fbe65447 GL	339	pr_debug(" probe mode: %d\n", mode);
	340
	341	if (mode == PCI_PROBE_DEVTREE)
	342	of_scan_bus(node, bus);
	343	else if (mode == PCI_PROBE_NORMAL)
	344	pci_scan_child_bus(bus);
	345	}
	346	EXPORT_SYMBOL(of_scan_pci_bridge);
	347
ab444ec9 GS	348	static struct pci_dev of_scan_pci_dev(struct pci_bus bus,
	349	struct device_node *dn)
	350	{
	351	struct pci_dev *dev = NULL;
3e7cec6b	352	const __be32 *reg;
ab444ec9	353	int reglen, devfn;
d2b0f6f7	354	#ifdef CONFIG_EEH
c6406d8f	355	struct eeh_dev *edev = pdn_to_eeh_dev(PCI_DN(dn));
d2b0f6f7	356	#endif
ab444ec9	357
b7c670d6	358	pr_debug(" * %pOF\n", dn);
ab444ec9 GS	359	if (!of_device_is_available(dn))
	360	return NULL;
	361
	362	reg = of_get_property(dn, "reg", &reglen);
	363	if (reg == NULL \|\| reglen < 20)
	364	return NULL;
3e7cec6b	365	devfn = (of_read_number(reg, 1) >> 8) & 0xff;
ab444ec9 GS	366
	367	/* Check if the PCI device is already there */
	368	dev = pci_get_slot(bus, devfn);
	369	if (dev) {
	370	pci_dev_put(dev);
	371	return dev;
	372	}
	373
d2b0f6f7 GS	374	/* Device removed permanently ? */
	375	#ifdef CONFIG_EEH
	376	if (edev && (edev->mode & EEH_DEV_REMOVED))
	377	return NULL;
	378	#endif
	379
ab444ec9 GS	380	/* create a new pci_dev for this device */
	381	dev = of_create_pci_dev(dn, bus, devfn);
	382	if (!dev)
	383	return NULL;
	384
	385	pr_debug(" dev header type: %x\n", dev->hdr_type);
	386	return dev;
	387	}
	388
fbe65447 GL	389	/**
	390	* __of_scan_bus - given a PCI bus node, setup bus and scan for child devices
	391	* @node: device tree node for the PCI bus
	392	* @bus: pci_bus structure for the PCI bus
	393	* @rescan_existing: Flag indicating bus has already been set up
	394	*/
cad5cef6 GKH	395	static void __of_scan_bus(struct device_node node, struct pci_bus bus,
cad5cef6 GKH	396	int rescan_existing)
fbe65447 GL	397	{
fbe65447 GL	398	struct device_node *child;
fbe65447 GL	399	struct pci_dev *dev;
fbe65447 GL	400
b7c670d6 RH	401	pr_debug("of_scan_bus(%pOF) bus no %d...\n",
b7c670d6 RH	402	node, bus->number);
fbe65447 GL	403
	404	/* Scan direct children */
	405	for_each_child_of_node(node, child) {
ab444ec9	406	dev = of_scan_pci_dev(bus, child);
fbe65447 GL	407	if (!dev)
	408	continue;
	409	pr_debug(" dev header type: %x\n", dev->hdr_type);
	410	}
	411
	412	/* Apply all fixups necessary. We don't fixup the bus "self"
	413	* for an existing bridge that is being rescanned
	414	*/
	415	if (!rescan_existing)
	416	pcibios_setup_bus_self(bus);
fbe65447 GL	417
fbe65447 GL	418	/* Now scan child busses */
dd1ea576 AS	419	for_each_pci_bridge(dev, bus)
dd1ea576 AS	420	of_scan_pci_bridge(dev);
fbe65447 GL	421	}
	422
	423	/**
	424	* of_scan_bus - given a PCI bus node, setup bus and scan for child devices
	425	* @node: device tree node for the PCI bus
	426	* @bus: pci_bus structure for the PCI bus
	427	*/
cad5cef6	428	void of_scan_bus(struct device_node node, struct pci_bus bus)
fbe65447 GL	429	{
	430	__of_scan_bus(node, bus, 0);
	431	}
	432	EXPORT_SYMBOL_GPL(of_scan_bus);
	433
	434	/**
	435	* of_rescan_bus - given a PCI bus node, scan for child devices
	436	* @node: device tree node for the PCI bus
	437	* @bus: pci_bus structure for the PCI bus
	438	*
	439	* Same as of_scan_bus, but for a pci_bus structure that has already been
	440	* setup.
	441	*/
cad5cef6	442	void of_rescan_bus(struct device_node node, struct pci_bus bus)
fbe65447 GL	443	{
	444	__of_scan_bus(node, bus, 1);
	445	}
	446	EXPORT_SYMBOL_GPL(of_rescan_bus);
	447