[linux-2.6-block.git] / arch / powerpc / kernel / pci_of_scan.c

/*
 * Helper routines to scan the device tree for PCI devices and busses
 *
 * Migrated out of PowerPC architecture pci_64.c file by Grant Likely
 * <grant.likely@secretlab.ca> so that these routines are available for
 * 32 bit also.
 *
 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
 *   Rework, based on alpha PCI code.
 * Copyright (c) 2009 Secret Lab Technologies Ltd.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 */

#include <linux/pci.h>
#include <linux/export.h>
#include <asm/pci-bridge.h>
#include <asm/prom.h>

/**
 * get_int_prop - Decode a u32 from a device tree property
 */
static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
{
	const __be32 *prop;
	int len;

	prop = of_get_property(np, name, &len);
	if (prop && len >= 4)
		return of_read_number(prop, 1);
	return def;
}

/**
 * pci_parse_of_flags - Parse the flags cell of a device tree PCI address
 * @addr0: value of 1st cell of a device tree PCI address.
 * @bridge: Set this flag if the address is from a bridge 'ranges' property
 */
unsigned int pci_parse_of_flags(u32 addr0, int bridge)
{
	unsigned int flags = 0;

	if (addr0 & 0x02000000) {
		flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
		flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
		if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
			flags |= IORESOURCE_MEM_64;
		flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
		if (addr0 & 0x40000000)
			flags |= IORESOURCE_PREFETCH
				 | PCI_BASE_ADDRESS_MEM_PREFETCH;
		/* Note: We don't know whether the ROM has been left enabled
		 * by the firmware or not. We mark it as disabled (ie, we do
		 * not set the IORESOURCE_ROM_ENABLE flag) for now rather than
		 * do a config space read, it will be force-enabled if needed
		 */
		if (!bridge && (addr0 & 0xff) == 0x30)
			flags |= IORESOURCE_READONLY;
	} else if (addr0 & 0x01000000)
		flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
	if (flags)
		flags |= IORESOURCE_SIZEALIGN;
	return flags;
}

/**
 * of_pci_parse_addrs - Parse PCI addresses assigned in the device tree node
 * @node: device tree node for the PCI device
 * @dev: pci_dev structure for the device
 *
 * This function parses the 'assigned-addresses' property of a PCI devices'
 * device tree node and writes them into the associated pci_dev structure.
 */
static void of_pci_parse_addrs(struct device_node *node, struct pci_dev *dev)
{
	u64 base, size;
	unsigned int flags;
	struct pci_bus_region region;
	struct resource *res;
	const __be32 *addrs;
	u32 i;
	int proplen;
	bool mark_unset = false;

	addrs = of_get_property(node, "assigned-addresses", &proplen);
	if (!addrs || !proplen) {
		addrs = of_get_property(node, "reg", &proplen);
		if (!addrs || !proplen)
			return;
		mark_unset = true;
	}

	pr_debug("    parse addresses (%d bytes) @ %p\n", proplen, addrs);
	for (; proplen >= 20; proplen -= 20, addrs += 5) {
		flags = pci_parse_of_flags(of_read_number(addrs, 1), 0);
		if (!flags)
			continue;
		base = of_read_number(&addrs[1], 2);
		size = of_read_number(&addrs[3], 2);
		if (!size)
			continue;
		i = of_read_number(addrs, 1) & 0xff;
		pr_debug("  base: %llx, size: %llx, i: %x\n",
			 (unsigned long long)base,
			 (unsigned long long)size, i);

		if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
			res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
		} else if (i == dev->rom_base_reg) {
			res = &dev->resource[PCI_ROM_RESOURCE];
			flags |= IORESOURCE_READONLY;
		} else {
			printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
			continue;
		}
		res->flags = flags;
		if (mark_unset)
			res->flags |= IORESOURCE_UNSET;
		res->name = pci_name(dev);
		region.start = base;
		region.end = base + size - 1;
		pcibios_bus_to_resource(dev->bus, res, &region);
	}
}

/**
 * of_create_pci_dev - Given a device tree node on a pci bus, create a pci_dev
 * @node: device tree node pointer
 * @bus: bus the device is sitting on
 * @devfn: PCI function number, extracted from device tree by caller.
 */
struct pci_dev *of_create_pci_dev(struct device_node *node,
				 struct pci_bus *bus, int devfn)
{
	struct pci_dev *dev;

	dev = pci_alloc_dev(bus);
	if (!dev)
		return NULL;

	pr_debug("    create device, devfn: %x, type: %s\n", devfn,
		 of_node_get_device_type(node));

	dev->dev.of_node = of_node_get(node);
	dev->dev.parent = bus->bridge;
	dev->dev.bus = &pci_bus_type;
	dev->devfn = devfn;
	dev->multifunction = 0;		/* maybe a lie? */
	dev->needs_freset = 0;		/* pcie fundamental reset required */
	set_pcie_port_type(dev);

	pci_dev_assign_slot(dev);
	dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
	dev->device = get_int_prop(node, "device-id", 0xffff);
	dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
	dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);

	dev->cfg_size = pci_cfg_space_size(dev);

	dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
		dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
	dev->class = get_int_prop(node, "class-code", 0);
	dev->revision = get_int_prop(node, "revision-id", 0);

	pr_debug("    class: 0x%x\n", dev->class);
	pr_debug("    revision: 0x%x\n", dev->revision);

	dev->current_state = PCI_UNKNOWN;	/* unknown power state */
	dev->error_state = pci_channel_io_normal;
	dev->dma_mask = 0xffffffff;

	/* Early fixups, before probing the BARs */
	pci_fixup_device(pci_fixup_early, dev);

	if (of_node_is_type(node, "pci") || of_node_is_type(node, "pciex")) {
		/* a PCI-PCI bridge */
		dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
		dev->rom_base_reg = PCI_ROM_ADDRESS1;
		set_pcie_hotplug_bridge(dev);
	} else if (of_node_is_type(node, "cardbus")) {
		dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
	} else {
		dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
		dev->rom_base_reg = PCI_ROM_ADDRESS;
		/* Maybe do a default OF mapping here */
		dev->irq = 0;
	}

	of_pci_parse_addrs(node, dev);

	pr_debug("    adding to system ...\n");

	pci_device_add(dev, bus);

	return dev;
}
EXPORT_SYMBOL(of_create_pci_dev);

/**
 * of_scan_pci_bridge - Set up a PCI bridge and scan for child nodes
 * @dev: pci_dev structure for the bridge
 *
 * of_scan_bus() calls this routine for each PCI bridge that it finds, and
 * this routine in turn call of_scan_bus() recusively to scan for more child
 * devices.
 */
void of_scan_pci_bridge(struct pci_dev *dev)
{
	struct device_node *node = dev->dev.of_node;
	struct pci_bus *bus;
	struct pci_controller *phb;
	const __be32 *busrange, *ranges;
	int len, i, mode;
	struct pci_bus_region region;
	struct resource *res;
	unsigned int flags;
	u64 size;

	pr_debug("of_scan_pci_bridge(%pOF)\n", node);

	/* parse bus-range property */
	busrange = of_get_property(node, "bus-range", &len);
	if (busrange == NULL || len != 8) {
		printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %pOF\n",
		       node);
		return;
	}
	ranges = of_get_property(node, "ranges", &len);
	if (ranges == NULL) {
		printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %pOF\n",
		       node);
		return;
	}

	bus = pci_find_bus(pci_domain_nr(dev->bus),
			   of_read_number(busrange, 1));
	if (!bus) {
		bus = pci_add_new_bus(dev->bus, dev,
				      of_read_number(busrange, 1));
		if (!bus) {
			printk(KERN_ERR "Failed to create pci bus for %pOF\n",
			       node);
			return;
		}
	}

	bus->primary = dev->bus->number;
	pci_bus_insert_busn_res(bus, of_read_number(busrange, 1),
				of_read_number(busrange+1, 1));
	bus->bridge_ctl = 0;

	/* parse ranges property */
	/* PCI #address-cells == 3 and #size-cells == 2 always */
	res = &dev->resource[PCI_BRIDGE_RESOURCES];
	for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
		res->flags = 0;
		bus->resource[i] = res;
		++res;
	}
	i = 1;
	for (; len >= 32; len -= 32, ranges += 8) {
		flags = pci_parse_of_flags(of_read_number(ranges, 1), 1);
		size = of_read_number(&ranges[6], 2);
		if (flags == 0 || size == 0)
			continue;
		if (flags & IORESOURCE_IO) {
			res = bus->resource[0];
			if (res->flags) {
				printk(KERN_ERR "PCI: ignoring extra I/O range"
				       " for bridge %pOF\n", node);
				continue;
			}
		} else {
			if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
				printk(KERN_ERR "PCI: too many memory ranges"
				       " for bridge %pOF\n", node);
				continue;
			}
			res = bus->resource[i];
			++i;
		}
		res->flags = flags;
		region.start = of_read_number(&ranges[1], 2);
		region.end = region.start + size - 1;
		pcibios_bus_to_resource(dev->bus, res, &region);
	}
	sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
		bus->number);
	pr_debug("    bus name: %s\n", bus->name);

	phb = pci_bus_to_host(bus);

	mode = PCI_PROBE_NORMAL;
	if (phb->controller_ops.probe_mode)
		mode = phb->controller_ops.probe_mode(bus);
	pr_debug("    probe mode: %d\n", mode);

	if (mode == PCI_PROBE_DEVTREE)
		of_scan_bus(node, bus);
	else if (mode == PCI_PROBE_NORMAL)
		pci_scan_child_bus(bus);
}
EXPORT_SYMBOL(of_scan_pci_bridge);

static struct pci_dev *of_scan_pci_dev(struct pci_bus *bus,
			    struct device_node *dn)
{
	struct pci_dev *dev = NULL;
	const __be32 *reg;
	int reglen, devfn;
#ifdef CONFIG_EEH
	struct eeh_dev *edev = pdn_to_eeh_dev(PCI_DN(dn));
#endif

	pr_debug("  * %pOF\n", dn);
	if (!of_device_is_available(dn))
		return NULL;

	reg = of_get_property(dn, "reg", &reglen);
	if (reg == NULL || reglen < 20)
		return NULL;
	devfn = (of_read_number(reg, 1) >> 8) & 0xff;

	/* Check if the PCI device is already there */
	dev = pci_get_slot(bus, devfn);
	if (dev) {
		pci_dev_put(dev);
		return dev;
	}

	/* Device removed permanently ? */
#ifdef CONFIG_EEH
	if (edev && (edev->mode & EEH_DEV_REMOVED))
		return NULL;
#endif

	/* create a new pci_dev for this device */
	dev = of_create_pci_dev(dn, bus, devfn);
	if (!dev)
		return NULL;

	pr_debug("  dev header type: %x\n", dev->hdr_type);
	return dev;
}

/**
 * __of_scan_bus - given a PCI bus node, setup bus and scan for child devices
 * @node: device tree node for the PCI bus
 * @bus: pci_bus structure for the PCI bus
 * @rescan_existing: Flag indicating bus has already been set up
 */
static void __of_scan_bus(struct device_node *node, struct pci_bus *bus,
			  int rescan_existing)
{
	struct device_node *child;
	struct pci_dev *dev;

	pr_debug("of_scan_bus(%pOF) bus no %d...\n",
		 node, bus->number);

	/* Scan direct children */
	for_each_child_of_node(node, child) {
		dev = of_scan_pci_dev(bus, child);
		if (!dev)
			continue;
		pr_debug("    dev header type: %x\n", dev->hdr_type);
	}

	/* Apply all fixups necessary. We don't fixup the bus "self"
	 * for an existing bridge that is being rescanned
	 */
	if (!rescan_existing)
		pcibios_setup_bus_self(bus);
	pcibios_setup_bus_devices(bus);

	/* Now scan child busses */
	for_each_pci_bridge(dev, bus)
		of_scan_pci_bridge(dev);
}

/**
 * of_scan_bus - given a PCI bus node, setup bus and scan for child devices
 * @node: device tree node for the PCI bus
 * @bus: pci_bus structure for the PCI bus
 */
void of_scan_bus(struct device_node *node, struct pci_bus *bus)
{
	__of_scan_bus(node, bus, 0);
}
EXPORT_SYMBOL_GPL(of_scan_bus);

/**
 * of_rescan_bus - given a PCI bus node, scan for child devices
 * @node: device tree node for the PCI bus
 * @bus: pci_bus structure for the PCI bus
 *
 * Same as of_scan_bus, but for a pci_bus structure that has already been
 * setup.
 */
void of_rescan_bus(struct device_node *node, struct pci_bus *bus)
{
	__of_scan_bus(node, bus, 1);
}
EXPORT_SYMBOL_GPL(of_rescan_bus);
Commit	Line	Data
fbe65447 GL	1	/*
	2	* Helper routines to scan the device tree for PCI devices and busses
	3	*
	4	* Migrated out of PowerPC architecture pci_64.c file by Grant Likely
	5	* <grant.likely@secretlab.ca> so that these routines are available for
	6	* 32 bit also.
	7	*
	8	* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
	9	* Rework, based on alpha PCI code.
	10	* Copyright (c) 2009 Secret Lab Technologies Ltd.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License
	14	* version 2 as published by the Free Software Foundation.
	15	*/
	16
	17	#include <linux/pci.h>
66b15db6	18	#include <linux/export.h>
fbe65447 GL	19	#include <asm/pci-bridge.h>
	20	#include <asm/prom.h>
	21
	22	/**
	23	* get_int_prop - Decode a u32 from a device tree property
	24	*/
	25	static u32 get_int_prop(struct device_node np, const char name, u32 def)
	26	{
a795dc54	27	const __be32 *prop;
fbe65447 GL	28	int len;
	29
	30	prop = of_get_property(np, name, &len);
	31	if (prop && len >= 4)
a795dc54	32	return of_read_number(prop, 1);
fbe65447 GL	33	return def;
	34	}
	35
	36	/**
	37	* pci_parse_of_flags - Parse the flags cell of a device tree PCI address
	38	* @addr0: value of 1st cell of a device tree PCI address.
	39	* @bridge: Set this flag if the address is from a bridge 'ranges' property
	40	*/
fc5f6221	41	unsigned int pci_parse_of_flags(u32 addr0, int bridge)
fbe65447 GL	42	{
	43	unsigned int flags = 0;
	44
	45	if (addr0 & 0x02000000) {
	46	flags = IORESOURCE_MEM \| PCI_BASE_ADDRESS_SPACE_MEMORY;
	47	flags \|= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
df5be5be AK	48	if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
df5be5be AK	49	flags \|= IORESOURCE_MEM_64;
fbe65447 GL	50	flags \|= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
	51	if (addr0 & 0x40000000)
	52	flags \|= IORESOURCE_PREFETCH
	53	\| PCI_BASE_ADDRESS_MEM_PREFETCH;
	54	/* Note: We don't know whether the ROM has been left enabled
	55	* by the firmware or not. We mark it as disabled (ie, we do
	56	* not set the IORESOURCE_ROM_ENABLE flag) for now rather than
	57	* do a config space read, it will be force-enabled if needed
	58	*/
	59	if (!bridge && (addr0 & 0xff) == 0x30)
	60	flags \|= IORESOURCE_READONLY;
	61	} else if (addr0 & 0x01000000)
	62	flags = IORESOURCE_IO \| PCI_BASE_ADDRESS_SPACE_IO;
	63	if (flags)
	64	flags \|= IORESOURCE_SIZEALIGN;
	65	return flags;
	66	}
	67
	68	/**
	69	* of_pci_parse_addrs - Parse PCI addresses assigned in the device tree node
	70	* @node: device tree node for the PCI device
	71	* @dev: pci_dev structure for the device
	72	*
	73	* This function parses the 'assigned-addresses' property of a PCI devices'
	74	* device tree node and writes them into the associated pci_dev structure.
	75	*/
	76	static void of_pci_parse_addrs(struct device_node node, struct pci_dev dev)
	77	{
	78	u64 base, size;
	79	unsigned int flags;
39aa146a	80	struct pci_bus_region region;
fbe65447	81	struct resource *res;
a795dc54	82	const __be32 *addrs;
fbe65447 GL	83	u32 i;
fbe65447 GL	84	int proplen;
dead1c84	85	bool mark_unset = false;
fbe65447 GL	86
fbe65447 GL	87	addrs = of_get_property(node, "assigned-addresses", &proplen);
dead1c84 AK	88	if (!addrs \|\| !proplen) {
	89	addrs = of_get_property(node, "reg", &proplen);
	90	if (!addrs \|\| !proplen)
	91	return;
	92	mark_unset = true;
	93	}
	94
fbe65447 GL	95	pr_debug(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
fbe65447 GL	96	for (; proplen >= 20; proplen -= 20, addrs += 5) {
a795dc54	97	flags = pci_parse_of_flags(of_read_number(addrs, 1), 0);
fbe65447 GL	98	if (!flags)
	99	continue;
	100	base = of_read_number(&addrs[1], 2);
	101	size = of_read_number(&addrs[3], 2);
	102	if (!size)
	103	continue;
a795dc54	104	i = of_read_number(addrs, 1) & 0xff;
fbe65447 GL	105	pr_debug(" base: %llx, size: %llx, i: %x\n",
	106	(unsigned long long)base,
	107	(unsigned long long)size, i);
	108
	109	if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
	110	res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
	111	} else if (i == dev->rom_base_reg) {
	112	res = &dev->resource[PCI_ROM_RESOURCE];
92b19ff5	113	flags \|= IORESOURCE_READONLY;
fbe65447 GL	114	} else {
	115	printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
	116	continue;
	117	}
fbe65447	118	res->flags = flags;
dead1c84 AK	119	if (mark_unset)
dead1c84 AK	120	res->flags \|= IORESOURCE_UNSET;
fbe65447	121	res->name = pci_name(dev);
39aa146a BH	122	region.start = base;
39aa146a BH	123	region.end = base + size - 1;
fc279850	124	pcibios_bus_to_resource(dev->bus, res, &region);
fbe65447 GL	125	}
	126	}
	127
	128	/**
	129	* of_create_pci_dev - Given a device tree node on a pci bus, create a pci_dev
	130	* @node: device tree node pointer
	131	* @bus: bus the device is sitting on
	132	* @devfn: PCI function number, extracted from device tree by caller.
	133	*/
	134	struct pci_dev of_create_pci_dev(struct device_node node,
	135	struct pci_bus *bus, int devfn)
	136	{
	137	struct pci_dev *dev;
fbe65447	138
8b1fce04	139	dev = pci_alloc_dev(bus);
fbe65447 GL	140	if (!dev)
fbe65447 GL	141	return NULL;
fbe65447	142
e5480bdc RH	143	pr_debug(" create device, devfn: %x, type: %s\n", devfn,
e5480bdc RH	144	of_node_get_device_type(node));
fbe65447	145
b5d937de	146	dev->dev.of_node = of_node_get(node);
fbe65447 GL	147	dev->dev.parent = bus->bridge;
	148	dev->dev.bus = &pci_bus_type;
	149	dev->devfn = devfn;
	150	dev->multifunction = 0; /* maybe a lie? */
4406c56d	151	dev->needs_freset = 0; /* pcie fundamental reset required */
bb209c82	152	set_pcie_port_type(dev);
fbe65447	153
017ffe64	154	pci_dev_assign_slot(dev);
fbe65447 GL	155	dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
	156	dev->device = get_int_prop(node, "device-id", 0xffff);
	157	dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
	158	dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
	159
	160	dev->cfg_size = pci_cfg_space_size(dev);
	161
	162	dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
	163	dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
	164	dev->class = get_int_prop(node, "class-code", 0);
	165	dev->revision = get_int_prop(node, "revision-id", 0);
	166
	167	pr_debug(" class: 0x%x\n", dev->class);
	168	pr_debug(" revision: 0x%x\n", dev->revision);
	169
c2defb5f	170	dev->current_state = PCI_UNKNOWN; /* unknown power state */
fbe65447 GL	171	dev->error_state = pci_channel_io_normal;
	172	dev->dma_mask = 0xffffffff;
	173
94afc008 BH	174	/* Early fixups, before probing the BARs */
	175	pci_fixup_device(pci_fixup_early, dev);
	176
e5480bdc	177	if (of_node_is_type(node, "pci") \|\| of_node_is_type(node, "pciex")) {
fbe65447 GL	178	/* a PCI-PCI bridge */
	179	dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
	180	dev->rom_base_reg = PCI_ROM_ADDRESS1;
bb209c82	181	set_pcie_hotplug_bridge(dev);
e5480bdc	182	} else if (of_node_is_type(node, "cardbus")) {
fbe65447 GL	183	dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
	184	} else {
	185	dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
	186	dev->rom_base_reg = PCI_ROM_ADDRESS;
	187	/* Maybe do a default OF mapping here */
ef24ba70	188	dev->irq = 0;
fbe65447 GL	189	}
	190
	191	of_pci_parse_addrs(node, dev);
	192
	193	pr_debug(" adding to system ...\n");
	194
	195	pci_device_add(dev, bus);
	196
	197	return dev;
	198	}
	199	EXPORT_SYMBOL(of_create_pci_dev);
	200
	201	/**
	202	* of_scan_pci_bridge - Set up a PCI bridge and scan for child nodes
fbe65447 GL	203	* @dev: pci_dev structure for the bridge
	204	*
	205	* of_scan_bus() calls this routine for each PCI bridge that it finds, and
	206	* this routine in turn call of_scan_bus() recusively to scan for more child
	207	* devices.
	208	*/
cad5cef6	209	void of_scan_pci_bridge(struct pci_dev *dev)
fbe65447	210	{
98d9f30c	211	struct device_node *node = dev->dev.of_node;
fbe65447	212	struct pci_bus *bus;
467efc2e	213	struct pci_controller *phb;
a795dc54	214	const __be32 busrange, ranges;
fbe65447	215	int len, i, mode;
39aa146a	216	struct pci_bus_region region;
fbe65447 GL	217	struct resource *res;
	218	unsigned int flags;
	219	u64 size;
	220
b7c670d6	221	pr_debug("of_scan_pci_bridge(%pOF)\n", node);
fbe65447 GL	222
	223	/* parse bus-range property */
	224	busrange = of_get_property(node, "bus-range", &len);
	225	if (busrange == NULL \|\| len != 8) {
b7c670d6 RH	226	printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %pOF\n",
b7c670d6 RH	227	node);
fbe65447 GL	228	return;
	229	}
	230	ranges = of_get_property(node, "ranges", &len);
	231	if (ranges == NULL) {
b7c670d6 RH	232	printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %pOF\n",
b7c670d6 RH	233	node);
fbe65447 GL	234	return;
	235	}
	236
a795dc54 AB	237	bus = pci_find_bus(pci_domain_nr(dev->bus),
a795dc54 AB	238	of_read_number(busrange, 1));
fbe65447	239	if (!bus) {
a795dc54 AB	240	bus = pci_add_new_bus(dev->bus, dev,
a795dc54 AB	241	of_read_number(busrange, 1));
ab444ec9	242	if (!bus) {
b7c670d6 RH	243	printk(KERN_ERR "Failed to create pci bus for %pOF\n",
b7c670d6 RH	244	node);
ab444ec9 GS	245	return;
ab444ec9 GS	246	}
fbe65447 GL	247	}
	248
	249	bus->primary = dev->bus->number;
a795dc54 AB	250	pci_bus_insert_busn_res(bus, of_read_number(busrange, 1),
a795dc54 AB	251	of_read_number(busrange+1, 1));
fbe65447	252	bus->bridge_ctl = 0;
fbe65447 GL	253
	254	/* parse ranges property */
	255	/* PCI #address-cells == 3 and #size-cells == 2 always */
	256	res = &dev->resource[PCI_BRIDGE_RESOURCES];
	257	for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
	258	res->flags = 0;
	259	bus->resource[i] = res;
	260	++res;
	261	}
	262	i = 1;
	263	for (; len >= 32; len -= 32, ranges += 8) {
a795dc54	264	flags = pci_parse_of_flags(of_read_number(ranges, 1), 1);
fbe65447 GL	265	size = of_read_number(&ranges[6], 2);
	266	if (flags == 0 \|\| size == 0)
	267	continue;
	268	if (flags & IORESOURCE_IO) {
	269	res = bus->resource[0];
	270	if (res->flags) {
	271	printk(KERN_ERR "PCI: ignoring extra I/O range"
b7c670d6	272	" for bridge %pOF\n", node);
fbe65447 GL	273	continue;
	274	}
	275	} else {
	276	if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
	277	printk(KERN_ERR "PCI: too many memory ranges"
b7c670d6	278	" for bridge %pOF\n", node);
fbe65447 GL	279	continue;
	280	}
	281	res = bus->resource[i];
	282	++i;
	283	}
fbe65447	284	res->flags = flags;
39aa146a BH	285	region.start = of_read_number(&ranges[1], 2);
39aa146a BH	286	region.end = region.start + size - 1;
fc279850	287	pcibios_bus_to_resource(dev->bus, res, &region);
fbe65447 GL	288	}
	289	sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
	290	bus->number);
	291	pr_debug(" bus name: %s\n", bus->name);
	292
467efc2e DA	293	phb = pci_bus_to_host(bus);
467efc2e DA	294
fbe65447	295	mode = PCI_PROBE_NORMAL;
467efc2e DA	296	if (phb->controller_ops.probe_mode)
467efc2e DA	297	mode = phb->controller_ops.probe_mode(bus);
fbe65447 GL	298	pr_debug(" probe mode: %d\n", mode);
	299
	300	if (mode == PCI_PROBE_DEVTREE)
	301	of_scan_bus(node, bus);
	302	else if (mode == PCI_PROBE_NORMAL)
	303	pci_scan_child_bus(bus);
	304	}
	305	EXPORT_SYMBOL(of_scan_pci_bridge);
	306
ab444ec9 GS	307	static struct pci_dev of_scan_pci_dev(struct pci_bus bus,
	308	struct device_node *dn)
	309	{
	310	struct pci_dev *dev = NULL;
3e7cec6b	311	const __be32 *reg;
ab444ec9	312	int reglen, devfn;
d2b0f6f7	313	#ifdef CONFIG_EEH
c6406d8f	314	struct eeh_dev *edev = pdn_to_eeh_dev(PCI_DN(dn));
d2b0f6f7	315	#endif
ab444ec9	316
b7c670d6	317	pr_debug(" * %pOF\n", dn);
ab444ec9 GS	318	if (!of_device_is_available(dn))
	319	return NULL;
	320
	321	reg = of_get_property(dn, "reg", &reglen);
	322	if (reg == NULL \|\| reglen < 20)
	323	return NULL;
3e7cec6b	324	devfn = (of_read_number(reg, 1) >> 8) & 0xff;
ab444ec9 GS	325
	326	/* Check if the PCI device is already there */
	327	dev = pci_get_slot(bus, devfn);
	328	if (dev) {
	329	pci_dev_put(dev);
	330	return dev;
	331	}
	332
d2b0f6f7 GS	333	/* Device removed permanently ? */
	334	#ifdef CONFIG_EEH
	335	if (edev && (edev->mode & EEH_DEV_REMOVED))
	336	return NULL;
	337	#endif
	338
ab444ec9 GS	339	/* create a new pci_dev for this device */
	340	dev = of_create_pci_dev(dn, bus, devfn);
	341	if (!dev)
	342	return NULL;
	343
	344	pr_debug(" dev header type: %x\n", dev->hdr_type);
	345	return dev;
	346	}
	347
fbe65447 GL	348	/**
	349	* __of_scan_bus - given a PCI bus node, setup bus and scan for child devices
	350	* @node: device tree node for the PCI bus
	351	* @bus: pci_bus structure for the PCI bus
	352	* @rescan_existing: Flag indicating bus has already been set up
	353	*/
cad5cef6 GKH	354	static void __of_scan_bus(struct device_node node, struct pci_bus bus,
cad5cef6 GKH	355	int rescan_existing)
fbe65447 GL	356	{
fbe65447 GL	357	struct device_node *child;
fbe65447 GL	358	struct pci_dev *dev;
fbe65447 GL	359
b7c670d6 RH	360	pr_debug("of_scan_bus(%pOF) bus no %d...\n",
b7c670d6 RH	361	node, bus->number);
fbe65447 GL	362
	363	/* Scan direct children */
	364	for_each_child_of_node(node, child) {
ab444ec9	365	dev = of_scan_pci_dev(bus, child);
fbe65447 GL	366	if (!dev)
	367	continue;
	368	pr_debug(" dev header type: %x\n", dev->hdr_type);
	369	}
	370
	371	/* Apply all fixups necessary. We don't fixup the bus "self"
	372	* for an existing bridge that is being rescanned
	373	*/
	374	if (!rescan_existing)
	375	pcibios_setup_bus_self(bus);
	376	pcibios_setup_bus_devices(bus);
	377
	378	/* Now scan child busses */
dd1ea576 AS	379	for_each_pci_bridge(dev, bus)
dd1ea576 AS	380	of_scan_pci_bridge(dev);
fbe65447 GL	381	}
	382
	383	/**
	384	* of_scan_bus - given a PCI bus node, setup bus and scan for child devices
	385	* @node: device tree node for the PCI bus
	386	* @bus: pci_bus structure for the PCI bus
	387	*/
cad5cef6	388	void of_scan_bus(struct device_node node, struct pci_bus bus)
fbe65447 GL	389	{
	390	__of_scan_bus(node, bus, 0);
	391	}
	392	EXPORT_SYMBOL_GPL(of_scan_bus);
	393
	394	/**
	395	* of_rescan_bus - given a PCI bus node, scan for child devices
	396	* @node: device tree node for the PCI bus
	397	* @bus: pci_bus structure for the PCI bus
	398	*
	399	* Same as of_scan_bus, but for a pci_bus structure that has already been
	400	* setup.
	401	*/
cad5cef6	402	void of_rescan_bus(struct device_node node, struct pci_bus bus)
fbe65447 GL	403	{
	404	__of_scan_bus(node, bus, 1);
	405	}
	406	EXPORT_SYMBOL_GPL(of_rescan_bus);
	407