[linux-2.6-block.git] / arch / powerpc / kernel / pci_64.c

/*
 * Port for PPC64 David Engebretsen, IBM Corp.
 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
 * 
 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
 *   Rework, based on alpha PCI code.
 *
 *      This program is free software; you can redistribute it and/or
 *      modify it under the terms of the GNU General Public License
 *      as published by the Free Software Foundation; either version
 *      2 of the License, or (at your option) any later version.
 */

#undef DEBUG

#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/mm.h>
#include <linux/list.h>
#include <linux/syscalls.h>
#include <linux/irq.h>
#include <linux/vmalloc.h>

#include <asm/processor.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <asm/byteorder.h>
#include <asm/machdep.h>
#include <asm/ppc-pci.h>

unsigned long pci_probe_only = 1;

/* pci_io_base -- the base address from which io bars are offsets.
 * This is the lowest I/O base address (so bar values are always positive),
 * and it *must* be the start of ISA space if an ISA bus exists because
 * ISA drivers use hard coded offsets.  If no ISA bus exists nothing
 * is mapped on the first 64K of IO space
 */
unsigned long pci_io_base = ISA_IO_BASE;
EXPORT_SYMBOL(pci_io_base);

void __devinit scan_phb(struct pci_controller *hose)
{
	struct pci_bus *bus;
	struct device_node *node = hose->dn;
	int mode;

	pr_debug("PCI: Scanning PHB %s\n",
		 node ? node->full_name : "<NO NAME>");

	/* Create an empty bus for the toplevel */
	bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
	if (bus == NULL) {
		printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
		       hose->global_number);
		return;
	}
	bus->secondary = hose->first_busno;
	hose->bus = bus;

	/* Get some IO space for the new PHB */
	pcibios_map_io_space(bus);

	/* Wire up PHB bus resources */
	pcibios_setup_phb_resources(hose);

	/* Get probe mode and perform scan */
	mode = PCI_PROBE_NORMAL;
	if (node && ppc_md.pci_probe_mode)
		mode = ppc_md.pci_probe_mode(bus);
	pr_debug("    probe mode: %d\n", mode);
	if (mode == PCI_PROBE_DEVTREE) {
		bus->subordinate = hose->last_busno;
		of_scan_bus(node, bus);
	}

	if (mode == PCI_PROBE_NORMAL)
		hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
}

static int __init pcibios_init(void)
{
	struct pci_controller *hose, *tmp;

	printk(KERN_INFO "PCI: Probing PCI hardware\n");

	/* For now, override phys_mem_access_prot. If we need it,g
	 * later, we may move that initialization to each ppc_md
	 */
	ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;

	if (pci_probe_only)
		ppc_pci_flags |= PPC_PCI_PROBE_ONLY;

	/* On ppc64, we always enable PCI domains and we keep domain 0
	 * backward compatible in /proc for video cards
	 */
	ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0;

	/* Scan all of the recorded PCI controllers.  */
	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
		scan_phb(hose);
		pci_bus_add_devices(hose->bus);
	}

	/* Call common code to handle resource allocation */
	pcibios_resource_survey();

	printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");

	return 0;
}

subsys_initcall(pcibios_init);

#ifdef CONFIG_HOTPLUG

int pcibios_unmap_io_space(struct pci_bus *bus)
{
	struct pci_controller *hose;

	WARN_ON(bus == NULL);

	/* If this is not a PHB, we only flush the hash table over
	 * the area mapped by this bridge. We don't play with the PTE
	 * mappings since we might have to deal with sub-page alignemnts
	 * so flushing the hash table is the only sane way to make sure
	 * that no hash entries are covering that removed bridge area
	 * while still allowing other busses overlapping those pages
	 *
	 * Note: If we ever support P2P hotplug on Book3E, we'll have
	 * to do an appropriate TLB flush here too
	 */
	if (bus->self) {
		struct resource *res = bus->resource[0];

		pr_debug("IO unmapping for PCI-PCI bridge %s\n",
			 pci_name(bus->self));

#ifdef CONFIG_PPC_STD_MMU_64
		__flush_hash_table_range(&init_mm, res->start + _IO_BASE,
					 res->end + _IO_BASE + 1);
#endif
		return 0;
	}

	/* Get the host bridge */
	hose = pci_bus_to_host(bus);

	/* Check if we have IOs allocated */
	if (hose->io_base_alloc == 0)
		return 0;

	pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name);
	pr_debug("  alloc=0x%p\n", hose->io_base_alloc);

	/* This is a PHB, we fully unmap the IO area */
	vunmap(hose->io_base_alloc);

	return 0;
}
EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);

#endif /* CONFIG_HOTPLUG */

int __devinit pcibios_map_io_space(struct pci_bus *bus)
{
	struct vm_struct *area;
	unsigned long phys_page;
	unsigned long size_page;
	unsigned long io_virt_offset;
	struct pci_controller *hose;

	WARN_ON(bus == NULL);

	/* If this not a PHB, nothing to do, page tables still exist and
	 * thus HPTEs will be faulted in when needed
	 */
	if (bus->self) {
		pr_debug("IO mapping for PCI-PCI bridge %s\n",
			 pci_name(bus->self));
		pr_debug("  virt=0x%016llx...0x%016llx\n",
			 bus->resource[0]->start + _IO_BASE,
			 bus->resource[0]->end + _IO_BASE);
		return 0;
	}

	/* Get the host bridge */
	hose = pci_bus_to_host(bus);
	phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
	size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);

	/* Make sure IO area address is clear */
	hose->io_base_alloc = NULL;

	/* If there's no IO to map on that bus, get away too */
	if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
		return 0;

	/* Let's allocate some IO space for that guy. We don't pass
	 * VM_IOREMAP because we don't care about alignment tricks that
	 * the core does in that case. Maybe we should due to stupid card
	 * with incomplete address decoding but I'd rather not deal with
	 * those outside of the reserved 64K legacy region.
	 */
	area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
	if (area == NULL)
		return -ENOMEM;
	hose->io_base_alloc = area->addr;
	hose->io_base_virt = (void __iomem *)(area->addr +
					      hose->io_base_phys - phys_page);

	pr_debug("IO mapping for PHB %s\n", hose->dn->full_name);
	pr_debug("  phys=0x%016llx, virt=0x%p (alloc=0x%p)\n",
		 hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
	pr_debug("  size=0x%016llx (alloc=0x%016lx)\n",
		 hose->pci_io_size, size_page);

	/* Establish the mapping */
	if (__ioremap_at(phys_page, area->addr, size_page,
			 _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)
		return -ENOMEM;

	/* Fixup hose IO resource */
	io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
	hose->io_resource.start += io_virt_offset;
	hose->io_resource.end += io_virt_offset;

	pr_debug("  hose->io_resource=0x%016llx...0x%016llx\n",
		 hose->io_resource.start, hose->io_resource.end);

	return 0;
}
EXPORT_SYMBOL_GPL(pcibios_map_io_space);

#define IOBASE_BRIDGE_NUMBER	0
#define IOBASE_MEMORY		1
#define IOBASE_IO		2
#define IOBASE_ISA_IO		3
#define IOBASE_ISA_MEM		4

long sys_pciconfig_iobase(long which, unsigned long in_bus,
			  unsigned long in_devfn)
{
	struct pci_controller* hose;
	struct list_head *ln;
	struct pci_bus *bus = NULL;
	struct device_node *hose_node;

	/* Argh ! Please forgive me for that hack, but that's the
	 * simplest way to get existing XFree to not lockup on some
	 * G5 machines... So when something asks for bus 0 io base
	 * (bus 0 is HT root), we return the AGP one instead.
	 */
	if (in_bus == 0 && machine_is_compatible("MacRISC4")) {
		struct device_node *agp;

		agp = of_find_compatible_node(NULL, NULL, "u3-agp");
		if (agp)
			in_bus = 0xf0;
		of_node_put(agp);
	}

	/* That syscall isn't quite compatible with PCI domains, but it's
	 * used on pre-domains setup. We return the first match
	 */

	for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
		bus = pci_bus_b(ln);
		if (in_bus >= bus->number && in_bus <= bus->subordinate)
			break;
		bus = NULL;
	}
	if (bus == NULL || bus->sysdata == NULL)
		return -ENODEV;

	hose_node = (struct device_node *)bus->sysdata;
	hose = PCI_DN(hose_node)->phb;

	switch (which) {
	case IOBASE_BRIDGE_NUMBER:
		return (long)hose->first_busno;
	case IOBASE_MEMORY:
		return (long)hose->pci_mem_offset;
	case IOBASE_IO:
		return (long)hose->io_base_phys;
	case IOBASE_ISA_IO:
		return (long)isa_io_base;
	case IOBASE_ISA_MEM:
		return -EINVAL;
	}

	return -EOPNOTSUPP;
}

#ifdef CONFIG_NUMA
int pcibus_to_node(struct pci_bus *bus)
{
	struct pci_controller *phb = pci_bus_to_host(bus);
	return phb->node;
}
EXPORT_SYMBOL(pcibus_to_node);
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Port for PPC64 David Engebretsen, IBM Corp.
	3	* Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
	4	*
	5	* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
	6	* Rework, based on alpha PCI code.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version
	11	* 2 of the License, or (at your option) any later version.
	12	*/
	13
	14	#undef DEBUG
	15
1da177e4 LT	16	#include <linux/kernel.h>
	17	#include <linux/pci.h>
	18	#include <linux/string.h>
	19	#include <linux/init.h>
	20	#include <linux/bootmem.h>
	21	#include <linux/mm.h>
	22	#include <linux/list.h>
b2ad7b5e	23	#include <linux/syscalls.h>
6e99e458	24	#include <linux/irq.h>
3d5134ee	25	#include <linux/vmalloc.h>
1da177e4 LT	26
	27	#include <asm/processor.h>
	28	#include <asm/io.h>
	29	#include <asm/prom.h>
	30	#include <asm/pci-bridge.h>
	31	#include <asm/byteorder.h>
1da177e4	32	#include <asm/machdep.h>
d387899f	33	#include <asm/ppc-pci.h>
1da177e4	34
1da177e4	35	unsigned long pci_probe_only = 1;
1da177e4	36
1da177e4 LT	37	/* pci_io_base -- the base address from which io bars are offsets.
	38	* This is the lowest I/O base address (so bar values are always positive),
	39	* and it must be the start of ISA space if an ISA bus exists because
3d5134ee BH	40	* ISA drivers use hard coded offsets. If no ISA bus exists nothing
3d5134ee BH	41	* is mapped on the first 64K of IO space
1da177e4	42	*/
3d5134ee	43	unsigned long pci_io_base = ISA_IO_BASE;
1da177e4 LT	44	EXPORT_SYMBOL(pci_io_base);
1da177e4 LT	45
ead83717	46	void __devinit scan_phb(struct pci_controller *hose)
4267292b PM	47	{
4267292b PM	48	struct pci_bus *bus;
44ef3390	49	struct device_node *node = hose->dn;
53280323	50	int mode;
4267292b	51
b0494bc8 BH	52	pr_debug("PCI: Scanning PHB %s\n",
b0494bc8 BH	53	node ? node->full_name : "<NO NAME>");
1beb6a7d	54
3fd94c6b	55	/* Create an empty bus for the toplevel */
803d4573	56	bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
4267292b PM	57	if (bus == NULL) {
	58	printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
	59	hose->global_number);
	60	return;
	61	}
	62	bus->secondary = hose->first_busno;
	63	hose->bus = bus;
	64
3fd94c6b	65	/* Get some IO space for the new PHB */
9ccc4fd2	66	pcibios_map_io_space(bus);
3d5134ee	67
3fd94c6b	68	/* Wire up PHB bus resources */
53280323	69	pcibios_setup_phb_resources(hose);
4267292b	70
3fd94c6b	71	/* Get probe mode and perform scan */
4267292b	72	mode = PCI_PROBE_NORMAL;
1beb6a7d	73	if (node && ppc_md.pci_probe_mode)
4267292b	74	mode = ppc_md.pci_probe_mode(bus);
b0494bc8	75	pr_debug(" probe mode: %d\n", mode);
4267292b PM	76	if (mode == PCI_PROBE_DEVTREE) {
	77	bus->subordinate = hose->last_busno;
	78	of_scan_bus(node, bus);
	79	}
99a565ba	80
4267292b PM	81	if (mode == PCI_PROBE_NORMAL)
4267292b PM	82	hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
4267292b PM	83	}
4267292b PM	84
1da177e4 LT	85	static int __init pcibios_init(void)
	86	{
	87	struct pci_controller hose, tmp;
1da177e4	88
3fd94c6b BH	89	printk(KERN_INFO "PCI: Probing PCI hardware\n");
3fd94c6b BH	90
53280323	91	/* For now, override phys_mem_access_prot. If we need it,g
1da177e4 LT	92	* later, we may move that initialization to each ppc_md
	93	*/
	94	ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
	95
3fd94c6b BH	96	if (pci_probe_only)
3fd94c6b BH	97	ppc_pci_flags \|= PPC_PCI_PROBE_ONLY;
1da177e4	98
1fd0f525 BH	99	/* On ppc64, we always enable PCI domains and we keep domain 0
	100	* backward compatible in /proc for video cards
	101	*/
	102	ppc_pci_flags \|= PPC_PCI_ENABLE_PROC_DOMAINS \| PPC_PCI_COMPAT_DOMAIN_0;
	103
1da177e4	104	/* Scan all of the recorded PCI controllers. */
92eb4602	105	list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
4267292b	106	scan_phb(hose);
92eb4602 JR	107	pci_bus_add_devices(hose->bus);
92eb4602 JR	108	}
1da177e4	109
3fd94c6b BH	110	/* Call common code to handle resource allocation */
3fd94c6b BH	111	pcibios_resource_survey();
1da177e4	112
e884e9c5	113	printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
1da177e4 LT	114
	115	return 0;
	116	}
	117
	118	subsys_initcall(pcibios_init);
	119
3d5134ee BH	120	#ifdef CONFIG_HOTPLUG
	121
	122	int pcibios_unmap_io_space(struct pci_bus *bus)
1da177e4	123	{
3d5134ee	124	struct pci_controller *hose;
1da177e4	125
3d5134ee	126	WARN_ON(bus == NULL);
de821204	127
3d5134ee BH	128	/* If this is not a PHB, we only flush the hash table over
	129	* the area mapped by this bridge. We don't play with the PTE
	130	* mappings since we might have to deal with sub-page alignemnts
	131	* so flushing the hash table is the only sane way to make sure
	132	* that no hash entries are covering that removed bridge area
	133	* while still allowing other busses overlapping those pages
94491685 BH	134	*
	135	* Note: If we ever support P2P hotplug on Book3E, we'll have
	136	* to do an appropriate TLB flush here too
3d5134ee BH	137	*/
	138	if (bus->self) {
	139	struct resource *res = bus->resource[0];
1da177e4	140
b0494bc8 BH	141	pr_debug("IO unmapping for PCI-PCI bridge %s\n",
b0494bc8 BH	142	pci_name(bus->self));
de821204	143
94491685	144	#ifdef CONFIG_PPC_STD_MMU_64
3d5134ee	145	__flush_hash_table_range(&init_mm, res->start + _IO_BASE,
b30115ea	146	res->end + _IO_BASE + 1);
94491685	147	#endif
3d5134ee BH	148	return 0;
3d5134ee BH	149	}
1da177e4	150
3d5134ee BH	151	/* Get the host bridge */
3d5134ee BH	152	hose = pci_bus_to_host(bus);
1da177e4	153
3d5134ee BH	154	/* Check if we have IOs allocated */
	155	if (hose->io_base_alloc == 0)
	156	return 0;
de821204	157
b0494bc8 BH	158	pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name);
b0494bc8 BH	159	pr_debug(" alloc=0x%p\n", hose->io_base_alloc);
1da177e4	160
3d5134ee BH	161	/* This is a PHB, we fully unmap the IO area */
3d5134ee BH	162	vunmap(hose->io_base_alloc);
1da177e4	163
3d5134ee	164	return 0;
1da177e4	165	}
3d5134ee	166	EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
1da177e4	167
3d5134ee	168	#endif /* CONFIG_HOTPLUG */
1da177e4	169
3d5134ee	170	int __devinit pcibios_map_io_space(struct pci_bus *bus)
1da177e4	171	{
3d5134ee BH	172	struct vm_struct *area;
	173	unsigned long phys_page;
	174	unsigned long size_page;
	175	unsigned long io_virt_offset;
	176	struct pci_controller *hose;
de821204	177
3d5134ee	178	WARN_ON(bus == NULL);
31e92e0a	179
3d5134ee BH	180	/* If this not a PHB, nothing to do, page tables still exist and
	181	* thus HPTEs will be faulted in when needed
	182	*/
	183	if (bus->self) {
b0494bc8 BH	184	pr_debug("IO mapping for PCI-PCI bridge %s\n",
b0494bc8 BH	185	pci_name(bus->self));
9477e455	186	pr_debug(" virt=0x%016llx...0x%016llx\n",
b0494bc8 BH	187	bus->resource[0]->start + _IO_BASE,
b0494bc8 BH	188	bus->resource[0]->end + _IO_BASE);
3d5134ee	189	return 0;
1da177e4 LT	190	}
1da177e4 LT	191
3d5134ee BH	192	/* Get the host bridge */
	193	hose = pci_bus_to_host(bus);
	194	phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
	195	size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
1da177e4	196
3d5134ee BH	197	/* Make sure IO area address is clear */
3d5134ee BH	198	hose->io_base_alloc = NULL;
1da177e4	199
3d5134ee BH	200	/* If there's no IO to map on that bus, get away too */
	201	if (hose->pci_io_size == 0 \|\| hose->io_base_phys == 0)
	202	return 0;
1da177e4	203
3d5134ee BH	204	/* Let's allocate some IO space for that guy. We don't pass
	205	* VM_IOREMAP because we don't care about alignment tricks that
	206	* the core does in that case. Maybe we should due to stupid card
	207	* with incomplete address decoding but I'd rather not deal with
	208	* those outside of the reserved 64K legacy region.
	209	*/
	210	area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
	211	if (area == NULL)
	212	return -ENOMEM;
	213	hose->io_base_alloc = area->addr;
	214	hose->io_base_virt = (void __iomem *)(area->addr +
	215	hose->io_base_phys - phys_page);
	216
b0494bc8	217	pr_debug("IO mapping for PHB %s\n", hose->dn->full_name);
9477e455	218	pr_debug(" phys=0x%016llx, virt=0x%p (alloc=0x%p)\n",
b0494bc8	219	hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
bcba0778	220	pr_debug(" size=0x%016llx (alloc=0x%016lx)\n",
b0494bc8	221	hose->pci_io_size, size_page);
3d5134ee BH	222
	223	/* Establish the mapping */
	224	if (__ioremap_at(phys_page, area->addr, size_page,
	225	_PAGE_NO_CACHE \| _PAGE_GUARDED) == NULL)
	226	return -ENOMEM;
	227
	228	/* Fixup hose IO resource */
	229	io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
	230	hose->io_resource.start += io_virt_offset;
	231	hose->io_resource.end += io_virt_offset;
	232
9477e455	233	pr_debug(" hose->io_resource=0x%016llx...0x%016llx\n",
b0494bc8	234	hose->io_resource.start, hose->io_resource.end);
1da177e4 LT	235
	236	return 0;
	237	}
3d5134ee	238	EXPORT_SYMBOL_GPL(pcibios_map_io_space);
1da177e4	239
b2ad7b5e PM	240	#define IOBASE_BRIDGE_NUMBER 0
	241	#define IOBASE_MEMORY 1
	242	#define IOBASE_IO 2
	243	#define IOBASE_ISA_IO 3
	244	#define IOBASE_ISA_MEM 4
	245
	246	long sys_pciconfig_iobase(long which, unsigned long in_bus,
	247	unsigned long in_devfn)
	248	{
	249	struct pci_controller* hose;
	250	struct list_head *ln;
	251	struct pci_bus *bus = NULL;
	252	struct device_node *hose_node;
	253
	254	/* Argh ! Please forgive me for that hack, but that's the
	255	* simplest way to get existing XFree to not lockup on some
	256	* G5 machines... So when something asks for bus 0 io base
	257	* (bus 0 is HT root), we return the AGP one instead.
	258	*/
16124f10 PM	259	if (in_bus == 0 && machine_is_compatible("MacRISC4")) {
	260	struct device_node *agp;
	261
	262	agp = of_find_compatible_node(NULL, NULL, "u3-agp");
	263	if (agp)
b2ad7b5e	264	in_bus = 0xf0;
16124f10 PM	265	of_node_put(agp);
16124f10 PM	266	}
b2ad7b5e PM	267
	268	/* That syscall isn't quite compatible with PCI domains, but it's
	269	* used on pre-domains setup. We return the first match
	270	*/
	271
	272	for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
	273	bus = pci_bus_b(ln);
545da94f	274	if (in_bus >= bus->number && in_bus <= bus->subordinate)
b2ad7b5e PM	275	break;
	276	bus = NULL;
	277	}
	278	if (bus == NULL \|\| bus->sysdata == NULL)
	279	return -ENODEV;
	280
	281	hose_node = (struct device_node *)bus->sysdata;
	282	hose = PCI_DN(hose_node)->phb;
	283
	284	switch (which) {
	285	case IOBASE_BRIDGE_NUMBER:
	286	return (long)hose->first_busno;
	287	case IOBASE_MEMORY:
	288	return (long)hose->pci_mem_offset;
	289	case IOBASE_IO:
	290	return (long)hose->io_base_phys;
	291	case IOBASE_ISA_IO:
	292	return (long)isa_io_base;
	293	case IOBASE_ISA_MEM:
	294	return -EINVAL;
	295	}
	296
	297	return -EOPNOTSUPP;
	298	}
357518fa AB	299
	300	#ifdef CONFIG_NUMA
	301	int pcibus_to_node(struct pci_bus *bus)
	302	{
	303	struct pci_controller *phb = pci_bus_to_host(bus);
	304	return phb->node;
	305	}
	306	EXPORT_SYMBOL(pcibus_to_node);
	307	#endif