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5516b540 KG |
1 | /* |
2 | * Contains common pci routines for ALL ppc platform | |
cf1d8a8a KG |
3 | * (based on pci_32.c and pci_64.c) |
4 | * | |
5 | * Port for PPC64 David Engebretsen, IBM Corp. | |
6 | * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. | |
7 | * | |
8 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * Rework, based on alpha PCI code. | |
10 | * | |
11 | * Common pmac/prep/chrp pci routines. -- Cort | |
5516b540 KG |
12 | * |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License | |
15 | * as published by the Free Software Foundation; either version | |
16 | * 2 of the License, or (at your option) any later version. | |
17 | */ | |
18 | ||
5516b540 KG |
19 | #include <linux/kernel.h> |
20 | #include <linux/pci.h> | |
21 | #include <linux/string.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/bootmem.h> | |
d92a208d | 24 | #include <linux/delay.h> |
66b15db6 | 25 | #include <linux/export.h> |
22ae782f | 26 | #include <linux/of_address.h> |
04bea68b | 27 | #include <linux/of_pci.h> |
5516b540 KG |
28 | #include <linux/mm.h> |
29 | #include <linux/list.h> | |
30 | #include <linux/syscalls.h> | |
31 | #include <linux/irq.h> | |
32 | #include <linux/vmalloc.h> | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
c2e1d845 | 34 | #include <linux/vgaarb.h> |
5516b540 KG |
35 | |
36 | #include <asm/processor.h> | |
37 | #include <asm/io.h> | |
38 | #include <asm/prom.h> | |
39 | #include <asm/pci-bridge.h> | |
40 | #include <asm/byteorder.h> | |
41 | #include <asm/machdep.h> | |
42 | #include <asm/ppc-pci.h> | |
8b8da358 | 43 | #include <asm/eeh.h> |
5516b540 | 44 | |
a4c9e328 | 45 | static DEFINE_SPINLOCK(hose_spinlock); |
c3bd517d | 46 | LIST_HEAD(hose_list); |
a4c9e328 KG |
47 | |
48 | /* XXX kill that some day ... */ | |
ebfc00f7 | 49 | static int global_phb_number; /* Global phb counter */ |
a4c9e328 | 50 | |
25e81f92 BH |
51 | /* ISA Memory physical address */ |
52 | resource_size_t isa_mem_base; | |
53 | ||
a4c9e328 | 54 | |
45223c54 | 55 | static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; |
4fc665b8 | 56 | |
45223c54 | 57 | void set_pci_dma_ops(struct dma_map_ops *dma_ops) |
4fc665b8 BB |
58 | { |
59 | pci_dma_ops = dma_ops; | |
60 | } | |
61 | ||
45223c54 | 62 | struct dma_map_ops *get_pci_dma_ops(void) |
4fc665b8 BB |
63 | { |
64 | return pci_dma_ops; | |
65 | } | |
66 | EXPORT_SYMBOL(get_pci_dma_ops); | |
67 | ||
e60516e3 | 68 | struct pci_controller *pcibios_alloc_controller(struct device_node *dev) |
a4c9e328 KG |
69 | { |
70 | struct pci_controller *phb; | |
71 | ||
e60516e3 | 72 | phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); |
a4c9e328 KG |
73 | if (phb == NULL) |
74 | return NULL; | |
e60516e3 SR |
75 | spin_lock(&hose_spinlock); |
76 | phb->global_number = global_phb_number++; | |
77 | list_add_tail(&phb->list_node, &hose_list); | |
78 | spin_unlock(&hose_spinlock); | |
44ef3390 | 79 | phb->dn = dev; |
a4c9e328 KG |
80 | phb->is_dynamic = mem_init_done; |
81 | #ifdef CONFIG_PPC64 | |
82 | if (dev) { | |
83 | int nid = of_node_to_nid(dev); | |
84 | ||
85 | if (nid < 0 || !node_online(nid)) | |
86 | nid = -1; | |
87 | ||
88 | PHB_SET_NODE(phb, nid); | |
89 | } | |
90 | #endif | |
91 | return phb; | |
92 | } | |
93 | ||
94 | void pcibios_free_controller(struct pci_controller *phb) | |
95 | { | |
96 | spin_lock(&hose_spinlock); | |
97 | list_del(&phb->list_node); | |
98 | spin_unlock(&hose_spinlock); | |
99 | ||
100 | if (phb->is_dynamic) | |
101 | kfree(phb); | |
102 | } | |
103 | ||
4c2245bb GS |
104 | /* |
105 | * The function is used to return the minimal alignment | |
106 | * for memory or I/O windows of the associated P2P bridge. | |
107 | * By default, 4KiB alignment for I/O windows and 1MiB for | |
108 | * memory windows. | |
109 | */ | |
110 | resource_size_t pcibios_window_alignment(struct pci_bus *bus, | |
111 | unsigned long type) | |
112 | { | |
113 | if (ppc_md.pcibios_window_alignment) | |
114 | return ppc_md.pcibios_window_alignment(bus, type); | |
115 | ||
116 | /* | |
117 | * PCI core will figure out the default | |
118 | * alignment: 4KiB for I/O and 1MiB for | |
119 | * memory window. | |
120 | */ | |
121 | return 1; | |
122 | } | |
123 | ||
d92a208d GS |
124 | void pcibios_reset_secondary_bus(struct pci_dev *dev) |
125 | { | |
d92a208d GS |
126 | if (ppc_md.pcibios_reset_secondary_bus) { |
127 | ppc_md.pcibios_reset_secondary_bus(dev); | |
128 | return; | |
129 | } | |
130 | ||
21dd5a43 | 131 | pci_reset_secondary_bus(dev); |
d92a208d GS |
132 | } |
133 | ||
c3bd517d MM |
134 | static resource_size_t pcibios_io_size(const struct pci_controller *hose) |
135 | { | |
136 | #ifdef CONFIG_PPC64 | |
137 | return hose->pci_io_size; | |
138 | #else | |
28f65c11 | 139 | return resource_size(&hose->io_resource); |
c3bd517d MM |
140 | #endif |
141 | } | |
142 | ||
6dfbde20 BH |
143 | int pcibios_vaddr_is_ioport(void __iomem *address) |
144 | { | |
145 | int ret = 0; | |
146 | struct pci_controller *hose; | |
c3bd517d | 147 | resource_size_t size; |
6dfbde20 BH |
148 | |
149 | spin_lock(&hose_spinlock); | |
150 | list_for_each_entry(hose, &hose_list, list_node) { | |
c3bd517d | 151 | size = pcibios_io_size(hose); |
6dfbde20 BH |
152 | if (address >= hose->io_base_virt && |
153 | address < (hose->io_base_virt + size)) { | |
154 | ret = 1; | |
155 | break; | |
156 | } | |
157 | } | |
158 | spin_unlock(&hose_spinlock); | |
159 | return ret; | |
160 | } | |
161 | ||
c3bd517d MM |
162 | unsigned long pci_address_to_pio(phys_addr_t address) |
163 | { | |
164 | struct pci_controller *hose; | |
165 | resource_size_t size; | |
166 | unsigned long ret = ~0; | |
167 | ||
168 | spin_lock(&hose_spinlock); | |
169 | list_for_each_entry(hose, &hose_list, list_node) { | |
170 | size = pcibios_io_size(hose); | |
171 | if (address >= hose->io_base_phys && | |
172 | address < (hose->io_base_phys + size)) { | |
173 | unsigned long base = | |
174 | (unsigned long)hose->io_base_virt - _IO_BASE; | |
175 | ret = base + (address - hose->io_base_phys); | |
176 | break; | |
177 | } | |
178 | } | |
179 | spin_unlock(&hose_spinlock); | |
180 | ||
181 | return ret; | |
182 | } | |
183 | EXPORT_SYMBOL_GPL(pci_address_to_pio); | |
184 | ||
5516b540 KG |
185 | /* |
186 | * Return the domain number for this bus. | |
187 | */ | |
188 | int pci_domain_nr(struct pci_bus *bus) | |
189 | { | |
6207e816 | 190 | struct pci_controller *hose = pci_bus_to_host(bus); |
5516b540 | 191 | |
6207e816 | 192 | return hose->global_number; |
5516b540 | 193 | } |
5516b540 | 194 | EXPORT_SYMBOL(pci_domain_nr); |
58083dad | 195 | |
a4c9e328 KG |
196 | /* This routine is meant to be used early during boot, when the |
197 | * PCI bus numbers have not yet been assigned, and you need to | |
198 | * issue PCI config cycles to an OF device. | |
199 | * It could also be used to "fix" RTAS config cycles if you want | |
200 | * to set pci_assign_all_buses to 1 and still use RTAS for PCI | |
201 | * config cycles. | |
202 | */ | |
203 | struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) | |
204 | { | |
a4c9e328 KG |
205 | while(node) { |
206 | struct pci_controller *hose, *tmp; | |
207 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
44ef3390 | 208 | if (hose->dn == node) |
a4c9e328 KG |
209 | return hose; |
210 | node = node->parent; | |
211 | } | |
212 | return NULL; | |
213 | } | |
214 | ||
58083dad KG |
215 | /* |
216 | * Reads the interrupt pin to determine if interrupt is use by card. | |
217 | * If the interrupt is used, then gets the interrupt line from the | |
218 | * openfirmware and sets it in the pci_dev and pci_config line. | |
219 | */ | |
4666ca2a | 220 | static int pci_read_irq_line(struct pci_dev *pci_dev) |
58083dad | 221 | { |
530210c7 | 222 | struct of_phandle_args oirq; |
58083dad KG |
223 | unsigned int virq; |
224 | ||
b0494bc8 | 225 | pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); |
58083dad KG |
226 | |
227 | #ifdef DEBUG | |
228 | memset(&oirq, 0xff, sizeof(oirq)); | |
229 | #endif | |
230 | /* Try to get a mapping from the device-tree */ | |
0c02c800 | 231 | if (of_irq_parse_pci(pci_dev, &oirq)) { |
58083dad KG |
232 | u8 line, pin; |
233 | ||
234 | /* If that fails, lets fallback to what is in the config | |
235 | * space and map that through the default controller. We | |
236 | * also set the type to level low since that's what PCI | |
237 | * interrupts are. If your platform does differently, then | |
238 | * either provide a proper interrupt tree or don't use this | |
239 | * function. | |
240 | */ | |
241 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) | |
242 | return -1; | |
243 | if (pin == 0) | |
244 | return -1; | |
245 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || | |
54a24cbb | 246 | line == 0xff || line == 0) { |
58083dad KG |
247 | return -1; |
248 | } | |
b0494bc8 BH |
249 | pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", |
250 | line, pin); | |
58083dad KG |
251 | |
252 | virq = irq_create_mapping(NULL, line); | |
253 | if (virq != NO_IRQ) | |
ec775d0e | 254 | irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); |
58083dad | 255 | } else { |
b0494bc8 | 256 | pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", |
530210c7 GL |
257 | oirq.args_count, oirq.args[0], oirq.args[1], |
258 | of_node_full_name(oirq.np)); | |
58083dad | 259 | |
e6d30ab1 | 260 | virq = irq_create_of_mapping(&oirq); |
58083dad KG |
261 | } |
262 | if(virq == NO_IRQ) { | |
b0494bc8 | 263 | pr_debug(" Failed to map !\n"); |
58083dad KG |
264 | return -1; |
265 | } | |
266 | ||
b0494bc8 | 267 | pr_debug(" Mapped to linux irq %d\n", virq); |
58083dad KG |
268 | |
269 | pci_dev->irq = virq; | |
270 | ||
271 | return 0; | |
272 | } | |
58083dad KG |
273 | |
274 | /* | |
275 | * Platform support for /proc/bus/pci/X/Y mmap()s, | |
276 | * modelled on the sparc64 implementation by Dave Miller. | |
277 | * -- paulus. | |
278 | */ | |
279 | ||
280 | /* | |
281 | * Adjust vm_pgoff of VMA such that it is the physical page offset | |
282 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. | |
283 | * | |
284 | * Basically, the user finds the base address for his device which he wishes | |
285 | * to mmap. They read the 32-bit value from the config space base register, | |
286 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
287 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
288 | * | |
289 | * Returns negative error code on failure, zero on success. | |
290 | */ | |
291 | static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, | |
292 | resource_size_t *offset, | |
293 | enum pci_mmap_state mmap_state) | |
294 | { | |
295 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
296 | unsigned long io_offset = 0; | |
297 | int i, res_bit; | |
298 | ||
b0d436c7 | 299 | if (hose == NULL) |
58083dad KG |
300 | return NULL; /* should never happen */ |
301 | ||
302 | /* If memory, add on the PCI bridge address offset */ | |
303 | if (mmap_state == pci_mmap_mem) { | |
304 | #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ | |
305 | *offset += hose->pci_mem_offset; | |
306 | #endif | |
307 | res_bit = IORESOURCE_MEM; | |
308 | } else { | |
309 | io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
310 | *offset += io_offset; | |
311 | res_bit = IORESOURCE_IO; | |
312 | } | |
313 | ||
314 | /* | |
315 | * Check that the offset requested corresponds to one of the | |
316 | * resources of the device. | |
317 | */ | |
318 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
319 | struct resource *rp = &dev->resource[i]; | |
320 | int flags = rp->flags; | |
321 | ||
322 | /* treat ROM as memory (should be already) */ | |
323 | if (i == PCI_ROM_RESOURCE) | |
324 | flags |= IORESOURCE_MEM; | |
325 | ||
326 | /* Active and same type? */ | |
327 | if ((flags & res_bit) == 0) | |
328 | continue; | |
329 | ||
330 | /* In the range of this resource? */ | |
331 | if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) | |
332 | continue; | |
333 | ||
334 | /* found it! construct the final physical address */ | |
335 | if (mmap_state == pci_mmap_io) | |
336 | *offset += hose->io_base_phys - io_offset; | |
337 | return rp; | |
338 | } | |
339 | ||
340 | return NULL; | |
341 | } | |
342 | ||
343 | /* | |
344 | * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
345 | * device mapping. | |
346 | */ | |
347 | static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, | |
348 | pgprot_t protection, | |
349 | enum pci_mmap_state mmap_state, | |
350 | int write_combine) | |
351 | { | |
58083dad KG |
352 | |
353 | /* Write combine is always 0 on non-memory space mappings. On | |
354 | * memory space, if the user didn't pass 1, we check for a | |
355 | * "prefetchable" resource. This is a bit hackish, but we use | |
356 | * this to workaround the inability of /sysfs to provide a write | |
357 | * combine bit | |
358 | */ | |
359 | if (mmap_state != pci_mmap_mem) | |
360 | write_combine = 0; | |
361 | else if (write_combine == 0) { | |
362 | if (rp->flags & IORESOURCE_PREFETCH) | |
363 | write_combine = 1; | |
364 | } | |
365 | ||
366 | /* XXX would be nice to have a way to ask for write-through */ | |
58083dad | 367 | if (write_combine) |
83d5e64b | 368 | return pgprot_noncached_wc(protection); |
58083dad | 369 | else |
83d5e64b | 370 | return pgprot_noncached(protection); |
58083dad KG |
371 | } |
372 | ||
373 | /* | |
374 | * This one is used by /dev/mem and fbdev who have no clue about the | |
375 | * PCI device, it tries to find the PCI device first and calls the | |
376 | * above routine | |
377 | */ | |
378 | pgprot_t pci_phys_mem_access_prot(struct file *file, | |
379 | unsigned long pfn, | |
380 | unsigned long size, | |
64b3d0e8 | 381 | pgprot_t prot) |
58083dad KG |
382 | { |
383 | struct pci_dev *pdev = NULL; | |
384 | struct resource *found = NULL; | |
7c12d906 | 385 | resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; |
58083dad KG |
386 | int i; |
387 | ||
388 | if (page_is_ram(pfn)) | |
64b3d0e8 | 389 | return prot; |
58083dad | 390 | |
64b3d0e8 | 391 | prot = pgprot_noncached(prot); |
58083dad KG |
392 | for_each_pci_dev(pdev) { |
393 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
394 | struct resource *rp = &pdev->resource[i]; | |
395 | int flags = rp->flags; | |
396 | ||
397 | /* Active and same type? */ | |
398 | if ((flags & IORESOURCE_MEM) == 0) | |
399 | continue; | |
400 | /* In the range of this resource? */ | |
401 | if (offset < (rp->start & PAGE_MASK) || | |
402 | offset > rp->end) | |
403 | continue; | |
404 | found = rp; | |
405 | break; | |
406 | } | |
407 | if (found) | |
408 | break; | |
409 | } | |
410 | if (found) { | |
411 | if (found->flags & IORESOURCE_PREFETCH) | |
64b3d0e8 | 412 | prot = pgprot_noncached_wc(prot); |
58083dad KG |
413 | pci_dev_put(pdev); |
414 | } | |
415 | ||
b0494bc8 | 416 | pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", |
64b3d0e8 | 417 | (unsigned long long)offset, pgprot_val(prot)); |
58083dad | 418 | |
64b3d0e8 | 419 | return prot; |
58083dad KG |
420 | } |
421 | ||
422 | ||
423 | /* | |
424 | * Perform the actual remap of the pages for a PCI device mapping, as | |
425 | * appropriate for this architecture. The region in the process to map | |
426 | * is described by vm_start and vm_end members of VMA, the base physical | |
427 | * address is found in vm_pgoff. | |
428 | * The pci device structure is provided so that architectures may make mapping | |
429 | * decisions on a per-device or per-bus basis. | |
430 | * | |
431 | * Returns a negative error code on failure, zero on success. | |
432 | */ | |
433 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
434 | enum pci_mmap_state mmap_state, int write_combine) | |
435 | { | |
7c12d906 BH |
436 | resource_size_t offset = |
437 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
58083dad KG |
438 | struct resource *rp; |
439 | int ret; | |
440 | ||
441 | rp = __pci_mmap_make_offset(dev, &offset, mmap_state); | |
442 | if (rp == NULL) | |
443 | return -EINVAL; | |
444 | ||
445 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
446 | vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, | |
447 | vma->vm_page_prot, | |
448 | mmap_state, write_combine); | |
449 | ||
450 | ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
451 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | |
452 | ||
453 | return ret; | |
454 | } | |
455 | ||
e9f82cb7 BH |
456 | /* This provides legacy IO read access on a bus */ |
457 | int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) | |
458 | { | |
459 | unsigned long offset; | |
460 | struct pci_controller *hose = pci_bus_to_host(bus); | |
461 | struct resource *rp = &hose->io_resource; | |
462 | void __iomem *addr; | |
463 | ||
464 | /* Check if port can be supported by that bus. We only check | |
465 | * the ranges of the PHB though, not the bus itself as the rules | |
466 | * for forwarding legacy cycles down bridges are not our problem | |
467 | * here. So if the host bridge supports it, we do it. | |
468 | */ | |
469 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
470 | offset += port; | |
471 | ||
472 | if (!(rp->flags & IORESOURCE_IO)) | |
473 | return -ENXIO; | |
474 | if (offset < rp->start || (offset + size) > rp->end) | |
475 | return -ENXIO; | |
476 | addr = hose->io_base_virt + port; | |
477 | ||
478 | switch(size) { | |
479 | case 1: | |
480 | *((u8 *)val) = in_8(addr); | |
481 | return 1; | |
482 | case 2: | |
483 | if (port & 1) | |
484 | return -EINVAL; | |
485 | *((u16 *)val) = in_le16(addr); | |
486 | return 2; | |
487 | case 4: | |
488 | if (port & 3) | |
489 | return -EINVAL; | |
490 | *((u32 *)val) = in_le32(addr); | |
491 | return 4; | |
492 | } | |
493 | return -EINVAL; | |
494 | } | |
495 | ||
496 | /* This provides legacy IO write access on a bus */ | |
497 | int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) | |
498 | { | |
499 | unsigned long offset; | |
500 | struct pci_controller *hose = pci_bus_to_host(bus); | |
501 | struct resource *rp = &hose->io_resource; | |
502 | void __iomem *addr; | |
503 | ||
504 | /* Check if port can be supported by that bus. We only check | |
505 | * the ranges of the PHB though, not the bus itself as the rules | |
506 | * for forwarding legacy cycles down bridges are not our problem | |
507 | * here. So if the host bridge supports it, we do it. | |
508 | */ | |
509 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
510 | offset += port; | |
511 | ||
512 | if (!(rp->flags & IORESOURCE_IO)) | |
513 | return -ENXIO; | |
514 | if (offset < rp->start || (offset + size) > rp->end) | |
515 | return -ENXIO; | |
516 | addr = hose->io_base_virt + port; | |
517 | ||
518 | /* WARNING: The generic code is idiotic. It gets passed a pointer | |
519 | * to what can be a 1, 2 or 4 byte quantity and always reads that | |
520 | * as a u32, which means that we have to correct the location of | |
521 | * the data read within those 32 bits for size 1 and 2 | |
522 | */ | |
523 | switch(size) { | |
524 | case 1: | |
525 | out_8(addr, val >> 24); | |
526 | return 1; | |
527 | case 2: | |
528 | if (port & 1) | |
529 | return -EINVAL; | |
530 | out_le16(addr, val >> 16); | |
531 | return 2; | |
532 | case 4: | |
533 | if (port & 3) | |
534 | return -EINVAL; | |
535 | out_le32(addr, val); | |
536 | return 4; | |
537 | } | |
538 | return -EINVAL; | |
539 | } | |
540 | ||
541 | /* This provides legacy IO or memory mmap access on a bus */ | |
542 | int pci_mmap_legacy_page_range(struct pci_bus *bus, | |
543 | struct vm_area_struct *vma, | |
544 | enum pci_mmap_state mmap_state) | |
545 | { | |
546 | struct pci_controller *hose = pci_bus_to_host(bus); | |
547 | resource_size_t offset = | |
548 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
549 | resource_size_t size = vma->vm_end - vma->vm_start; | |
550 | struct resource *rp; | |
551 | ||
552 | pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", | |
553 | pci_domain_nr(bus), bus->number, | |
554 | mmap_state == pci_mmap_mem ? "MEM" : "IO", | |
555 | (unsigned long long)offset, | |
556 | (unsigned long long)(offset + size - 1)); | |
557 | ||
558 | if (mmap_state == pci_mmap_mem) { | |
5b11abfd BH |
559 | /* Hack alert ! |
560 | * | |
561 | * Because X is lame and can fail starting if it gets an error trying | |
562 | * to mmap legacy_mem (instead of just moving on without legacy memory | |
563 | * access) we fake it here by giving it anonymous memory, effectively | |
564 | * behaving just like /dev/zero | |
565 | */ | |
566 | if ((offset + size) > hose->isa_mem_size) { | |
567 | printk(KERN_DEBUG | |
568 | "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", | |
569 | current->comm, current->pid, pci_domain_nr(bus), bus->number); | |
570 | if (vma->vm_flags & VM_SHARED) | |
571 | return shmem_zero_setup(vma); | |
572 | return 0; | |
573 | } | |
e9f82cb7 BH |
574 | offset += hose->isa_mem_phys; |
575 | } else { | |
576 | unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
577 | unsigned long roffset = offset + io_offset; | |
578 | rp = &hose->io_resource; | |
579 | if (!(rp->flags & IORESOURCE_IO)) | |
580 | return -ENXIO; | |
581 | if (roffset < rp->start || (roffset + size) > rp->end) | |
582 | return -ENXIO; | |
583 | offset += hose->io_base_phys; | |
584 | } | |
585 | pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); | |
586 | ||
587 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
64b3d0e8 | 588 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
e9f82cb7 BH |
589 | return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, |
590 | vma->vm_end - vma->vm_start, | |
591 | vma->vm_page_prot); | |
592 | } | |
593 | ||
58083dad KG |
594 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
595 | const struct resource *rsrc, | |
596 | resource_size_t *start, resource_size_t *end) | |
597 | { | |
598 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
599 | resource_size_t offset = 0; | |
600 | ||
601 | if (hose == NULL) | |
602 | return; | |
603 | ||
604 | if (rsrc->flags & IORESOURCE_IO) | |
605 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
606 | ||
607 | /* We pass a fully fixed up address to userland for MMIO instead of | |
608 | * a BAR value because X is lame and expects to be able to use that | |
609 | * to pass to /dev/mem ! | |
610 | * | |
611 | * That means that we'll have potentially 64 bits values where some | |
612 | * userland apps only expect 32 (like X itself since it thinks only | |
613 | * Sparc has 64 bits MMIO) but if we don't do that, we break it on | |
614 | * 32 bits CHRPs :-( | |
615 | * | |
616 | * Hopefully, the sysfs insterface is immune to that gunk. Once X | |
617 | * has been fixed (and the fix spread enough), we can re-enable the | |
618 | * 2 lines below and pass down a BAR value to userland. In that case | |
619 | * we'll also have to re-enable the matching code in | |
620 | * __pci_mmap_make_offset(). | |
621 | * | |
622 | * BenH. | |
623 | */ | |
624 | #if 0 | |
625 | else if (rsrc->flags & IORESOURCE_MEM) | |
626 | offset = hose->pci_mem_offset; | |
627 | #endif | |
628 | ||
629 | *start = rsrc->start - offset; | |
630 | *end = rsrc->end - offset; | |
631 | } | |
13dccb9e BH |
632 | |
633 | /** | |
634 | * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree | |
635 | * @hose: newly allocated pci_controller to be setup | |
636 | * @dev: device node of the host bridge | |
637 | * @primary: set if primary bus (32 bits only, soon to be deprecated) | |
638 | * | |
639 | * This function will parse the "ranges" property of a PCI host bridge device | |
640 | * node and setup the resource mapping of a pci controller based on its | |
641 | * content. | |
642 | * | |
643 | * Life would be boring if it wasn't for a few issues that we have to deal | |
644 | * with here: | |
645 | * | |
646 | * - We can only cope with one IO space range and up to 3 Memory space | |
647 | * ranges. However, some machines (thanks Apple !) tend to split their | |
648 | * space into lots of small contiguous ranges. So we have to coalesce. | |
649 | * | |
13dccb9e BH |
650 | * - Some busses have IO space not starting at 0, which causes trouble with |
651 | * the way we do our IO resource renumbering. The code somewhat deals with | |
652 | * it for 64 bits but I would expect problems on 32 bits. | |
653 | * | |
654 | * - Some 32 bits platforms such as 4xx can have physical space larger than | |
655 | * 32 bits so we need to use 64 bits values for the parsing | |
656 | */ | |
cad5cef6 GKH |
657 | void pci_process_bridge_OF_ranges(struct pci_controller *hose, |
658 | struct device_node *dev, int primary) | |
13dccb9e | 659 | { |
858957ab | 660 | int memno = 0; |
13dccb9e | 661 | struct resource *res; |
654837e8 AM |
662 | struct of_pci_range range; |
663 | struct of_pci_range_parser parser; | |
13dccb9e BH |
664 | |
665 | printk(KERN_INFO "PCI host bridge %s %s ranges:\n", | |
666 | dev->full_name, primary ? "(primary)" : ""); | |
667 | ||
654837e8 AM |
668 | /* Check for ranges property */ |
669 | if (of_pci_range_parser_init(&parser, dev)) | |
13dccb9e BH |
670 | return; |
671 | ||
672 | /* Parse it */ | |
654837e8 | 673 | for_each_of_pci_range(&parser, &range) { |
e9f82cb7 BH |
674 | /* If we failed translation or got a zero-sized region |
675 | * (some FW try to feed us with non sensical zero sized regions | |
676 | * such as power3 which look like some kind of attempt at exposing | |
677 | * the VGA memory hole) | |
678 | */ | |
654837e8 | 679 | if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) |
13dccb9e BH |
680 | continue; |
681 | ||
13dccb9e BH |
682 | /* Act based on address space type */ |
683 | res = NULL; | |
654837e8 AM |
684 | switch (range.flags & IORESOURCE_TYPE_BITS) { |
685 | case IORESOURCE_IO: | |
13dccb9e BH |
686 | printk(KERN_INFO |
687 | " IO 0x%016llx..0x%016llx -> 0x%016llx\n", | |
654837e8 AM |
688 | range.cpu_addr, range.cpu_addr + range.size - 1, |
689 | range.pci_addr); | |
13dccb9e BH |
690 | |
691 | /* We support only one IO range */ | |
692 | if (hose->pci_io_size) { | |
693 | printk(KERN_INFO | |
694 | " \\--> Skipped (too many) !\n"); | |
695 | continue; | |
696 | } | |
697 | #ifdef CONFIG_PPC32 | |
698 | /* On 32 bits, limit I/O space to 16MB */ | |
654837e8 AM |
699 | if (range.size > 0x01000000) |
700 | range.size = 0x01000000; | |
13dccb9e BH |
701 | |
702 | /* 32 bits needs to map IOs here */ | |
654837e8 AM |
703 | hose->io_base_virt = ioremap(range.cpu_addr, |
704 | range.size); | |
13dccb9e BH |
705 | |
706 | /* Expect trouble if pci_addr is not 0 */ | |
707 | if (primary) | |
708 | isa_io_base = | |
709 | (unsigned long)hose->io_base_virt; | |
710 | #endif /* CONFIG_PPC32 */ | |
711 | /* pci_io_size and io_base_phys always represent IO | |
712 | * space starting at 0 so we factor in pci_addr | |
713 | */ | |
654837e8 AM |
714 | hose->pci_io_size = range.pci_addr + range.size; |
715 | hose->io_base_phys = range.cpu_addr - range.pci_addr; | |
13dccb9e BH |
716 | |
717 | /* Build resource */ | |
718 | res = &hose->io_resource; | |
654837e8 | 719 | range.cpu_addr = range.pci_addr; |
13dccb9e | 720 | break; |
654837e8 | 721 | case IORESOURCE_MEM: |
13dccb9e BH |
722 | printk(KERN_INFO |
723 | " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", | |
654837e8 AM |
724 | range.cpu_addr, range.cpu_addr + range.size - 1, |
725 | range.pci_addr, | |
726 | (range.pci_space & 0x40000000) ? | |
727 | "Prefetch" : ""); | |
13dccb9e BH |
728 | |
729 | /* We support only 3 memory ranges */ | |
730 | if (memno >= 3) { | |
731 | printk(KERN_INFO | |
732 | " \\--> Skipped (too many) !\n"); | |
733 | continue; | |
734 | } | |
735 | /* Handles ISA memory hole space here */ | |
654837e8 | 736 | if (range.pci_addr == 0) { |
13dccb9e | 737 | if (primary || isa_mem_base == 0) |
654837e8 AM |
738 | isa_mem_base = range.cpu_addr; |
739 | hose->isa_mem_phys = range.cpu_addr; | |
740 | hose->isa_mem_size = range.size; | |
13dccb9e BH |
741 | } |
742 | ||
13dccb9e | 743 | /* Build resource */ |
654837e8 AM |
744 | hose->mem_offset[memno] = range.cpu_addr - |
745 | range.pci_addr; | |
13dccb9e | 746 | res = &hose->mem_resources[memno++]; |
13dccb9e BH |
747 | break; |
748 | } | |
749 | if (res != NULL) { | |
aeba3731 ME |
750 | res->name = dev->full_name; |
751 | res->flags = range.flags; | |
752 | res->start = range.cpu_addr; | |
753 | res->end = range.cpu_addr + range.size - 1; | |
754 | res->parent = res->child = res->sibling = NULL; | |
13dccb9e BH |
755 | } |
756 | } | |
13dccb9e | 757 | } |
fa462f2d BH |
758 | |
759 | /* Decide whether to display the domain number in /proc */ | |
760 | int pci_proc_domain(struct pci_bus *bus) | |
761 | { | |
762 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1fd0f525 | 763 | |
0e47ff1c | 764 | if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) |
fa462f2d | 765 | return 0; |
0e47ff1c | 766 | if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) |
fa462f2d BH |
767 | return hose->global_number != 0; |
768 | return 1; | |
fa462f2d BH |
769 | } |
770 | ||
d82fb31a KSS |
771 | int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) |
772 | { | |
773 | if (ppc_md.pcibios_root_bridge_prepare) | |
774 | return ppc_md.pcibios_root_bridge_prepare(bridge); | |
775 | ||
776 | return 0; | |
777 | } | |
778 | ||
bf5e2ba2 BH |
779 | /* This header fixup will do the resource fixup for all devices as they are |
780 | * probed, but not for bridge ranges | |
781 | */ | |
cad5cef6 | 782 | static void pcibios_fixup_resources(struct pci_dev *dev) |
bf5e2ba2 BH |
783 | { |
784 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
785 | int i; | |
786 | ||
787 | if (!hose) { | |
788 | printk(KERN_ERR "No host bridge for PCI dev %s !\n", | |
789 | pci_name(dev)); | |
790 | return; | |
791 | } | |
792 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
793 | struct resource *res = dev->resource + i; | |
c5df457f | 794 | struct pci_bus_region reg; |
bf5e2ba2 BH |
795 | if (!res->flags) |
796 | continue; | |
48c2ce97 BH |
797 | |
798 | /* If we're going to re-assign everything, we mark all resources | |
799 | * as unset (and 0-base them). In addition, we mark BARs starting | |
800 | * at 0 as unset as well, except if PCI_PROBE_ONLY is also set | |
801 | * since in that case, we don't want to re-assign anything | |
7f172890 | 802 | */ |
fc279850 | 803 | pcibios_resource_to_bus(dev->bus, ®, res); |
48c2ce97 | 804 | if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || |
c5df457f | 805 | (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { |
48c2ce97 BH |
806 | /* Only print message if not re-assigning */ |
807 | if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) | |
808 | pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] " | |
809 | "is unassigned\n", | |
810 | pci_name(dev), i, | |
811 | (unsigned long long)res->start, | |
812 | (unsigned long long)res->end, | |
813 | (unsigned int)res->flags); | |
bf5e2ba2 BH |
814 | res->end -= res->start; |
815 | res->start = 0; | |
816 | res->flags |= IORESOURCE_UNSET; | |
817 | continue; | |
818 | } | |
819 | ||
6c5705fe | 820 | pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n", |
bf5e2ba2 BH |
821 | pci_name(dev), i, |
822 | (unsigned long long)res->start,\ | |
823 | (unsigned long long)res->end, | |
824 | (unsigned int)res->flags); | |
bf5e2ba2 BH |
825 | } |
826 | ||
827 | /* Call machine specific resource fixup */ | |
828 | if (ppc_md.pcibios_fixup_resources) | |
829 | ppc_md.pcibios_fixup_resources(dev); | |
830 | } | |
831 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); | |
832 | ||
b5561511 BH |
833 | /* This function tries to figure out if a bridge resource has been initialized |
834 | * by the firmware or not. It doesn't have to be absolutely bullet proof, but | |
835 | * things go more smoothly when it gets it right. It should covers cases such | |
836 | * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges | |
837 | */ | |
cad5cef6 GKH |
838 | static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, |
839 | struct resource *res) | |
bf5e2ba2 | 840 | { |
be8cbcd8 | 841 | struct pci_controller *hose = pci_bus_to_host(bus); |
bf5e2ba2 | 842 | struct pci_dev *dev = bus->self; |
b5561511 | 843 | resource_size_t offset; |
3fd47f06 | 844 | struct pci_bus_region region; |
b5561511 BH |
845 | u16 command; |
846 | int i; | |
bf5e2ba2 | 847 | |
b5561511 | 848 | /* We don't do anything if PCI_PROBE_ONLY is set */ |
0e47ff1c | 849 | if (pci_has_flag(PCI_PROBE_ONLY)) |
b5561511 | 850 | return 0; |
bf5e2ba2 | 851 | |
b5561511 BH |
852 | /* Job is a bit different between memory and IO */ |
853 | if (res->flags & IORESOURCE_MEM) { | |
fc279850 | 854 | pcibios_resource_to_bus(dev->bus, ®ion, res); |
3fd47f06 BH |
855 | |
856 | /* If the BAR is non-0 then it's probably been initialized */ | |
857 | if (region.start != 0) | |
b5561511 | 858 | return 0; |
bf5e2ba2 | 859 | |
b5561511 BH |
860 | /* The BAR is 0, let's check if memory decoding is enabled on |
861 | * the bridge. If not, we consider it unassigned | |
862 | */ | |
863 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
864 | if ((command & PCI_COMMAND_MEMORY) == 0) | |
865 | return 1; | |
be8cbcd8 | 866 | |
b5561511 BH |
867 | /* Memory decoding is enabled and the BAR is 0. If any of the bridge |
868 | * resources covers that starting address (0 then it's good enough for | |
3fd47f06 | 869 | * us for memory space) |
b5561511 BH |
870 | */ |
871 | for (i = 0; i < 3; i++) { | |
872 | if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && | |
3fd47f06 | 873 | hose->mem_resources[i].start == hose->mem_offset[i]) |
b5561511 BH |
874 | return 0; |
875 | } | |
876 | ||
877 | /* Well, it starts at 0 and we know it will collide so we may as | |
878 | * well consider it as unassigned. That covers the Apple case. | |
879 | */ | |
880 | return 1; | |
881 | } else { | |
882 | /* If the BAR is non-0, then we consider it assigned */ | |
883 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
884 | if (((res->start - offset) & 0xfffffffful) != 0) | |
885 | return 0; | |
886 | ||
887 | /* Here, we are a bit different than memory as typically IO space | |
888 | * starting at low addresses -is- valid. What we do instead if that | |
889 | * we consider as unassigned anything that doesn't have IO enabled | |
890 | * in the PCI command register, and that's it. | |
891 | */ | |
892 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
893 | if (command & PCI_COMMAND_IO) | |
894 | return 0; | |
895 | ||
896 | /* It's starting at 0 and IO is disabled in the bridge, consider | |
897 | * it unassigned | |
898 | */ | |
899 | return 1; | |
900 | } | |
901 | } | |
902 | ||
903 | /* Fixup resources of a PCI<->PCI bridge */ | |
cad5cef6 | 904 | static void pcibios_fixup_bridge(struct pci_bus *bus) |
b5561511 BH |
905 | { |
906 | struct resource *res; | |
907 | int i; | |
908 | ||
909 | struct pci_dev *dev = bus->self; | |
910 | ||
89a74ecc BH |
911 | pci_bus_for_each_resource(bus, res, i) { |
912 | if (!res || !res->flags) | |
b5561511 BH |
913 | continue; |
914 | if (i >= 3 && bus->self->transparent) | |
915 | continue; | |
916 | ||
cf1a4cf8 GS |
917 | /* If we're going to reassign everything, we can |
918 | * shrink the P2P resource to have size as being | |
919 | * of 0 in order to save space. | |
48c2ce97 BH |
920 | */ |
921 | if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { | |
922 | res->flags |= IORESOURCE_UNSET; | |
48c2ce97 | 923 | res->start = 0; |
cf1a4cf8 | 924 | res->end = -1; |
48c2ce97 BH |
925 | continue; |
926 | } | |
927 | ||
6c5705fe | 928 | pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n", |
b5561511 BH |
929 | pci_name(dev), i, |
930 | (unsigned long long)res->start,\ | |
931 | (unsigned long long)res->end, | |
932 | (unsigned int)res->flags); | |
bf5e2ba2 | 933 | |
b5561511 BH |
934 | /* Try to detect uninitialized P2P bridge resources, |
935 | * and clear them out so they get re-assigned later | |
936 | */ | |
937 | if (pcibios_uninitialized_bridge_resource(bus, res)) { | |
938 | res->flags = 0; | |
939 | pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); | |
bf5e2ba2 BH |
940 | } |
941 | } | |
b5561511 BH |
942 | } |
943 | ||
cad5cef6 | 944 | void pcibios_setup_bus_self(struct pci_bus *bus) |
8b8da358 | 945 | { |
7eef440a | 946 | /* Fix up the bus resources for P2P bridges */ |
8b8da358 BH |
947 | if (bus->self != NULL) |
948 | pcibios_fixup_bridge(bus); | |
949 | ||
950 | /* Platform specific bus fixups. This is currently only used | |
7eef440a | 951 | * by fsl_pci and I'm hoping to get rid of it at some point |
8b8da358 BH |
952 | */ |
953 | if (ppc_md.pcibios_fixup_bus) | |
954 | ppc_md.pcibios_fixup_bus(bus); | |
955 | ||
956 | /* Setup bus DMA mappings */ | |
957 | if (ppc_md.pci_dma_bus_setup) | |
958 | ppc_md.pci_dma_bus_setup(bus); | |
959 | } | |
960 | ||
7846de40 | 961 | static void pcibios_setup_device(struct pci_dev *dev) |
37f02195 YC |
962 | { |
963 | /* Fixup NUMA node as it may not be setup yet by the generic | |
964 | * code and is needed by the DMA init | |
965 | */ | |
966 | set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); | |
967 | ||
968 | /* Hook up default DMA ops */ | |
969 | set_dma_ops(&dev->dev, pci_dma_ops); | |
970 | set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); | |
971 | ||
972 | /* Additional platform DMA/iommu setup */ | |
973 | if (ppc_md.pci_dma_dev_setup) | |
974 | ppc_md.pci_dma_dev_setup(dev); | |
975 | ||
976 | /* Read default IRQs and fixup if necessary */ | |
977 | pci_read_irq_line(dev); | |
978 | if (ppc_md.pci_irq_fixup) | |
979 | ppc_md.pci_irq_fixup(dev); | |
980 | } | |
981 | ||
7846de40 GR |
982 | int pcibios_add_device(struct pci_dev *dev) |
983 | { | |
984 | /* | |
985 | * We can only call pcibios_setup_device() after bus setup is complete, | |
986 | * since some of the platform specific DMA setup code depends on it. | |
987 | */ | |
988 | if (dev->bus->is_added) | |
989 | pcibios_setup_device(dev); | |
990 | return 0; | |
991 | } | |
992 | ||
cad5cef6 | 993 | void pcibios_setup_bus_devices(struct pci_bus *bus) |
7eef440a BH |
994 | { |
995 | struct pci_dev *dev; | |
996 | ||
997 | pr_debug("PCI: Fixup bus devices %d (%s)\n", | |
998 | bus->number, bus->self ? pci_name(bus->self) : "PHB"); | |
999 | ||
1000 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
2d1c8618 BH |
1001 | /* Cardbus can call us to add new devices to a bus, so ignore |
1002 | * those who are already fully discovered | |
1003 | */ | |
1004 | if (dev->is_added) | |
1005 | continue; | |
1006 | ||
37f02195 | 1007 | pcibios_setup_device(dev); |
7eef440a BH |
1008 | } |
1009 | } | |
1010 | ||
79c8be83 MS |
1011 | void pcibios_set_master(struct pci_dev *dev) |
1012 | { | |
1013 | /* No special bus mastering setup handling */ | |
1014 | } | |
1015 | ||
cad5cef6 | 1016 | void pcibios_fixup_bus(struct pci_bus *bus) |
bf5e2ba2 BH |
1017 | { |
1018 | /* When called from the generic PCI probe, read PCI<->PCI bridge | |
7eef440a | 1019 | * bases. This is -not- called when generating the PCI tree from |
8b8da358 | 1020 | * the OF device-tree. |
bf5e2ba2 | 1021 | */ |
1a85d66b | 1022 | pci_read_bridge_bases(bus); |
bf5e2ba2 | 1023 | |
8b8da358 BH |
1024 | /* Now fixup the bus bus */ |
1025 | pcibios_setup_bus_self(bus); | |
1026 | ||
1027 | /* Now fixup devices on that bus */ | |
1028 | pcibios_setup_bus_devices(bus); | |
bf5e2ba2 | 1029 | } |
8b8da358 | 1030 | EXPORT_SYMBOL(pcibios_fixup_bus); |
3fd94c6b | 1031 | |
cad5cef6 | 1032 | void pci_fixup_cardbus(struct pci_bus *bus) |
2d1c8618 BH |
1033 | { |
1034 | /* Now fixup devices on that bus */ | |
1035 | pcibios_setup_bus_devices(bus); | |
1036 | } | |
1037 | ||
1038 | ||
3fd94c6b BH |
1039 | static int skip_isa_ioresource_align(struct pci_dev *dev) |
1040 | { | |
0e47ff1c | 1041 | if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && |
3fd94c6b BH |
1042 | !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) |
1043 | return 1; | |
1044 | return 0; | |
1045 | } | |
1046 | ||
1047 | /* | |
1048 | * We need to avoid collisions with `mirrored' VGA ports | |
1049 | * and other strange ISA hardware, so we always want the | |
1050 | * addresses to be allocated in the 0x000-0x0ff region | |
1051 | * modulo 0x400. | |
1052 | * | |
1053 | * Why? Because some silly external IO cards only decode | |
1054 | * the low 10 bits of the IO address. The 0x00-0xff region | |
1055 | * is reserved for motherboard devices that decode all 16 | |
1056 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
1057 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
1058 | * which might have be mirrored at 0x0100-0x03ff.. | |
1059 | */ | |
3b7a17fc | 1060 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
3fd94c6b BH |
1061 | resource_size_t size, resource_size_t align) |
1062 | { | |
1063 | struct pci_dev *dev = data; | |
b26b2d49 | 1064 | resource_size_t start = res->start; |
3fd94c6b BH |
1065 | |
1066 | if (res->flags & IORESOURCE_IO) { | |
3fd94c6b | 1067 | if (skip_isa_ioresource_align(dev)) |
b26b2d49 DB |
1068 | return start; |
1069 | if (start & 0x300) | |
3fd94c6b | 1070 | start = (start + 0x3ff) & ~0x3ff; |
3fd94c6b | 1071 | } |
b26b2d49 DB |
1072 | |
1073 | return start; | |
3fd94c6b BH |
1074 | } |
1075 | EXPORT_SYMBOL(pcibios_align_resource); | |
1076 | ||
1077 | /* | |
1078 | * Reparent resource children of pr that conflict with res | |
1079 | * under res, and make res replace those children. | |
1080 | */ | |
0f6023d5 | 1081 | static int reparent_resources(struct resource *parent, |
3fd94c6b BH |
1082 | struct resource *res) |
1083 | { | |
1084 | struct resource *p, **pp; | |
1085 | struct resource **firstpp = NULL; | |
1086 | ||
1087 | for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { | |
1088 | if (p->end < res->start) | |
1089 | continue; | |
1090 | if (res->end < p->start) | |
1091 | break; | |
1092 | if (p->start < res->start || p->end > res->end) | |
1093 | return -1; /* not completely contained */ | |
1094 | if (firstpp == NULL) | |
1095 | firstpp = pp; | |
1096 | } | |
1097 | if (firstpp == NULL) | |
1098 | return -1; /* didn't find any conflicting entries? */ | |
1099 | res->parent = parent; | |
1100 | res->child = *firstpp; | |
1101 | res->sibling = *pp; | |
1102 | *firstpp = res; | |
1103 | *pp = NULL; | |
1104 | for (p = res->child; p != NULL; p = p->sibling) { | |
1105 | p->parent = res; | |
b0494bc8 BH |
1106 | pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", |
1107 | p->name, | |
1108 | (unsigned long long)p->start, | |
1109 | (unsigned long long)p->end, res->name); | |
3fd94c6b BH |
1110 | } |
1111 | return 0; | |
1112 | } | |
1113 | ||
1114 | /* | |
1115 | * Handle resources of PCI devices. If the world were perfect, we could | |
1116 | * just allocate all the resource regions and do nothing more. It isn't. | |
1117 | * On the other hand, we cannot just re-allocate all devices, as it would | |
1118 | * require us to know lots of host bridge internals. So we attempt to | |
1119 | * keep as much of the original configuration as possible, but tweak it | |
1120 | * when it's found to be wrong. | |
1121 | * | |
1122 | * Known BIOS problems we have to work around: | |
1123 | * - I/O or memory regions not configured | |
1124 | * - regions configured, but not enabled in the command register | |
1125 | * - bogus I/O addresses above 64K used | |
1126 | * - expansion ROMs left enabled (this may sound harmless, but given | |
1127 | * the fact the PCI specs explicitly allow address decoders to be | |
1128 | * shared between expansion ROMs and other resource regions, it's | |
1129 | * at least dangerous) | |
1130 | * | |
1131 | * Our solution: | |
1132 | * (1) Allocate resources for all buses behind PCI-to-PCI bridges. | |
1133 | * This gives us fixed barriers on where we can allocate. | |
1134 | * (2) Allocate resources for all enabled devices. If there is | |
1135 | * a collision, just mark the resource as unallocated. Also | |
1136 | * disable expansion ROMs during this step. | |
1137 | * (3) Try to allocate resources for disabled devices. If the | |
1138 | * resources were assigned correctly, everything goes well, | |
1139 | * if they weren't, they won't disturb allocation of other | |
1140 | * resources. | |
1141 | * (4) Assign new addresses to resources which were either | |
1142 | * not configured at all or misconfigured. If explicitly | |
1143 | * requested by the user, configure expansion ROM address | |
1144 | * as well. | |
1145 | */ | |
1146 | ||
e51df2c1 | 1147 | static void pcibios_allocate_bus_resources(struct pci_bus *bus) |
3fd94c6b | 1148 | { |
e90a1318 | 1149 | struct pci_bus *b; |
3fd94c6b BH |
1150 | int i; |
1151 | struct resource *res, *pr; | |
1152 | ||
b5ae5f91 BH |
1153 | pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", |
1154 | pci_domain_nr(bus), bus->number); | |
1155 | ||
89a74ecc BH |
1156 | pci_bus_for_each_resource(bus, res, i) { |
1157 | if (!res || !res->flags || res->start > res->end || res->parent) | |
e90a1318 | 1158 | continue; |
48c2ce97 BH |
1159 | |
1160 | /* If the resource was left unset at this point, we clear it */ | |
1161 | if (res->flags & IORESOURCE_UNSET) | |
1162 | goto clear_resource; | |
1163 | ||
e90a1318 NF |
1164 | if (bus->parent == NULL) |
1165 | pr = (res->flags & IORESOURCE_IO) ? | |
1166 | &ioport_resource : &iomem_resource; | |
1167 | else { | |
e90a1318 NF |
1168 | pr = pci_find_parent_resource(bus->self, res); |
1169 | if (pr == res) { | |
1170 | /* this happens when the generic PCI | |
1171 | * code (wrongly) decides that this | |
1172 | * bridge is transparent -- paulus | |
3fd94c6b | 1173 | */ |
e90a1318 | 1174 | continue; |
3fd94c6b | 1175 | } |
e90a1318 | 1176 | } |
3fd94c6b | 1177 | |
b0494bc8 BH |
1178 | pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " |
1179 | "[0x%x], parent %p (%s)\n", | |
1180 | bus->self ? pci_name(bus->self) : "PHB", | |
1181 | bus->number, i, | |
1182 | (unsigned long long)res->start, | |
1183 | (unsigned long long)res->end, | |
1184 | (unsigned int)res->flags, | |
1185 | pr, (pr && pr->name) ? pr->name : "nil"); | |
e90a1318 NF |
1186 | |
1187 | if (pr && !(pr->flags & IORESOURCE_UNSET)) { | |
1188 | if (request_resource(pr, res) == 0) | |
1189 | continue; | |
1190 | /* | |
1191 | * Must be a conflict with an existing entry. | |
1192 | * Move that entry (or entries) under the | |
1193 | * bridge resource and try again. | |
1194 | */ | |
1195 | if (reparent_resources(pr, res) == 0) | |
1196 | continue; | |
3fd94c6b | 1197 | } |
48c2ce97 BH |
1198 | pr_warning("PCI: Cannot allocate resource region " |
1199 | "%d of PCI bridge %d, will remap\n", i, bus->number); | |
1200 | clear_resource: | |
cf1a4cf8 GS |
1201 | /* The resource might be figured out when doing |
1202 | * reassignment based on the resources required | |
1203 | * by the downstream PCI devices. Here we set | |
1204 | * the size of the resource to be 0 in order to | |
1205 | * save more space. | |
1206 | */ | |
1207 | res->start = 0; | |
1208 | res->end = -1; | |
e90a1318 | 1209 | res->flags = 0; |
3fd94c6b | 1210 | } |
e90a1318 NF |
1211 | |
1212 | list_for_each_entry(b, &bus->children, node) | |
1213 | pcibios_allocate_bus_resources(b); | |
3fd94c6b BH |
1214 | } |
1215 | ||
cad5cef6 | 1216 | static inline void alloc_resource(struct pci_dev *dev, int idx) |
3fd94c6b BH |
1217 | { |
1218 | struct resource *pr, *r = &dev->resource[idx]; | |
1219 | ||
b0494bc8 BH |
1220 | pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", |
1221 | pci_name(dev), idx, | |
1222 | (unsigned long long)r->start, | |
1223 | (unsigned long long)r->end, | |
1224 | (unsigned int)r->flags); | |
3fd94c6b BH |
1225 | |
1226 | pr = pci_find_parent_resource(dev, r); | |
1227 | if (!pr || (pr->flags & IORESOURCE_UNSET) || | |
1228 | request_resource(pr, r) < 0) { | |
1229 | printk(KERN_WARNING "PCI: Cannot allocate resource region %d" | |
1230 | " of device %s, will remap\n", idx, pci_name(dev)); | |
1231 | if (pr) | |
b0494bc8 BH |
1232 | pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", |
1233 | pr, | |
1234 | (unsigned long long)pr->start, | |
1235 | (unsigned long long)pr->end, | |
1236 | (unsigned int)pr->flags); | |
3fd94c6b BH |
1237 | /* We'll assign a new address later */ |
1238 | r->flags |= IORESOURCE_UNSET; | |
1239 | r->end -= r->start; | |
1240 | r->start = 0; | |
1241 | } | |
1242 | } | |
1243 | ||
1244 | static void __init pcibios_allocate_resources(int pass) | |
1245 | { | |
1246 | struct pci_dev *dev = NULL; | |
1247 | int idx, disabled; | |
1248 | u16 command; | |
1249 | struct resource *r; | |
1250 | ||
1251 | for_each_pci_dev(dev) { | |
1252 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
ad892a63 | 1253 | for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { |
3fd94c6b BH |
1254 | r = &dev->resource[idx]; |
1255 | if (r->parent) /* Already allocated */ | |
1256 | continue; | |
1257 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) | |
1258 | continue; /* Not assigned at all */ | |
ad892a63 BH |
1259 | /* We only allocate ROMs on pass 1 just in case they |
1260 | * have been screwed up by firmware | |
1261 | */ | |
1262 | if (idx == PCI_ROM_RESOURCE ) | |
1263 | disabled = 1; | |
3fd94c6b BH |
1264 | if (r->flags & IORESOURCE_IO) |
1265 | disabled = !(command & PCI_COMMAND_IO); | |
1266 | else | |
1267 | disabled = !(command & PCI_COMMAND_MEMORY); | |
533b1928 PM |
1268 | if (pass == disabled) |
1269 | alloc_resource(dev, idx); | |
3fd94c6b BH |
1270 | } |
1271 | if (pass) | |
1272 | continue; | |
1273 | r = &dev->resource[PCI_ROM_RESOURCE]; | |
ad892a63 | 1274 | if (r->flags) { |
3fd94c6b BH |
1275 | /* Turn the ROM off, leave the resource region, |
1276 | * but keep it unregistered. | |
1277 | */ | |
1278 | u32 reg; | |
3fd94c6b | 1279 | pci_read_config_dword(dev, dev->rom_base_reg, ®); |
ad892a63 BH |
1280 | if (reg & PCI_ROM_ADDRESS_ENABLE) { |
1281 | pr_debug("PCI: Switching off ROM of %s\n", | |
1282 | pci_name(dev)); | |
1283 | r->flags &= ~IORESOURCE_ROM_ENABLE; | |
1284 | pci_write_config_dword(dev, dev->rom_base_reg, | |
1285 | reg & ~PCI_ROM_ADDRESS_ENABLE); | |
1286 | } | |
3fd94c6b BH |
1287 | } |
1288 | } | |
1289 | } | |
1290 | ||
c1f34302 BH |
1291 | static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) |
1292 | { | |
1293 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1294 | resource_size_t offset; | |
1295 | struct resource *res, *pres; | |
1296 | int i; | |
1297 | ||
1298 | pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); | |
1299 | ||
1300 | /* Check for IO */ | |
1301 | if (!(hose->io_resource.flags & IORESOURCE_IO)) | |
1302 | goto no_io; | |
1303 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
1304 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
1305 | BUG_ON(res == NULL); | |
1306 | res->name = "Legacy IO"; | |
1307 | res->flags = IORESOURCE_IO; | |
1308 | res->start = offset; | |
1309 | res->end = (offset + 0xfff) & 0xfffffffful; | |
1310 | pr_debug("Candidate legacy IO: %pR\n", res); | |
1311 | if (request_resource(&hose->io_resource, res)) { | |
1312 | printk(KERN_DEBUG | |
1313 | "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", | |
1314 | pci_domain_nr(bus), bus->number, res); | |
1315 | kfree(res); | |
1316 | } | |
1317 | ||
1318 | no_io: | |
1319 | /* Check for memory */ | |
c1f34302 BH |
1320 | for (i = 0; i < 3; i++) { |
1321 | pres = &hose->mem_resources[i]; | |
3fd47f06 | 1322 | offset = hose->mem_offset[i]; |
c1f34302 BH |
1323 | if (!(pres->flags & IORESOURCE_MEM)) |
1324 | continue; | |
1325 | pr_debug("hose mem res: %pR\n", pres); | |
1326 | if ((pres->start - offset) <= 0xa0000 && | |
1327 | (pres->end - offset) >= 0xbffff) | |
1328 | break; | |
1329 | } | |
1330 | if (i >= 3) | |
1331 | return; | |
1332 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
1333 | BUG_ON(res == NULL); | |
1334 | res->name = "Legacy VGA memory"; | |
1335 | res->flags = IORESOURCE_MEM; | |
1336 | res->start = 0xa0000 + offset; | |
1337 | res->end = 0xbffff + offset; | |
1338 | pr_debug("Candidate VGA memory: %pR\n", res); | |
1339 | if (request_resource(pres, res)) { | |
1340 | printk(KERN_DEBUG | |
1341 | "PCI %04x:%02x Cannot reserve VGA memory %pR\n", | |
1342 | pci_domain_nr(bus), bus->number, res); | |
1343 | kfree(res); | |
1344 | } | |
1345 | } | |
1346 | ||
3fd94c6b BH |
1347 | void __init pcibios_resource_survey(void) |
1348 | { | |
e90a1318 NF |
1349 | struct pci_bus *b; |
1350 | ||
48c2ce97 | 1351 | /* Allocate and assign resources */ |
e90a1318 NF |
1352 | list_for_each_entry(b, &pci_root_buses, node) |
1353 | pcibios_allocate_bus_resources(b); | |
48c2ce97 BH |
1354 | pcibios_allocate_resources(0); |
1355 | pcibios_allocate_resources(1); | |
3fd94c6b | 1356 | |
c1f34302 BH |
1357 | /* Before we start assigning unassigned resource, we try to reserve |
1358 | * the low IO area and the VGA memory area if they intersect the | |
1359 | * bus available resources to avoid allocating things on top of them | |
1360 | */ | |
0e47ff1c | 1361 | if (!pci_has_flag(PCI_PROBE_ONLY)) { |
c1f34302 BH |
1362 | list_for_each_entry(b, &pci_root_buses, node) |
1363 | pcibios_reserve_legacy_regions(b); | |
1364 | } | |
1365 | ||
1366 | /* Now, if the platform didn't decide to blindly trust the firmware, | |
1367 | * we proceed to assigning things that were left unassigned | |
1368 | */ | |
0e47ff1c | 1369 | if (!pci_has_flag(PCI_PROBE_ONLY)) { |
a77acda0 | 1370 | pr_debug("PCI: Assigning unassigned resources...\n"); |
3fd94c6b BH |
1371 | pci_assign_unassigned_resources(); |
1372 | } | |
1373 | ||
1374 | /* Call machine dependent fixup */ | |
1375 | if (ppc_md.pcibios_fixup) | |
1376 | ppc_md.pcibios_fixup(); | |
1377 | } | |
1378 | ||
fd6852c8 | 1379 | /* This is used by the PCI hotplug driver to allocate resource |
3fd94c6b | 1380 | * of newly plugged busses. We can try to consolidate with the |
fd6852c8 BH |
1381 | * rest of the code later, for now, keep it as-is as our main |
1382 | * resource allocation function doesn't deal with sub-trees yet. | |
3fd94c6b | 1383 | */ |
baf75b0a | 1384 | void pcibios_claim_one_bus(struct pci_bus *bus) |
3fd94c6b BH |
1385 | { |
1386 | struct pci_dev *dev; | |
1387 | struct pci_bus *child_bus; | |
1388 | ||
1389 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1390 | int i; | |
1391 | ||
1392 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1393 | struct resource *r = &dev->resource[i]; | |
1394 | ||
1395 | if (r->parent || !r->start || !r->flags) | |
1396 | continue; | |
fd6852c8 BH |
1397 | |
1398 | pr_debug("PCI: Claiming %s: " | |
1399 | "Resource %d: %016llx..%016llx [%x]\n", | |
1400 | pci_name(dev), i, | |
1401 | (unsigned long long)r->start, | |
1402 | (unsigned long long)r->end, | |
1403 | (unsigned int)r->flags); | |
1404 | ||
3fd94c6b BH |
1405 | pci_claim_resource(dev, i); |
1406 | } | |
1407 | } | |
1408 | ||
1409 | list_for_each_entry(child_bus, &bus->children, node) | |
1410 | pcibios_claim_one_bus(child_bus); | |
1411 | } | |
fd6852c8 BH |
1412 | |
1413 | ||
1414 | /* pcibios_finish_adding_to_bus | |
1415 | * | |
1416 | * This is to be called by the hotplug code after devices have been | |
1417 | * added to a bus, this include calling it for a PHB that is just | |
1418 | * being added | |
1419 | */ | |
1420 | void pcibios_finish_adding_to_bus(struct pci_bus *bus) | |
1421 | { | |
1422 | pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", | |
1423 | pci_domain_nr(bus), bus->number); | |
1424 | ||
1425 | /* Allocate bus and devices resources */ | |
1426 | pcibios_allocate_bus_resources(bus); | |
1427 | pcibios_claim_one_bus(bus); | |
ab444ec9 GS |
1428 | if (!pci_has_flag(PCI_PROBE_ONLY)) |
1429 | pci_assign_unassigned_bus_resources(bus); | |
fd6852c8 | 1430 | |
6a040ce7 TLSC |
1431 | /* Fixup EEH */ |
1432 | eeh_add_device_tree_late(bus); | |
1433 | ||
fd6852c8 BH |
1434 | /* Add new devices to global lists. Register in proc, sysfs. */ |
1435 | pci_bus_add_devices(bus); | |
1436 | ||
6a040ce7 TLSC |
1437 | /* sysfs files should only be added after devices are added */ |
1438 | eeh_add_sysfs_files(bus); | |
fd6852c8 BH |
1439 | } |
1440 | EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); | |
1441 | ||
549beb9b BH |
1442 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
1443 | { | |
549beb9b BH |
1444 | if (ppc_md.pcibios_enable_device_hook) |
1445 | if (ppc_md.pcibios_enable_device_hook(dev)) | |
1446 | return -EINVAL; | |
1447 | ||
7cfb5f9a | 1448 | return pci_enable_resources(dev, mask); |
549beb9b | 1449 | } |
53280323 | 1450 | |
38973ba7 BH |
1451 | resource_size_t pcibios_io_space_offset(struct pci_controller *hose) |
1452 | { | |
1453 | return (unsigned long) hose->io_base_virt - _IO_BASE; | |
1454 | } | |
1455 | ||
cad5cef6 GKH |
1456 | static void pcibios_setup_phb_resources(struct pci_controller *hose, |
1457 | struct list_head *resources) | |
53280323 | 1458 | { |
53280323 | 1459 | struct resource *res; |
3fd47f06 | 1460 | resource_size_t offset; |
53280323 BH |
1461 | int i; |
1462 | ||
1463 | /* Hookup PHB IO resource */ | |
45a709f8 | 1464 | res = &hose->io_resource; |
53280323 BH |
1465 | |
1466 | if (!res->flags) { | |
adb7cd73 | 1467 | pr_info("PCI: I/O resource not set for host" |
53280323 BH |
1468 | " bridge %s (domain %d)\n", |
1469 | hose->dn->full_name, hose->global_number); | |
3fd47f06 BH |
1470 | } else { |
1471 | offset = pcibios_io_space_offset(hose); | |
1472 | ||
1473 | pr_debug("PCI: PHB IO resource = %08llx-%08llx [%lx] off 0x%08llx\n", | |
a0b8e76f BH |
1474 | (unsigned long long)res->start, |
1475 | (unsigned long long)res->end, | |
3fd47f06 BH |
1476 | (unsigned long)res->flags, |
1477 | (unsigned long long)offset); | |
1478 | pci_add_resource_offset(resources, res, offset); | |
a0b8e76f | 1479 | } |
53280323 BH |
1480 | |
1481 | /* Hookup PHB Memory resources */ | |
1482 | for (i = 0; i < 3; ++i) { | |
1483 | res = &hose->mem_resources[i]; | |
1484 | if (!res->flags) { | |
bee7dd9c BH |
1485 | if (i == 0) |
1486 | printk(KERN_ERR "PCI: Memory resource 0 not set for " | |
1487 | "host bridge %s (domain %d)\n", | |
1488 | hose->dn->full_name, hose->global_number); | |
3fd47f06 | 1489 | continue; |
a0b8e76f | 1490 | } |
3fd47f06 | 1491 | offset = hose->mem_offset[i]; |
53280323 | 1492 | |
3fd47f06 BH |
1493 | |
1494 | pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i, | |
1495 | (unsigned long long)res->start, | |
1496 | (unsigned long long)res->end, | |
1497 | (unsigned long)res->flags, | |
1498 | (unsigned long long)offset); | |
1499 | ||
1500 | pci_add_resource_offset(resources, res, offset); | |
1501 | } | |
53280323 | 1502 | } |
89c2dd62 KG |
1503 | |
1504 | /* | |
1505 | * Null PCI config access functions, for the case when we can't | |
1506 | * find a hose. | |
1507 | */ | |
1508 | #define NULL_PCI_OP(rw, size, type) \ | |
1509 | static int \ | |
1510 | null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ | |
1511 | { \ | |
1512 | return PCIBIOS_DEVICE_NOT_FOUND; \ | |
1513 | } | |
1514 | ||
1515 | static int | |
1516 | null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1517 | int len, u32 *val) | |
1518 | { | |
1519 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1520 | } | |
1521 | ||
1522 | static int | |
1523 | null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1524 | int len, u32 val) | |
1525 | { | |
1526 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1527 | } | |
1528 | ||
1529 | static struct pci_ops null_pci_ops = | |
1530 | { | |
1531 | .read = null_read_config, | |
1532 | .write = null_write_config, | |
1533 | }; | |
1534 | ||
1535 | /* | |
1536 | * These functions are used early on before PCI scanning is done | |
1537 | * and all of the pci_dev and pci_bus structures have been created. | |
1538 | */ | |
1539 | static struct pci_bus * | |
1540 | fake_pci_bus(struct pci_controller *hose, int busnr) | |
1541 | { | |
1542 | static struct pci_bus bus; | |
1543 | ||
b0d436c7 | 1544 | if (hose == NULL) { |
89c2dd62 KG |
1545 | printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); |
1546 | } | |
1547 | bus.number = busnr; | |
1548 | bus.sysdata = hose; | |
1549 | bus.ops = hose? hose->ops: &null_pci_ops; | |
1550 | return &bus; | |
1551 | } | |
1552 | ||
1553 | #define EARLY_PCI_OP(rw, size, type) \ | |
1554 | int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ | |
1555 | int devfn, int offset, type value) \ | |
1556 | { \ | |
1557 | return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ | |
1558 | devfn, offset, value); \ | |
1559 | } | |
1560 | ||
1561 | EARLY_PCI_OP(read, byte, u8 *) | |
1562 | EARLY_PCI_OP(read, word, u16 *) | |
1563 | EARLY_PCI_OP(read, dword, u32 *) | |
1564 | EARLY_PCI_OP(write, byte, u8) | |
1565 | EARLY_PCI_OP(write, word, u16) | |
1566 | EARLY_PCI_OP(write, dword, u32) | |
1567 | ||
89c2dd62 KG |
1568 | int early_find_capability(struct pci_controller *hose, int bus, int devfn, |
1569 | int cap) | |
1570 | { | |
1571 | return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); | |
1572 | } | |
0ed2c722 | 1573 | |
98d9f30c BH |
1574 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) |
1575 | { | |
1576 | struct pci_controller *hose = bus->sysdata; | |
1577 | ||
1578 | return of_node_get(hose->dn); | |
1579 | } | |
1580 | ||
0ed2c722 GL |
1581 | /** |
1582 | * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus | |
1583 | * @hose: Pointer to the PCI host controller instance structure | |
0ed2c722 | 1584 | */ |
cad5cef6 | 1585 | void pcibios_scan_phb(struct pci_controller *hose) |
0ed2c722 | 1586 | { |
45a709f8 | 1587 | LIST_HEAD(resources); |
0ed2c722 GL |
1588 | struct pci_bus *bus; |
1589 | struct device_node *node = hose->dn; | |
1590 | int mode; | |
1591 | ||
74a7f084 | 1592 | pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node)); |
0ed2c722 | 1593 | |
45a709f8 BH |
1594 | /* Get some IO space for the new PHB */ |
1595 | pcibios_setup_phb_io_space(hose); | |
1596 | ||
1597 | /* Wire up PHB bus resources */ | |
1598 | pcibios_setup_phb_resources(hose, &resources); | |
1599 | ||
be8e60d8 YL |
1600 | hose->busn.start = hose->first_busno; |
1601 | hose->busn.end = hose->last_busno; | |
1602 | hose->busn.flags = IORESOURCE_BUS; | |
1603 | pci_add_resource(&resources, &hose->busn); | |
1604 | ||
0ed2c722 | 1605 | /* Create an empty bus for the toplevel */ |
45a709f8 BH |
1606 | bus = pci_create_root_bus(hose->parent, hose->first_busno, |
1607 | hose->ops, hose, &resources); | |
0ed2c722 GL |
1608 | if (bus == NULL) { |
1609 | pr_err("Failed to create bus for PCI domain %04x\n", | |
1610 | hose->global_number); | |
45a709f8 | 1611 | pci_free_resource_list(&resources); |
0ed2c722 GL |
1612 | return; |
1613 | } | |
0ed2c722 GL |
1614 | hose->bus = bus; |
1615 | ||
0ed2c722 GL |
1616 | /* Get probe mode and perform scan */ |
1617 | mode = PCI_PROBE_NORMAL; | |
1618 | if (node && ppc_md.pci_probe_mode) | |
1619 | mode = ppc_md.pci_probe_mode(bus); | |
1620 | pr_debug(" probe mode: %d\n", mode); | |
be8e60d8 | 1621 | if (mode == PCI_PROBE_DEVTREE) |
0ed2c722 | 1622 | of_scan_bus(node, bus); |
0ed2c722 | 1623 | |
be8e60d8 YL |
1624 | if (mode == PCI_PROBE_NORMAL) { |
1625 | pci_bus_update_busn_res_end(bus, 255); | |
1626 | hose->last_busno = pci_scan_child_bus(bus); | |
1627 | pci_bus_update_busn_res_end(bus, hose->last_busno); | |
1628 | } | |
781fb7a3 | 1629 | |
491b98c3 BH |
1630 | /* Platform gets a chance to do some global fixups before |
1631 | * we proceed to resource allocation | |
1632 | */ | |
1633 | if (ppc_md.pcibios_fixup_phb) | |
1634 | ppc_md.pcibios_fixup_phb(hose); | |
1635 | ||
781fb7a3 | 1636 | /* Configure PCI Express settings */ |
bb36c445 | 1637 | if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { |
781fb7a3 | 1638 | struct pci_bus *child; |
a58674ff BH |
1639 | list_for_each_entry(child, &bus->children, node) |
1640 | pcie_bus_configure_settings(child); | |
781fb7a3 | 1641 | } |
0ed2c722 | 1642 | } |
c065488f KG |
1643 | |
1644 | static void fixup_hide_host_resource_fsl(struct pci_dev *dev) | |
1645 | { | |
1646 | int i, class = dev->class >> 8; | |
05737c7c JJ |
1647 | /* When configured as agent, programing interface = 1 */ |
1648 | int prog_if = dev->class & 0xf; | |
c065488f KG |
1649 | |
1650 | if ((class == PCI_CLASS_PROCESSOR_POWERPC || | |
1651 | class == PCI_CLASS_BRIDGE_OTHER) && | |
1652 | (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && | |
05737c7c | 1653 | (prog_if == 0) && |
c065488f KG |
1654 | (dev->bus->parent == NULL)) { |
1655 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1656 | dev->resource[i].start = 0; | |
1657 | dev->resource[i].end = 0; | |
1658 | dev->resource[i].flags = 0; | |
1659 | } | |
1660 | } | |
1661 | } | |
1662 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); | |
1663 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); | |
c2e1d845 BK |
1664 | |
1665 | static void fixup_vga(struct pci_dev *pdev) | |
1666 | { | |
1667 | u16 cmd; | |
1668 | ||
1669 | pci_read_config_word(pdev, PCI_COMMAND, &cmd); | |
1670 | if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device()) | |
1671 | vga_set_default_device(pdev); | |
1672 | ||
1673 | } | |
1674 | DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, | |
1675 | PCI_CLASS_DISPLAY_VGA, 8, fixup_vga); |