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5516b540 KG |
1 | /* |
2 | * Contains common pci routines for ALL ppc platform | |
cf1d8a8a KG |
3 | * (based on pci_32.c and pci_64.c) |
4 | * | |
5 | * Port for PPC64 David Engebretsen, IBM Corp. | |
6 | * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. | |
7 | * | |
8 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * Rework, based on alpha PCI code. | |
10 | * | |
11 | * Common pmac/prep/chrp pci routines. -- Cort | |
5516b540 KG |
12 | * |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License | |
15 | * as published by the Free Software Foundation; either version | |
16 | * 2 of the License, or (at your option) any later version. | |
17 | */ | |
18 | ||
19 | #undef DEBUG | |
20 | ||
21 | #include <linux/kernel.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/string.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/bootmem.h> | |
26 | #include <linux/mm.h> | |
27 | #include <linux/list.h> | |
28 | #include <linux/syscalls.h> | |
29 | #include <linux/irq.h> | |
30 | #include <linux/vmalloc.h> | |
31 | ||
32 | #include <asm/processor.h> | |
33 | #include <asm/io.h> | |
34 | #include <asm/prom.h> | |
35 | #include <asm/pci-bridge.h> | |
36 | #include <asm/byteorder.h> | |
37 | #include <asm/machdep.h> | |
38 | #include <asm/ppc-pci.h> | |
39 | #include <asm/firmware.h> | |
40 | ||
41 | #ifdef DEBUG | |
42 | #include <asm/udbg.h> | |
43 | #define DBG(fmt...) printk(fmt) | |
44 | #else | |
45 | #define DBG(fmt...) | |
46 | #endif | |
47 | ||
a4c9e328 KG |
48 | static DEFINE_SPINLOCK(hose_spinlock); |
49 | ||
50 | /* XXX kill that some day ... */ | |
ebfc00f7 | 51 | static int global_phb_number; /* Global phb counter */ |
a4c9e328 | 52 | |
25e81f92 BH |
53 | /* ISA Memory physical address */ |
54 | resource_size_t isa_mem_base; | |
55 | ||
3fd94c6b BH |
56 | /* Default PCI flags is 0 */ |
57 | unsigned int ppc_pci_flags; | |
a4c9e328 | 58 | |
4fc665b8 BB |
59 | static struct dma_mapping_ops *pci_dma_ops; |
60 | ||
61 | void set_pci_dma_ops(struct dma_mapping_ops *dma_ops) | |
62 | { | |
63 | pci_dma_ops = dma_ops; | |
64 | } | |
65 | ||
66 | struct dma_mapping_ops *get_pci_dma_ops(void) | |
67 | { | |
68 | return pci_dma_ops; | |
69 | } | |
70 | EXPORT_SYMBOL(get_pci_dma_ops); | |
71 | ||
72 | int pci_set_dma_mask(struct pci_dev *dev, u64 mask) | |
73 | { | |
74 | return dma_set_mask(&dev->dev, mask); | |
75 | } | |
76 | ||
77 | int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |
78 | { | |
79 | int rc; | |
80 | ||
81 | rc = dma_set_mask(&dev->dev, mask); | |
82 | dev->dev.coherent_dma_mask = dev->dma_mask; | |
83 | ||
84 | return rc; | |
85 | } | |
86 | ||
e60516e3 | 87 | struct pci_controller *pcibios_alloc_controller(struct device_node *dev) |
a4c9e328 KG |
88 | { |
89 | struct pci_controller *phb; | |
90 | ||
e60516e3 | 91 | phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); |
a4c9e328 KG |
92 | if (phb == NULL) |
93 | return NULL; | |
e60516e3 SR |
94 | spin_lock(&hose_spinlock); |
95 | phb->global_number = global_phb_number++; | |
96 | list_add_tail(&phb->list_node, &hose_list); | |
97 | spin_unlock(&hose_spinlock); | |
44ef3390 | 98 | phb->dn = dev; |
a4c9e328 KG |
99 | phb->is_dynamic = mem_init_done; |
100 | #ifdef CONFIG_PPC64 | |
101 | if (dev) { | |
102 | int nid = of_node_to_nid(dev); | |
103 | ||
104 | if (nid < 0 || !node_online(nid)) | |
105 | nid = -1; | |
106 | ||
107 | PHB_SET_NODE(phb, nid); | |
108 | } | |
109 | #endif | |
110 | return phb; | |
111 | } | |
112 | ||
113 | void pcibios_free_controller(struct pci_controller *phb) | |
114 | { | |
115 | spin_lock(&hose_spinlock); | |
116 | list_del(&phb->list_node); | |
117 | spin_unlock(&hose_spinlock); | |
118 | ||
119 | if (phb->is_dynamic) | |
120 | kfree(phb); | |
121 | } | |
122 | ||
6dfbde20 BH |
123 | int pcibios_vaddr_is_ioport(void __iomem *address) |
124 | { | |
125 | int ret = 0; | |
126 | struct pci_controller *hose; | |
127 | unsigned long size; | |
128 | ||
129 | spin_lock(&hose_spinlock); | |
130 | list_for_each_entry(hose, &hose_list, list_node) { | |
131 | #ifdef CONFIG_PPC64 | |
132 | size = hose->pci_io_size; | |
133 | #else | |
134 | size = hose->io_resource.end - hose->io_resource.start + 1; | |
135 | #endif | |
136 | if (address >= hose->io_base_virt && | |
137 | address < (hose->io_base_virt + size)) { | |
138 | ret = 1; | |
139 | break; | |
140 | } | |
141 | } | |
142 | spin_unlock(&hose_spinlock); | |
143 | return ret; | |
144 | } | |
145 | ||
5516b540 KG |
146 | /* |
147 | * Return the domain number for this bus. | |
148 | */ | |
149 | int pci_domain_nr(struct pci_bus *bus) | |
150 | { | |
6207e816 | 151 | struct pci_controller *hose = pci_bus_to_host(bus); |
5516b540 | 152 | |
6207e816 | 153 | return hose->global_number; |
5516b540 | 154 | } |
5516b540 | 155 | EXPORT_SYMBOL(pci_domain_nr); |
58083dad KG |
156 | |
157 | #ifdef CONFIG_PPC_OF | |
a4c9e328 KG |
158 | |
159 | /* This routine is meant to be used early during boot, when the | |
160 | * PCI bus numbers have not yet been assigned, and you need to | |
161 | * issue PCI config cycles to an OF device. | |
162 | * It could also be used to "fix" RTAS config cycles if you want | |
163 | * to set pci_assign_all_buses to 1 and still use RTAS for PCI | |
164 | * config cycles. | |
165 | */ | |
166 | struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) | |
167 | { | |
168 | if (!have_of) | |
169 | return NULL; | |
170 | while(node) { | |
171 | struct pci_controller *hose, *tmp; | |
172 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
44ef3390 | 173 | if (hose->dn == node) |
a4c9e328 KG |
174 | return hose; |
175 | node = node->parent; | |
176 | } | |
177 | return NULL; | |
178 | } | |
179 | ||
58083dad KG |
180 | static ssize_t pci_show_devspec(struct device *dev, |
181 | struct device_attribute *attr, char *buf) | |
182 | { | |
183 | struct pci_dev *pdev; | |
184 | struct device_node *np; | |
185 | ||
186 | pdev = to_pci_dev (dev); | |
187 | np = pci_device_to_OF_node(pdev); | |
188 | if (np == NULL || np->full_name == NULL) | |
189 | return 0; | |
190 | return sprintf(buf, "%s", np->full_name); | |
191 | } | |
192 | static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL); | |
193 | #endif /* CONFIG_PPC_OF */ | |
194 | ||
195 | /* Add sysfs properties */ | |
4f3731da | 196 | int pcibios_add_platform_entries(struct pci_dev *pdev) |
58083dad KG |
197 | { |
198 | #ifdef CONFIG_PPC_OF | |
4f3731da TB |
199 | return device_create_file(&pdev->dev, &dev_attr_devspec); |
200 | #else | |
201 | return 0; | |
58083dad | 202 | #endif /* CONFIG_PPC_OF */ |
4f3731da | 203 | |
58083dad KG |
204 | } |
205 | ||
a2b7390a | 206 | char __devinit *pcibios_setup(char *str) |
58083dad KG |
207 | { |
208 | return str; | |
209 | } | |
210 | ||
4fc665b8 BB |
211 | void __devinit pcibios_setup_new_device(struct pci_dev *dev) |
212 | { | |
213 | struct dev_archdata *sd = &dev->dev.archdata; | |
214 | ||
215 | sd->of_node = pci_device_to_OF_node(dev); | |
216 | ||
217 | DBG("PCI: device %s OF node: %s\n", pci_name(dev), | |
218 | sd->of_node ? sd->of_node->full_name : "<none>"); | |
219 | ||
220 | sd->dma_ops = pci_dma_ops; | |
221 | #ifdef CONFIG_PPC32 | |
222 | sd->dma_data = (void *)PCI_DRAM_OFFSET; | |
223 | #endif | |
224 | set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); | |
225 | ||
226 | if (ppc_md.pci_dma_dev_setup) | |
227 | ppc_md.pci_dma_dev_setup(dev); | |
228 | } | |
229 | EXPORT_SYMBOL(pcibios_setup_new_device); | |
230 | ||
58083dad KG |
231 | /* |
232 | * Reads the interrupt pin to determine if interrupt is use by card. | |
233 | * If the interrupt is used, then gets the interrupt line from the | |
234 | * openfirmware and sets it in the pci_dev and pci_config line. | |
235 | */ | |
236 | int pci_read_irq_line(struct pci_dev *pci_dev) | |
237 | { | |
238 | struct of_irq oirq; | |
239 | unsigned int virq; | |
240 | ||
50c9bc2f BH |
241 | /* The current device-tree that iSeries generates from the HV |
242 | * PCI informations doesn't contain proper interrupt routing, | |
243 | * and all the fallback would do is print out crap, so we | |
244 | * don't attempt to resolve the interrupts here at all, some | |
245 | * iSeries specific fixup does it. | |
246 | * | |
247 | * In the long run, we will hopefully fix the generated device-tree | |
248 | * instead. | |
249 | */ | |
250 | #ifdef CONFIG_PPC_ISERIES | |
251 | if (firmware_has_feature(FW_FEATURE_ISERIES)) | |
252 | return -1; | |
253 | #endif | |
254 | ||
58083dad KG |
255 | DBG("Try to map irq for %s...\n", pci_name(pci_dev)); |
256 | ||
257 | #ifdef DEBUG | |
258 | memset(&oirq, 0xff, sizeof(oirq)); | |
259 | #endif | |
260 | /* Try to get a mapping from the device-tree */ | |
261 | if (of_irq_map_pci(pci_dev, &oirq)) { | |
262 | u8 line, pin; | |
263 | ||
264 | /* If that fails, lets fallback to what is in the config | |
265 | * space and map that through the default controller. We | |
266 | * also set the type to level low since that's what PCI | |
267 | * interrupts are. If your platform does differently, then | |
268 | * either provide a proper interrupt tree or don't use this | |
269 | * function. | |
270 | */ | |
271 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) | |
272 | return -1; | |
273 | if (pin == 0) | |
274 | return -1; | |
275 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || | |
54a24cbb | 276 | line == 0xff || line == 0) { |
58083dad KG |
277 | return -1; |
278 | } | |
54a24cbb BH |
279 | DBG(" -> no map ! Using line %d (pin %d) from PCI config\n", |
280 | line, pin); | |
58083dad KG |
281 | |
282 | virq = irq_create_mapping(NULL, line); | |
283 | if (virq != NO_IRQ) | |
284 | set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); | |
285 | } else { | |
286 | DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n", | |
287 | oirq.size, oirq.specifier[0], oirq.specifier[1], | |
288 | oirq.controller->full_name); | |
289 | ||
290 | virq = irq_create_of_mapping(oirq.controller, oirq.specifier, | |
291 | oirq.size); | |
292 | } | |
293 | if(virq == NO_IRQ) { | |
294 | DBG(" -> failed to map !\n"); | |
295 | return -1; | |
296 | } | |
297 | ||
298 | DBG(" -> mapped to linux irq %d\n", virq); | |
299 | ||
300 | pci_dev->irq = virq; | |
301 | ||
302 | return 0; | |
303 | } | |
304 | EXPORT_SYMBOL(pci_read_irq_line); | |
305 | ||
306 | /* | |
307 | * Platform support for /proc/bus/pci/X/Y mmap()s, | |
308 | * modelled on the sparc64 implementation by Dave Miller. | |
309 | * -- paulus. | |
310 | */ | |
311 | ||
312 | /* | |
313 | * Adjust vm_pgoff of VMA such that it is the physical page offset | |
314 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. | |
315 | * | |
316 | * Basically, the user finds the base address for his device which he wishes | |
317 | * to mmap. They read the 32-bit value from the config space base register, | |
318 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
319 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
320 | * | |
321 | * Returns negative error code on failure, zero on success. | |
322 | */ | |
323 | static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, | |
324 | resource_size_t *offset, | |
325 | enum pci_mmap_state mmap_state) | |
326 | { | |
327 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
328 | unsigned long io_offset = 0; | |
329 | int i, res_bit; | |
330 | ||
331 | if (hose == 0) | |
332 | return NULL; /* should never happen */ | |
333 | ||
334 | /* If memory, add on the PCI bridge address offset */ | |
335 | if (mmap_state == pci_mmap_mem) { | |
336 | #if 0 /* See comment in pci_resource_to_user() for why this is disabled */ | |
337 | *offset += hose->pci_mem_offset; | |
338 | #endif | |
339 | res_bit = IORESOURCE_MEM; | |
340 | } else { | |
341 | io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
342 | *offset += io_offset; | |
343 | res_bit = IORESOURCE_IO; | |
344 | } | |
345 | ||
346 | /* | |
347 | * Check that the offset requested corresponds to one of the | |
348 | * resources of the device. | |
349 | */ | |
350 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
351 | struct resource *rp = &dev->resource[i]; | |
352 | int flags = rp->flags; | |
353 | ||
354 | /* treat ROM as memory (should be already) */ | |
355 | if (i == PCI_ROM_RESOURCE) | |
356 | flags |= IORESOURCE_MEM; | |
357 | ||
358 | /* Active and same type? */ | |
359 | if ((flags & res_bit) == 0) | |
360 | continue; | |
361 | ||
362 | /* In the range of this resource? */ | |
363 | if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) | |
364 | continue; | |
365 | ||
366 | /* found it! construct the final physical address */ | |
367 | if (mmap_state == pci_mmap_io) | |
368 | *offset += hose->io_base_phys - io_offset; | |
369 | return rp; | |
370 | } | |
371 | ||
372 | return NULL; | |
373 | } | |
374 | ||
375 | /* | |
376 | * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
377 | * device mapping. | |
378 | */ | |
379 | static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, | |
380 | pgprot_t protection, | |
381 | enum pci_mmap_state mmap_state, | |
382 | int write_combine) | |
383 | { | |
384 | unsigned long prot = pgprot_val(protection); | |
385 | ||
386 | /* Write combine is always 0 on non-memory space mappings. On | |
387 | * memory space, if the user didn't pass 1, we check for a | |
388 | * "prefetchable" resource. This is a bit hackish, but we use | |
389 | * this to workaround the inability of /sysfs to provide a write | |
390 | * combine bit | |
391 | */ | |
392 | if (mmap_state != pci_mmap_mem) | |
393 | write_combine = 0; | |
394 | else if (write_combine == 0) { | |
395 | if (rp->flags & IORESOURCE_PREFETCH) | |
396 | write_combine = 1; | |
397 | } | |
398 | ||
399 | /* XXX would be nice to have a way to ask for write-through */ | |
400 | prot |= _PAGE_NO_CACHE; | |
401 | if (write_combine) | |
402 | prot &= ~_PAGE_GUARDED; | |
403 | else | |
404 | prot |= _PAGE_GUARDED; | |
405 | ||
406 | return __pgprot(prot); | |
407 | } | |
408 | ||
409 | /* | |
410 | * This one is used by /dev/mem and fbdev who have no clue about the | |
411 | * PCI device, it tries to find the PCI device first and calls the | |
412 | * above routine | |
413 | */ | |
414 | pgprot_t pci_phys_mem_access_prot(struct file *file, | |
415 | unsigned long pfn, | |
416 | unsigned long size, | |
417 | pgprot_t protection) | |
418 | { | |
419 | struct pci_dev *pdev = NULL; | |
420 | struct resource *found = NULL; | |
421 | unsigned long prot = pgprot_val(protection); | |
7c12d906 | 422 | resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; |
58083dad KG |
423 | int i; |
424 | ||
425 | if (page_is_ram(pfn)) | |
426 | return __pgprot(prot); | |
427 | ||
428 | prot |= _PAGE_NO_CACHE | _PAGE_GUARDED; | |
429 | ||
430 | for_each_pci_dev(pdev) { | |
431 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
432 | struct resource *rp = &pdev->resource[i]; | |
433 | int flags = rp->flags; | |
434 | ||
435 | /* Active and same type? */ | |
436 | if ((flags & IORESOURCE_MEM) == 0) | |
437 | continue; | |
438 | /* In the range of this resource? */ | |
439 | if (offset < (rp->start & PAGE_MASK) || | |
440 | offset > rp->end) | |
441 | continue; | |
442 | found = rp; | |
443 | break; | |
444 | } | |
445 | if (found) | |
446 | break; | |
447 | } | |
448 | if (found) { | |
449 | if (found->flags & IORESOURCE_PREFETCH) | |
450 | prot &= ~_PAGE_GUARDED; | |
451 | pci_dev_put(pdev); | |
452 | } | |
453 | ||
e9f82cb7 BH |
454 | DBG("non-PCI map for %llx, prot: %lx\n", |
455 | (unsigned long long)offset, prot); | |
58083dad KG |
456 | |
457 | return __pgprot(prot); | |
458 | } | |
459 | ||
460 | ||
461 | /* | |
462 | * Perform the actual remap of the pages for a PCI device mapping, as | |
463 | * appropriate for this architecture. The region in the process to map | |
464 | * is described by vm_start and vm_end members of VMA, the base physical | |
465 | * address is found in vm_pgoff. | |
466 | * The pci device structure is provided so that architectures may make mapping | |
467 | * decisions on a per-device or per-bus basis. | |
468 | * | |
469 | * Returns a negative error code on failure, zero on success. | |
470 | */ | |
471 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
472 | enum pci_mmap_state mmap_state, int write_combine) | |
473 | { | |
7c12d906 BH |
474 | resource_size_t offset = |
475 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
58083dad KG |
476 | struct resource *rp; |
477 | int ret; | |
478 | ||
479 | rp = __pci_mmap_make_offset(dev, &offset, mmap_state); | |
480 | if (rp == NULL) | |
481 | return -EINVAL; | |
482 | ||
483 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
484 | vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, | |
485 | vma->vm_page_prot, | |
486 | mmap_state, write_combine); | |
487 | ||
488 | ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, | |
489 | vma->vm_end - vma->vm_start, vma->vm_page_prot); | |
490 | ||
491 | return ret; | |
492 | } | |
493 | ||
e9f82cb7 BH |
494 | /* This provides legacy IO read access on a bus */ |
495 | int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) | |
496 | { | |
497 | unsigned long offset; | |
498 | struct pci_controller *hose = pci_bus_to_host(bus); | |
499 | struct resource *rp = &hose->io_resource; | |
500 | void __iomem *addr; | |
501 | ||
502 | /* Check if port can be supported by that bus. We only check | |
503 | * the ranges of the PHB though, not the bus itself as the rules | |
504 | * for forwarding legacy cycles down bridges are not our problem | |
505 | * here. So if the host bridge supports it, we do it. | |
506 | */ | |
507 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
508 | offset += port; | |
509 | ||
510 | if (!(rp->flags & IORESOURCE_IO)) | |
511 | return -ENXIO; | |
512 | if (offset < rp->start || (offset + size) > rp->end) | |
513 | return -ENXIO; | |
514 | addr = hose->io_base_virt + port; | |
515 | ||
516 | switch(size) { | |
517 | case 1: | |
518 | *((u8 *)val) = in_8(addr); | |
519 | return 1; | |
520 | case 2: | |
521 | if (port & 1) | |
522 | return -EINVAL; | |
523 | *((u16 *)val) = in_le16(addr); | |
524 | return 2; | |
525 | case 4: | |
526 | if (port & 3) | |
527 | return -EINVAL; | |
528 | *((u32 *)val) = in_le32(addr); | |
529 | return 4; | |
530 | } | |
531 | return -EINVAL; | |
532 | } | |
533 | ||
534 | /* This provides legacy IO write access on a bus */ | |
535 | int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) | |
536 | { | |
537 | unsigned long offset; | |
538 | struct pci_controller *hose = pci_bus_to_host(bus); | |
539 | struct resource *rp = &hose->io_resource; | |
540 | void __iomem *addr; | |
541 | ||
542 | /* Check if port can be supported by that bus. We only check | |
543 | * the ranges of the PHB though, not the bus itself as the rules | |
544 | * for forwarding legacy cycles down bridges are not our problem | |
545 | * here. So if the host bridge supports it, we do it. | |
546 | */ | |
547 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
548 | offset += port; | |
549 | ||
550 | if (!(rp->flags & IORESOURCE_IO)) | |
551 | return -ENXIO; | |
552 | if (offset < rp->start || (offset + size) > rp->end) | |
553 | return -ENXIO; | |
554 | addr = hose->io_base_virt + port; | |
555 | ||
556 | /* WARNING: The generic code is idiotic. It gets passed a pointer | |
557 | * to what can be a 1, 2 or 4 byte quantity and always reads that | |
558 | * as a u32, which means that we have to correct the location of | |
559 | * the data read within those 32 bits for size 1 and 2 | |
560 | */ | |
561 | switch(size) { | |
562 | case 1: | |
563 | out_8(addr, val >> 24); | |
564 | return 1; | |
565 | case 2: | |
566 | if (port & 1) | |
567 | return -EINVAL; | |
568 | out_le16(addr, val >> 16); | |
569 | return 2; | |
570 | case 4: | |
571 | if (port & 3) | |
572 | return -EINVAL; | |
573 | out_le32(addr, val); | |
574 | return 4; | |
575 | } | |
576 | return -EINVAL; | |
577 | } | |
578 | ||
579 | /* This provides legacy IO or memory mmap access on a bus */ | |
580 | int pci_mmap_legacy_page_range(struct pci_bus *bus, | |
581 | struct vm_area_struct *vma, | |
582 | enum pci_mmap_state mmap_state) | |
583 | { | |
584 | struct pci_controller *hose = pci_bus_to_host(bus); | |
585 | resource_size_t offset = | |
586 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
587 | resource_size_t size = vma->vm_end - vma->vm_start; | |
588 | struct resource *rp; | |
589 | ||
590 | pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", | |
591 | pci_domain_nr(bus), bus->number, | |
592 | mmap_state == pci_mmap_mem ? "MEM" : "IO", | |
593 | (unsigned long long)offset, | |
594 | (unsigned long long)(offset + size - 1)); | |
595 | ||
596 | if (mmap_state == pci_mmap_mem) { | |
597 | if ((offset + size) > hose->isa_mem_size) | |
598 | return -ENXIO; | |
599 | offset += hose->isa_mem_phys; | |
600 | } else { | |
601 | unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
602 | unsigned long roffset = offset + io_offset; | |
603 | rp = &hose->io_resource; | |
604 | if (!(rp->flags & IORESOURCE_IO)) | |
605 | return -ENXIO; | |
606 | if (roffset < rp->start || (roffset + size) > rp->end) | |
607 | return -ENXIO; | |
608 | offset += hose->io_base_phys; | |
609 | } | |
610 | pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); | |
611 | ||
612 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
201bdc86 DG |
613 | vma->vm_page_prot = __pgprot(pgprot_val(vma->vm_page_prot) |
614 | | _PAGE_NO_CACHE | _PAGE_GUARDED); | |
e9f82cb7 BH |
615 | return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, |
616 | vma->vm_end - vma->vm_start, | |
617 | vma->vm_page_prot); | |
618 | } | |
619 | ||
58083dad KG |
620 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
621 | const struct resource *rsrc, | |
622 | resource_size_t *start, resource_size_t *end) | |
623 | { | |
624 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
625 | resource_size_t offset = 0; | |
626 | ||
627 | if (hose == NULL) | |
628 | return; | |
629 | ||
630 | if (rsrc->flags & IORESOURCE_IO) | |
631 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
632 | ||
633 | /* We pass a fully fixed up address to userland for MMIO instead of | |
634 | * a BAR value because X is lame and expects to be able to use that | |
635 | * to pass to /dev/mem ! | |
636 | * | |
637 | * That means that we'll have potentially 64 bits values where some | |
638 | * userland apps only expect 32 (like X itself since it thinks only | |
639 | * Sparc has 64 bits MMIO) but if we don't do that, we break it on | |
640 | * 32 bits CHRPs :-( | |
641 | * | |
642 | * Hopefully, the sysfs insterface is immune to that gunk. Once X | |
643 | * has been fixed (and the fix spread enough), we can re-enable the | |
644 | * 2 lines below and pass down a BAR value to userland. In that case | |
645 | * we'll also have to re-enable the matching code in | |
646 | * __pci_mmap_make_offset(). | |
647 | * | |
648 | * BenH. | |
649 | */ | |
650 | #if 0 | |
651 | else if (rsrc->flags & IORESOURCE_MEM) | |
652 | offset = hose->pci_mem_offset; | |
653 | #endif | |
654 | ||
655 | *start = rsrc->start - offset; | |
656 | *end = rsrc->end - offset; | |
657 | } | |
13dccb9e BH |
658 | |
659 | /** | |
660 | * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree | |
661 | * @hose: newly allocated pci_controller to be setup | |
662 | * @dev: device node of the host bridge | |
663 | * @primary: set if primary bus (32 bits only, soon to be deprecated) | |
664 | * | |
665 | * This function will parse the "ranges" property of a PCI host bridge device | |
666 | * node and setup the resource mapping of a pci controller based on its | |
667 | * content. | |
668 | * | |
669 | * Life would be boring if it wasn't for a few issues that we have to deal | |
670 | * with here: | |
671 | * | |
672 | * - We can only cope with one IO space range and up to 3 Memory space | |
673 | * ranges. However, some machines (thanks Apple !) tend to split their | |
674 | * space into lots of small contiguous ranges. So we have to coalesce. | |
675 | * | |
676 | * - We can only cope with all memory ranges having the same offset | |
677 | * between CPU addresses and PCI addresses. Unfortunately, some bridges | |
678 | * are setup for a large 1:1 mapping along with a small "window" which | |
679 | * maps PCI address 0 to some arbitrary high address of the CPU space in | |
680 | * order to give access to the ISA memory hole. | |
681 | * The way out of here that I've chosen for now is to always set the | |
682 | * offset based on the first resource found, then override it if we | |
683 | * have a different offset and the previous was set by an ISA hole. | |
684 | * | |
685 | * - Some busses have IO space not starting at 0, which causes trouble with | |
686 | * the way we do our IO resource renumbering. The code somewhat deals with | |
687 | * it for 64 bits but I would expect problems on 32 bits. | |
688 | * | |
689 | * - Some 32 bits platforms such as 4xx can have physical space larger than | |
690 | * 32 bits so we need to use 64 bits values for the parsing | |
691 | */ | |
692 | void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose, | |
693 | struct device_node *dev, | |
694 | int primary) | |
695 | { | |
696 | const u32 *ranges; | |
697 | int rlen; | |
698 | int pna = of_n_addr_cells(dev); | |
699 | int np = pna + 5; | |
700 | int memno = 0, isa_hole = -1; | |
701 | u32 pci_space; | |
702 | unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size; | |
703 | unsigned long long isa_mb = 0; | |
704 | struct resource *res; | |
705 | ||
706 | printk(KERN_INFO "PCI host bridge %s %s ranges:\n", | |
707 | dev->full_name, primary ? "(primary)" : ""); | |
708 | ||
709 | /* Get ranges property */ | |
710 | ranges = of_get_property(dev, "ranges", &rlen); | |
711 | if (ranges == NULL) | |
712 | return; | |
713 | ||
714 | /* Parse it */ | |
715 | while ((rlen -= np * 4) >= 0) { | |
716 | /* Read next ranges element */ | |
717 | pci_space = ranges[0]; | |
718 | pci_addr = of_read_number(ranges + 1, 2); | |
719 | cpu_addr = of_translate_address(dev, ranges + 3); | |
720 | size = of_read_number(ranges + pna + 3, 2); | |
721 | ranges += np; | |
e9f82cb7 BH |
722 | |
723 | /* If we failed translation or got a zero-sized region | |
724 | * (some FW try to feed us with non sensical zero sized regions | |
725 | * such as power3 which look like some kind of attempt at exposing | |
726 | * the VGA memory hole) | |
727 | */ | |
13dccb9e BH |
728 | if (cpu_addr == OF_BAD_ADDR || size == 0) |
729 | continue; | |
730 | ||
731 | /* Now consume following elements while they are contiguous */ | |
732 | for (; rlen >= np * sizeof(u32); | |
733 | ranges += np, rlen -= np * 4) { | |
734 | if (ranges[0] != pci_space) | |
735 | break; | |
736 | pci_next = of_read_number(ranges + 1, 2); | |
737 | cpu_next = of_translate_address(dev, ranges + 3); | |
738 | if (pci_next != pci_addr + size || | |
739 | cpu_next != cpu_addr + size) | |
740 | break; | |
741 | size += of_read_number(ranges + pna + 3, 2); | |
742 | } | |
743 | ||
744 | /* Act based on address space type */ | |
745 | res = NULL; | |
746 | switch ((pci_space >> 24) & 0x3) { | |
747 | case 1: /* PCI IO space */ | |
748 | printk(KERN_INFO | |
749 | " IO 0x%016llx..0x%016llx -> 0x%016llx\n", | |
750 | cpu_addr, cpu_addr + size - 1, pci_addr); | |
751 | ||
752 | /* We support only one IO range */ | |
753 | if (hose->pci_io_size) { | |
754 | printk(KERN_INFO | |
755 | " \\--> Skipped (too many) !\n"); | |
756 | continue; | |
757 | } | |
758 | #ifdef CONFIG_PPC32 | |
759 | /* On 32 bits, limit I/O space to 16MB */ | |
760 | if (size > 0x01000000) | |
761 | size = 0x01000000; | |
762 | ||
763 | /* 32 bits needs to map IOs here */ | |
764 | hose->io_base_virt = ioremap(cpu_addr, size); | |
765 | ||
766 | /* Expect trouble if pci_addr is not 0 */ | |
767 | if (primary) | |
768 | isa_io_base = | |
769 | (unsigned long)hose->io_base_virt; | |
770 | #endif /* CONFIG_PPC32 */ | |
771 | /* pci_io_size and io_base_phys always represent IO | |
772 | * space starting at 0 so we factor in pci_addr | |
773 | */ | |
774 | hose->pci_io_size = pci_addr + size; | |
775 | hose->io_base_phys = cpu_addr - pci_addr; | |
776 | ||
777 | /* Build resource */ | |
778 | res = &hose->io_resource; | |
779 | res->flags = IORESOURCE_IO; | |
780 | res->start = pci_addr; | |
781 | break; | |
782 | case 2: /* PCI Memory space */ | |
67260ac9 | 783 | case 3: /* PCI 64 bits Memory space */ |
13dccb9e BH |
784 | printk(KERN_INFO |
785 | " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", | |
786 | cpu_addr, cpu_addr + size - 1, pci_addr, | |
787 | (pci_space & 0x40000000) ? "Prefetch" : ""); | |
788 | ||
789 | /* We support only 3 memory ranges */ | |
790 | if (memno >= 3) { | |
791 | printk(KERN_INFO | |
792 | " \\--> Skipped (too many) !\n"); | |
793 | continue; | |
794 | } | |
795 | /* Handles ISA memory hole space here */ | |
796 | if (pci_addr == 0) { | |
797 | isa_mb = cpu_addr; | |
798 | isa_hole = memno; | |
799 | if (primary || isa_mem_base == 0) | |
800 | isa_mem_base = cpu_addr; | |
e9f82cb7 BH |
801 | hose->isa_mem_phys = cpu_addr; |
802 | hose->isa_mem_size = size; | |
13dccb9e BH |
803 | } |
804 | ||
805 | /* We get the PCI/Mem offset from the first range or | |
806 | * the, current one if the offset came from an ISA | |
807 | * hole. If they don't match, bugger. | |
808 | */ | |
809 | if (memno == 0 || | |
810 | (isa_hole >= 0 && pci_addr != 0 && | |
811 | hose->pci_mem_offset == isa_mb)) | |
812 | hose->pci_mem_offset = cpu_addr - pci_addr; | |
813 | else if (pci_addr != 0 && | |
814 | hose->pci_mem_offset != cpu_addr - pci_addr) { | |
815 | printk(KERN_INFO | |
816 | " \\--> Skipped (offset mismatch) !\n"); | |
817 | continue; | |
818 | } | |
819 | ||
820 | /* Build resource */ | |
821 | res = &hose->mem_resources[memno++]; | |
822 | res->flags = IORESOURCE_MEM; | |
823 | if (pci_space & 0x40000000) | |
824 | res->flags |= IORESOURCE_PREFETCH; | |
825 | res->start = cpu_addr; | |
826 | break; | |
827 | } | |
828 | if (res != NULL) { | |
829 | res->name = dev->full_name; | |
830 | res->end = res->start + size - 1; | |
831 | res->parent = NULL; | |
832 | res->sibling = NULL; | |
833 | res->child = NULL; | |
834 | } | |
835 | } | |
836 | ||
8db13a0e BH |
837 | /* If there's an ISA hole and the pci_mem_offset is -not- matching |
838 | * the ISA hole offset, then we need to remove the ISA hole from | |
839 | * the resource list for that brige | |
840 | */ | |
841 | if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { | |
842 | unsigned int next = isa_hole + 1; | |
843 | printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb); | |
844 | if (next < memno) | |
845 | memmove(&hose->mem_resources[isa_hole], | |
846 | &hose->mem_resources[next], | |
847 | sizeof(struct resource) * (memno - next)); | |
848 | hose->mem_resources[--memno].flags = 0; | |
13dccb9e BH |
849 | } |
850 | } | |
fa462f2d BH |
851 | |
852 | /* Decide whether to display the domain number in /proc */ | |
853 | int pci_proc_domain(struct pci_bus *bus) | |
854 | { | |
855 | struct pci_controller *hose = pci_bus_to_host(bus); | |
856 | #ifdef CONFIG_PPC64 | |
857 | return hose->buid != 0; | |
858 | #else | |
859 | if (!(ppc_pci_flags & PPC_PCI_ENABLE_PROC_DOMAINS)) | |
860 | return 0; | |
861 | if (ppc_pci_flags & PPC_PCI_COMPAT_DOMAIN_0) | |
862 | return hose->global_number != 0; | |
863 | return 1; | |
864 | #endif | |
865 | } | |
866 | ||
fe2d338c BH |
867 | void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, |
868 | struct resource *res) | |
869 | { | |
870 | resource_size_t offset = 0, mask = (resource_size_t)-1; | |
871 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
872 | ||
873 | if (!hose) | |
874 | return; | |
875 | if (res->flags & IORESOURCE_IO) { | |
876 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
877 | mask = 0xffffffffu; | |
878 | } else if (res->flags & IORESOURCE_MEM) | |
879 | offset = hose->pci_mem_offset; | |
880 | ||
881 | region->start = (res->start - offset) & mask; | |
882 | region->end = (res->end - offset) & mask; | |
883 | } | |
884 | EXPORT_SYMBOL(pcibios_resource_to_bus); | |
885 | ||
886 | void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | |
887 | struct pci_bus_region *region) | |
888 | { | |
889 | resource_size_t offset = 0, mask = (resource_size_t)-1; | |
890 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
891 | ||
892 | if (!hose) | |
893 | return; | |
894 | if (res->flags & IORESOURCE_IO) { | |
895 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
896 | mask = 0xffffffffu; | |
897 | } else if (res->flags & IORESOURCE_MEM) | |
898 | offset = hose->pci_mem_offset; | |
899 | res->start = (region->start + offset) & mask; | |
900 | res->end = (region->end + offset) & mask; | |
901 | } | |
902 | EXPORT_SYMBOL(pcibios_bus_to_resource); | |
bf5e2ba2 BH |
903 | |
904 | /* Fixup a bus resource into a linux resource */ | |
905 | static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev) | |
906 | { | |
907 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
908 | resource_size_t offset = 0, mask = (resource_size_t)-1; | |
909 | ||
910 | if (res->flags & IORESOURCE_IO) { | |
911 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
912 | mask = 0xffffffffu; | |
913 | } else if (res->flags & IORESOURCE_MEM) | |
914 | offset = hose->pci_mem_offset; | |
915 | ||
916 | res->start = (res->start + offset) & mask; | |
917 | res->end = (res->end + offset) & mask; | |
bf5e2ba2 BH |
918 | } |
919 | ||
920 | ||
921 | /* This header fixup will do the resource fixup for all devices as they are | |
922 | * probed, but not for bridge ranges | |
923 | */ | |
924 | static void __devinit pcibios_fixup_resources(struct pci_dev *dev) | |
925 | { | |
926 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
927 | int i; | |
928 | ||
929 | if (!hose) { | |
930 | printk(KERN_ERR "No host bridge for PCI dev %s !\n", | |
931 | pci_name(dev)); | |
932 | return; | |
933 | } | |
934 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
935 | struct resource *res = dev->resource + i; | |
936 | if (!res->flags) | |
937 | continue; | |
7f172890 BH |
938 | /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't |
939 | * consider 0 as an unassigned BAR value. It's technically | |
940 | * a valid value, but linux doesn't like it... so when we can | |
941 | * re-assign things, we do so, but if we can't, we keep it | |
942 | * around and hope for the best... | |
943 | */ | |
944 | if (res->start == 0 && !(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { | |
bf5e2ba2 BH |
945 | pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n", |
946 | pci_name(dev), i, | |
947 | (unsigned long long)res->start, | |
948 | (unsigned long long)res->end, | |
949 | (unsigned int)res->flags); | |
950 | res->end -= res->start; | |
951 | res->start = 0; | |
952 | res->flags |= IORESOURCE_UNSET; | |
953 | continue; | |
954 | } | |
955 | ||
956 | pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n", | |
957 | pci_name(dev), i, | |
958 | (unsigned long long)res->start,\ | |
959 | (unsigned long long)res->end, | |
960 | (unsigned int)res->flags); | |
961 | ||
962 | fixup_resource(res, dev); | |
b5561511 BH |
963 | |
964 | pr_debug("PCI:%s %016llx-%016llx\n", | |
965 | pci_name(dev), | |
966 | (unsigned long long)res->start, | |
967 | (unsigned long long)res->end); | |
bf5e2ba2 BH |
968 | } |
969 | ||
970 | /* Call machine specific resource fixup */ | |
971 | if (ppc_md.pcibios_fixup_resources) | |
972 | ppc_md.pcibios_fixup_resources(dev); | |
973 | } | |
974 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); | |
975 | ||
b5561511 BH |
976 | /* This function tries to figure out if a bridge resource has been initialized |
977 | * by the firmware or not. It doesn't have to be absolutely bullet proof, but | |
978 | * things go more smoothly when it gets it right. It should covers cases such | |
979 | * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges | |
980 | */ | |
981 | static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus, | |
982 | struct resource *res) | |
bf5e2ba2 | 983 | { |
be8cbcd8 | 984 | struct pci_controller *hose = pci_bus_to_host(bus); |
bf5e2ba2 | 985 | struct pci_dev *dev = bus->self; |
b5561511 BH |
986 | resource_size_t offset; |
987 | u16 command; | |
988 | int i; | |
bf5e2ba2 | 989 | |
b5561511 BH |
990 | /* We don't do anything if PCI_PROBE_ONLY is set */ |
991 | if (ppc_pci_flags & PPC_PCI_PROBE_ONLY) | |
992 | return 0; | |
bf5e2ba2 | 993 | |
b5561511 BH |
994 | /* Job is a bit different between memory and IO */ |
995 | if (res->flags & IORESOURCE_MEM) { | |
996 | /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been | |
997 | * initialized by somebody | |
998 | */ | |
999 | if (res->start != hose->pci_mem_offset) | |
1000 | return 0; | |
bf5e2ba2 | 1001 | |
b5561511 BH |
1002 | /* The BAR is 0, let's check if memory decoding is enabled on |
1003 | * the bridge. If not, we consider it unassigned | |
1004 | */ | |
1005 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
1006 | if ((command & PCI_COMMAND_MEMORY) == 0) | |
1007 | return 1; | |
be8cbcd8 | 1008 | |
b5561511 BH |
1009 | /* Memory decoding is enabled and the BAR is 0. If any of the bridge |
1010 | * resources covers that starting address (0 then it's good enough for | |
1011 | * us for memory | |
1012 | */ | |
1013 | for (i = 0; i < 3; i++) { | |
1014 | if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && | |
1015 | hose->mem_resources[i].start == hose->pci_mem_offset) | |
1016 | return 0; | |
1017 | } | |
1018 | ||
1019 | /* Well, it starts at 0 and we know it will collide so we may as | |
1020 | * well consider it as unassigned. That covers the Apple case. | |
1021 | */ | |
1022 | return 1; | |
1023 | } else { | |
1024 | /* If the BAR is non-0, then we consider it assigned */ | |
1025 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
1026 | if (((res->start - offset) & 0xfffffffful) != 0) | |
1027 | return 0; | |
1028 | ||
1029 | /* Here, we are a bit different than memory as typically IO space | |
1030 | * starting at low addresses -is- valid. What we do instead if that | |
1031 | * we consider as unassigned anything that doesn't have IO enabled | |
1032 | * in the PCI command register, and that's it. | |
1033 | */ | |
1034 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
1035 | if (command & PCI_COMMAND_IO) | |
1036 | return 0; | |
1037 | ||
1038 | /* It's starting at 0 and IO is disabled in the bridge, consider | |
1039 | * it unassigned | |
1040 | */ | |
1041 | return 1; | |
1042 | } | |
1043 | } | |
1044 | ||
1045 | /* Fixup resources of a PCI<->PCI bridge */ | |
1046 | static void __devinit pcibios_fixup_bridge(struct pci_bus *bus) | |
1047 | { | |
1048 | struct resource *res; | |
1049 | int i; | |
1050 | ||
1051 | struct pci_dev *dev = bus->self; | |
1052 | ||
1053 | for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) { | |
1054 | if ((res = bus->resource[i]) == NULL) | |
1055 | continue; | |
1056 | if (!res->flags) | |
1057 | continue; | |
1058 | if (i >= 3 && bus->self->transparent) | |
1059 | continue; | |
1060 | ||
1061 | pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n", | |
1062 | pci_name(dev), i, | |
1063 | (unsigned long long)res->start,\ | |
1064 | (unsigned long long)res->end, | |
1065 | (unsigned int)res->flags); | |
bf5e2ba2 | 1066 | |
b5561511 BH |
1067 | /* Perform fixup */ |
1068 | fixup_resource(res, dev); | |
1069 | ||
1070 | /* Try to detect uninitialized P2P bridge resources, | |
1071 | * and clear them out so they get re-assigned later | |
1072 | */ | |
1073 | if (pcibios_uninitialized_bridge_resource(bus, res)) { | |
1074 | res->flags = 0; | |
1075 | pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); | |
1076 | } else { | |
1077 | ||
1078 | pr_debug("PCI:%s %016llx-%016llx\n", | |
1079 | pci_name(dev), | |
1080 | (unsigned long long)res->start, | |
1081 | (unsigned long long)res->end); | |
bf5e2ba2 BH |
1082 | } |
1083 | } | |
b5561511 BH |
1084 | } |
1085 | ||
1086 | static void __devinit __pcibios_fixup_bus(struct pci_bus *bus) | |
1087 | { | |
1088 | struct pci_dev *dev = bus->self; | |
1089 | ||
1090 | pr_debug("PCI: Fixup bus %d (%s)\n", bus->number, dev ? pci_name(dev) : "PHB"); | |
1091 | ||
1092 | /* Fixup PCI<->PCI bridges. Host bridges are handled separately, for | |
1093 | * now differently between 32 and 64 bits. | |
1094 | */ | |
1095 | if (dev != NULL) | |
1096 | pcibios_fixup_bridge(bus); | |
bf5e2ba2 BH |
1097 | |
1098 | /* Additional setup that is different between 32 and 64 bits for now */ | |
1099 | pcibios_do_bus_setup(bus); | |
1100 | ||
1101 | /* Platform specific bus fixups */ | |
1102 | if (ppc_md.pcibios_fixup_bus) | |
1103 | ppc_md.pcibios_fixup_bus(bus); | |
1104 | ||
1105 | /* Read default IRQs and fixup if necessary */ | |
1106 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1107 | pci_read_irq_line(dev); | |
1108 | if (ppc_md.pci_irq_fixup) | |
1109 | ppc_md.pci_irq_fixup(dev); | |
1110 | } | |
1111 | } | |
1112 | ||
1113 | void __devinit pcibios_fixup_bus(struct pci_bus *bus) | |
1114 | { | |
1115 | /* When called from the generic PCI probe, read PCI<->PCI bridge | |
1116 | * bases before proceeding | |
1117 | */ | |
1118 | if (bus->self != NULL) | |
1119 | pci_read_bridge_bases(bus); | |
1120 | __pcibios_fixup_bus(bus); | |
1121 | } | |
1122 | EXPORT_SYMBOL(pcibios_fixup_bus); | |
1123 | ||
1124 | /* When building a bus from the OF tree rather than probing, we need a | |
1125 | * slightly different version of the fixup which doesn't read the | |
1126 | * bridge bases using config space accesses | |
1127 | */ | |
1128 | void __devinit pcibios_fixup_of_probed_bus(struct pci_bus *bus) | |
1129 | { | |
1130 | __pcibios_fixup_bus(bus); | |
1131 | } | |
3fd94c6b BH |
1132 | |
1133 | static int skip_isa_ioresource_align(struct pci_dev *dev) | |
1134 | { | |
1135 | if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) && | |
1136 | !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) | |
1137 | return 1; | |
1138 | return 0; | |
1139 | } | |
1140 | ||
1141 | /* | |
1142 | * We need to avoid collisions with `mirrored' VGA ports | |
1143 | * and other strange ISA hardware, so we always want the | |
1144 | * addresses to be allocated in the 0x000-0x0ff region | |
1145 | * modulo 0x400. | |
1146 | * | |
1147 | * Why? Because some silly external IO cards only decode | |
1148 | * the low 10 bits of the IO address. The 0x00-0xff region | |
1149 | * is reserved for motherboard devices that decode all 16 | |
1150 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
1151 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
1152 | * which might have be mirrored at 0x0100-0x03ff.. | |
1153 | */ | |
1154 | void pcibios_align_resource(void *data, struct resource *res, | |
1155 | resource_size_t size, resource_size_t align) | |
1156 | { | |
1157 | struct pci_dev *dev = data; | |
1158 | ||
1159 | if (res->flags & IORESOURCE_IO) { | |
1160 | resource_size_t start = res->start; | |
1161 | ||
1162 | if (skip_isa_ioresource_align(dev)) | |
1163 | return; | |
1164 | if (start & 0x300) { | |
1165 | start = (start + 0x3ff) & ~0x3ff; | |
1166 | res->start = start; | |
1167 | } | |
1168 | } | |
1169 | } | |
1170 | EXPORT_SYMBOL(pcibios_align_resource); | |
1171 | ||
1172 | /* | |
1173 | * Reparent resource children of pr that conflict with res | |
1174 | * under res, and make res replace those children. | |
1175 | */ | |
1176 | static int __init reparent_resources(struct resource *parent, | |
1177 | struct resource *res) | |
1178 | { | |
1179 | struct resource *p, **pp; | |
1180 | struct resource **firstpp = NULL; | |
1181 | ||
1182 | for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { | |
1183 | if (p->end < res->start) | |
1184 | continue; | |
1185 | if (res->end < p->start) | |
1186 | break; | |
1187 | if (p->start < res->start || p->end > res->end) | |
1188 | return -1; /* not completely contained */ | |
1189 | if (firstpp == NULL) | |
1190 | firstpp = pp; | |
1191 | } | |
1192 | if (firstpp == NULL) | |
1193 | return -1; /* didn't find any conflicting entries? */ | |
1194 | res->parent = parent; | |
1195 | res->child = *firstpp; | |
1196 | res->sibling = *pp; | |
1197 | *firstpp = res; | |
1198 | *pp = NULL; | |
1199 | for (p = res->child; p != NULL; p = p->sibling) { | |
1200 | p->parent = res; | |
1201 | DBG(KERN_INFO "PCI: reparented %s [%llx..%llx] under %s\n", | |
1202 | p->name, | |
1203 | (unsigned long long)p->start, | |
1204 | (unsigned long long)p->end, res->name); | |
1205 | } | |
1206 | return 0; | |
1207 | } | |
1208 | ||
1209 | /* | |
1210 | * Handle resources of PCI devices. If the world were perfect, we could | |
1211 | * just allocate all the resource regions and do nothing more. It isn't. | |
1212 | * On the other hand, we cannot just re-allocate all devices, as it would | |
1213 | * require us to know lots of host bridge internals. So we attempt to | |
1214 | * keep as much of the original configuration as possible, but tweak it | |
1215 | * when it's found to be wrong. | |
1216 | * | |
1217 | * Known BIOS problems we have to work around: | |
1218 | * - I/O or memory regions not configured | |
1219 | * - regions configured, but not enabled in the command register | |
1220 | * - bogus I/O addresses above 64K used | |
1221 | * - expansion ROMs left enabled (this may sound harmless, but given | |
1222 | * the fact the PCI specs explicitly allow address decoders to be | |
1223 | * shared between expansion ROMs and other resource regions, it's | |
1224 | * at least dangerous) | |
1225 | * | |
1226 | * Our solution: | |
1227 | * (1) Allocate resources for all buses behind PCI-to-PCI bridges. | |
1228 | * This gives us fixed barriers on where we can allocate. | |
1229 | * (2) Allocate resources for all enabled devices. If there is | |
1230 | * a collision, just mark the resource as unallocated. Also | |
1231 | * disable expansion ROMs during this step. | |
1232 | * (3) Try to allocate resources for disabled devices. If the | |
1233 | * resources were assigned correctly, everything goes well, | |
1234 | * if they weren't, they won't disturb allocation of other | |
1235 | * resources. | |
1236 | * (4) Assign new addresses to resources which were either | |
1237 | * not configured at all or misconfigured. If explicitly | |
1238 | * requested by the user, configure expansion ROM address | |
1239 | * as well. | |
1240 | */ | |
1241 | ||
1242 | static void __init pcibios_allocate_bus_resources(struct list_head *bus_list) | |
1243 | { | |
1244 | struct pci_bus *bus; | |
1245 | int i; | |
1246 | struct resource *res, *pr; | |
1247 | ||
1248 | /* Depth-First Search on bus tree */ | |
1249 | list_for_each_entry(bus, bus_list, node) { | |
1250 | for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) { | |
1251 | if ((res = bus->resource[i]) == NULL || !res->flags | |
1252 | || res->start > res->end) | |
1253 | continue; | |
1254 | if (bus->parent == NULL) | |
50c9bc2f | 1255 | pr = (res->flags & IORESOURCE_IO) ? |
3fd94c6b BH |
1256 | &ioport_resource : &iomem_resource; |
1257 | else { | |
1258 | /* Don't bother with non-root busses when | |
1259 | * re-assigning all resources. We clear the | |
1260 | * resource flags as if they were colliding | |
1261 | * and as such ensure proper re-allocation | |
1262 | * later. | |
1263 | */ | |
1264 | if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC) | |
1265 | goto clear_resource; | |
1266 | pr = pci_find_parent_resource(bus->self, res); | |
1267 | if (pr == res) { | |
1268 | /* this happens when the generic PCI | |
1269 | * code (wrongly) decides that this | |
1270 | * bridge is transparent -- paulus | |
1271 | */ | |
1272 | continue; | |
1273 | } | |
1274 | } | |
1275 | ||
1276 | DBG("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " | |
1277 | "[0x%x], parent %p (%s)\n", | |
1278 | bus->self ? pci_name(bus->self) : "PHB", | |
1279 | bus->number, i, | |
1280 | (unsigned long long)res->start, | |
1281 | (unsigned long long)res->end, | |
1282 | (unsigned int)res->flags, | |
1283 | pr, (pr && pr->name) ? pr->name : "nil"); | |
1284 | ||
1285 | if (pr && !(pr->flags & IORESOURCE_UNSET)) { | |
1286 | if (request_resource(pr, res) == 0) | |
1287 | continue; | |
1288 | /* | |
1289 | * Must be a conflict with an existing entry. | |
1290 | * Move that entry (or entries) under the | |
1291 | * bridge resource and try again. | |
1292 | */ | |
1293 | if (reparent_resources(pr, res) == 0) | |
1294 | continue; | |
1295 | } | |
1296 | printk(KERN_WARNING | |
1297 | "PCI: Cannot allocate resource region " | |
1298 | "%d of PCI bridge %d, will remap\n", | |
1299 | i, bus->number); | |
1300 | clear_resource: | |
1301 | res->flags = 0; | |
1302 | } | |
1303 | pcibios_allocate_bus_resources(&bus->children); | |
1304 | } | |
1305 | } | |
1306 | ||
533b1928 | 1307 | static inline void __devinit alloc_resource(struct pci_dev *dev, int idx) |
3fd94c6b BH |
1308 | { |
1309 | struct resource *pr, *r = &dev->resource[idx]; | |
1310 | ||
1311 | DBG("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", | |
1312 | pci_name(dev), idx, | |
1313 | (unsigned long long)r->start, | |
1314 | (unsigned long long)r->end, | |
1315 | (unsigned int)r->flags); | |
1316 | ||
1317 | pr = pci_find_parent_resource(dev, r); | |
1318 | if (!pr || (pr->flags & IORESOURCE_UNSET) || | |
1319 | request_resource(pr, r) < 0) { | |
1320 | printk(KERN_WARNING "PCI: Cannot allocate resource region %d" | |
1321 | " of device %s, will remap\n", idx, pci_name(dev)); | |
1322 | if (pr) | |
1323 | DBG("PCI: parent is %p: %016llx-%016llx [%x]\n", pr, | |
1324 | (unsigned long long)pr->start, | |
1325 | (unsigned long long)pr->end, | |
1326 | (unsigned int)pr->flags); | |
1327 | /* We'll assign a new address later */ | |
1328 | r->flags |= IORESOURCE_UNSET; | |
1329 | r->end -= r->start; | |
1330 | r->start = 0; | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | static void __init pcibios_allocate_resources(int pass) | |
1335 | { | |
1336 | struct pci_dev *dev = NULL; | |
1337 | int idx, disabled; | |
1338 | u16 command; | |
1339 | struct resource *r; | |
1340 | ||
1341 | for_each_pci_dev(dev) { | |
1342 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
1343 | for (idx = 0; idx < 6; idx++) { | |
1344 | r = &dev->resource[idx]; | |
1345 | if (r->parent) /* Already allocated */ | |
1346 | continue; | |
1347 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) | |
1348 | continue; /* Not assigned at all */ | |
1349 | if (r->flags & IORESOURCE_IO) | |
1350 | disabled = !(command & PCI_COMMAND_IO); | |
1351 | else | |
1352 | disabled = !(command & PCI_COMMAND_MEMORY); | |
533b1928 PM |
1353 | if (pass == disabled) |
1354 | alloc_resource(dev, idx); | |
3fd94c6b BH |
1355 | } |
1356 | if (pass) | |
1357 | continue; | |
1358 | r = &dev->resource[PCI_ROM_RESOURCE]; | |
1359 | if (r->flags & IORESOURCE_ROM_ENABLE) { | |
1360 | /* Turn the ROM off, leave the resource region, | |
1361 | * but keep it unregistered. | |
1362 | */ | |
1363 | u32 reg; | |
1364 | DBG("PCI: Switching off ROM of %s\n", pci_name(dev)); | |
1365 | r->flags &= ~IORESOURCE_ROM_ENABLE; | |
1366 | pci_read_config_dword(dev, dev->rom_base_reg, ®); | |
1367 | pci_write_config_dword(dev, dev->rom_base_reg, | |
1368 | reg & ~PCI_ROM_ADDRESS_ENABLE); | |
1369 | } | |
1370 | } | |
1371 | } | |
1372 | ||
1373 | void __init pcibios_resource_survey(void) | |
1374 | { | |
1375 | /* Allocate and assign resources. If we re-assign everything, then | |
1376 | * we skip the allocate phase | |
1377 | */ | |
1378 | pcibios_allocate_bus_resources(&pci_root_buses); | |
1379 | ||
1380 | if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) { | |
1381 | pcibios_allocate_resources(0); | |
1382 | pcibios_allocate_resources(1); | |
1383 | } | |
1384 | ||
1385 | if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) { | |
1386 | DBG("PCI: Assigning unassigned resouces...\n"); | |
1387 | pci_assign_unassigned_resources(); | |
1388 | } | |
1389 | ||
1390 | /* Call machine dependent fixup */ | |
1391 | if (ppc_md.pcibios_fixup) | |
1392 | ppc_md.pcibios_fixup(); | |
1393 | } | |
1394 | ||
1395 | #ifdef CONFIG_HOTPLUG | |
1396 | /* This is used by the pSeries hotplug driver to allocate resource | |
1397 | * of newly plugged busses. We can try to consolidate with the | |
1398 | * rest of the code later, for now, keep it as-is | |
1399 | */ | |
1400 | void __devinit pcibios_claim_one_bus(struct pci_bus *bus) | |
1401 | { | |
1402 | struct pci_dev *dev; | |
1403 | struct pci_bus *child_bus; | |
1404 | ||
1405 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1406 | int i; | |
1407 | ||
1408 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1409 | struct resource *r = &dev->resource[i]; | |
1410 | ||
1411 | if (r->parent || !r->start || !r->flags) | |
1412 | continue; | |
1413 | pci_claim_resource(dev, i); | |
1414 | } | |
1415 | } | |
1416 | ||
1417 | list_for_each_entry(child_bus, &bus->children, node) | |
1418 | pcibios_claim_one_bus(child_bus); | |
1419 | } | |
1420 | EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); | |
1421 | #endif /* CONFIG_HOTPLUG */ | |
549beb9b BH |
1422 | |
1423 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
1424 | { | |
549beb9b BH |
1425 | if (ppc_md.pcibios_enable_device_hook) |
1426 | if (ppc_md.pcibios_enable_device_hook(dev)) | |
1427 | return -EINVAL; | |
1428 | ||
7cfb5f9a | 1429 | return pci_enable_resources(dev, mask); |
549beb9b | 1430 | } |