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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 156
[linux-block.git] / arch / powerpc / kernel / mce_power.c
CommitLineData
1a59d1b8 1// SPDX-License-Identifier: GPL-2.0-or-later
e22a2274
MS		 2/*
3 * Machine check exception handling CPU-side for power7 and power8
4 *
e22a2274
MS		 5 * Copyright 2013 IBM Corporation
6 * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
7 */
8
9#undef DEBUG
10#define pr_fmt(fmt) "mce_power: " fmt
11
12#include <linux/types.h>
13#include <linux/ptrace.h>
14#include <asm/mmu.h>
15#include <asm/mce.h>
55672ecf 16#include <asm/machdep.h>
ba41e1e1
BS		 17#include <asm/pgtable.h>
18#include <asm/pte-walk.h>
19#include <asm/sstep.h>
20#include <asm/exception-64s.h>
21
22/*
23 * Convert an address related to an mm to a PFN. NOTE: we are in real
24 * mode, we could potentially race with page table updates.
25 */
7f177f98 26unsigned long addr_to_pfn(struct pt_regs *regs, unsigned long addr)
ba41e1e1
BS		 27{
28 pte_t *ptep;
29 unsigned long flags;
30 struct mm_struct *mm;
31
32 if (user_mode(regs))
33 mm = current->mm;
34 else
35 mm = &init_mm;
36
37 local_irq_save(flags);
38 if (mm == current->mm)
39 ptep = find_current_mm_pte(mm->pgd, addr, NULL, NULL);
40 else
41 ptep = find_init_mm_pte(addr, NULL);
42 local_irq_restore(flags);
43 if (!ptep || pte_special(*ptep))
44 return ULONG_MAX;
45 return pte_pfn(*ptep);
46}
e22a2274
MS		 47
48/* flush SLBs and reload */
4e003747 49#ifdef CONFIG_PPC_BOOK3S_64
a43c1590 50void flush_and_reload_slb(void)
e22a2274 51{
e22a2274 52 /* Invalidate all SLBs */
e7e81847 53 slb_flush_all_realmode();
e22a2274
MS		 54
55#ifdef CONFIG_KVM_BOOK3S_HANDLER
56 /*
57 * If machine check is hit when in guest or in transition, we will
58 * only flush the SLBs and continue.
59 */
60 if (get_paca()->kvm_hstate.in_guest)
61 return;
62#endif
e7e81847 63 if (early_radix_enabled())
e22a2274
MS		 64 return;
65
e7e81847
NP		 66 /*
67 * This probably shouldn't happen, but it may be possible it's
68 * called in early boot before SLB shadows are allocated.
69 */
70 if (!get_slb_shadow())
71 return;
e22a2274 72
e7e81847 73 slb_restore_bolted_realmode();
e22a2274 74}
caca285e 75#endif
e22a2274 76
7b9f71f9
NP		 77static void flush_erat(void)
78{
bc276ecb
NP		 79#ifdef CONFIG_PPC_BOOK3S_64
80 if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) {
81 flush_and_reload_slb();
82 return;
83 }
84#endif
85 /* PPC_INVALIDATE_ERAT can only be used on ISA v3 and newer */
7b9f71f9
NP		 86 asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
87}
88
89#define MCE_FLUSH_SLB 1
90#define MCE_FLUSH_TLB 2
91#define MCE_FLUSH_ERAT 3
92
93static int mce_flush(int what)
94{
4e003747 95#ifdef CONFIG_PPC_BOOK3S_64
7b9f71f9
NP		 96 if (what == MCE_FLUSH_SLB) {
97 flush_and_reload_slb();
98 return 1;
99 }
100#endif
101 if (what == MCE_FLUSH_ERAT) {
102 flush_erat();
103 return 1;
104 }
105 if (what == MCE_FLUSH_TLB) {
d4748276
NP		 106 tlbiel_all();
107 return 1;
7b9f71f9
NP		 108 }
109
110 return 0;
111}
112
755309be 113#define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42))
58c8d17f 114
631bc46c
NP		 115struct mce_ierror_table {
116 unsigned long srr1_mask;
117 unsigned long srr1_value;
118 bool nip_valid; /* nip is a valid indicator of faulting address */
119 unsigned int error_type;
120 unsigned int error_subtype;
50dbabe0 121 unsigned int error_class;
631bc46c
NP		 122 unsigned int initiator;
123 unsigned int severity;
cda6618d 124 bool sync_error;
631bc46c
NP		 125};
126
127static const struct mce_ierror_table mce_p7_ierror_table[] = {
128{ 0x00000000001c0000, 0x0000000000040000, true,
50dbabe0 129 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
cda6618d 130 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c 131{ 0x00000000001c0000, 0x0000000000080000, true,
50dbabe0 132 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
cda6618d 133 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c 134{ 0x00000000001c0000, 0x00000000000c0000, true,
50dbabe0 135 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 136 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
631bc46c
NP		 137{ 0x00000000001c0000, 0x0000000000100000, true,
138 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_INDETERMINATE, /* BOTH */
50dbabe0 139 MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 140 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
631bc46c 141{ 0x00000000001c0000, 0x0000000000140000, true,
50dbabe0 142 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 143 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
631bc46c 144{ 0x00000000001c0000, 0x0000000000180000, true,
50dbabe0 145 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_HARDWARE,
cda6618d 146 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c 147{ 0x00000000001c0000, 0x00000000001c0000, true,
50dbabe0 148 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
cda6618d
MS		 149 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
150{ 0, 0, 0, 0, 0, 0, 0 } };
631bc46c
NP		 151
152static const struct mce_ierror_table mce_p8_ierror_table[] = {
c7e790c5 153{ 0x00000000081c0000, 0x0000000000040000, true,
50dbabe0 154 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
cda6618d 155 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
c7e790c5 156{ 0x00000000081c0000, 0x0000000000080000, true,
50dbabe0 157 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
cda6618d 158 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
c7e790c5 159{ 0x00000000081c0000, 0x00000000000c0000, true,
50dbabe0 160 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 161 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
c7e790c5 162{ 0x00000000081c0000, 0x0000000000100000, true,
50dbabe0 163 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 164 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
c7e790c5 165{ 0x00000000081c0000, 0x0000000000140000, true,
50dbabe0 166 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 167 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
c7e790c5 168{ 0x00000000081c0000, 0x0000000000180000, true,
631bc46c 169 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH,
50dbabe0 170 MCE_ECLASS_HARDWARE,
cda6618d 171 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
c7e790c5 172{ 0x00000000081c0000, 0x00000000001c0000, true,
50dbabe0 173 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
cda6618d 174 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
c7e790c5 175{ 0x00000000081c0000, 0x0000000008000000, true,
50dbabe0 176 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_IFETCH_TIMEOUT, MCE_ECLASS_HARDWARE,
cda6618d 177 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
c7e790c5
NP		 178{ 0x00000000081c0000, 0x0000000008040000, true,
179 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT,
50dbabe0 180 MCE_ECLASS_HARDWARE,
cda6618d
MS		 181 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
182{ 0, 0, 0, 0, 0, 0, 0 } };
631bc46c
NP		 183
184static const struct mce_ierror_table mce_p9_ierror_table[] = {
185{ 0x00000000081c0000, 0x0000000000040000, true,
50dbabe0 186 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
cda6618d 187 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c 188{ 0x00000000081c0000, 0x0000000000080000, true,
50dbabe0 189 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
cda6618d 190 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c 191{ 0x00000000081c0000, 0x00000000000c0000, true,
50dbabe0 192 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 193 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
631bc46c 194{ 0x00000000081c0000, 0x0000000000100000, true,
50dbabe0 195 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 196 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
631bc46c 197{ 0x00000000081c0000, 0x0000000000140000, true,
50dbabe0 198 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 199 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
631bc46c 200{ 0x00000000081c0000, 0x0000000000180000, true,
50dbabe0 201 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_HARDWARE,
cda6618d 202 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
90df4bfb 203{ 0x00000000081c0000, 0x00000000001c0000, true,
50dbabe0 204 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH_FOREIGN, MCE_ECLASS_SOFTWARE,
cda6618d 205 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c 206{ 0x00000000081c0000, 0x0000000008000000, true,
50dbabe0 207 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_IFETCH_TIMEOUT, MCE_ECLASS_HARDWARE,
cda6618d 208 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c
NP		 209{ 0x00000000081c0000, 0x0000000008040000, true,
210 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT,
50dbabe0 211 MCE_ECLASS_HARDWARE,
cda6618d 212 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c 213{ 0x00000000081c0000, 0x00000000080c0000, true,
50dbabe0 214 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH, MCE_ECLASS_SOFTWARE,
cda6618d 215 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c 216{ 0x00000000081c0000, 0x0000000008100000, true,
50dbabe0 217 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_SOFTWARE,
cda6618d 218 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c 219{ 0x00000000081c0000, 0x0000000008140000, false,
50dbabe0 220 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_STORE, MCE_ECLASS_HARDWARE,
cda6618d 221 MCE_INITIATOR_CPU, MCE_SEV_FATAL, false }, /* ASYNC is fatal */
631bc46c
NP		 222{ 0x00000000081c0000, 0x0000000008180000, false,
223 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_STORE_TIMEOUT,
cda6618d 224 MCE_INITIATOR_CPU, MCE_SEV_FATAL, false }, /* ASYNC is fatal */
50dbabe0 225{ 0x00000000081c0000, 0x00000000081c0000, true, MCE_ECLASS_HARDWARE,
631bc46c 226 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN,
cda6618d
MS		 227 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
228{ 0, 0, 0, 0, 0, 0, 0 } };
631bc46c
NP		 229
230struct mce_derror_table {
231 unsigned long dsisr_value;
232 bool dar_valid; /* dar is a valid indicator of faulting address */
233 unsigned int error_type;
234 unsigned int error_subtype;
50dbabe0 235 unsigned int error_class;
631bc46c
NP		 236 unsigned int initiator;
237 unsigned int severity;
cda6618d 238 bool sync_error;
631bc46c
NP		 239};
240
241static const struct mce_derror_table mce_p7_derror_table[] = {
242{ 0x00008000, false,
50dbabe0 243 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE,
cda6618d 244 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c
NP		 245{ 0x00004000, true,
246 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
50dbabe0 247 MCE_ECLASS_HARDWARE,
cda6618d 248 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c 249{ 0x00000800, true,
50dbabe0 250 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 251 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
631bc46c 252{ 0x00000400, true,
50dbabe0 253 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 254 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
54dbcfc2 255{ 0x00000080, true,
50dbabe0 256 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 257 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
631bc46c 258{ 0x00000100, true,
50dbabe0 259 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
cda6618d 260 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c
NP		 261{ 0x00000040, true,
262 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_INDETERMINATE, /* BOTH */
50dbabe0 263 MCE_ECLASS_HARD_INDETERMINATE,
cda6618d
MS		 264 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
265{ 0, false, 0, 0, 0, 0, 0 } };
631bc46c
NP		 266
267static const struct mce_derror_table mce_p8_derror_table[] = {
268{ 0x00008000, false,
50dbabe0 269 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE,
cda6618d 270 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c
NP		 271{ 0x00004000, true,
272 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
50dbabe0 273 MCE_ECLASS_HARDWARE,
cda6618d 274 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
c7e790c5 275{ 0x00002000, true,
50dbabe0 276 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_LOAD_TIMEOUT, MCE_ECLASS_HARDWARE,
cda6618d 277 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
c7e790c5
NP		 278{ 0x00001000, true,
279 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT,
50dbabe0 280 MCE_ECLASS_HARDWARE,
cda6618d 281 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c 282{ 0x00000800, true,
50dbabe0 283 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 284 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
631bc46c 285{ 0x00000400, true,
50dbabe0 286 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 287 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
631bc46c
NP		 288{ 0x00000200, true,
289 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, /* SECONDARY ERAT */
50dbabe0 290 MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 291 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
54dbcfc2
ME		 292{ 0x00000080, true,
293 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, /* Before PARITY */
50dbabe0 294 MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 295 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
631bc46c 296{ 0x00000100, true,
50dbabe0 297 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
cda6618d
MS		 298 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
299{ 0, false, 0, 0, 0, 0, 0 } };
631bc46c
NP		 300
301static const struct mce_derror_table mce_p9_derror_table[] = {
302{ 0x00008000, false,
50dbabe0 303 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE,
cda6618d 304 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c
NP		 305{ 0x00004000, true,
306 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
50dbabe0 307 MCE_ECLASS_HARDWARE,
cda6618d 308 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c 309{ 0x00002000, true,
50dbabe0 310 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_LOAD_TIMEOUT, MCE_ECLASS_HARDWARE,
cda6618d 311 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c
NP		 312{ 0x00001000, true,
313 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT,
50dbabe0 314 MCE_ECLASS_HARDWARE,
cda6618d 315 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c 316{ 0x00000800, true,
50dbabe0 317 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 318 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
631bc46c 319{ 0x00000400, true,
50dbabe0 320 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 321 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
631bc46c 322{ 0x00000200, false,
50dbabe0 323 MCE_ERROR_TYPE_USER, MCE_USER_ERROR_TLBIE, MCE_ECLASS_SOFTWARE,
cda6618d 324 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
54dbcfc2
ME		 325{ 0x00000080, true,
326 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, /* Before PARITY */
50dbabe0 327 MCE_ECLASS_SOFT_INDETERMINATE,
cda6618d 328 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
631bc46c 329{ 0x00000100, true,
50dbabe0 330 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
cda6618d 331 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c 332{ 0x00000040, true,
50dbabe0 333 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD, MCE_ECLASS_HARDWARE,
cda6618d 334 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c
NP		 335{ 0x00000020, false,
336 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
50dbabe0 337 MCE_ECLASS_HARDWARE,
cda6618d 338 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c
NP		 339{ 0x00000010, false,
340 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN,
50dbabe0 341 MCE_ECLASS_HARDWARE,
cda6618d 342 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
631bc46c 343{ 0x00000008, false,
50dbabe0 344 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD_STORE_FOREIGN, MCE_ECLASS_HARDWARE,
cda6618d
MS		 345 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
346{ 0, false, 0, 0, 0, 0, 0 } };
631bc46c 347
ba41e1e1
BS		 348static int mce_find_instr_ea_and_pfn(struct pt_regs *regs, uint64_t *addr,
349 uint64_t *phys_addr)
350{
351 /*
352 * Carefully look at the NIP to determine
353 * the instruction to analyse. Reading the NIP
354 * in real-mode is tricky and can lead to recursive
355 * faults
356 */
357 int instr;
358 unsigned long pfn, instr_addr;
359 struct instruction_op op;
360 struct pt_regs tmp = *regs;
361
362 pfn = addr_to_pfn(regs, regs->nip);
363 if (pfn != ULONG_MAX) {
364 instr_addr = (pfn << PAGE_SHIFT) + (regs->nip & ~PAGE_MASK);
365 instr = *(unsigned int *)(instr_addr);
366 if (!analyse_instr(&op, &tmp, instr)) {
367 pfn = addr_to_pfn(regs, op.ea);
368 *addr = op.ea;
369 *phys_addr = (pfn << PAGE_SHIFT);
370 return 0;
371 }
372 /*
373 * analyse_instr() might fail if the instruction
374 * is not a load/store, although this is unexpected
375 * for load/store errors or if we got the NIP
376 * wrong
377 */
378 }
379 *addr = 0;
380 return -1;
381}
382
755309be 383static int mce_handle_ierror(struct pt_regs *regs,
631bc46c 384 const struct mce_ierror_table table[],
01eaac2b
BS		 385 struct mce_error_info *mce_err, uint64_t *addr,
386 uint64_t *phys_addr)
e22a2274 387{
631bc46c 388 uint64_t srr1 = regs->msr;
755309be 389 int handled = 0;
631bc46c
NP		 390 int i;
391
392 *addr = 0;
393
394 for (i = 0; table[i].srr1_mask; i++) {
395 if ((srr1 & table[i].srr1_mask) != table[i].srr1_value)
396 continue;
397
755309be
NP		 398 /* attempt to correct the error */
399 switch (table[i].error_type) {
400 case MCE_ERROR_TYPE_SLB:
401 handled = mce_flush(MCE_FLUSH_SLB);
402 break;
403 case MCE_ERROR_TYPE_ERAT:
404 handled = mce_flush(MCE_FLUSH_ERAT);
405 break;
406 case MCE_ERROR_TYPE_TLB:
407 handled = mce_flush(MCE_FLUSH_TLB);
408 break;
409 }
410
411 /* now fill in mce_error_info */
631bc46c 412 mce_err->error_type = table[i].error_type;
50dbabe0 413 mce_err->error_class = table[i].error_class;
631bc46c
NP		 414 switch (table[i].error_type) {
415 case MCE_ERROR_TYPE_UE:
416 mce_err->u.ue_error_type = table[i].error_subtype;
417 break;
418 case MCE_ERROR_TYPE_SLB:
419 mce_err->u.slb_error_type = table[i].error_subtype;
420 break;
421 case MCE_ERROR_TYPE_ERAT:
422 mce_err->u.erat_error_type = table[i].error_subtype;
423 break;
424 case MCE_ERROR_TYPE_TLB:
425 mce_err->u.tlb_error_type = table[i].error_subtype;
426 break;
427 case MCE_ERROR_TYPE_USER:
428 mce_err->u.user_error_type = table[i].error_subtype;
429 break;
430 case MCE_ERROR_TYPE_RA:
431 mce_err->u.ra_error_type = table[i].error_subtype;
432 break;
433 case MCE_ERROR_TYPE_LINK:
434 mce_err->u.link_error_type = table[i].error_subtype;
435 break;
436 }
cda6618d 437 mce_err->sync_error = table[i].sync_error;
631bc46c
NP		 438 mce_err->severity = table[i].severity;
439 mce_err->initiator = table[i].initiator;
01eaac2b 440 if (table[i].nip_valid) {
631bc46c 441 *addr = regs->nip;
cda6618d 442 if (mce_err->sync_error &&
01eaac2b
BS		 443 table[i].error_type == MCE_ERROR_TYPE_UE) {
444 unsigned long pfn;
445
446 if (get_paca()->in_mce < MAX_MCE_DEPTH) {
447 pfn = addr_to_pfn(regs, regs->nip);
448 if (pfn != ULONG_MAX) {
449 *phys_addr =
450 (pfn << PAGE_SHIFT);
01eaac2b
BS		 451 }
452 }
453 }
454 }
755309be 455 return handled;
e22a2274 456 }
e22a2274 457
631bc46c 458 mce_err->error_type = MCE_ERROR_TYPE_UNKNOWN;
50dbabe0 459 mce_err->error_class = MCE_ECLASS_UNKNOWN;
cda6618d 460 mce_err->severity = MCE_SEV_SEVERE;
631bc46c 461 mce_err->initiator = MCE_INITIATOR_CPU;
cda6618d 462 mce_err->sync_error = true;
755309be
NP		 463
464 return 0;
36df96f8
MS		 465}
466
755309be 467static int mce_handle_derror(struct pt_regs *regs,
631bc46c 468 const struct mce_derror_table table[],
ba41e1e1
BS		 469 struct mce_error_info *mce_err, uint64_t *addr,
470 uint64_t *phys_addr)
36df96f8 471{
631bc46c 472 uint64_t dsisr = regs->dsisr;
755309be
NP		 473 int handled = 0;
474 int found = 0;
631bc46c
NP		 475 int i;
476
477 *addr = 0;
478
479 for (i = 0; table[i].dsisr_value; i++) {
480 if (!(dsisr & table[i].dsisr_value))
481 continue;
482
755309be
NP		 483 /* attempt to correct the error */
484 switch (table[i].error_type) {
485 case MCE_ERROR_TYPE_SLB:
486 if (mce_flush(MCE_FLUSH_SLB))
487 handled = 1;
488 break;
489 case MCE_ERROR_TYPE_ERAT:
490 if (mce_flush(MCE_FLUSH_ERAT))
491 handled = 1;
492 break;
493 case MCE_ERROR_TYPE_TLB:
494 if (mce_flush(MCE_FLUSH_TLB))
495 handled = 1;
496 break;
497 }
498
499 /*
500 * Attempt to handle multiple conditions, but only return
501 * one. Ensure uncorrectable errors are first in the table
502 * to match.
503 */
504 if (found)
505 continue;
506
507 /* now fill in mce_error_info */
631bc46c 508 mce_err->error_type = table[i].error_type;
50dbabe0 509 mce_err->error_class = table[i].error_class;
631bc46c
NP		 510 switch (table[i].error_type) {
511 case MCE_ERROR_TYPE_UE:
512 mce_err->u.ue_error_type = table[i].error_subtype;
513 break;
514 case MCE_ERROR_TYPE_SLB:
515 mce_err->u.slb_error_type = table[i].error_subtype;
516 break;
517 case MCE_ERROR_TYPE_ERAT:
518 mce_err->u.erat_error_type = table[i].error_subtype;
519 break;
520 case MCE_ERROR_TYPE_TLB:
521 mce_err->u.tlb_error_type = table[i].error_subtype;
522 break;
523 case MCE_ERROR_TYPE_USER:
524 mce_err->u.user_error_type = table[i].error_subtype;
525 break;
526 case MCE_ERROR_TYPE_RA:
527 mce_err->u.ra_error_type = table[i].error_subtype;
528 break;
529 case MCE_ERROR_TYPE_LINK:
530 mce_err->u.link_error_type = table[i].error_subtype;
531 break;
532 }
cda6618d 533 mce_err->sync_error = table[i].sync_error;
631bc46c
NP		 534 mce_err->severity = table[i].severity;
535 mce_err->initiator = table[i].initiator;
536 if (table[i].dar_valid)
537 *addr = regs->dar;
cda6618d 538 else if (mce_err->sync_error &&
ba41e1e1
BS		 539 table[i].error_type == MCE_ERROR_TYPE_UE) {
540 /*
541 * We do a maximum of 4 nested MCE calls, see
542 * kernel/exception-64s.h
543 */
544 if (get_paca()->in_mce < MAX_MCE_DEPTH)
75ecfb49 545 mce_find_instr_ea_and_pfn(regs, addr, phys_addr);
ba41e1e1 546 }
755309be 547 found = 1;
36df96f8 548 }
631bc46c 549
755309be
NP		 550 if (found)
551 return handled;
552
631bc46c 553 mce_err->error_type = MCE_ERROR_TYPE_UNKNOWN;
50dbabe0 554 mce_err->error_class = MCE_ECLASS_UNKNOWN;
cda6618d 555 mce_err->severity = MCE_SEV_SEVERE;
631bc46c 556 mce_err->initiator = MCE_INITIATOR_CPU;
cda6618d 557 mce_err->sync_error = true;
755309be
NP		 558
559 return 0;
36df96f8
MS		 560}
561
55672ecf
MS		 562static long mce_handle_ue_error(struct pt_regs *regs)
563{
564 long handled = 0;
565
566 /*
567 * On specific SCOM read via MMIO we may get a machine check
568 * exception with SRR0 pointing inside opal. If that is the
569 * case OPAL may have recovery address to re-read SCOM data in
570 * different way and hence we can recover from this MC.
571 */
572
573 if (ppc_md.mce_check_early_recovery) {
574 if (ppc_md.mce_check_early_recovery(regs))
575 handled = 1;
576 }
577 return handled;
578}
579
755309be
NP		 580static long mce_handle_error(struct pt_regs *regs,
581 const struct mce_derror_table dtable[],
582 const struct mce_ierror_table itable[])
e22a2274 583{
755309be 584 struct mce_error_info mce_err = { 0 };
75ecfb49 585 uint64_t addr, phys_addr = ULONG_MAX;
755309be
NP		 586 uint64_t srr1 = regs->msr;
587 long handled;
e22a2274 588
755309be 589 if (SRR1_MC_LOADSTORE(srr1))
ba41e1e1
BS		 590 handled = mce_handle_derror(regs, dtable, &mce_err, &addr,
591 &phys_addr);
755309be 592 else
01eaac2b
BS		 593 handled = mce_handle_ierror(regs, itable, &mce_err, &addr,
594 &phys_addr);
631bc46c 595
755309be 596 if (!handled && mce_err.error_type == MCE_ERROR_TYPE_UE)
55672ecf
MS		 597 handled = mce_handle_ue_error(regs);
598
ba41e1e1 599 save_mce_event(regs, handled, &mce_err, regs->nip, addr, phys_addr);
55672ecf 600
ae744f34
MS		 601 return handled;
602}
7b9f71f9 603
755309be 604long __machine_check_early_realmode_p7(struct pt_regs *regs)
7b9f71f9 605{
755309be
NP		 606 /* P7 DD1 leaves top bits of DSISR undefined */
607 regs->dsisr &= 0x0000ffff;
7b9f71f9 608
755309be 609 return mce_handle_error(regs, mce_p7_derror_table, mce_p7_ierror_table);
7b9f71f9
NP		 610}
611
755309be 612long __machine_check_early_realmode_p8(struct pt_regs *regs)
7b9f71f9 613{
755309be 614 return mce_handle_error(regs, mce_p8_derror_table, mce_p8_ierror_table);
7b9f71f9
NP		 615}
616
7b9f71f9
NP		 617long __machine_check_early_realmode_p9(struct pt_regs *regs)
618{
d8bd9f3f
MN		 619 /*
620 * On POWER9 DD2.1 and below, it's possible to get a machine check
bca73f59 621 * caused by a paste instruction where only DSISR bit 25 is set. This
d8bd9f3f
MN		 622 * will result in the MCE handler seeing an unknown event and the kernel
623 * crashing. An MCE that occurs like this is spurious, so we don't need
624 * to do anything in terms of servicing it. If there is something that
625 * needs to be serviced, the CPU will raise the MCE again with the
626 * correct DSISR so that it can be serviced properly. So detect this
627 * case and mark it as handled.
628 */
bca73f59 629 if (SRR1_MC_LOADSTORE(regs->msr) && regs->dsisr == 0x02000000)
d8bd9f3f
MN		 630 return 1;
631
755309be 632 return mce_handle_error(regs, mce_p9_derror_table, mce_p9_ierror_table);
7b9f71f9 633}
Linux 6.x block layer and io_uring tree(s)