Commit | Line | Data |
---|---|---|
948cf67c | 1 | /* |
bcef83a0 SP |
2 | * This file contains idle entry/exit functions for POWER7, |
3 | * POWER8 and POWER9 CPUs. | |
948cf67c BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | */ | |
10 | ||
11 | #include <linux/threads.h> | |
12 | #include <asm/processor.h> | |
13 | #include <asm/page.h> | |
14 | #include <asm/cputable.h> | |
15 | #include <asm/thread_info.h> | |
16 | #include <asm/ppc_asm.h> | |
17 | #include <asm/asm-offsets.h> | |
18 | #include <asm/ppc-opcode.h> | |
7230c564 | 19 | #include <asm/hw_irq.h> |
f0888f70 | 20 | #include <asm/kvm_book3s_asm.h> |
97eb001f | 21 | #include <asm/opal.h> |
7cba160a | 22 | #include <asm/cpuidle.h> |
bf0153c1 | 23 | #include <asm/exception-64s.h> |
f64e8084 | 24 | #include <asm/book3s/64/mmu-hash.h> |
bcef83a0 | 25 | #include <asm/mmu.h> |
948cf67c BH |
26 | |
27 | #undef DEBUG | |
28 | ||
77b54e9f SP |
29 | /* |
30 | * Use unused space in the interrupt stack to save and restore | |
31 | * registers for winkle support. | |
32 | */ | |
33 | #define _SDR1 GPR3 | |
34 | #define _RPR GPR4 | |
35 | #define _SPURR GPR5 | |
36 | #define _PURR GPR6 | |
37 | #define _TSCR GPR7 | |
38 | #define _DSCR GPR8 | |
39 | #define _AMOR GPR9 | |
40 | #define _WORT GPR10 | |
41 | #define _WORC GPR11 | |
bcef83a0 SP |
42 | #define _PTCR GPR12 |
43 | ||
09206b60 | 44 | #define PSSCR_EC_ESL_MASK_SHIFTED (PSSCR_EC | PSSCR_ESL) >> 16 |
77b54e9f | 45 | |
aca79d2b VS |
46 | .text |
47 | ||
0dfffb48 SP |
48 | /* |
49 | * Used by threads before entering deep idle states. Saves SPRs | |
50 | * in interrupt stack frame | |
51 | */ | |
52 | save_sprs_to_stack: | |
53 | /* | |
54 | * Note all register i.e per-core, per-subcore or per-thread is saved | |
55 | * here since any thread in the core might wake up first | |
56 | */ | |
bcef83a0 SP |
57 | BEGIN_FTR_SECTION |
58 | mfspr r3,SPRN_PTCR | |
59 | std r3,_PTCR(r1) | |
60 | /* | |
61 | * Note - SDR1 is dropped in Power ISA v3. Hence not restoring | |
62 | * SDR1 here | |
63 | */ | |
64 | FTR_SECTION_ELSE | |
0dfffb48 SP |
65 | mfspr r3,SPRN_SDR1 |
66 | std r3,_SDR1(r1) | |
bcef83a0 | 67 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300) |
0dfffb48 SP |
68 | mfspr r3,SPRN_RPR |
69 | std r3,_RPR(r1) | |
70 | mfspr r3,SPRN_SPURR | |
71 | std r3,_SPURR(r1) | |
72 | mfspr r3,SPRN_PURR | |
73 | std r3,_PURR(r1) | |
74 | mfspr r3,SPRN_TSCR | |
75 | std r3,_TSCR(r1) | |
76 | mfspr r3,SPRN_DSCR | |
77 | std r3,_DSCR(r1) | |
78 | mfspr r3,SPRN_AMOR | |
79 | std r3,_AMOR(r1) | |
80 | mfspr r3,SPRN_WORT | |
81 | std r3,_WORT(r1) | |
82 | mfspr r3,SPRN_WORC | |
83 | std r3,_WORC(r1) | |
84 | ||
85 | blr | |
86 | ||
b32aadc1 SP |
87 | /* |
88 | * Used by threads when the lock bit of core_idle_state is set. | |
89 | * Threads will spin in HMT_LOW until the lock bit is cleared. | |
90 | * r14 - pointer to core_idle_state | |
91 | * r15 - used to load contents of core_idle_state | |
09b7e37b | 92 | * r9 - used as a temporary variable |
b32aadc1 SP |
93 | */ |
94 | ||
95 | core_idle_lock_held: | |
96 | HMT_LOW | |
97 | 3: lwz r15,0(r14) | |
adbcf8d7 | 98 | andis. r15,r15,PNV_CORE_IDLE_LOCK_BIT@h |
b32aadc1 SP |
99 | bne 3b |
100 | HMT_MEDIUM | |
101 | lwarx r15,0,r14 | |
adbcf8d7 NP |
102 | andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h |
103 | bne- core_idle_lock_held | |
b32aadc1 SP |
104 | blr |
105 | ||
aca79d2b VS |
106 | /* |
107 | * Pass requested state in r3: | |
bcef83a0 SP |
108 | * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8 |
109 | * - Requested STOP state in POWER9 | |
8d6f7c5a ME |
110 | * |
111 | * To check IRQ_HAPPENED in r4 | |
112 | * 0 - don't check | |
113 | * 1 - check | |
4eae2c9a SP |
114 | * |
115 | * Address to 'rfid' to in r5 | |
aca79d2b | 116 | */ |
bf0153c1 | 117 | pnv_powersave_common: |
aca79d2b | 118 | /* Use r3 to pass state nap/sleep/winkle */ |
948cf67c BH |
119 | /* NAP is a state loss, we create a regs frame on the |
120 | * stack, fill it up with the state we care about and | |
121 | * stick a pointer to it in PACAR1. We really only | |
122 | * need to save PC, some CR bits and the NV GPRs, | |
123 | * but for now an interrupt frame will do. | |
124 | */ | |
125 | mflr r0 | |
126 | std r0,16(r1) | |
127 | stdu r1,-INT_FRAME_SIZE(r1) | |
128 | std r0,_LINK(r1) | |
129 | std r0,_NIP(r1) | |
130 | ||
948cf67c BH |
131 | /* Hard disable interrupts */ |
132 | mfmsr r9 | |
133 | rldicl r9,r9,48,1 | |
134 | rotldi r9,r9,16 | |
135 | mtmsrd r9,1 /* hard-disable interrupts */ | |
7230c564 BH |
136 | |
137 | /* Check if something happened while soft-disabled */ | |
138 | lbz r0,PACAIRQHAPPENED(r13) | |
d6a4f709 | 139 | andi. r0,r0,~PACA_IRQ_HARD_DIS@l |
7230c564 | 140 | beq 1f |
8d6f7c5a ME |
141 | cmpwi cr0,r4,0 |
142 | beq 1f | |
7230c564 BH |
143 | addi r1,r1,INT_FRAME_SIZE |
144 | ld r0,16(r1) | |
f57333a7 | 145 | li r3,0 /* Return 0 (no nap) */ |
7230c564 BH |
146 | mtlr r0 |
147 | blr | |
148 | ||
149 | 1: /* We mark irqs hard disabled as this is the state we'll | |
150 | * be in when returning and we need to tell arch_local_irq_restore() | |
151 | * about it | |
152 | */ | |
153 | li r0,PACA_IRQ_HARD_DIS | |
154 | stb r0,PACAIRQHAPPENED(r13) | |
155 | ||
156 | /* We haven't lost state ... yet */ | |
948cf67c | 157 | li r0,0 |
2fde6d20 | 158 | stb r0,PACA_NAPSTATELOST(r13) |
948cf67c BH |
159 | |
160 | /* Continue saving state */ | |
161 | SAVE_GPR(2, r1) | |
162 | SAVE_NVGPRS(r1) | |
aca79d2b VS |
163 | mfcr r4 |
164 | std r4,_CCR(r1) | |
948cf67c BH |
165 | std r9,_MSR(r1) |
166 | std r1,PACAR1(r13) | |
167 | ||
8117ac6a PM |
168 | /* |
169 | * Go to real mode to do the nap, as required by the architecture. | |
170 | * Also, we need to be in real mode before setting hwthread_state, | |
171 | * because as soon as we do that, another thread can switch | |
172 | * the MMU context to the guest. | |
173 | */ | |
4eae2c9a | 174 | LOAD_REG_IMMEDIATE(r7, MSR_IDLE) |
8117ac6a PM |
175 | li r6, MSR_RI |
176 | andc r6, r9, r6 | |
8117ac6a | 177 | mtmsrd r6, 1 /* clear RI before setting SRR0/1 */ |
4eae2c9a SP |
178 | mtspr SPRN_SRR0, r5 |
179 | mtspr SPRN_SRR1, r7 | |
8117ac6a PM |
180 | rfid |
181 | ||
5fa6b6bd SP |
182 | .globl pnv_enter_arch207_idle_mode |
183 | pnv_enter_arch207_idle_mode: | |
56c46222 PM |
184 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
185 | /* Tell KVM we're entering idle */ | |
186 | li r4,KVM_HWTHREAD_IN_IDLE | |
187 | /******************************************************/ | |
188 | /* N O T E W E L L ! ! ! N O T E W E L L */ | |
189 | /* The following store to HSTATE_HWTHREAD_STATE(r13) */ | |
190 | /* MUST occur in real mode, i.e. with the MMU off, */ | |
191 | /* and the MMU must stay off until we clear this flag */ | |
bf0153c1 NP |
192 | /* and test HSTATE_HWTHREAD_REQ(r13) in */ |
193 | /* pnv_powersave_wakeup in this file. */ | |
56c46222 PM |
194 | /* The reason is that another thread can switch the */ |
195 | /* MMU to a guest context whenever this flag is set */ | |
196 | /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */ | |
197 | /* that would potentially cause this thread to start */ | |
198 | /* executing instructions from guest memory in */ | |
199 | /* hypervisor mode, leading to a host crash or data */ | |
200 | /* corruption, or worse. */ | |
201 | /******************************************************/ | |
202 | stb r4,HSTATE_HWTHREAD_STATE(r13) | |
203 | #endif | |
7cba160a | 204 | stb r3,PACA_THREAD_IDLE_STATE(r13) |
77b54e9f SP |
205 | cmpwi cr3,r3,PNV_THREAD_SLEEP |
206 | bge cr3,2f | |
823b7bd5 | 207 | IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP) |
aca79d2b | 208 | /* No return */ |
7cba160a SP |
209 | 2: |
210 | /* Sleep or winkle */ | |
211 | lbz r7,PACA_THREAD_MASK(r13) | |
212 | ld r14,PACA_CORE_IDLE_STATE_PTR(r13) | |
213 | lwarx_loop1: | |
214 | lwarx r15,0,r14 | |
b32aadc1 | 215 | |
adbcf8d7 NP |
216 | andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h |
217 | bnel- core_idle_lock_held | |
b32aadc1 | 218 | |
7cba160a SP |
219 | andc r15,r15,r7 /* Clear thread bit */ |
220 | ||
221 | andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS | |
222 | ||
223 | /* | |
224 | * If cr0 = 0, then current thread is the last thread of the core entering | |
225 | * sleep. Last thread needs to execute the hardware bug workaround code if | |
226 | * required by the platform. | |
227 | * Make the workaround call unconditionally here. The below branch call is | |
228 | * patched out when the idle states are discovered if the platform does not | |
229 | * require it. | |
230 | */ | |
231 | .global pnv_fastsleep_workaround_at_entry | |
232 | pnv_fastsleep_workaround_at_entry: | |
233 | beq fastsleep_workaround_at_entry | |
234 | ||
235 | stwcx. r15,0,r14 | |
236 | bne- lwarx_loop1 | |
237 | isync | |
238 | ||
77b54e9f SP |
239 | common_enter: /* common code for all the threads entering sleep or winkle */ |
240 | bgt cr3,enter_winkle | |
823b7bd5 | 241 | IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP) |
7cba160a SP |
242 | |
243 | fastsleep_workaround_at_entry: | |
adbcf8d7 | 244 | oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h |
7cba160a SP |
245 | stwcx. r15,0,r14 |
246 | bne- lwarx_loop1 | |
247 | isync | |
248 | ||
249 | /* Fast sleep workaround */ | |
250 | li r3,1 | |
251 | li r4,1 | |
ab9bad0e | 252 | bl opal_config_cpu_idle_state |
7cba160a | 253 | |
adbcf8d7 NP |
254 | /* Unlock */ |
255 | xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h | |
7cba160a | 256 | lwsync |
adbcf8d7 | 257 | stw r15,0(r14) |
7cba160a SP |
258 | b common_enter |
259 | ||
77b54e9f | 260 | enter_winkle: |
0dfffb48 SP |
261 | bl save_sprs_to_stack |
262 | ||
823b7bd5 | 263 | IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE) |
f0888f70 | 264 | |
bcef83a0 | 265 | /* |
09206b60 | 266 | * r3 - PSSCR value corresponding to the requested stop state. |
bcef83a0 SP |
267 | */ |
268 | power_enter_stop: | |
56c46222 PM |
269 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
270 | /* Tell KVM we're entering idle */ | |
271 | li r4,KVM_HWTHREAD_IN_IDLE | |
272 | /* DO THIS IN REAL MODE! See comment above. */ | |
273 | stb r4,HSTATE_HWTHREAD_STATE(r13) | |
274 | #endif | |
09206b60 GS |
275 | /* |
276 | * Check if we are executing the lite variant with ESL=EC=0 | |
277 | */ | |
278 | andis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED | |
279 | clrldi r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */ | |
424f8acd | 280 | bne .Lhandle_esl_ec_set |
09206b60 GS |
281 | IDLE_STATE_ENTER_SEQ(PPC_STOP) |
282 | li r3,0 /* Since we didn't lose state, return 0 */ | |
283 | b pnv_wakeup_noloss | |
424f8acd GS |
284 | |
285 | .Lhandle_esl_ec_set: | |
bcef83a0 SP |
286 | /* |
287 | * Check if the requested state is a deep idle state. | |
288 | */ | |
424f8acd | 289 | LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state) |
bcef83a0 SP |
290 | ld r4,ADDROFF(pnv_first_deep_stop_state)(r5) |
291 | cmpd r3,r4 | |
424f8acd | 292 | bge .Lhandle_deep_stop |
823b7bd5 | 293 | IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP) |
424f8acd | 294 | .Lhandle_deep_stop: |
bcef83a0 SP |
295 | /* |
296 | * Entering deep idle state. | |
297 | * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to | |
298 | * stack and enter stop | |
299 | */ | |
300 | lbz r7,PACA_THREAD_MASK(r13) | |
301 | ld r14,PACA_CORE_IDLE_STATE_PTR(r13) | |
302 | ||
303 | lwarx_loop_stop: | |
304 | lwarx r15,0,r14 | |
adbcf8d7 NP |
305 | andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h |
306 | bnel- core_idle_lock_held | |
bcef83a0 SP |
307 | andc r15,r15,r7 /* Clear thread bit */ |
308 | ||
309 | stwcx. r15,0,r14 | |
310 | bne- lwarx_loop_stop | |
311 | isync | |
312 | ||
313 | bl save_sprs_to_stack | |
314 | ||
823b7bd5 | 315 | IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP) |
bcef83a0 | 316 | |
aca79d2b VS |
317 | _GLOBAL(power7_idle) |
318 | /* Now check if user or arch enabled NAP mode */ | |
319 | LOAD_REG_ADDRBASE(r3,powersave_nap) | |
320 | lwz r4,ADDROFF(powersave_nap)(r3) | |
321 | cmpwi 0,r4,0 | |
322 | beqlr | |
8d6f7c5a | 323 | li r3, 1 |
aca79d2b VS |
324 | /* fall through */ |
325 | ||
326 | _GLOBAL(power7_nap) | |
8d6f7c5a | 327 | mr r4,r3 |
7cba160a | 328 | li r3,PNV_THREAD_NAP |
4eae2c9a | 329 | LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode) |
5fa6b6bd | 330 | b pnv_powersave_common |
aca79d2b VS |
331 | /* No return */ |
332 | ||
333 | _GLOBAL(power7_sleep) | |
7cba160a | 334 | li r3,PNV_THREAD_SLEEP |
c733cf83 | 335 | li r4,1 |
4eae2c9a | 336 | LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode) |
5fa6b6bd | 337 | b pnv_powersave_common |
aca79d2b | 338 | /* No return */ |
948cf67c | 339 | |
77b54e9f | 340 | _GLOBAL(power7_winkle) |
bfd1b7ae | 341 | li r3,PNV_THREAD_WINKLE |
77b54e9f | 342 | li r4,1 |
4eae2c9a | 343 | LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode) |
5fa6b6bd | 344 | b pnv_powersave_common |
77b54e9f SP |
345 | /* No return */ |
346 | ||
bbdb760d MS |
347 | #define CHECK_HMI_INTERRUPT \ |
348 | mfspr r0,SPRN_SRR1; \ | |
349 | BEGIN_FTR_SECTION_NESTED(66); \ | |
350 | rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \ | |
351 | FTR_SECTION_ELSE_NESTED(66); \ | |
352 | rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \ | |
353 | ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \ | |
354 | cmpwi r0,0xa; /* Hypervisor maintenance ? */ \ | |
355 | bne 20f; \ | |
356 | /* Invoke opal call to handle hmi */ \ | |
357 | ld r2,PACATOC(r13); \ | |
358 | ld r1,PACAR1(r13); \ | |
359 | std r3,ORIG_GPR3(r1); /* Save original r3 */ \ | |
fd7bacbc MS |
360 | li r3,0; /* NULL argument */ \ |
361 | bl hmi_exception_realmode; \ | |
362 | nop; \ | |
bbdb760d MS |
363 | ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \ |
364 | 20: nop; | |
365 | ||
bcef83a0 | 366 | /* |
09206b60 GS |
367 | * r3 - The PSSCR value corresponding to the stop state. |
368 | * r4 - The PSSCR mask corrresonding to the stop state. | |
bcef83a0 SP |
369 | */ |
370 | _GLOBAL(power9_idle_stop) | |
09206b60 GS |
371 | mfspr r5,SPRN_PSSCR |
372 | andc r5,r5,r4 | |
373 | or r3,r3,r5 | |
374 | mtspr SPRN_PSSCR,r3 | |
bcef83a0 | 375 | LOAD_REG_ADDR(r5,power_enter_stop) |
09206b60 | 376 | li r4,1 |
bcef83a0 SP |
377 | b pnv_powersave_common |
378 | /* No return */ | |
17ed4c8f | 379 | |
17ed4c8f GS |
380 | /* |
381 | * On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1, | |
382 | * HSPRG0 will be set to the HSPRG0 value of one of the | |
383 | * threads in this core. Thus the value we have in r13 | |
384 | * may not be this thread's paca pointer. | |
385 | * | |
386 | * Fortunately, the TIR remains invariant. Since this thread's | |
387 | * paca pointer is recorded in all its sibling's paca, we can | |
388 | * correctly recover this thread's paca pointer if we | |
389 | * know the index of this thread in the core. | |
390 | * | |
391 | * This index can be obtained from the TIR. | |
392 | * | |
393 | * i.e, thread's position in the core = TIR. | |
394 | * If this value is i, then this thread's paca is | |
395 | * paca->thread_sibling_pacas[i]. | |
396 | */ | |
397 | power9_dd1_recover_paca: | |
398 | mfspr r4, SPRN_TIR | |
399 | /* | |
400 | * Since each entry in thread_sibling_pacas is 8 bytes | |
401 | * we need to left-shift by 3 bits. Thus r4 = i * 8 | |
402 | */ | |
403 | sldi r4, r4, 3 | |
404 | /* Get &paca->thread_sibling_pacas[0] in r5 */ | |
405 | ld r5, PACA_SIBLING_PACA_PTRS(r13) | |
406 | /* Load paca->thread_sibling_pacas[i] into r13 */ | |
407 | ldx r13, r4, r5 | |
408 | SET_PACA(r13) | |
409 | ld r2, PACATOC(r13) | |
410 | /* | |
411 | * Indicate that we have lost NVGPR state | |
412 | * which needs to be restored from the stack. | |
413 | */ | |
414 | li r3, 1 | |
415 | stb r0,PACA_NAPSTATELOST(r13) | |
416 | blr | |
417 | ||
1945bc45 NP |
418 | /* |
419 | * Called from machine check handler for powersave wakeups. | |
420 | * Low level machine check processing has already been done. Now just | |
421 | * go through the wake up path to get everything in order. | |
422 | * | |
423 | * r3 - The original SRR1 value. | |
424 | * Original SRR[01] have been clobbered. | |
425 | * MSR_RI is clear. | |
426 | */ | |
427 | .global pnv_powersave_wakeup_mce | |
428 | pnv_powersave_wakeup_mce: | |
429 | /* Set cr3 for pnv_powersave_wakeup */ | |
430 | rlwinm r11,r3,47-31,30,31 | |
431 | cmpwi cr3,r11,2 | |
432 | ||
433 | /* | |
434 | * Now put the original SRR1 with SRR1_WAKEMCE_RESVD as the wake | |
435 | * reason into SRR1, which allows reuse of the system reset wakeup | |
436 | * code without being mistaken for another type of wakeup. | |
437 | */ | |
438 | oris r3,r3,SRR1_WAKEMCE_RESVD@h | |
439 | mtspr SPRN_SRR1,r3 | |
440 | ||
441 | b pnv_powersave_wakeup | |
442 | ||
544686ca NP |
443 | /* |
444 | * Called from reset vector for powersave wakeups. | |
445 | * cr3 - set to gt if waking up with partial/complete hypervisor state loss | |
446 | */ | |
bf0153c1 NP |
447 | .global pnv_powersave_wakeup |
448 | pnv_powersave_wakeup: | |
10101aa9 NP |
449 | BEGIN_FTR_SECTION |
450 | bl pnv_restore_hyp_resource_arch300 | |
451 | FTR_SECTION_ELSE | |
452 | bl pnv_restore_hyp_resource_arch207 | |
453 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300) | |
bf0153c1 NP |
454 | |
455 | li r0,PNV_THREAD_RUNNING | |
456 | stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */ | |
457 | ||
458 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE | |
459 | li r0,KVM_HWTHREAD_IN_KERNEL | |
460 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
461 | /* Order setting hwthread_state vs. testing hwthread_req */ | |
462 | sync | |
463 | lbz r0,HSTATE_HWTHREAD_REQ(r13) | |
464 | cmpwi r0,0 | |
465 | beq 1f | |
466 | b kvm_start_guest | |
467 | 1: | |
468 | #endif | |
469 | ||
470 | /* Return SRR1 from power7_nap() */ | |
471 | mfspr r3,SPRN_SRR1 | |
472 | blt cr3,pnv_wakeup_noloss | |
473 | b pnv_wakeup_loss | |
474 | ||
17065671 | 475 | /* |
bf0153c1 NP |
476 | * Check whether we have woken up with hypervisor state loss. |
477 | * If yes, restore hypervisor state and return back to link. | |
17065671 | 478 | * |
17065671 SP |
479 | * cr3 - set to gt if waking up with partial/complete hypervisor state loss |
480 | */ | |
10101aa9 NP |
481 | pnv_restore_hyp_resource_arch300: |
482 | /* | |
483 | * POWER ISA 3. Use PSSCR to determine if we | |
484 | * are waking up from deep idle state | |
485 | */ | |
bcef83a0 | 486 | BEGIN_FTR_SECTION |
17ed4c8f GS |
487 | mflr r6 |
488 | bl power9_dd1_recover_paca | |
489 | mtlr r6 | |
544686ca | 490 | FTR_SECTION_ELSE |
17ed4c8f | 491 | ld r2, PACATOC(r13) |
544686ca NP |
492 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_POWER9_DD1) |
493 | ||
bcef83a0 SP |
494 | LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state) |
495 | ld r4,ADDROFF(pnv_first_deep_stop_state)(r5) | |
496 | ||
497 | mfspr r5,SPRN_PSSCR | |
17065671 | 498 | /* |
bcef83a0 SP |
499 | * 0-3 bits correspond to Power-Saving Level Status |
500 | * which indicates the idle state we are waking up from | |
501 | */ | |
502 | rldicl r5,r5,4,60 | |
503 | cmpd cr4,r5,r4 | |
bf0153c1 NP |
504 | bge cr4,pnv_wakeup_tb_loss /* returns to caller */ |
505 | ||
506 | blr /* Waking up without hypervisor state loss. */ | |
bcef83a0 | 507 | |
10101aa9 NP |
508 | /* Same calling convention as arch300 */ |
509 | pnv_restore_hyp_resource_arch207: | |
bcef83a0 SP |
510 | /* |
511 | * POWER ISA 2.07 or less. | |
544686ca | 512 | * Check if we slept with winkle. |
17065671 | 513 | */ |
10101aa9 NP |
514 | ld r2,PACATOC(r13); |
515 | ||
17065671 SP |
516 | lbz r0,PACA_THREAD_IDLE_STATE(r13) |
517 | cmpwi cr2,r0,PNV_THREAD_NAP | |
544686ca | 518 | cmpwi cr4,r0,PNV_THREAD_WINKLE |
5fa6b6bd | 519 | bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */ |
17065671 SP |
520 | |
521 | /* | |
522 | * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking | |
523 | * up from nap. At this stage CR3 shouldn't contains 'gt' since that | |
524 | * indicates we are waking with hypervisor state loss from nap. | |
525 | */ | |
526 | bgt cr3,. | |
527 | ||
bf0153c1 | 528 | blr /* Waking up without hypervisor state loss */ |
17065671 | 529 | |
bcef83a0 SP |
530 | /* |
531 | * Called if waking up from idle state which can cause either partial or | |
532 | * complete hyp state loss. | |
533 | * In POWER8, called if waking up from fastsleep or winkle | |
534 | * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state | |
535 | * | |
536 | * r13 - PACA | |
537 | * cr3 - gt if waking up with partial/complete hypervisor state loss | |
bd00a240 | 538 | * cr4 - gt or eq if waking up from complete hypervisor state loss. |
bcef83a0 | 539 | */ |
bf0153c1 | 540 | pnv_wakeup_tb_loss: |
97eb001f | 541 | ld r1,PACAR1(r13) |
7cba160a SP |
542 | /* |
543 | * Before entering any idle state, the NVGPRs are saved in the stack | |
544 | * and they are restored before switching to the process context. Hence | |
545 | * until they are restored, they are free to be used. | |
546 | * | |
17065671 | 547 | * Save SRR1 and LR in NVGPRs as they might be clobbered in |
69c592ed | 548 | * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required |
17065671 SP |
549 | * to determine the wakeup reason if we branch to kvm_start_guest. LR |
550 | * is required to return back to reset vector after hypervisor state | |
551 | * restore is complete. | |
7cba160a | 552 | */ |
17065671 | 553 | mflr r17 |
7cba160a | 554 | mfspr r16,SPRN_SRR1 |
bbdb760d MS |
555 | BEGIN_FTR_SECTION |
556 | CHECK_HMI_INTERRUPT | |
557 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
7cba160a | 558 | |
7cba160a | 559 | ld r14,PACA_CORE_IDLE_STATE_PTR(r13) |
e420249d NP |
560 | lbz r7,PACA_THREAD_MASK(r13) |
561 | ||
7cba160a | 562 | /* |
e420249d NP |
563 | * Take the core lock to synchronize against other threads. |
564 | * | |
7cba160a SP |
565 | * Lock bit is set in one of the 2 cases- |
566 | * a. In the sleep/winkle enter path, the last thread is executing | |
567 | * fastsleep workaround code. | |
568 | * b. In the wake up path, another thread is executing fastsleep | |
569 | * workaround undo code or resyncing timebase or restoring context | |
570 | * In either case loop until the lock bit is cleared. | |
571 | */ | |
e420249d NP |
572 | 1: |
573 | lwarx r15,0,r14 | |
574 | andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h | |
adbcf8d7 | 575 | bnel- core_idle_lock_held |
e420249d NP |
576 | oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h |
577 | stwcx. r15,0,r14 | |
578 | bne- 1b | |
579 | isync | |
7cba160a | 580 | |
adbcf8d7 NP |
581 | andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS |
582 | cmpwi cr2,r9,0 | |
77b54e9f SP |
583 | |
584 | /* | |
585 | * At this stage | |
bcef83a0 SP |
586 | * cr2 - eq if first thread to wakeup in core |
587 | * cr3- gt if waking up with partial/complete hypervisor state loss | |
bd00a240 | 588 | * cr4 - gt or eq if waking up from complete hypervisor state loss. |
77b54e9f SP |
589 | */ |
590 | ||
bcef83a0 SP |
591 | BEGIN_FTR_SECTION |
592 | lbz r4,PACA_SUBCORE_SIBLING_MASK(r13) | |
593 | and r4,r4,r15 | |
594 | cmpwi r4,0 /* Check if first in subcore */ | |
595 | ||
596 | or r15,r15,r7 /* Set thread bit */ | |
597 | beq first_thread_in_subcore | |
598 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) | |
599 | ||
600 | or r15,r15,r7 /* Set thread bit */ | |
601 | beq cr2,first_thread_in_core | |
602 | ||
603 | /* Not first thread in core or subcore to wake up */ | |
604 | b clear_lock | |
605 | ||
606 | first_thread_in_subcore: | |
77b54e9f SP |
607 | /* |
608 | * If waking up from sleep, subcore state is not lost. Hence | |
609 | * skip subcore state restore | |
610 | */ | |
bd00a240 | 611 | blt cr4,subcore_state_restored |
77b54e9f SP |
612 | |
613 | /* Restore per-subcore state */ | |
614 | ld r4,_SDR1(r1) | |
615 | mtspr SPRN_SDR1,r4 | |
bcef83a0 | 616 | |
77b54e9f SP |
617 | ld r4,_RPR(r1) |
618 | mtspr SPRN_RPR,r4 | |
619 | ld r4,_AMOR(r1) | |
620 | mtspr SPRN_AMOR,r4 | |
621 | ||
622 | subcore_state_restored: | |
623 | /* | |
624 | * Check if the thread is also the first thread in the core. If not, | |
625 | * skip to clear_lock. | |
626 | */ | |
627 | bne cr2,clear_lock | |
628 | ||
629 | first_thread_in_core: | |
630 | ||
7cba160a | 631 | /* |
bcef83a0 SP |
632 | * First thread in the core waking up from any state which can cause |
633 | * partial or complete hypervisor state loss. It needs to | |
7cba160a SP |
634 | * call the fastsleep workaround code if the platform requires it. |
635 | * Call it unconditionally here. The below branch instruction will | |
bcef83a0 SP |
636 | * be patched out if the platform does not have fastsleep or does not |
637 | * require the workaround. Patching will be performed during the | |
638 | * discovery of idle-states. | |
7cba160a SP |
639 | */ |
640 | .global pnv_fastsleep_workaround_at_exit | |
641 | pnv_fastsleep_workaround_at_exit: | |
642 | b fastsleep_workaround_at_exit | |
643 | ||
644 | timebase_resync: | |
bcef83a0 SP |
645 | /* |
646 | * Use cr3 which indicates that we are waking up with atleast partial | |
647 | * hypervisor state loss to determine if TIMEBASE RESYNC is needed. | |
648 | */ | |
7cba160a | 649 | ble cr3,clear_lock |
97eb001f | 650 | /* Time base re-sync */ |
ab9bad0e | 651 | bl opal_resync_timebase; |
77b54e9f SP |
652 | /* |
653 | * If waking up from sleep, per core state is not lost, skip to | |
654 | * clear_lock. | |
655 | */ | |
bd00a240 | 656 | blt cr4,clear_lock |
77b54e9f | 657 | |
bcef83a0 SP |
658 | /* |
659 | * First thread in the core to wake up and its waking up with | |
660 | * complete hypervisor state loss. Restore per core hypervisor | |
661 | * state. | |
662 | */ | |
663 | BEGIN_FTR_SECTION | |
664 | ld r4,_PTCR(r1) | |
665 | mtspr SPRN_PTCR,r4 | |
666 | ld r4,_RPR(r1) | |
667 | mtspr SPRN_RPR,r4 | |
668 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
669 | ||
77b54e9f SP |
670 | ld r4,_TSCR(r1) |
671 | mtspr SPRN_TSCR,r4 | |
672 | ld r4,_WORC(r1) | |
673 | mtspr SPRN_WORC,r4 | |
674 | ||
7cba160a | 675 | clear_lock: |
adbcf8d7 | 676 | xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h |
7cba160a SP |
677 | lwsync |
678 | stw r15,0(r14) | |
679 | ||
680 | common_exit: | |
77b54e9f SP |
681 | /* |
682 | * Common to all threads. | |
683 | * | |
684 | * If waking up from sleep, hypervisor state is not lost. Hence | |
685 | * skip hypervisor state restore. | |
686 | */ | |
bd00a240 | 687 | blt cr4,hypervisor_state_restored |
77b54e9f SP |
688 | |
689 | /* Waking up from winkle */ | |
690 | ||
bcef83a0 SP |
691 | BEGIN_MMU_FTR_SECTION |
692 | b no_segments | |
5a25b6f5 | 693 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX) |
77b54e9f SP |
694 | /* Restore SLB from PACA */ |
695 | ld r8,PACA_SLBSHADOWPTR(r13) | |
696 | ||
697 | .rept SLB_NUM_BOLTED | |
698 | li r3, SLBSHADOW_SAVEAREA | |
699 | LDX_BE r5, r8, r3 | |
700 | addi r3, r3, 8 | |
701 | LDX_BE r6, r8, r3 | |
702 | andis. r7,r5,SLB_ESID_V@h | |
703 | beq 1f | |
704 | slbmte r6,r5 | |
705 | 1: addi r8,r8,16 | |
706 | .endr | |
bcef83a0 SP |
707 | no_segments: |
708 | ||
709 | /* Restore per thread state */ | |
77b54e9f SP |
710 | |
711 | ld r4,_SPURR(r1) | |
712 | mtspr SPRN_SPURR,r4 | |
713 | ld r4,_PURR(r1) | |
714 | mtspr SPRN_PURR,r4 | |
715 | ld r4,_DSCR(r1) | |
716 | mtspr SPRN_DSCR,r4 | |
717 | ld r4,_WORT(r1) | |
718 | mtspr SPRN_WORT,r4 | |
719 | ||
bcef83a0 SP |
720 | /* Call cur_cpu_spec->cpu_restore() */ |
721 | LOAD_REG_ADDR(r4, cur_cpu_spec) | |
722 | ld r4,0(r4) | |
723 | ld r12,CPU_SPEC_RESTORE(r4) | |
724 | #ifdef PPC64_ELF_ABI_v1 | |
725 | ld r12,0(r12) | |
726 | #endif | |
727 | mtctr r12 | |
728 | bctrl | |
729 | ||
77b54e9f SP |
730 | hypervisor_state_restored: |
731 | ||
7cba160a | 732 | mtspr SPRN_SRR1,r16 |
17065671 | 733 | mtlr r17 |
bf0153c1 | 734 | blr /* return to pnv_powersave_wakeup */ |
97eb001f | 735 | |
7cba160a SP |
736 | fastsleep_workaround_at_exit: |
737 | li r3,1 | |
738 | li r4,0 | |
ab9bad0e | 739 | bl opal_config_cpu_idle_state |
7cba160a SP |
740 | b timebase_resync |
741 | ||
56548fc0 PM |
742 | /* |
743 | * R3 here contains the value that will be returned to the caller | |
744 | * of power7_nap. | |
745 | */ | |
bf0153c1 NP |
746 | .global pnv_wakeup_loss |
747 | pnv_wakeup_loss: | |
948cf67c | 748 | ld r1,PACAR1(r13) |
bbdb760d MS |
749 | BEGIN_FTR_SECTION |
750 | CHECK_HMI_INTERRUPT | |
751 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
948cf67c BH |
752 | REST_NVGPRS(r1) |
753 | REST_GPR(2, r1) | |
56548fc0 | 754 | ld r6,_CCR(r1) |
948cf67c BH |
755 | ld r4,_MSR(r1) |
756 | ld r5,_NIP(r1) | |
757 | addi r1,r1,INT_FRAME_SIZE | |
56548fc0 | 758 | mtcr r6 |
948cf67c BH |
759 | mtspr SPRN_SRR1,r4 |
760 | mtspr SPRN_SRR0,r5 | |
761 | rfid | |
762 | ||
56548fc0 PM |
763 | /* |
764 | * R3 here contains the value that will be returned to the caller | |
765 | * of power7_nap. | |
766 | */ | |
bf0153c1 | 767 | pnv_wakeup_noloss: |
2fde6d20 PM |
768 | lbz r0,PACA_NAPSTATELOST(r13) |
769 | cmpwi r0,0 | |
5fa6b6bd | 770 | bne pnv_wakeup_loss |
bbdb760d MS |
771 | BEGIN_FTR_SECTION |
772 | CHECK_HMI_INTERRUPT | |
773 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
948cf67c | 774 | ld r1,PACAR1(r13) |
0aab3747 | 775 | ld r6,_CCR(r1) |
948cf67c BH |
776 | ld r4,_MSR(r1) |
777 | ld r5,_NIP(r1) | |
778 | addi r1,r1,INT_FRAME_SIZE | |
0aab3747 | 779 | mtcr r6 |
948cf67c BH |
780 | mtspr SPRN_SRR1,r4 |
781 | mtspr SPRN_SRR0,r5 | |
782 | rfid |