Commit | Line | Data |
---|---|---|
948cf67c | 1 | /* |
bcef83a0 SP |
2 | * This file contains idle entry/exit functions for POWER7, |
3 | * POWER8 and POWER9 CPUs. | |
948cf67c BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | */ | |
10 | ||
11 | #include <linux/threads.h> | |
12 | #include <asm/processor.h> | |
13 | #include <asm/page.h> | |
14 | #include <asm/cputable.h> | |
15 | #include <asm/thread_info.h> | |
16 | #include <asm/ppc_asm.h> | |
17 | #include <asm/asm-offsets.h> | |
18 | #include <asm/ppc-opcode.h> | |
7230c564 | 19 | #include <asm/hw_irq.h> |
f0888f70 | 20 | #include <asm/kvm_book3s_asm.h> |
97eb001f | 21 | #include <asm/opal.h> |
7cba160a | 22 | #include <asm/cpuidle.h> |
bf0153c1 | 23 | #include <asm/exception-64s.h> |
f64e8084 | 24 | #include <asm/book3s/64/mmu-hash.h> |
bcef83a0 | 25 | #include <asm/mmu.h> |
ec0c464c | 26 | #include <asm/asm-compat.h> |
2c86cd18 | 27 | #include <asm/feature-fixups.h> |
948cf67c BH |
28 | |
29 | #undef DEBUG | |
30 | ||
77b54e9f SP |
31 | /* |
32 | * Use unused space in the interrupt stack to save and restore | |
33 | * registers for winkle support. | |
34 | */ | |
101dd590 | 35 | #define _MMCR0 GPR0 |
77b54e9f | 36 | #define _SDR1 GPR3 |
cb0be7ec | 37 | #define _PTCR GPR3 |
77b54e9f SP |
38 | #define _RPR GPR4 |
39 | #define _SPURR GPR5 | |
40 | #define _PURR GPR6 | |
41 | #define _TSCR GPR7 | |
42 | #define _DSCR GPR8 | |
43 | #define _AMOR GPR9 | |
44 | #define _WORT GPR10 | |
45 | #define _WORC GPR11 | |
cb0be7ec | 46 | #define _LPCR GPR12 |
bcef83a0 | 47 | |
09206b60 | 48 | #define PSSCR_EC_ESL_MASK_SHIFTED (PSSCR_EC | PSSCR_ESL) >> 16 |
77b54e9f | 49 | |
aca79d2b VS |
50 | .text |
51 | ||
0dfffb48 SP |
52 | /* |
53 | * Used by threads before entering deep idle states. Saves SPRs | |
54 | * in interrupt stack frame | |
55 | */ | |
56 | save_sprs_to_stack: | |
57 | /* | |
58 | * Note all register i.e per-core, per-subcore or per-thread is saved | |
59 | * here since any thread in the core might wake up first | |
60 | */ | |
bcef83a0 | 61 | BEGIN_FTR_SECTION |
bcef83a0 SP |
62 | /* |
63 | * Note - SDR1 is dropped in Power ISA v3. Hence not restoring | |
64 | * SDR1 here | |
65 | */ | |
cb0be7ec GS |
66 | mfspr r3,SPRN_PTCR |
67 | std r3,_PTCR(r1) | |
68 | mfspr r3,SPRN_LPCR | |
69 | std r3,_LPCR(r1) | |
bcef83a0 | 70 | FTR_SECTION_ELSE |
0dfffb48 SP |
71 | mfspr r3,SPRN_SDR1 |
72 | std r3,_SDR1(r1) | |
bcef83a0 | 73 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300) |
0dfffb48 SP |
74 | mfspr r3,SPRN_RPR |
75 | std r3,_RPR(r1) | |
76 | mfspr r3,SPRN_SPURR | |
77 | std r3,_SPURR(r1) | |
78 | mfspr r3,SPRN_PURR | |
79 | std r3,_PURR(r1) | |
80 | mfspr r3,SPRN_TSCR | |
81 | std r3,_TSCR(r1) | |
82 | mfspr r3,SPRN_DSCR | |
83 | std r3,_DSCR(r1) | |
84 | mfspr r3,SPRN_AMOR | |
85 | std r3,_AMOR(r1) | |
86 | mfspr r3,SPRN_WORT | |
87 | std r3,_WORT(r1) | |
88 | mfspr r3,SPRN_WORC | |
89 | std r3,_WORC(r1) | |
e1c1cfed GS |
90 | /* |
91 | * On POWER9, there are idle states such as stop4, invoked via cpuidle, | |
92 | * that lose hypervisor resources. In such cases, we need to save | |
93 | * additional SPRs before entering those idle states so that they can | |
94 | * be restored to their older values on wakeup from the idle state. | |
95 | * | |
96 | * On POWER8, the only such deep idle state is winkle which is used | |
97 | * only in the context of CPU-Hotplug, where these additional SPRs are | |
98 | * reinitiazed to a sane value. Hence there is no need to save/restore | |
99 | * these SPRs. | |
100 | */ | |
101 | BEGIN_FTR_SECTION | |
102 | blr | |
103 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) | |
104 | ||
105 | power9_save_additional_sprs: | |
106 | mfspr r3, SPRN_PID | |
107 | mfspr r4, SPRN_LDBAR | |
108 | std r3, STOP_PID(r13) | |
109 | std r4, STOP_LDBAR(r13) | |
0dfffb48 | 110 | |
e1c1cfed GS |
111 | mfspr r3, SPRN_FSCR |
112 | mfspr r4, SPRN_HFSCR | |
113 | std r3, STOP_FSCR(r13) | |
114 | std r4, STOP_HFSCR(r13) | |
115 | ||
116 | mfspr r3, SPRN_MMCRA | |
e3646330 | 117 | mfspr r4, SPRN_MMCR0 |
e1c1cfed | 118 | std r3, STOP_MMCRA(r13) |
e3646330 | 119 | std r4, _MMCR0(r1) |
e1c1cfed | 120 | |
e3646330 NP |
121 | mfspr r3, SPRN_MMCR1 |
122 | mfspr r4, SPRN_MMCR2 | |
123 | std r3, STOP_MMCR1(r13) | |
124 | std r4, STOP_MMCR2(r13) | |
e1c1cfed GS |
125 | blr |
126 | ||
127 | power9_restore_additional_sprs: | |
128 | ld r3,_LPCR(r1) | |
129 | ld r4, STOP_PID(r13) | |
130 | mtspr SPRN_LPCR,r3 | |
131 | mtspr SPRN_PID, r4 | |
132 | ||
133 | ld r3, STOP_LDBAR(r13) | |
134 | ld r4, STOP_FSCR(r13) | |
135 | mtspr SPRN_LDBAR, r3 | |
136 | mtspr SPRN_FSCR, r4 | |
137 | ||
138 | ld r3, STOP_HFSCR(r13) | |
139 | ld r4, STOP_MMCRA(r13) | |
140 | mtspr SPRN_HFSCR, r3 | |
141 | mtspr SPRN_MMCRA, r4 | |
e3646330 NP |
142 | |
143 | ld r3, _MMCR0(r1) | |
144 | ld r4, STOP_MMCR1(r13) | |
145 | mtspr SPRN_MMCR0, r3 | |
146 | mtspr SPRN_MMCR1, r4 | |
147 | ||
148 | ld r3, STOP_MMCR2(r13) | |
b03897cf | 149 | ld r4, PACA_SPRG_VDSO(r13) |
e3646330 | 150 | mtspr SPRN_MMCR2, r3 |
b03897cf | 151 | mtspr SPRN_SPRG3, r4 |
0dfffb48 SP |
152 | blr |
153 | ||
b32aadc1 SP |
154 | /* |
155 | * Used by threads when the lock bit of core_idle_state is set. | |
156 | * Threads will spin in HMT_LOW until the lock bit is cleared. | |
157 | * r14 - pointer to core_idle_state | |
158 | * r15 - used to load contents of core_idle_state | |
09b7e37b | 159 | * r9 - used as a temporary variable |
b32aadc1 SP |
160 | */ |
161 | ||
162 | core_idle_lock_held: | |
163 | HMT_LOW | |
164 | 3: lwz r15,0(r14) | |
adbcf8d7 | 165 | andis. r15,r15,PNV_CORE_IDLE_LOCK_BIT@h |
b32aadc1 SP |
166 | bne 3b |
167 | HMT_MEDIUM | |
168 | lwarx r15,0,r14 | |
adbcf8d7 NP |
169 | andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h |
170 | bne- core_idle_lock_held | |
b32aadc1 SP |
171 | blr |
172 | ||
a3f3072d RC |
173 | /* Reuse an unused pt_regs slot for IAMR */ |
174 | #define PNV_POWERSAVE_IAMR _DAR | |
175 | ||
aca79d2b VS |
176 | /* |
177 | * Pass requested state in r3: | |
bcef83a0 | 178 | * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8 |
2201f994 | 179 | * - Requested PSSCR value in POWER9 |
8d6f7c5a | 180 | * |
9d292501 | 181 | * Address of idle handler to branch to in realmode in r4 |
aca79d2b | 182 | */ |
bf0153c1 | 183 | pnv_powersave_common: |
aca79d2b | 184 | /* Use r3 to pass state nap/sleep/winkle */ |
948cf67c BH |
185 | /* NAP is a state loss, we create a regs frame on the |
186 | * stack, fill it up with the state we care about and | |
187 | * stick a pointer to it in PACAR1. We really only | |
188 | * need to save PC, some CR bits and the NV GPRs, | |
189 | * but for now an interrupt frame will do. | |
190 | */ | |
9d292501 NP |
191 | mtctr r4 |
192 | ||
948cf67c BH |
193 | mflr r0 |
194 | std r0,16(r1) | |
195 | stdu r1,-INT_FRAME_SIZE(r1) | |
196 | std r0,_LINK(r1) | |
197 | std r0,_NIP(r1) | |
198 | ||
7230c564 | 199 | /* We haven't lost state ... yet */ |
948cf67c | 200 | li r0,0 |
2fde6d20 | 201 | stb r0,PACA_NAPSTATELOST(r13) |
948cf67c BH |
202 | |
203 | /* Continue saving state */ | |
204 | SAVE_GPR(2, r1) | |
205 | SAVE_NVGPRS(r1) | |
a3f3072d RC |
206 | |
207 | BEGIN_FTR_SECTION | |
208 | mfspr r5, SPRN_IAMR | |
209 | std r5, PNV_POWERSAVE_IAMR(r1) | |
210 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
211 | ||
2201f994 NP |
212 | mfcr r5 |
213 | std r5,_CCR(r1) | |
948cf67c BH |
214 | std r1,PACAR1(r13) |
215 | ||
72b0d51d NP |
216 | BEGIN_FTR_SECTION |
217 | /* | |
218 | * POWER9 does not require real mode to stop, and presently does not | |
219 | * set hwthread_state for KVM (threads don't share MMU context), so | |
220 | * we can remain in virtual mode for this. | |
221 | */ | |
222 | bctr | |
223 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
8117ac6a | 224 | /* |
72b0d51d | 225 | * POWER8 |
8117ac6a PM |
226 | * Go to real mode to do the nap, as required by the architecture. |
227 | * Also, we need to be in real mode before setting hwthread_state, | |
228 | * because as soon as we do that, another thread can switch | |
229 | * the MMU context to the guest. | |
230 | */ | |
4eae2c9a | 231 | LOAD_REG_IMMEDIATE(r7, MSR_IDLE) |
9d292501 NP |
232 | mtmsrd r7,0 |
233 | bctr | |
8117ac6a | 234 | |
aafc8a83 NP |
235 | /* |
236 | * This is the sequence required to execute idle instructions, as | |
237 | * specified in ISA v2.07 (and earlier). MSR[IR] and MSR[DR] must be 0. | |
238 | */ | |
65dbbe81 | 239 | #define IDLE_STATE_ENTER_SEQ_NORET(IDLE_INST) \ |
aafc8a83 NP |
240 | /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \ |
241 | std r0,0(r1); \ | |
242 | ptesync; \ | |
243 | ld r0,0(r1); \ | |
244 | 236: cmpd cr0,r0,r0; \ | |
245 | bne 236b; \ | |
246 | IDLE_INST; | |
247 | ||
aafc8a83 | 248 | |
5fa6b6bd SP |
249 | .globl pnv_enter_arch207_idle_mode |
250 | pnv_enter_arch207_idle_mode: | |
56c46222 PM |
251 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
252 | /* Tell KVM we're entering idle */ | |
253 | li r4,KVM_HWTHREAD_IN_IDLE | |
254 | /******************************************************/ | |
255 | /* N O T E W E L L ! ! ! N O T E W E L L */ | |
256 | /* The following store to HSTATE_HWTHREAD_STATE(r13) */ | |
257 | /* MUST occur in real mode, i.e. with the MMU off, */ | |
258 | /* and the MMU must stay off until we clear this flag */ | |
bf0153c1 NP |
259 | /* and test HSTATE_HWTHREAD_REQ(r13) in */ |
260 | /* pnv_powersave_wakeup in this file. */ | |
56c46222 PM |
261 | /* The reason is that another thread can switch the */ |
262 | /* MMU to a guest context whenever this flag is set */ | |
263 | /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */ | |
264 | /* that would potentially cause this thread to start */ | |
265 | /* executing instructions from guest memory in */ | |
266 | /* hypervisor mode, leading to a host crash or data */ | |
267 | /* corruption, or worse. */ | |
268 | /******************************************************/ | |
269 | stb r4,HSTATE_HWTHREAD_STATE(r13) | |
270 | #endif | |
7cba160a | 271 | stb r3,PACA_THREAD_IDLE_STATE(r13) |
77b54e9f SP |
272 | cmpwi cr3,r3,PNV_THREAD_SLEEP |
273 | bge cr3,2f | |
823b7bd5 | 274 | IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP) |
aca79d2b | 275 | /* No return */ |
7cba160a SP |
276 | 2: |
277 | /* Sleep or winkle */ | |
278 | lbz r7,PACA_THREAD_MASK(r13) | |
279 | ld r14,PACA_CORE_IDLE_STATE_PTR(r13) | |
0d7720a2 NP |
280 | li r5,0 |
281 | beq cr3,3f | |
282 | lis r5,PNV_CORE_IDLE_WINKLE_COUNT@h | |
283 | 3: | |
7cba160a SP |
284 | lwarx_loop1: |
285 | lwarx r15,0,r14 | |
b32aadc1 | 286 | |
adbcf8d7 NP |
287 | andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h |
288 | bnel- core_idle_lock_held | |
b32aadc1 | 289 | |
0d7720a2 | 290 | add r15,r15,r5 /* Add if winkle */ |
7cba160a SP |
291 | andc r15,r15,r7 /* Clear thread bit */ |
292 | ||
0d7720a2 | 293 | andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS |
7cba160a SP |
294 | |
295 | /* | |
296 | * If cr0 = 0, then current thread is the last thread of the core entering | |
297 | * sleep. Last thread needs to execute the hardware bug workaround code if | |
298 | * required by the platform. | |
299 | * Make the workaround call unconditionally here. The below branch call is | |
300 | * patched out when the idle states are discovered if the platform does not | |
301 | * require it. | |
302 | */ | |
303 | .global pnv_fastsleep_workaround_at_entry | |
304 | pnv_fastsleep_workaround_at_entry: | |
305 | beq fastsleep_workaround_at_entry | |
306 | ||
307 | stwcx. r15,0,r14 | |
308 | bne- lwarx_loop1 | |
309 | isync | |
310 | ||
77b54e9f SP |
311 | common_enter: /* common code for all the threads entering sleep or winkle */ |
312 | bgt cr3,enter_winkle | |
823b7bd5 | 313 | IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP) |
7cba160a SP |
314 | |
315 | fastsleep_workaround_at_entry: | |
adbcf8d7 | 316 | oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h |
7cba160a SP |
317 | stwcx. r15,0,r14 |
318 | bne- lwarx_loop1 | |
319 | isync | |
320 | ||
321 | /* Fast sleep workaround */ | |
322 | li r3,1 | |
323 | li r4,1 | |
ab9bad0e | 324 | bl opal_config_cpu_idle_state |
7cba160a | 325 | |
adbcf8d7 NP |
326 | /* Unlock */ |
327 | xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h | |
7cba160a | 328 | lwsync |
adbcf8d7 | 329 | stw r15,0(r14) |
7cba160a SP |
330 | b common_enter |
331 | ||
77b54e9f | 332 | enter_winkle: |
0dfffb48 SP |
333 | bl save_sprs_to_stack |
334 | ||
823b7bd5 | 335 | IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE) |
f0888f70 | 336 | |
bcef83a0 | 337 | /* |
09206b60 | 338 | * r3 - PSSCR value corresponding to the requested stop state. |
bcef83a0 | 339 | */ |
a67cc594 ME |
340 | power_enter_stop: |
341 | /* | |
342 | * Check if we are executing the lite variant with ESL=EC=0 | |
343 | */ | |
344 | andis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED | |
09206b60 | 345 | clrldi r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */ |
a67cc594 ME |
346 | bne .Lhandle_esl_ec_set |
347 | PPC_STOP | |
348 | li r3,0 /* Since we didn't lose state, return 0 */ | |
349 | std r3, PACA_REQ_PSSCR(r13) | |
350 | ||
351 | /* | |
352 | * pnv_wakeup_noloss() expects r12 to contain the SRR1 value so | |
353 | * it can determine if the wakeup reason is an HMI in | |
354 | * CHECK_HMI_INTERRUPT. | |
355 | * | |
356 | * However, when we wakeup with ESL=0, SRR1 will not contain the wakeup | |
357 | * reason, so there is no point setting r12 to SRR1. | |
358 | * | |
359 | * Further, we clear r12 here, so that we don't accidentally enter the | |
360 | * HMI in pnv_wakeup_noloss() if the value of r12[42:45] == WAKE_HMI. | |
361 | */ | |
362 | li r12, 0 | |
363 | b pnv_wakeup_noloss | |
364 | ||
365 | .Lhandle_esl_ec_set: | |
e3646330 | 366 | BEGIN_FTR_SECTION |
101dd590 | 367 | /* |
3ffa9d9e ME |
368 | * POWER9 DD2.0 or earlier can incorrectly set PMAO when waking up after |
369 | * a state-loss idle. Saving and restoring MMCR0 over idle is a | |
101dd590 NP |
370 | * workaround. |
371 | */ | |
372 | mfspr r4,SPRN_MMCR0 | |
373 | std r4,_MMCR0(r1) | |
3ffa9d9e | 374 | END_FTR_SECTION_IFCLR(CPU_FTR_POWER9_DD2_1) |
101dd590 | 375 | |
bcef83a0 SP |
376 | /* |
377 | * Check if the requested state is a deep idle state. | |
378 | */ | |
424f8acd | 379 | LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state) |
bcef83a0 SP |
380 | ld r4,ADDROFF(pnv_first_deep_stop_state)(r5) |
381 | cmpd r3,r4 | |
424f8acd | 382 | bge .Lhandle_deep_stop |
56ee5240 NP |
383 | PPC_STOP /* Does not return (system reset interrupt) */ |
384 | ||
424f8acd | 385 | .Lhandle_deep_stop: |
bcef83a0 SP |
386 | /* |
387 | * Entering deep idle state. | |
388 | * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to | |
389 | * stack and enter stop | |
390 | */ | |
391 | lbz r7,PACA_THREAD_MASK(r13) | |
392 | ld r14,PACA_CORE_IDLE_STATE_PTR(r13) | |
393 | ||
394 | lwarx_loop_stop: | |
395 | lwarx r15,0,r14 | |
adbcf8d7 NP |
396 | andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h |
397 | bnel- core_idle_lock_held | |
bcef83a0 SP |
398 | andc r15,r15,r7 /* Clear thread bit */ |
399 | ||
400 | stwcx. r15,0,r14 | |
401 | bne- lwarx_loop_stop | |
402 | isync | |
403 | ||
404 | bl save_sprs_to_stack | |
405 | ||
56ee5240 | 406 | PPC_STOP /* Does not return (system reset interrupt) */ |
bcef83a0 | 407 | |
2201f994 NP |
408 | /* |
409 | * Entered with MSR[EE]=0 and no soft-masked interrupts pending. | |
410 | * r3 contains desired idle state (PNV_THREAD_NAP/SLEEP/WINKLE). | |
411 | */ | |
412 | _GLOBAL(power7_idle_insn) | |
aca79d2b | 413 | /* Now check if user or arch enabled NAP mode */ |
2201f994 | 414 | LOAD_REG_ADDR(r4, pnv_enter_arch207_idle_mode) |
5fa6b6bd | 415 | b pnv_powersave_common |
77b54e9f | 416 | |
bbdb760d | 417 | #define CHECK_HMI_INTERRUPT \ |
bbdb760d | 418 | BEGIN_FTR_SECTION_NESTED(66); \ |
9d292501 | 419 | rlwinm r0,r12,45-31,0xf; /* extract wake reason field (P8) */ \ |
bbdb760d | 420 | FTR_SECTION_ELSE_NESTED(66); \ |
9d292501 | 421 | rlwinm r0,r12,45-31,0xe; /* P7 wake reason field is 3 bits */ \ |
bbdb760d MS |
422 | ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \ |
423 | cmpwi r0,0xa; /* Hypervisor maintenance ? */ \ | |
95acdc07 | 424 | bne+ 20f; \ |
bbdb760d MS |
425 | /* Invoke opal call to handle hmi */ \ |
426 | ld r2,PACATOC(r13); \ | |
427 | ld r1,PACAR1(r13); \ | |
428 | std r3,ORIG_GPR3(r1); /* Save original r3 */ \ | |
fd7bacbc MS |
429 | li r3,0; /* NULL argument */ \ |
430 | bl hmi_exception_realmode; \ | |
431 | nop; \ | |
bbdb760d MS |
432 | ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \ |
433 | 20: nop; | |
434 | ||
3d4fbffd NP |
435 | /* |
436 | * Entered with MSR[EE]=0 and no soft-masked interrupts pending. | |
437 | * r3 contains desired PSSCR register value. | |
d0b791c0 ME |
438 | * |
439 | * Offline (CPU unplug) case also must notify KVM that the CPU is | |
440 | * idle. | |
3d4fbffd NP |
441 | */ |
442 | _GLOBAL(power9_offline_stop) | |
3d4fbffd | 443 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
d0b791c0 ME |
444 | /* |
445 | * Tell KVM we're entering idle. | |
446 | * This does not have to be done in real mode because the P9 MMU | |
447 | * is independent per-thread. Some steppings share radix/hash mode | |
448 | * between threads, but in that case KVM has a barrier sync in real | |
449 | * mode before and after switching between radix and hash. | |
450 | */ | |
3d4fbffd | 451 | li r4,KVM_HWTHREAD_IN_IDLE |
3d4fbffd NP |
452 | stb r4,HSTATE_HWTHREAD_STATE(r13) |
453 | #endif | |
d0b791c0 | 454 | /* fall through */ |
3d4fbffd | 455 | |
bcef83a0 | 456 | _GLOBAL(power9_idle_stop) |
22c6663d | 457 | std r3, PACA_REQ_PSSCR(r13) |
a2b5e056 NP |
458 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
459 | BEGIN_FTR_SECTION | |
7672691a PM |
460 | sync |
461 | lwz r5, PACA_DONT_STOP(r13) | |
462 | cmpwi r5, 0 | |
a67cc594 | 463 | bne 1f |
7672691a | 464 | END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG) |
a2b5e056 | 465 | #endif |
a67cc594 ME |
466 | mtspr SPRN_PSSCR,r3 |
467 | LOAD_REG_ADDR(r4,power_enter_stop) | |
bcef83a0 SP |
468 | b pnv_powersave_common |
469 | /* No return */ | |
a2b5e056 | 470 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
a67cc594 | 471 | 1: |
7672691a PM |
472 | /* |
473 | * We get here when TM / thread reconfiguration bug workaround | |
474 | * code wants to get the CPU into SMT4 mode, and therefore | |
475 | * we are being asked not to stop. | |
476 | */ | |
477 | li r3, 0 | |
478 | std r3, PACA_REQ_PSSCR(r13) | |
479 | blr /* return 0 for wakeup cause / SRR1 value */ | |
a2b5e056 | 480 | #endif |
17ed4c8f | 481 | |
1945bc45 NP |
482 | /* |
483 | * Called from machine check handler for powersave wakeups. | |
484 | * Low level machine check processing has already been done. Now just | |
485 | * go through the wake up path to get everything in order. | |
486 | * | |
487 | * r3 - The original SRR1 value. | |
488 | * Original SRR[01] have been clobbered. | |
489 | * MSR_RI is clear. | |
490 | */ | |
491 | .global pnv_powersave_wakeup_mce | |
492 | pnv_powersave_wakeup_mce: | |
493 | /* Set cr3 for pnv_powersave_wakeup */ | |
494 | rlwinm r11,r3,47-31,30,31 | |
495 | cmpwi cr3,r11,2 | |
496 | ||
497 | /* | |
498 | * Now put the original SRR1 with SRR1_WAKEMCE_RESVD as the wake | |
9d292501 | 499 | * reason into r12, which allows reuse of the system reset wakeup |
1945bc45 NP |
500 | * code without being mistaken for another type of wakeup. |
501 | */ | |
9d292501 | 502 | oris r12,r3,SRR1_WAKEMCE_RESVD@h |
1945bc45 NP |
503 | |
504 | b pnv_powersave_wakeup | |
505 | ||
544686ca NP |
506 | /* |
507 | * Called from reset vector for powersave wakeups. | |
17065671 | 508 | * cr3 - set to gt if waking up with partial/complete hypervisor state loss |
9d292501 | 509 | * r12 - SRR1 |
17065671 | 510 | */ |
bf0153c1 NP |
511 | .global pnv_powersave_wakeup |
512 | pnv_powersave_wakeup: | |
9cba253d NP |
513 | ld r2, PACATOC(r13) |
514 | ||
bcef83a0 | 515 | BEGIN_FTR_SECTION |
10101aa9 NP |
516 | bl pnv_restore_hyp_resource_arch300 |
517 | FTR_SECTION_ELSE | |
518 | bl pnv_restore_hyp_resource_arch207 | |
519 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300) | |
bf0153c1 NP |
520 | |
521 | li r0,PNV_THREAD_RUNNING | |
522 | stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */ | |
523 | ||
9d292501 NP |
524 | mr r3,r12 |
525 | ||
bf0153c1 | 526 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
8c1c7fb0 NP |
527 | lbz r0,HSTATE_HWTHREAD_STATE(r13) |
528 | cmpwi r0,KVM_HWTHREAD_IN_KERNEL | |
56376c58 | 529 | beq 0f |
31a4d448 PM |
530 | li r0,KVM_HWTHREAD_IN_KERNEL |
531 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
532 | /* Order setting hwthread_state vs. testing hwthread_req */ | |
533 | sync | |
56376c58 | 534 | 0: lbz r0,HSTATE_HWTHREAD_REQ(r13) |
31a4d448 PM |
535 | cmpwi r0,0 |
536 | beq 1f | |
537 | b kvm_start_guest | |
538 | 1: | |
bf0153c1 NP |
539 | #endif |
540 | ||
541 | /* Return SRR1 from power7_nap() */ | |
bf0153c1 NP |
542 | blt cr3,pnv_wakeup_noloss |
543 | b pnv_wakeup_loss | |
544 | ||
17065671 | 545 | /* |
bf0153c1 NP |
546 | * Check whether we have woken up with hypervisor state loss. |
547 | * If yes, restore hypervisor state and return back to link. | |
17065671 | 548 | * |
17065671 SP |
549 | * cr3 - set to gt if waking up with partial/complete hypervisor state loss |
550 | */ | |
10101aa9 | 551 | pnv_restore_hyp_resource_arch300: |
ba6d334a BH |
552 | /* |
553 | * Workaround for POWER9, if we lost resources, the ERAT | |
101dd590 | 554 | * might have been mixed up and needs flushing. We also need |
09539f9b NP |
555 | * to reload MMCR0 (see comment above). We also need to set |
556 | * then clear bit 60 in MMCRA to ensure the PMU starts running. | |
ba6d334a BH |
557 | */ |
558 | blt cr3,1f | |
9d2f510a | 559 | BEGIN_FTR_SECTION |
ba6d334a | 560 | PPC_INVALIDATE_ERAT |
101dd590 | 561 | ld r1,PACAR1(r13) |
e3646330 NP |
562 | ld r4,_MMCR0(r1) |
563 | mtspr SPRN_MMCR0,r4 | |
3ffa9d9e | 564 | END_FTR_SECTION_IFCLR(CPU_FTR_POWER9_DD2_1) |
09539f9b NP |
565 | mfspr r4,SPRN_MMCRA |
566 | ori r4,r4,(1 << (63-60)) | |
567 | mtspr SPRN_MMCRA,r4 | |
568 | xori r4,r4,(1 << (63-60)) | |
569 | mtspr SPRN_MMCRA,r4 | |
ba6d334a | 570 | 1: |
bcef83a0 SP |
571 | /* |
572 | * POWER ISA 3. Use PSSCR to determine if we | |
573 | * are waking up from deep idle state | |
574 | */ | |
575 | LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state) | |
576 | ld r4,ADDROFF(pnv_first_deep_stop_state)(r5) | |
577 | ||
17065671 | 578 | /* |
bcef83a0 SP |
579 | * 0-3 bits correspond to Power-Saving Level Status |
580 | * which indicates the idle state we are waking up from | |
581 | */ | |
22c6663d | 582 | mfspr r5, SPRN_PSSCR |
bcef83a0 | 583 | rldicl r5,r5,4,60 |
7672691a PM |
584 | li r0, 0 /* clear requested_psscr to say we're awake */ |
585 | std r0, PACA_REQ_PSSCR(r13) | |
bcef83a0 | 586 | cmpd cr4,r5,r4 |
bf0153c1 | 587 | bge cr4,pnv_wakeup_tb_loss /* returns to caller */ |
bcef83a0 | 588 | |
bf0153c1 | 589 | blr /* Waking up without hypervisor state loss. */ |
bcef83a0 | 590 | |
10101aa9 NP |
591 | /* Same calling convention as arch300 */ |
592 | pnv_restore_hyp_resource_arch207: | |
bcef83a0 SP |
593 | /* |
594 | * POWER ISA 2.07 or less. | |
0d7720a2 | 595 | * Check if we slept with sleep or winkle. |
17065671 | 596 | */ |
0d7720a2 NP |
597 | lbz r4,PACA_THREAD_IDLE_STATE(r13) |
598 | cmpwi cr2,r4,PNV_THREAD_NAP | |
599 | bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */ | |
17065671 SP |
600 | |
601 | /* | |
602 | * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking | |
603 | * up from nap. At this stage CR3 shouldn't contains 'gt' since that | |
604 | * indicates we are waking with hypervisor state loss from nap. | |
605 | */ | |
606 | bgt cr3,. | |
607 | ||
bf0153c1 | 608 | blr /* Waking up without hypervisor state loss */ |
17065671 | 609 | |
bcef83a0 SP |
610 | /* |
611 | * Called if waking up from idle state which can cause either partial or | |
612 | * complete hyp state loss. | |
613 | * In POWER8, called if waking up from fastsleep or winkle | |
614 | * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state | |
615 | * | |
616 | * r13 - PACA | |
617 | * cr3 - gt if waking up with partial/complete hypervisor state loss | |
0d7720a2 NP |
618 | * |
619 | * If ISA300: | |
bd00a240 | 620 | * cr4 - gt or eq if waking up from complete hypervisor state loss. |
0d7720a2 NP |
621 | * |
622 | * If ISA207: | |
623 | * r4 - PACA_THREAD_IDLE_STATE | |
bcef83a0 | 624 | */ |
bf0153c1 | 625 | pnv_wakeup_tb_loss: |
97eb001f | 626 | ld r1,PACAR1(r13) |
7cba160a | 627 | /* |
6d98ce0b NP |
628 | * Before entering any idle state, the NVGPRs are saved in the stack. |
629 | * If there was a state loss, or PACA_NAPSTATELOST was set, then the | |
630 | * NVGPRs are restored. If we are here, it is likely that state is lost, | |
631 | * but not guaranteed -- neither ISA207 nor ISA300 tests to reach | |
632 | * here are the same as the test to restore NVGPRS: | |
633 | * PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300, | |
634 | * and SRR1 test for restoring NVGPRs. | |
635 | * | |
636 | * We are about to clobber NVGPRs now, so set NAPSTATELOST to | |
637 | * guarantee they will always be restored. This might be tightened | |
638 | * with careful reading of specs (particularly for ISA300) but this | |
639 | * is already a slow wakeup path and it's simpler to be safe. | |
640 | */ | |
641 | li r0,1 | |
642 | stb r0,PACA_NAPSTATELOST(r13) | |
643 | ||
644 | /* | |
7cba160a | 645 | * |
17065671 | 646 | * Save SRR1 and LR in NVGPRs as they might be clobbered in |
69c592ed | 647 | * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required |
17065671 SP |
648 | * to determine the wakeup reason if we branch to kvm_start_guest. LR |
649 | * is required to return back to reset vector after hypervisor state | |
650 | * restore is complete. | |
7cba160a | 651 | */ |
9d292501 | 652 | mr r19,r12 |
0d7720a2 | 653 | mr r18,r4 |
17065671 | 654 | mflr r17 |
bbdb760d MS |
655 | BEGIN_FTR_SECTION |
656 | CHECK_HMI_INTERRUPT | |
657 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
7cba160a | 658 | |
7cba160a | 659 | ld r14,PACA_CORE_IDLE_STATE_PTR(r13) |
e420249d NP |
660 | lbz r7,PACA_THREAD_MASK(r13) |
661 | ||
7cba160a | 662 | /* |
e420249d NP |
663 | * Take the core lock to synchronize against other threads. |
664 | * | |
7cba160a SP |
665 | * Lock bit is set in one of the 2 cases- |
666 | * a. In the sleep/winkle enter path, the last thread is executing | |
667 | * fastsleep workaround code. | |
668 | * b. In the wake up path, another thread is executing fastsleep | |
669 | * workaround undo code or resyncing timebase or restoring context | |
670 | * In either case loop until the lock bit is cleared. | |
671 | */ | |
e420249d NP |
672 | 1: |
673 | lwarx r15,0,r14 | |
674 | andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h | |
adbcf8d7 | 675 | bnel- core_idle_lock_held |
e420249d NP |
676 | oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h |
677 | stwcx. r15,0,r14 | |
678 | bne- 1b | |
679 | isync | |
7cba160a | 680 | |
adbcf8d7 NP |
681 | andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS |
682 | cmpwi cr2,r9,0 | |
77b54e9f SP |
683 | |
684 | /* | |
685 | * At this stage | |
bcef83a0 SP |
686 | * cr2 - eq if first thread to wakeup in core |
687 | * cr3- gt if waking up with partial/complete hypervisor state loss | |
0d7720a2 | 688 | * ISA300: |
bd00a240 | 689 | * cr4 - gt or eq if waking up from complete hypervisor state loss. |
77b54e9f SP |
690 | */ |
691 | ||
bcef83a0 | 692 | BEGIN_FTR_SECTION |
0d7720a2 NP |
693 | /* |
694 | * Were we in winkle? | |
695 | * If yes, check if all threads were in winkle, decrement our | |
696 | * winkle count, set all thread winkle bits if all were in winkle. | |
697 | * Check if our thread has a winkle bit set, and set cr4 accordingly | |
698 | * (to match ISA300, above). Pseudo-code for core idle state | |
699 | * transitions for ISA207 is as follows (everything happens atomically | |
700 | * due to store conditional and/or lock bit): | |
701 | * | |
702 | * nap_idle() { } | |
703 | * nap_wake() { } | |
704 | * | |
705 | * sleep_idle() | |
706 | * { | |
707 | * core_idle_state &= ~thread_in_core | |
708 | * } | |
709 | * | |
710 | * sleep_wake() | |
711 | * { | |
712 | * bool first_in_core, first_in_subcore; | |
713 | * | |
714 | * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0; | |
715 | * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0; | |
716 | * | |
717 | * core_idle_state |= thread_in_core; | |
718 | * } | |
719 | * | |
720 | * winkle_idle() | |
721 | * { | |
722 | * core_idle_state &= ~thread_in_core; | |
723 | * core_idle_state += 1 << WINKLE_COUNT_SHIFT; | |
724 | * } | |
725 | * | |
726 | * winkle_wake() | |
727 | * { | |
728 | * bool first_in_core, first_in_subcore, winkle_state_lost; | |
729 | * | |
730 | * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0; | |
731 | * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0; | |
732 | * | |
733 | * core_idle_state |= thread_in_core; | |
734 | * | |
735 | * if ((core_idle_state & WINKLE_MASK) == (8 << WINKLE_COUNT_SIHFT)) | |
736 | * core_idle_state |= THREAD_WINKLE_BITS; | |
737 | * core_idle_state -= 1 << WINKLE_COUNT_SHIFT; | |
738 | * | |
739 | * winkle_state_lost = core_idle_state & | |
740 | * (thread_in_core << WINKLE_THREAD_SHIFT); | |
741 | * core_idle_state &= ~(thread_in_core << WINKLE_THREAD_SHIFT); | |
742 | * } | |
743 | * | |
744 | */ | |
745 | cmpwi r18,PNV_THREAD_WINKLE | |
746 | bne 2f | |
747 | andis. r9,r15,PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT@h | |
748 | subis r15,r15,PNV_CORE_IDLE_WINKLE_COUNT@h | |
749 | beq 2f | |
750 | ori r15,r15,PNV_CORE_IDLE_THREAD_WINKLE_BITS /* all were winkle */ | |
751 | 2: | |
752 | /* Shift thread bit to winkle mask, then test if this thread is set, | |
753 | * and remove it from the winkle bits */ | |
754 | slwi r8,r7,8 | |
755 | and r8,r8,r15 | |
756 | andc r15,r15,r8 | |
757 | cmpwi cr4,r8,1 /* cr4 will be gt if our bit is set, lt if not */ | |
758 | ||
bcef83a0 SP |
759 | lbz r4,PACA_SUBCORE_SIBLING_MASK(r13) |
760 | and r4,r4,r15 | |
761 | cmpwi r4,0 /* Check if first in subcore */ | |
762 | ||
763 | or r15,r15,r7 /* Set thread bit */ | |
764 | beq first_thread_in_subcore | |
765 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) | |
766 | ||
767 | or r15,r15,r7 /* Set thread bit */ | |
768 | beq cr2,first_thread_in_core | |
769 | ||
770 | /* Not first thread in core or subcore to wake up */ | |
771 | b clear_lock | |
772 | ||
773 | first_thread_in_subcore: | |
77b54e9f SP |
774 | /* |
775 | * If waking up from sleep, subcore state is not lost. Hence | |
776 | * skip subcore state restore | |
777 | */ | |
bd00a240 | 778 | blt cr4,subcore_state_restored |
77b54e9f SP |
779 | |
780 | /* Restore per-subcore state */ | |
781 | ld r4,_SDR1(r1) | |
782 | mtspr SPRN_SDR1,r4 | |
bcef83a0 | 783 | |
77b54e9f SP |
784 | ld r4,_RPR(r1) |
785 | mtspr SPRN_RPR,r4 | |
786 | ld r4,_AMOR(r1) | |
787 | mtspr SPRN_AMOR,r4 | |
788 | ||
789 | subcore_state_restored: | |
790 | /* | |
791 | * Check if the thread is also the first thread in the core. If not, | |
792 | * skip to clear_lock. | |
793 | */ | |
794 | bne cr2,clear_lock | |
795 | ||
796 | first_thread_in_core: | |
797 | ||
7cba160a | 798 | /* |
bcef83a0 SP |
799 | * First thread in the core waking up from any state which can cause |
800 | * partial or complete hypervisor state loss. It needs to | |
7cba160a SP |
801 | * call the fastsleep workaround code if the platform requires it. |
802 | * Call it unconditionally here. The below branch instruction will | |
bcef83a0 SP |
803 | * be patched out if the platform does not have fastsleep or does not |
804 | * require the workaround. Patching will be performed during the | |
805 | * discovery of idle-states. | |
7cba160a SP |
806 | */ |
807 | .global pnv_fastsleep_workaround_at_exit | |
808 | pnv_fastsleep_workaround_at_exit: | |
809 | b fastsleep_workaround_at_exit | |
810 | ||
811 | timebase_resync: | |
bcef83a0 SP |
812 | /* |
813 | * Use cr3 which indicates that we are waking up with atleast partial | |
814 | * hypervisor state loss to determine if TIMEBASE RESYNC is needed. | |
815 | */ | |
ec486735 | 816 | ble cr3,.Ltb_resynced |
97eb001f | 817 | /* Time base re-sync */ |
ab9bad0e | 818 | bl opal_resync_timebase; |
77b54e9f | 819 | /* |
ec486735 GS |
820 | * If waking up from sleep (POWER8), per core state |
821 | * is not lost, skip to clear_lock. | |
77b54e9f | 822 | */ |
ec486735 | 823 | .Ltb_resynced: |
bd00a240 | 824 | blt cr4,clear_lock |
77b54e9f | 825 | |
bcef83a0 SP |
826 | /* |
827 | * First thread in the core to wake up and its waking up with | |
828 | * complete hypervisor state loss. Restore per core hypervisor | |
829 | * state. | |
830 | */ | |
831 | BEGIN_FTR_SECTION | |
832 | ld r4,_PTCR(r1) | |
833 | mtspr SPRN_PTCR,r4 | |
834 | ld r4,_RPR(r1) | |
835 | mtspr SPRN_RPR,r4 | |
c1b25a17 NP |
836 | ld r4,_AMOR(r1) |
837 | mtspr SPRN_AMOR,r4 | |
bcef83a0 SP |
838 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) |
839 | ||
77b54e9f SP |
840 | ld r4,_TSCR(r1) |
841 | mtspr SPRN_TSCR,r4 | |
842 | ld r4,_WORC(r1) | |
843 | mtspr SPRN_WORC,r4 | |
844 | ||
7cba160a | 845 | clear_lock: |
adbcf8d7 | 846 | xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h |
7cba160a SP |
847 | lwsync |
848 | stw r15,0(r14) | |
849 | ||
850 | common_exit: | |
77b54e9f SP |
851 | /* |
852 | * Common to all threads. | |
853 | * | |
854 | * If waking up from sleep, hypervisor state is not lost. Hence | |
855 | * skip hypervisor state restore. | |
856 | */ | |
bd00a240 | 857 | blt cr4,hypervisor_state_restored |
77b54e9f SP |
858 | |
859 | /* Waking up from winkle */ | |
860 | ||
bcef83a0 SP |
861 | BEGIN_MMU_FTR_SECTION |
862 | b no_segments | |
5a25b6f5 | 863 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX) |
77b54e9f SP |
864 | /* Restore SLB from PACA */ |
865 | ld r8,PACA_SLBSHADOWPTR(r13) | |
866 | ||
867 | .rept SLB_NUM_BOLTED | |
868 | li r3, SLBSHADOW_SAVEAREA | |
869 | LDX_BE r5, r8, r3 | |
870 | addi r3, r3, 8 | |
871 | LDX_BE r6, r8, r3 | |
872 | andis. r7,r5,SLB_ESID_V@h | |
873 | beq 1f | |
874 | slbmte r6,r5 | |
875 | 1: addi r8,r8,16 | |
876 | .endr | |
bcef83a0 SP |
877 | no_segments: |
878 | ||
879 | /* Restore per thread state */ | |
77b54e9f SP |
880 | |
881 | ld r4,_SPURR(r1) | |
882 | mtspr SPRN_SPURR,r4 | |
883 | ld r4,_PURR(r1) | |
884 | mtspr SPRN_PURR,r4 | |
885 | ld r4,_DSCR(r1) | |
886 | mtspr SPRN_DSCR,r4 | |
887 | ld r4,_WORT(r1) | |
888 | mtspr SPRN_WORT,r4 | |
889 | ||
bcef83a0 SP |
890 | /* Call cur_cpu_spec->cpu_restore() */ |
891 | LOAD_REG_ADDR(r4, cur_cpu_spec) | |
892 | ld r4,0(r4) | |
893 | ld r12,CPU_SPEC_RESTORE(r4) | |
894 | #ifdef PPC64_ELF_ABI_v1 | |
895 | ld r12,0(r12) | |
896 | #endif | |
897 | mtctr r12 | |
898 | bctrl | |
899 | ||
e1c1cfed GS |
900 | /* |
901 | * On POWER9, we can come here on wakeup from a cpuidle stop state. | |
902 | * Hence restore the additional SPRs to the saved value. | |
903 | * | |
904 | * On POWER8, we come here only on winkle. Since winkle is used | |
905 | * only in the case of CPU-Hotplug, we don't need to restore | |
906 | * the additional SPRs. | |
907 | */ | |
cb0be7ec | 908 | BEGIN_FTR_SECTION |
e1c1cfed | 909 | bl power9_restore_additional_sprs |
cb0be7ec | 910 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) |
77b54e9f SP |
911 | hypervisor_state_restored: |
912 | ||
9d292501 | 913 | mr r12,r19 |
17065671 | 914 | mtlr r17 |
bf0153c1 | 915 | blr /* return to pnv_powersave_wakeup */ |
97eb001f | 916 | |
7cba160a SP |
917 | fastsleep_workaround_at_exit: |
918 | li r3,1 | |
919 | li r4,0 | |
ab9bad0e | 920 | bl opal_config_cpu_idle_state |
7cba160a SP |
921 | b timebase_resync |
922 | ||
56548fc0 PM |
923 | /* |
924 | * R3 here contains the value that will be returned to the caller | |
925 | * of power7_nap. | |
9d292501 | 926 | * R12 contains SRR1 for CHECK_HMI_INTERRUPT. |
56548fc0 | 927 | */ |
bf0153c1 NP |
928 | .global pnv_wakeup_loss |
929 | pnv_wakeup_loss: | |
948cf67c | 930 | ld r1,PACAR1(r13) |
bbdb760d MS |
931 | BEGIN_FTR_SECTION |
932 | CHECK_HMI_INTERRUPT | |
933 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
948cf67c BH |
934 | REST_NVGPRS(r1) |
935 | REST_GPR(2, r1) | |
a3f3072d RC |
936 | |
937 | BEGIN_FTR_SECTION | |
938 | /* IAMR was saved in pnv_powersave_common() */ | |
939 | ld r5, PNV_POWERSAVE_IAMR(r1) | |
940 | mtspr SPRN_IAMR, r5 | |
941 | /* | |
942 | * We don't need an isync here because the upcoming mtmsrd is | |
943 | * execution synchronizing. | |
944 | */ | |
945 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) | |
946 | ||
9d292501 NP |
947 | ld r4,PACAKMSR(r13) |
948 | ld r5,_LINK(r1) | |
56548fc0 | 949 | ld r6,_CCR(r1) |
948cf67c | 950 | addi r1,r1,INT_FRAME_SIZE |
9d292501 | 951 | mtlr r5 |
56548fc0 | 952 | mtcr r6 |
9d292501 NP |
953 | mtmsrd r4 |
954 | blr | |
948cf67c | 955 | |
56548fc0 PM |
956 | /* |
957 | * R3 here contains the value that will be returned to the caller | |
958 | * of power7_nap. | |
9d292501 | 959 | * R12 contains SRR1 for CHECK_HMI_INTERRUPT. |
56548fc0 | 960 | */ |
bf0153c1 | 961 | pnv_wakeup_noloss: |
2fde6d20 PM |
962 | lbz r0,PACA_NAPSTATELOST(r13) |
963 | cmpwi r0,0 | |
5fa6b6bd | 964 | bne pnv_wakeup_loss |
9d292501 | 965 | ld r1,PACAR1(r13) |
bbdb760d MS |
966 | BEGIN_FTR_SECTION |
967 | CHECK_HMI_INTERRUPT | |
968 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
9d292501 | 969 | ld r4,PACAKMSR(r13) |
948cf67c | 970 | ld r5,_NIP(r1) |
9d292501 | 971 | ld r6,_CCR(r1) |
948cf67c | 972 | addi r1,r1,INT_FRAME_SIZE |
9d292501 | 973 | mtlr r5 |
0aab3747 | 974 | mtcr r6 |
9d292501 NP |
975 | mtmsrd r4 |
976 | blr |