[linux-2.6-block.git] / arch / powerpc / kernel / idle_book3s.S

/*
 *  This file contains idle entry/exit functions for POWER7 and
 *  POWER8 CPUs.
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 */

#include <linux/threads.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/cputable.h>
#include <asm/thread_info.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/ppc-opcode.h>
#include <asm/hw_irq.h>
#include <asm/kvm_book3s_asm.h>
#include <asm/opal.h>
#include <asm/cpuidle.h>
#include <asm/book3s/64/mmu-hash.h>

#undef DEBUG

/*
 * Use unused space in the interrupt stack to save and restore
 * registers for winkle support.
 */
#define _SDR1	GPR3
#define _RPR	GPR4
#define _SPURR	GPR5
#define _PURR	GPR6
#define _TSCR	GPR7
#define _DSCR	GPR8
#define _AMOR	GPR9
#define _WORT	GPR10
#define _WORC	GPR11

/* Idle state entry routines */

#define	IDLE_STATE_ENTER_SEQ(IDLE_INST)				\
	/* Magic NAP/SLEEP/WINKLE mode enter sequence */	\
	std	r0,0(r1);					\
	ptesync;						\
	ld	r0,0(r1);					\
1:	cmp	cr0,r0,r0;					\
	bne	1b;						\
	IDLE_INST;						\
	b	.

	.text

/*
 * Used by threads when the lock bit of core_idle_state is set.
 * Threads will spin in HMT_LOW until the lock bit is cleared.
 * r14 - pointer to core_idle_state
 * r15 - used to load contents of core_idle_state
 */

core_idle_lock_held:
	HMT_LOW
3:	lwz	r15,0(r14)
	andi.   r15,r15,PNV_CORE_IDLE_LOCK_BIT
	bne	3b
	HMT_MEDIUM
	lwarx	r15,0,r14
	blr

/*
 * Pass requested state in r3:
 *	r3 - PNV_THREAD_NAP/SLEEP/WINKLE
 *
 * To check IRQ_HAPPENED in r4
 * 	0 - don't check
 * 	1 - check
 */
_GLOBAL(pnv_powersave_common)
	/* Use r3 to pass state nap/sleep/winkle */
	/* NAP is a state loss, we create a regs frame on the
	 * stack, fill it up with the state we care about and
	 * stick a pointer to it in PACAR1. We really only
	 * need to save PC, some CR bits and the NV GPRs,
	 * but for now an interrupt frame will do.
	 */
	mflr	r0
	std	r0,16(r1)
	stdu	r1,-INT_FRAME_SIZE(r1)
	std	r0,_LINK(r1)
	std	r0,_NIP(r1)

	/* Hard disable interrupts */
	mfmsr	r9
	rldicl	r9,r9,48,1
	rotldi	r9,r9,16
	mtmsrd	r9,1			/* hard-disable interrupts */

	/* Check if something happened while soft-disabled */
	lbz	r0,PACAIRQHAPPENED(r13)
	andi.	r0,r0,~PACA_IRQ_HARD_DIS@l
	beq	1f
	cmpwi	cr0,r4,0
	beq	1f
	addi	r1,r1,INT_FRAME_SIZE
	ld	r0,16(r1)
	li	r3,0			/* Return 0 (no nap) */
	mtlr	r0
	blr

1:	/* We mark irqs hard disabled as this is the state we'll
	 * be in when returning and we need to tell arch_local_irq_restore()
	 * about it
	 */
	li	r0,PACA_IRQ_HARD_DIS
	stb	r0,PACAIRQHAPPENED(r13)

	/* We haven't lost state ... yet */
	li	r0,0
	stb	r0,PACA_NAPSTATELOST(r13)

	/* Continue saving state */
	SAVE_GPR(2, r1)
	SAVE_NVGPRS(r1)
	mfcr	r4
	std	r4,_CCR(r1)
	std	r9,_MSR(r1)
	std	r1,PACAR1(r13)

	/*
	 * Go to real mode to do the nap, as required by the architecture.
	 * Also, we need to be in real mode before setting hwthread_state,
	 * because as soon as we do that, another thread can switch
	 * the MMU context to the guest.
	 */
	LOAD_REG_IMMEDIATE(r5, MSR_IDLE)
	li	r6, MSR_RI
	andc	r6, r9, r6
	LOAD_REG_ADDR(r7, pnv_enter_arch207_idle_mode)
	mtmsrd	r6, 1		/* clear RI before setting SRR0/1 */
	mtspr	SPRN_SRR0, r7
	mtspr	SPRN_SRR1, r5
	rfid

	.globl pnv_enter_arch207_idle_mode
pnv_enter_arch207_idle_mode:
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
	/* Tell KVM we're napping */
	li	r4,KVM_HWTHREAD_IN_NAP
	stb	r4,HSTATE_HWTHREAD_STATE(r13)
#endif
	stb	r3,PACA_THREAD_IDLE_STATE(r13)
	cmpwi	cr3,r3,PNV_THREAD_SLEEP
	bge	cr3,2f
	IDLE_STATE_ENTER_SEQ(PPC_NAP)
	/* No return */
2:
	/* Sleep or winkle */
	lbz	r7,PACA_THREAD_MASK(r13)
	ld	r14,PACA_CORE_IDLE_STATE_PTR(r13)
lwarx_loop1:
	lwarx	r15,0,r14

	andi.   r9,r15,PNV_CORE_IDLE_LOCK_BIT
	bnel	core_idle_lock_held

	andc	r15,r15,r7			/* Clear thread bit */

	andi.	r15,r15,PNV_CORE_IDLE_THREAD_BITS

/*
 * If cr0 = 0, then current thread is the last thread of the core entering
 * sleep. Last thread needs to execute the hardware bug workaround code if
 * required by the platform.
 * Make the workaround call unconditionally here. The below branch call is
 * patched out when the idle states are discovered if the platform does not
 * require it.
 */
.global pnv_fastsleep_workaround_at_entry
pnv_fastsleep_workaround_at_entry:
	beq	fastsleep_workaround_at_entry

	stwcx.	r15,0,r14
	bne-	lwarx_loop1
	isync

common_enter: /* common code for all the threads entering sleep or winkle */
	bgt	cr3,enter_winkle
	IDLE_STATE_ENTER_SEQ(PPC_SLEEP)

fastsleep_workaround_at_entry:
	ori	r15,r15,PNV_CORE_IDLE_LOCK_BIT
	stwcx.	r15,0,r14
	bne-	lwarx_loop1
	isync

	/* Fast sleep workaround */
	li	r3,1
	li	r4,1
	li	r0,OPAL_CONFIG_CPU_IDLE_STATE
	bl	opal_call_realmode

	/* Clear Lock bit */
	li	r0,0
	lwsync
	stw	r0,0(r14)
	b	common_enter

enter_winkle:
	/*
	 * Note all register i.e per-core, per-subcore or per-thread is saved
	 * here since any thread in the core might wake up first
	 */
	mfspr	r3,SPRN_SDR1
	std	r3,_SDR1(r1)
	mfspr	r3,SPRN_RPR
	std	r3,_RPR(r1)
	mfspr	r3,SPRN_SPURR
	std	r3,_SPURR(r1)
	mfspr	r3,SPRN_PURR
	std	r3,_PURR(r1)
	mfspr	r3,SPRN_TSCR
	std	r3,_TSCR(r1)
	mfspr	r3,SPRN_DSCR
	std	r3,_DSCR(r1)
	mfspr	r3,SPRN_AMOR
	std	r3,_AMOR(r1)
	mfspr	r3,SPRN_WORT
	std	r3,_WORT(r1)
	mfspr	r3,SPRN_WORC
	std	r3,_WORC(r1)
	IDLE_STATE_ENTER_SEQ(PPC_WINKLE)

_GLOBAL(power7_idle)
	/* Now check if user or arch enabled NAP mode */
	LOAD_REG_ADDRBASE(r3,powersave_nap)
	lwz	r4,ADDROFF(powersave_nap)(r3)
	cmpwi	0,r4,0
	beqlr
	li	r3, 1
	/* fall through */

_GLOBAL(power7_nap)
	mr	r4,r3
	li	r3,PNV_THREAD_NAP
	b	pnv_powersave_common
	/* No return */

_GLOBAL(power7_sleep)
	li	r3,PNV_THREAD_SLEEP
	li	r4,1
	b	pnv_powersave_common
	/* No return */

_GLOBAL(power7_winkle)
	li	r3,PNV_THREAD_WINKLE
	li	r4,1
	b	pnv_powersave_common
	/* No return */

#define CHECK_HMI_INTERRUPT						\
	mfspr	r0,SPRN_SRR1;						\
BEGIN_FTR_SECTION_NESTED(66);						\
	rlwinm	r0,r0,45-31,0xf;  /* extract wake reason field (P8) */	\
FTR_SECTION_ELSE_NESTED(66);						\
	rlwinm	r0,r0,45-31,0xe;  /* P7 wake reason field is 3 bits */	\
ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66);		\
	cmpwi	r0,0xa;			/* Hypervisor maintenance ? */	\
	bne	20f;							\
	/* Invoke opal call to handle hmi */				\
	ld	r2,PACATOC(r13);					\
	ld	r1,PACAR1(r13);						\
	std	r3,ORIG_GPR3(r1);	/* Save original r3 */		\
	li	r0,OPAL_HANDLE_HMI;	/* Pass opal token argument*/	\
	bl	opal_call_realmode;					\
	ld	r3,ORIG_GPR3(r1);	/* Restore original r3 */	\
20:	nop;


/*
 * Called from reset vector. Check whether we have woken up with
 * hypervisor state loss. If yes, restore hypervisor state and return
 * back to reset vector.
 *
 * r13 - Contents of HSPRG0
 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
 */
_GLOBAL(pnv_restore_hyp_resource)
	/*
	 * Check if last bit of HSPGR0 is set. This indicates whether we are
	 * waking up from winkle.
	 */
	clrldi	r5,r13,63
	clrrdi	r13,r13,1
	cmpwi	cr4,r5,1
	mtspr	SPRN_HSPRG0,r13

	lbz	r0,PACA_THREAD_IDLE_STATE(r13)
	cmpwi   cr2,r0,PNV_THREAD_NAP
	bgt     cr2,pnv_wakeup_tb_loss	/* Either sleep or Winkle */

	/*
	 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
	 * up from nap. At this stage CR3 shouldn't contains 'gt' since that
	 * indicates we are waking with hypervisor state loss from nap.
	 */
	bgt	cr3,.

	blr	/* Return back to System Reset vector from where
		   pnv_restore_hyp_resource was invoked */


_GLOBAL(pnv_wakeup_tb_loss)
	ld	r2,PACATOC(r13);
	ld	r1,PACAR1(r13)
	/*
	 * Before entering any idle state, the NVGPRs are saved in the stack
	 * and they are restored before switching to the process context. Hence
	 * until they are restored, they are free to be used.
	 *
	 * Save SRR1 and LR in NVGPRs as they might be clobbered in
	 * opal_call_realmode (called in CHECK_HMI_INTERRUPT). SRR1 is required
	 * to determine the wakeup reason if we branch to kvm_start_guest. LR
	 * is required to return back to reset vector after hypervisor state
	 * restore is complete.
	 */
	mflr	r17
	mfspr	r16,SPRN_SRR1
BEGIN_FTR_SECTION
	CHECK_HMI_INTERRUPT
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)

	lbz	r7,PACA_THREAD_MASK(r13)
	ld	r14,PACA_CORE_IDLE_STATE_PTR(r13)
lwarx_loop2:
	lwarx	r15,0,r14
	andi.	r9,r15,PNV_CORE_IDLE_LOCK_BIT
	/*
	 * Lock bit is set in one of the 2 cases-
	 * a. In the sleep/winkle enter path, the last thread is executing
	 * fastsleep workaround code.
	 * b. In the wake up path, another thread is executing fastsleep
	 * workaround undo code or resyncing timebase or restoring context
	 * In either case loop until the lock bit is cleared.
	 */
	bnel	core_idle_lock_held

	cmpwi	cr2,r15,0
	lbz	r4,PACA_SUBCORE_SIBLING_MASK(r13)
	and	r4,r4,r15
	cmpwi	cr1,r4,0	/* Check if first in subcore */

	/*
	 * At this stage
	 * cr1 - 0b0100 if first thread to wakeup in subcore
	 * cr2 - 0b0100 if first thread to wakeup in core
	 * cr3-  0b0010 if waking up from sleep or winkle
	 * cr4 - 0b0100 if waking up from winkle
	 */

	or	r15,r15,r7		/* Set thread bit */

	beq	cr1,first_thread_in_subcore

	/* Not first thread in subcore to wake up */
	stwcx.	r15,0,r14
	bne-	lwarx_loop2
	isync
	b	common_exit

first_thread_in_subcore:
	/* First thread in subcore to wakeup */
	ori	r15,r15,PNV_CORE_IDLE_LOCK_BIT
	stwcx.	r15,0,r14
	bne-	lwarx_loop2
	isync

	/*
	 * If waking up from sleep, subcore state is not lost. Hence
	 * skip subcore state restore
	 */
	bne	cr4,subcore_state_restored

	/* Restore per-subcore state */
	ld      r4,_SDR1(r1)
	mtspr   SPRN_SDR1,r4
	ld      r4,_RPR(r1)
	mtspr   SPRN_RPR,r4
	ld	r4,_AMOR(r1)
	mtspr	SPRN_AMOR,r4

subcore_state_restored:
	/*
	 * Check if the thread is also the first thread in the core. If not,
	 * skip to clear_lock.
	 */
	bne	cr2,clear_lock

first_thread_in_core:

	/*
	 * First thread in the core waking up from fastsleep. It needs to
	 * call the fastsleep workaround code if the platform requires it.
	 * Call it unconditionally here. The below branch instruction will
	 * be patched out when the idle states are discovered if platform
	 * does not require workaround.
	 */
.global pnv_fastsleep_workaround_at_exit
pnv_fastsleep_workaround_at_exit:
	b	fastsleep_workaround_at_exit

timebase_resync:
	/* Do timebase resync if we are waking up from sleep. Use cr3 value
	 * set in exceptions-64s.S */
	ble	cr3,clear_lock
	/* Time base re-sync */
	li	r0,OPAL_RESYNC_TIMEBASE
	bl	opal_call_realmode;
	/* TODO: Check r3 for failure */

	/*
	 * If waking up from sleep, per core state is not lost, skip to
	 * clear_lock.
	 */
	bne	cr4,clear_lock

	/* Restore per core state */
	ld	r4,_TSCR(r1)
	mtspr	SPRN_TSCR,r4
	ld	r4,_WORC(r1)
	mtspr	SPRN_WORC,r4

clear_lock:
	andi.	r15,r15,PNV_CORE_IDLE_THREAD_BITS
	lwsync
	stw	r15,0(r14)

common_exit:
	/*
	 * Common to all threads.
	 *
	 * If waking up from sleep, hypervisor state is not lost. Hence
	 * skip hypervisor state restore.
	 */
	bne	cr4,hypervisor_state_restored

	/* Waking up from winkle */

	/* Restore per thread state */
	bl	__restore_cpu_power8

	/* Restore SLB  from PACA */
	ld	r8,PACA_SLBSHADOWPTR(r13)

	.rept	SLB_NUM_BOLTED
	li	r3, SLBSHADOW_SAVEAREA
	LDX_BE	r5, r8, r3
	addi	r3, r3, 8
	LDX_BE	r6, r8, r3
	andis.	r7,r5,SLB_ESID_V@h
	beq	1f
	slbmte	r6,r5
1:	addi	r8,r8,16
	.endr

	ld	r4,_SPURR(r1)
	mtspr	SPRN_SPURR,r4
	ld	r4,_PURR(r1)
	mtspr	SPRN_PURR,r4
	ld	r4,_DSCR(r1)
	mtspr	SPRN_DSCR,r4
	ld	r4,_WORT(r1)
	mtspr	SPRN_WORT,r4

hypervisor_state_restored:

	mtspr	SPRN_SRR1,r16
	mtlr	r17
	blr	/* Return back to System Reset vector from where
		   pnv_restore_hyp_resource was invoked */

fastsleep_workaround_at_exit:
	li	r3,1
	li	r4,0
	li	r0,OPAL_CONFIG_CPU_IDLE_STATE
	bl	opal_call_realmode
	b	timebase_resync

/*
 * R3 here contains the value that will be returned to the caller
 * of power7_nap.
 */
_GLOBAL(pnv_wakeup_loss)
	ld	r1,PACAR1(r13)
BEGIN_FTR_SECTION
	CHECK_HMI_INTERRUPT
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
	REST_NVGPRS(r1)
	REST_GPR(2, r1)
	ld	r6,_CCR(r1)
	ld	r4,_MSR(r1)
	ld	r5,_NIP(r1)
	addi	r1,r1,INT_FRAME_SIZE
	mtcr	r6
	mtspr	SPRN_SRR1,r4
	mtspr	SPRN_SRR0,r5
	rfid

/*
 * R3 here contains the value that will be returned to the caller
 * of power7_nap.
 */
_GLOBAL(pnv_wakeup_noloss)
	lbz	r0,PACA_NAPSTATELOST(r13)
	cmpwi	r0,0
	bne	pnv_wakeup_loss
BEGIN_FTR_SECTION
	CHECK_HMI_INTERRUPT
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
	ld	r1,PACAR1(r13)
	ld	r6,_CCR(r1)
	ld	r4,_MSR(r1)
	ld	r5,_NIP(r1)
	addi	r1,r1,INT_FRAME_SIZE
	mtcr	r6
	mtspr	SPRN_SRR1,r4
	mtspr	SPRN_SRR0,r5
	rfid
Commit	Line	Data
948cf67c	1	/*
5fa6b6bd SP	2	* This file contains idle entry/exit functions for POWER7 and
5fa6b6bd SP	3	* POWER8 CPUs.
948cf67c BH	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version
	8	* 2 of the License, or (at your option) any later version.
	9	*/
	10
	11	#include <linux/threads.h>
	12	#include <asm/processor.h>
	13	#include <asm/page.h>
	14	#include <asm/cputable.h>
	15	#include <asm/thread_info.h>
	16	#include <asm/ppc_asm.h>
	17	#include <asm/asm-offsets.h>
	18	#include <asm/ppc-opcode.h>
7230c564	19	#include <asm/hw_irq.h>
f0888f70	20	#include <asm/kvm_book3s_asm.h>
97eb001f	21	#include <asm/opal.h>
7cba160a	22	#include <asm/cpuidle.h>
f64e8084	23	#include <asm/book3s/64/mmu-hash.h>
948cf67c BH	24
	25	#undef DEBUG
	26
77b54e9f SP	27	/*
	28	* Use unused space in the interrupt stack to save and restore
	29	* registers for winkle support.
	30	*/
	31	#define _SDR1 GPR3
	32	#define _RPR GPR4
	33	#define _SPURR GPR5
	34	#define _PURR GPR6
	35	#define _TSCR GPR7
	36	#define _DSCR GPR8
	37	#define _AMOR GPR9
	38	#define _WORT GPR10
	39	#define _WORC GPR11
	40
aca79d2b	41	/* Idle state entry routines */
948cf67c	42
aca79d2b VS	43	#define IDLE_STATE_ENTER_SEQ(IDLE_INST) \
	44	/* Magic NAP/SLEEP/WINKLE mode enter sequence */ \
	45	std r0,0(r1); \
	46	ptesync; \
	47	ld r0,0(r1); \
	48	1: cmp cr0,r0,r0; \
	49	bne 1b; \
	50	IDLE_INST; \
	51	b .
948cf67c	52
aca79d2b VS	53	.text
aca79d2b VS	54
b32aadc1 SP	55	/*
	56	* Used by threads when the lock bit of core_idle_state is set.
	57	* Threads will spin in HMT_LOW until the lock bit is cleared.
	58	* r14 - pointer to core_idle_state
	59	* r15 - used to load contents of core_idle_state
	60	*/
	61
	62	core_idle_lock_held:
	63	HMT_LOW
	64	3: lwz r15,0(r14)
	65	andi. r15,r15,PNV_CORE_IDLE_LOCK_BIT
	66	bne 3b
	67	HMT_MEDIUM
	68	lwarx r15,0,r14
	69	blr
	70
aca79d2b VS	71	/*
aca79d2b VS	72	* Pass requested state in r3:
7cba160a	73	* r3 - PNV_THREAD_NAP/SLEEP/WINKLE
8d6f7c5a ME	74	*
	75	* To check IRQ_HAPPENED in r4
	76	* 0 - don't check
	77	* 1 - check
aca79d2b	78	*/
5fa6b6bd	79	_GLOBAL(pnv_powersave_common)
aca79d2b	80	/* Use r3 to pass state nap/sleep/winkle */
948cf67c BH	81	/* NAP is a state loss, we create a regs frame on the
	82	* stack, fill it up with the state we care about and
	83	* stick a pointer to it in PACAR1. We really only
	84	* need to save PC, some CR bits and the NV GPRs,
	85	* but for now an interrupt frame will do.
	86	*/
	87	mflr r0
	88	std r0,16(r1)
	89	stdu r1,-INT_FRAME_SIZE(r1)
	90	std r0,_LINK(r1)
	91	std r0,_NIP(r1)
	92
948cf67c BH	93	/* Hard disable interrupts */
	94	mfmsr r9
	95	rldicl r9,r9,48,1
	96	rotldi r9,r9,16
	97	mtmsrd r9,1 /* hard-disable interrupts */
7230c564 BH	98
	99	/* Check if something happened while soft-disabled */
	100	lbz r0,PACAIRQHAPPENED(r13)
d6a4f709	101	andi. r0,r0,~PACA_IRQ_HARD_DIS@l
7230c564	102	beq 1f
8d6f7c5a ME	103	cmpwi cr0,r4,0
8d6f7c5a ME	104	beq 1f
7230c564 BH	105	addi r1,r1,INT_FRAME_SIZE
7230c564 BH	106	ld r0,16(r1)
f57333a7	107	li r3,0 /* Return 0 (no nap) */
7230c564 BH	108	mtlr r0
	109	blr
	110
	111	1: /* We mark irqs hard disabled as this is the state we'll
	112	* be in when returning and we need to tell arch_local_irq_restore()
	113	* about it
	114	*/
	115	li r0,PACA_IRQ_HARD_DIS
	116	stb r0,PACAIRQHAPPENED(r13)
	117
	118	/* We haven't lost state ... yet */
948cf67c	119	li r0,0
2fde6d20	120	stb r0,PACA_NAPSTATELOST(r13)
948cf67c BH	121
	122	/* Continue saving state */
	123	SAVE_GPR(2, r1)
	124	SAVE_NVGPRS(r1)
aca79d2b VS	125	mfcr r4
aca79d2b VS	126	std r4,_CCR(r1)
948cf67c BH	127	std r9,_MSR(r1)
	128	std r1,PACAR1(r13)
	129
8117ac6a PM	130	/*
	131	* Go to real mode to do the nap, as required by the architecture.
	132	* Also, we need to be in real mode before setting hwthread_state,
	133	* because as soon as we do that, another thread can switch
	134	* the MMU context to the guest.
	135	*/
	136	LOAD_REG_IMMEDIATE(r5, MSR_IDLE)
	137	li r6, MSR_RI
	138	andc r6, r9, r6
5fa6b6bd	139	LOAD_REG_ADDR(r7, pnv_enter_arch207_idle_mode)
8117ac6a PM	140	mtmsrd r6, 1 /* clear RI before setting SRR0/1 */
	141	mtspr SPRN_SRR0, r7
	142	mtspr SPRN_SRR1, r5
	143	rfid
	144
5fa6b6bd SP	145	.globl pnv_enter_arch207_idle_mode
5fa6b6bd SP	146	pnv_enter_arch207_idle_mode:
9975f5e3	147	#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
f0888f70 PM	148	/* Tell KVM we're napping */
	149	li r4,KVM_HWTHREAD_IN_NAP
	150	stb r4,HSTATE_HWTHREAD_STATE(r13)
	151	#endif
7cba160a	152	stb r3,PACA_THREAD_IDLE_STATE(r13)
77b54e9f SP	153	cmpwi cr3,r3,PNV_THREAD_SLEEP
77b54e9f SP	154	bge cr3,2f
aca79d2b VS	155	IDLE_STATE_ENTER_SEQ(PPC_NAP)
aca79d2b VS	156	/* No return */
7cba160a SP	157	2:
	158	/* Sleep or winkle */
	159	lbz r7,PACA_THREAD_MASK(r13)
	160	ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
	161	lwarx_loop1:
	162	lwarx r15,0,r14
b32aadc1 SP	163
	164	andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
	165	bnel core_idle_lock_held
	166
7cba160a SP	167	andc r15,r15,r7 /* Clear thread bit */
	168
	169	andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
	170
	171	/*
	172	* If cr0 = 0, then current thread is the last thread of the core entering
	173	* sleep. Last thread needs to execute the hardware bug workaround code if
	174	* required by the platform.
	175	* Make the workaround call unconditionally here. The below branch call is
	176	* patched out when the idle states are discovered if the platform does not
	177	* require it.
	178	*/
	179	.global pnv_fastsleep_workaround_at_entry
	180	pnv_fastsleep_workaround_at_entry:
	181	beq fastsleep_workaround_at_entry
	182
	183	stwcx. r15,0,r14
	184	bne- lwarx_loop1
	185	isync
	186
77b54e9f SP	187	common_enter: /* common code for all the threads entering sleep or winkle */
77b54e9f SP	188	bgt cr3,enter_winkle
7cba160a SP	189	IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
	190
	191	fastsleep_workaround_at_entry:
	192	ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
	193	stwcx. r15,0,r14
	194	bne- lwarx_loop1
	195	isync
	196
	197	/* Fast sleep workaround */
	198	li r3,1
	199	li r4,1
	200	li r0,OPAL_CONFIG_CPU_IDLE_STATE
	201	bl opal_call_realmode
	202
	203	/* Clear Lock bit */
	204	li r0,0
	205	lwsync
	206	stw r0,0(r14)
	207	b common_enter
	208
77b54e9f SP	209	enter_winkle:
	210	/*
	211	* Note all register i.e per-core, per-subcore or per-thread is saved
	212	* here since any thread in the core might wake up first
	213	*/
	214	mfspr r3,SPRN_SDR1
	215	std r3,_SDR1(r1)
	216	mfspr r3,SPRN_RPR
	217	std r3,_RPR(r1)
	218	mfspr r3,SPRN_SPURR
	219	std r3,_SPURR(r1)
	220	mfspr r3,SPRN_PURR
	221	std r3,_PURR(r1)
	222	mfspr r3,SPRN_TSCR
	223	std r3,_TSCR(r1)
	224	mfspr r3,SPRN_DSCR
	225	std r3,_DSCR(r1)
	226	mfspr r3,SPRN_AMOR
	227	std r3,_AMOR(r1)
	228	mfspr r3,SPRN_WORT
	229	std r3,_WORT(r1)
	230	mfspr r3,SPRN_WORC
	231	std r3,_WORC(r1)
	232	IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
f0888f70	233
aca79d2b VS	234	_GLOBAL(power7_idle)
	235	/* Now check if user or arch enabled NAP mode */
	236	LOAD_REG_ADDRBASE(r3,powersave_nap)
	237	lwz r4,ADDROFF(powersave_nap)(r3)
	238	cmpwi 0,r4,0
	239	beqlr
8d6f7c5a	240	li r3, 1
aca79d2b VS	241	/* fall through */
	242
	243	_GLOBAL(power7_nap)
8d6f7c5a	244	mr r4,r3
7cba160a	245	li r3,PNV_THREAD_NAP
5fa6b6bd	246	b pnv_powersave_common
aca79d2b VS	247	/* No return */
	248
	249	_GLOBAL(power7_sleep)
7cba160a	250	li r3,PNV_THREAD_SLEEP
c733cf83	251	li r4,1
5fa6b6bd	252	b pnv_powersave_common
aca79d2b	253	/* No return */
948cf67c	254
77b54e9f	255	_GLOBAL(power7_winkle)
bfd1b7ae	256	li r3,PNV_THREAD_WINKLE
77b54e9f	257	li r4,1
5fa6b6bd	258	b pnv_powersave_common
77b54e9f SP	259	/* No return */
77b54e9f SP	260
bbdb760d MS	261	#define CHECK_HMI_INTERRUPT \
	262	mfspr r0,SPRN_SRR1; \
	263	BEGIN_FTR_SECTION_NESTED(66); \
	264	rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \
	265	FTR_SECTION_ELSE_NESTED(66); \
	266	rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \
	267	ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
	268	cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
	269	bne 20f; \
	270	/* Invoke opal call to handle hmi */ \
	271	ld r2,PACATOC(r13); \
	272	ld r1,PACAR1(r13); \
	273	std r3,ORIG_GPR3(r1); /* Save original r3 */ \
7cba160a	274	li r0,OPAL_HANDLE_HMI; /* Pass opal token argument*/ \
db97efff	275	bl opal_call_realmode; \
bbdb760d MS	276	ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
	277	20: nop;
	278
	279
17065671 SP	280	/*
	281	* Called from reset vector. Check whether we have woken up with
	282	* hypervisor state loss. If yes, restore hypervisor state and return
	283	* back to reset vector.
	284	*
	285	* r13 - Contents of HSPRG0
	286	* cr3 - set to gt if waking up with partial/complete hypervisor state loss
	287	*/
5fa6b6bd	288	_GLOBAL(pnv_restore_hyp_resource)
17065671 SP	289	/*
	290	* Check if last bit of HSPGR0 is set. This indicates whether we are
	291	* waking up from winkle.
	292	*/
	293	clrldi r5,r13,63
	294	clrrdi r13,r13,1
	295	cmpwi cr4,r5,1
	296	mtspr SPRN_HSPRG0,r13
	297
	298	lbz r0,PACA_THREAD_IDLE_STATE(r13)
	299	cmpwi cr2,r0,PNV_THREAD_NAP
5fa6b6bd	300	bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */
17065671 SP	301
	302	/*
	303	* We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
	304	* up from nap. At this stage CR3 shouldn't contains 'gt' since that
	305	* indicates we are waking with hypervisor state loss from nap.
	306	*/
	307	bgt cr3,.
	308
	309	blr /* Return back to System Reset vector from where
5fa6b6bd	310	pnv_restore_hyp_resource was invoked */
17065671 SP	311
17065671 SP	312
5fa6b6bd	313	_GLOBAL(pnv_wakeup_tb_loss)
97eb001f VS	314	ld r2,PACATOC(r13);
97eb001f VS	315	ld r1,PACAR1(r13)
7cba160a SP	316	/*
	317	* Before entering any idle state, the NVGPRs are saved in the stack
	318	* and they are restored before switching to the process context. Hence
	319	* until they are restored, they are free to be used.
	320	*
17065671 SP	321	* Save SRR1 and LR in NVGPRs as they might be clobbered in
	322	* opal_call_realmode (called in CHECK_HMI_INTERRUPT). SRR1 is required
	323	* to determine the wakeup reason if we branch to kvm_start_guest. LR
	324	* is required to return back to reset vector after hypervisor state
	325	* restore is complete.
7cba160a	326	*/
17065671	327	mflr r17
7cba160a	328	mfspr r16,SPRN_SRR1
bbdb760d MS	329	BEGIN_FTR_SECTION
	330	CHECK_HMI_INTERRUPT
	331	END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
7cba160a SP	332
	333	lbz r7,PACA_THREAD_MASK(r13)
	334	ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
	335	lwarx_loop2:
	336	lwarx r15,0,r14
	337	andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
	338	/*
	339	* Lock bit is set in one of the 2 cases-
	340	* a. In the sleep/winkle enter path, the last thread is executing
	341	* fastsleep workaround code.
	342	* b. In the wake up path, another thread is executing fastsleep
	343	* workaround undo code or resyncing timebase or restoring context
	344	* In either case loop until the lock bit is cleared.
	345	*/
b32aadc1	346	bnel core_idle_lock_held
7cba160a SP	347
7cba160a SP	348	cmpwi cr2,r15,0
77b54e9f SP	349	lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
	350	and r4,r4,r15
	351	cmpwi cr1,r4,0 /* Check if first in subcore */
	352
	353	/*
	354	* At this stage
	355	* cr1 - 0b0100 if first thread to wakeup in subcore
	356	* cr2 - 0b0100 if first thread to wakeup in core
	357	* cr3- 0b0010 if waking up from sleep or winkle
	358	* cr4 - 0b0100 if waking up from winkle
	359	*/
	360
7cba160a SP	361	or r15,r15,r7 /* Set thread bit */
7cba160a SP	362
77b54e9f	363	beq cr1,first_thread_in_subcore
7cba160a	364
77b54e9f	365	/* Not first thread in subcore to wake up */
7cba160a SP	366	stwcx. r15,0,r14
	367	bne- lwarx_loop2
	368	isync
	369	b common_exit
	370
77b54e9f SP	371	first_thread_in_subcore:
77b54e9f SP	372	/* First thread in subcore to wakeup */
7cba160a SP	373	ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
	374	stwcx. r15,0,r14
	375	bne- lwarx_loop2
	376	isync
	377
77b54e9f SP	378	/*
	379	* If waking up from sleep, subcore state is not lost. Hence
	380	* skip subcore state restore
	381	*/
	382	bne cr4,subcore_state_restored
	383
	384	/* Restore per-subcore state */
	385	ld r4,_SDR1(r1)
	386	mtspr SPRN_SDR1,r4
	387	ld r4,_RPR(r1)
	388	mtspr SPRN_RPR,r4
	389	ld r4,_AMOR(r1)
	390	mtspr SPRN_AMOR,r4
	391
	392	subcore_state_restored:
	393	/*
	394	* Check if the thread is also the first thread in the core. If not,
	395	* skip to clear_lock.
	396	*/
	397	bne cr2,clear_lock
	398
	399	first_thread_in_core:
	400
7cba160a SP	401	/*
	402	* First thread in the core waking up from fastsleep. It needs to
	403	* call the fastsleep workaround code if the platform requires it.
	404	* Call it unconditionally here. The below branch instruction will
	405	* be patched out when the idle states are discovered if platform
	406	* does not require workaround.
	407	*/
	408	.global pnv_fastsleep_workaround_at_exit
	409	pnv_fastsleep_workaround_at_exit:
	410	b fastsleep_workaround_at_exit
	411
	412	timebase_resync:
	413	/* Do timebase resync if we are waking up from sleep. Use cr3 value
	414	* set in exceptions-64s.S */
	415	ble cr3,clear_lock
97eb001f	416	/* Time base re-sync */
7cba160a	417	li r0,OPAL_RESYNC_TIMEBASE
db97efff	418	bl opal_call_realmode;
97eb001f VS	419	/* TODO: Check r3 for failure */
97eb001f VS	420
77b54e9f SP	421	/*
	422	* If waking up from sleep, per core state is not lost, skip to
	423	* clear_lock.
	424	*/
	425	bne cr4,clear_lock
	426
	427	/* Restore per core state */
	428	ld r4,_TSCR(r1)
	429	mtspr SPRN_TSCR,r4
	430	ld r4,_WORC(r1)
	431	mtspr SPRN_WORC,r4
	432
7cba160a SP	433	clear_lock:
	434	andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
	435	lwsync
	436	stw r15,0(r14)
	437
	438	common_exit:
77b54e9f SP	439	/*
	440	* Common to all threads.
	441	*
	442	* If waking up from sleep, hypervisor state is not lost. Hence
	443	* skip hypervisor state restore.
	444	*/
	445	bne cr4,hypervisor_state_restored
	446
	447	/* Waking up from winkle */
	448
	449	/* Restore per thread state */
	450	bl __restore_cpu_power8
	451
	452	/* Restore SLB from PACA */
	453	ld r8,PACA_SLBSHADOWPTR(r13)
	454
	455	.rept SLB_NUM_BOLTED
	456	li r3, SLBSHADOW_SAVEAREA
	457	LDX_BE r5, r8, r3
	458	addi r3, r3, 8
	459	LDX_BE r6, r8, r3
	460	andis. r7,r5,SLB_ESID_V@h
	461	beq 1f
	462	slbmte r6,r5
	463	1: addi r8,r8,16
	464	.endr
	465
	466	ld r4,_SPURR(r1)
	467	mtspr SPRN_SPURR,r4
	468	ld r4,_PURR(r1)
	469	mtspr SPRN_PURR,r4
	470	ld r4,_DSCR(r1)
	471	mtspr SPRN_DSCR,r4
	472	ld r4,_WORT(r1)
	473	mtspr SPRN_WORT,r4
	474
	475	hypervisor_state_restored:
	476
7cba160a	477	mtspr SPRN_SRR1,r16
17065671 SP	478	mtlr r17
17065671 SP	479	blr /* Return back to System Reset vector from where
5fa6b6bd	480	pnv_restore_hyp_resource was invoked */
97eb001f	481
7cba160a SP	482	fastsleep_workaround_at_exit:
	483	li r3,1
	484	li r4,0
	485	li r0,OPAL_CONFIG_CPU_IDLE_STATE
	486	bl opal_call_realmode
	487	b timebase_resync
	488
56548fc0 PM	489	/*
	490	* R3 here contains the value that will be returned to the caller
	491	* of power7_nap.
	492	*/
5fa6b6bd	493	_GLOBAL(pnv_wakeup_loss)
948cf67c	494	ld r1,PACAR1(r13)
bbdb760d MS	495	BEGIN_FTR_SECTION
	496	CHECK_HMI_INTERRUPT
	497	END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
948cf67c BH	498	REST_NVGPRS(r1)
948cf67c BH	499	REST_GPR(2, r1)
56548fc0	500	ld r6,_CCR(r1)
948cf67c BH	501	ld r4,_MSR(r1)
	502	ld r5,_NIP(r1)
	503	addi r1,r1,INT_FRAME_SIZE
56548fc0	504	mtcr r6
948cf67c BH	505	mtspr SPRN_SRR1,r4
	506	mtspr SPRN_SRR0,r5
	507	rfid
	508
56548fc0 PM	509	/*
	510	* R3 here contains the value that will be returned to the caller
	511	* of power7_nap.
	512	*/
5fa6b6bd	513	_GLOBAL(pnv_wakeup_noloss)
2fde6d20 PM	514	lbz r0,PACA_NAPSTATELOST(r13)
2fde6d20 PM	515	cmpwi r0,0
5fa6b6bd	516	bne pnv_wakeup_loss
bbdb760d MS	517	BEGIN_FTR_SECTION
	518	CHECK_HMI_INTERRUPT
	519	END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
948cf67c	520	ld r1,PACAR1(r13)
0aab3747	521	ld r6,_CCR(r1)
948cf67c BH	522	ld r4,_MSR(r1)
	523	ld r5,_NIP(r1)
	524	addi r1,r1,INT_FRAME_SIZE
0aab3747	525	mtcr r6
948cf67c BH	526	mtspr SPRN_SRR1,r4
	527	mtspr SPRN_SRR0,r5
	528	rfid