Commit | Line | Data |
---|---|---|
948cf67c | 1 | /* |
5fa6b6bd SP |
2 | * This file contains idle entry/exit functions for POWER7 and |
3 | * POWER8 CPUs. | |
948cf67c BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | */ | |
10 | ||
11 | #include <linux/threads.h> | |
12 | #include <asm/processor.h> | |
13 | #include <asm/page.h> | |
14 | #include <asm/cputable.h> | |
15 | #include <asm/thread_info.h> | |
16 | #include <asm/ppc_asm.h> | |
17 | #include <asm/asm-offsets.h> | |
18 | #include <asm/ppc-opcode.h> | |
7230c564 | 19 | #include <asm/hw_irq.h> |
f0888f70 | 20 | #include <asm/kvm_book3s_asm.h> |
97eb001f | 21 | #include <asm/opal.h> |
7cba160a | 22 | #include <asm/cpuidle.h> |
f64e8084 | 23 | #include <asm/book3s/64/mmu-hash.h> |
948cf67c BH |
24 | |
25 | #undef DEBUG | |
26 | ||
77b54e9f SP |
27 | /* |
28 | * Use unused space in the interrupt stack to save and restore | |
29 | * registers for winkle support. | |
30 | */ | |
31 | #define _SDR1 GPR3 | |
32 | #define _RPR GPR4 | |
33 | #define _SPURR GPR5 | |
34 | #define _PURR GPR6 | |
35 | #define _TSCR GPR7 | |
36 | #define _DSCR GPR8 | |
37 | #define _AMOR GPR9 | |
38 | #define _WORT GPR10 | |
39 | #define _WORC GPR11 | |
40 | ||
aca79d2b | 41 | /* Idle state entry routines */ |
948cf67c | 42 | |
aca79d2b VS |
43 | #define IDLE_STATE_ENTER_SEQ(IDLE_INST) \ |
44 | /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \ | |
45 | std r0,0(r1); \ | |
46 | ptesync; \ | |
47 | ld r0,0(r1); \ | |
48 | 1: cmp cr0,r0,r0; \ | |
49 | bne 1b; \ | |
50 | IDLE_INST; \ | |
51 | b . | |
948cf67c | 52 | |
aca79d2b VS |
53 | .text |
54 | ||
b32aadc1 SP |
55 | /* |
56 | * Used by threads when the lock bit of core_idle_state is set. | |
57 | * Threads will spin in HMT_LOW until the lock bit is cleared. | |
58 | * r14 - pointer to core_idle_state | |
59 | * r15 - used to load contents of core_idle_state | |
60 | */ | |
61 | ||
62 | core_idle_lock_held: | |
63 | HMT_LOW | |
64 | 3: lwz r15,0(r14) | |
65 | andi. r15,r15,PNV_CORE_IDLE_LOCK_BIT | |
66 | bne 3b | |
67 | HMT_MEDIUM | |
68 | lwarx r15,0,r14 | |
69 | blr | |
70 | ||
aca79d2b VS |
71 | /* |
72 | * Pass requested state in r3: | |
7cba160a | 73 | * r3 - PNV_THREAD_NAP/SLEEP/WINKLE |
8d6f7c5a ME |
74 | * |
75 | * To check IRQ_HAPPENED in r4 | |
76 | * 0 - don't check | |
77 | * 1 - check | |
4eae2c9a SP |
78 | * |
79 | * Address to 'rfid' to in r5 | |
aca79d2b | 80 | */ |
5fa6b6bd | 81 | _GLOBAL(pnv_powersave_common) |
aca79d2b | 82 | /* Use r3 to pass state nap/sleep/winkle */ |
948cf67c BH |
83 | /* NAP is a state loss, we create a regs frame on the |
84 | * stack, fill it up with the state we care about and | |
85 | * stick a pointer to it in PACAR1. We really only | |
86 | * need to save PC, some CR bits and the NV GPRs, | |
87 | * but for now an interrupt frame will do. | |
88 | */ | |
89 | mflr r0 | |
90 | std r0,16(r1) | |
91 | stdu r1,-INT_FRAME_SIZE(r1) | |
92 | std r0,_LINK(r1) | |
93 | std r0,_NIP(r1) | |
94 | ||
948cf67c BH |
95 | /* Hard disable interrupts */ |
96 | mfmsr r9 | |
97 | rldicl r9,r9,48,1 | |
98 | rotldi r9,r9,16 | |
99 | mtmsrd r9,1 /* hard-disable interrupts */ | |
7230c564 BH |
100 | |
101 | /* Check if something happened while soft-disabled */ | |
102 | lbz r0,PACAIRQHAPPENED(r13) | |
d6a4f709 | 103 | andi. r0,r0,~PACA_IRQ_HARD_DIS@l |
7230c564 | 104 | beq 1f |
8d6f7c5a ME |
105 | cmpwi cr0,r4,0 |
106 | beq 1f | |
7230c564 BH |
107 | addi r1,r1,INT_FRAME_SIZE |
108 | ld r0,16(r1) | |
f57333a7 | 109 | li r3,0 /* Return 0 (no nap) */ |
7230c564 BH |
110 | mtlr r0 |
111 | blr | |
112 | ||
113 | 1: /* We mark irqs hard disabled as this is the state we'll | |
114 | * be in when returning and we need to tell arch_local_irq_restore() | |
115 | * about it | |
116 | */ | |
117 | li r0,PACA_IRQ_HARD_DIS | |
118 | stb r0,PACAIRQHAPPENED(r13) | |
119 | ||
120 | /* We haven't lost state ... yet */ | |
948cf67c | 121 | li r0,0 |
2fde6d20 | 122 | stb r0,PACA_NAPSTATELOST(r13) |
948cf67c BH |
123 | |
124 | /* Continue saving state */ | |
125 | SAVE_GPR(2, r1) | |
126 | SAVE_NVGPRS(r1) | |
aca79d2b VS |
127 | mfcr r4 |
128 | std r4,_CCR(r1) | |
948cf67c BH |
129 | std r9,_MSR(r1) |
130 | std r1,PACAR1(r13) | |
131 | ||
4eae2c9a SP |
132 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
133 | /* Tell KVM we're entering idle */ | |
134 | li r4,KVM_HWTHREAD_IN_NAP | |
135 | stb r4,HSTATE_HWTHREAD_STATE(r13) | |
136 | #endif | |
137 | ||
8117ac6a PM |
138 | /* |
139 | * Go to real mode to do the nap, as required by the architecture. | |
140 | * Also, we need to be in real mode before setting hwthread_state, | |
141 | * because as soon as we do that, another thread can switch | |
142 | * the MMU context to the guest. | |
143 | */ | |
4eae2c9a | 144 | LOAD_REG_IMMEDIATE(r7, MSR_IDLE) |
8117ac6a PM |
145 | li r6, MSR_RI |
146 | andc r6, r9, r6 | |
8117ac6a | 147 | mtmsrd r6, 1 /* clear RI before setting SRR0/1 */ |
4eae2c9a SP |
148 | mtspr SPRN_SRR0, r5 |
149 | mtspr SPRN_SRR1, r7 | |
8117ac6a PM |
150 | rfid |
151 | ||
5fa6b6bd SP |
152 | .globl pnv_enter_arch207_idle_mode |
153 | pnv_enter_arch207_idle_mode: | |
7cba160a | 154 | stb r3,PACA_THREAD_IDLE_STATE(r13) |
77b54e9f SP |
155 | cmpwi cr3,r3,PNV_THREAD_SLEEP |
156 | bge cr3,2f | |
aca79d2b VS |
157 | IDLE_STATE_ENTER_SEQ(PPC_NAP) |
158 | /* No return */ | |
7cba160a SP |
159 | 2: |
160 | /* Sleep or winkle */ | |
161 | lbz r7,PACA_THREAD_MASK(r13) | |
162 | ld r14,PACA_CORE_IDLE_STATE_PTR(r13) | |
163 | lwarx_loop1: | |
164 | lwarx r15,0,r14 | |
b32aadc1 SP |
165 | |
166 | andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT | |
167 | bnel core_idle_lock_held | |
168 | ||
7cba160a SP |
169 | andc r15,r15,r7 /* Clear thread bit */ |
170 | ||
171 | andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS | |
172 | ||
173 | /* | |
174 | * If cr0 = 0, then current thread is the last thread of the core entering | |
175 | * sleep. Last thread needs to execute the hardware bug workaround code if | |
176 | * required by the platform. | |
177 | * Make the workaround call unconditionally here. The below branch call is | |
178 | * patched out when the idle states are discovered if the platform does not | |
179 | * require it. | |
180 | */ | |
181 | .global pnv_fastsleep_workaround_at_entry | |
182 | pnv_fastsleep_workaround_at_entry: | |
183 | beq fastsleep_workaround_at_entry | |
184 | ||
185 | stwcx. r15,0,r14 | |
186 | bne- lwarx_loop1 | |
187 | isync | |
188 | ||
77b54e9f SP |
189 | common_enter: /* common code for all the threads entering sleep or winkle */ |
190 | bgt cr3,enter_winkle | |
7cba160a SP |
191 | IDLE_STATE_ENTER_SEQ(PPC_SLEEP) |
192 | ||
193 | fastsleep_workaround_at_entry: | |
194 | ori r15,r15,PNV_CORE_IDLE_LOCK_BIT | |
195 | stwcx. r15,0,r14 | |
196 | bne- lwarx_loop1 | |
197 | isync | |
198 | ||
199 | /* Fast sleep workaround */ | |
200 | li r3,1 | |
201 | li r4,1 | |
202 | li r0,OPAL_CONFIG_CPU_IDLE_STATE | |
203 | bl opal_call_realmode | |
204 | ||
205 | /* Clear Lock bit */ | |
206 | li r0,0 | |
207 | lwsync | |
208 | stw r0,0(r14) | |
209 | b common_enter | |
210 | ||
77b54e9f SP |
211 | enter_winkle: |
212 | /* | |
213 | * Note all register i.e per-core, per-subcore or per-thread is saved | |
214 | * here since any thread in the core might wake up first | |
215 | */ | |
216 | mfspr r3,SPRN_SDR1 | |
217 | std r3,_SDR1(r1) | |
218 | mfspr r3,SPRN_RPR | |
219 | std r3,_RPR(r1) | |
220 | mfspr r3,SPRN_SPURR | |
221 | std r3,_SPURR(r1) | |
222 | mfspr r3,SPRN_PURR | |
223 | std r3,_PURR(r1) | |
224 | mfspr r3,SPRN_TSCR | |
225 | std r3,_TSCR(r1) | |
226 | mfspr r3,SPRN_DSCR | |
227 | std r3,_DSCR(r1) | |
228 | mfspr r3,SPRN_AMOR | |
229 | std r3,_AMOR(r1) | |
230 | mfspr r3,SPRN_WORT | |
231 | std r3,_WORT(r1) | |
232 | mfspr r3,SPRN_WORC | |
233 | std r3,_WORC(r1) | |
234 | IDLE_STATE_ENTER_SEQ(PPC_WINKLE) | |
f0888f70 | 235 | |
aca79d2b VS |
236 | _GLOBAL(power7_idle) |
237 | /* Now check if user or arch enabled NAP mode */ | |
238 | LOAD_REG_ADDRBASE(r3,powersave_nap) | |
239 | lwz r4,ADDROFF(powersave_nap)(r3) | |
240 | cmpwi 0,r4,0 | |
241 | beqlr | |
8d6f7c5a | 242 | li r3, 1 |
aca79d2b VS |
243 | /* fall through */ |
244 | ||
245 | _GLOBAL(power7_nap) | |
8d6f7c5a | 246 | mr r4,r3 |
7cba160a | 247 | li r3,PNV_THREAD_NAP |
4eae2c9a | 248 | LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode) |
5fa6b6bd | 249 | b pnv_powersave_common |
aca79d2b VS |
250 | /* No return */ |
251 | ||
252 | _GLOBAL(power7_sleep) | |
7cba160a | 253 | li r3,PNV_THREAD_SLEEP |
c733cf83 | 254 | li r4,1 |
4eae2c9a | 255 | LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode) |
5fa6b6bd | 256 | b pnv_powersave_common |
aca79d2b | 257 | /* No return */ |
948cf67c | 258 | |
77b54e9f | 259 | _GLOBAL(power7_winkle) |
bfd1b7ae | 260 | li r3,PNV_THREAD_WINKLE |
77b54e9f | 261 | li r4,1 |
4eae2c9a | 262 | LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode) |
5fa6b6bd | 263 | b pnv_powersave_common |
77b54e9f SP |
264 | /* No return */ |
265 | ||
bbdb760d MS |
266 | #define CHECK_HMI_INTERRUPT \ |
267 | mfspr r0,SPRN_SRR1; \ | |
268 | BEGIN_FTR_SECTION_NESTED(66); \ | |
269 | rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \ | |
270 | FTR_SECTION_ELSE_NESTED(66); \ | |
271 | rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \ | |
272 | ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \ | |
273 | cmpwi r0,0xa; /* Hypervisor maintenance ? */ \ | |
274 | bne 20f; \ | |
275 | /* Invoke opal call to handle hmi */ \ | |
276 | ld r2,PACATOC(r13); \ | |
277 | ld r1,PACAR1(r13); \ | |
278 | std r3,ORIG_GPR3(r1); /* Save original r3 */ \ | |
7cba160a | 279 | li r0,OPAL_HANDLE_HMI; /* Pass opal token argument*/ \ |
db97efff | 280 | bl opal_call_realmode; \ |
bbdb760d MS |
281 | ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \ |
282 | 20: nop; | |
283 | ||
284 | ||
17065671 SP |
285 | /* |
286 | * Called from reset vector. Check whether we have woken up with | |
287 | * hypervisor state loss. If yes, restore hypervisor state and return | |
288 | * back to reset vector. | |
289 | * | |
290 | * r13 - Contents of HSPRG0 | |
291 | * cr3 - set to gt if waking up with partial/complete hypervisor state loss | |
292 | */ | |
5fa6b6bd | 293 | _GLOBAL(pnv_restore_hyp_resource) |
17065671 SP |
294 | /* |
295 | * Check if last bit of HSPGR0 is set. This indicates whether we are | |
296 | * waking up from winkle. | |
297 | */ | |
298 | clrldi r5,r13,63 | |
299 | clrrdi r13,r13,1 | |
300 | cmpwi cr4,r5,1 | |
301 | mtspr SPRN_HSPRG0,r13 | |
302 | ||
303 | lbz r0,PACA_THREAD_IDLE_STATE(r13) | |
304 | cmpwi cr2,r0,PNV_THREAD_NAP | |
5fa6b6bd | 305 | bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */ |
17065671 SP |
306 | |
307 | /* | |
308 | * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking | |
309 | * up from nap. At this stage CR3 shouldn't contains 'gt' since that | |
310 | * indicates we are waking with hypervisor state loss from nap. | |
311 | */ | |
312 | bgt cr3,. | |
313 | ||
314 | blr /* Return back to System Reset vector from where | |
5fa6b6bd | 315 | pnv_restore_hyp_resource was invoked */ |
17065671 SP |
316 | |
317 | ||
5fa6b6bd | 318 | _GLOBAL(pnv_wakeup_tb_loss) |
97eb001f VS |
319 | ld r2,PACATOC(r13); |
320 | ld r1,PACAR1(r13) | |
7cba160a SP |
321 | /* |
322 | * Before entering any idle state, the NVGPRs are saved in the stack | |
323 | * and they are restored before switching to the process context. Hence | |
324 | * until they are restored, they are free to be used. | |
325 | * | |
17065671 SP |
326 | * Save SRR1 and LR in NVGPRs as they might be clobbered in |
327 | * opal_call_realmode (called in CHECK_HMI_INTERRUPT). SRR1 is required | |
328 | * to determine the wakeup reason if we branch to kvm_start_guest. LR | |
329 | * is required to return back to reset vector after hypervisor state | |
330 | * restore is complete. | |
7cba160a | 331 | */ |
17065671 | 332 | mflr r17 |
7cba160a | 333 | mfspr r16,SPRN_SRR1 |
bbdb760d MS |
334 | BEGIN_FTR_SECTION |
335 | CHECK_HMI_INTERRUPT | |
336 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
7cba160a SP |
337 | |
338 | lbz r7,PACA_THREAD_MASK(r13) | |
339 | ld r14,PACA_CORE_IDLE_STATE_PTR(r13) | |
340 | lwarx_loop2: | |
341 | lwarx r15,0,r14 | |
342 | andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT | |
343 | /* | |
344 | * Lock bit is set in one of the 2 cases- | |
345 | * a. In the sleep/winkle enter path, the last thread is executing | |
346 | * fastsleep workaround code. | |
347 | * b. In the wake up path, another thread is executing fastsleep | |
348 | * workaround undo code or resyncing timebase or restoring context | |
349 | * In either case loop until the lock bit is cleared. | |
350 | */ | |
b32aadc1 | 351 | bnel core_idle_lock_held |
7cba160a SP |
352 | |
353 | cmpwi cr2,r15,0 | |
77b54e9f SP |
354 | lbz r4,PACA_SUBCORE_SIBLING_MASK(r13) |
355 | and r4,r4,r15 | |
356 | cmpwi cr1,r4,0 /* Check if first in subcore */ | |
357 | ||
358 | /* | |
359 | * At this stage | |
360 | * cr1 - 0b0100 if first thread to wakeup in subcore | |
361 | * cr2 - 0b0100 if first thread to wakeup in core | |
362 | * cr3- 0b0010 if waking up from sleep or winkle | |
363 | * cr4 - 0b0100 if waking up from winkle | |
364 | */ | |
365 | ||
7cba160a SP |
366 | or r15,r15,r7 /* Set thread bit */ |
367 | ||
77b54e9f | 368 | beq cr1,first_thread_in_subcore |
7cba160a | 369 | |
77b54e9f | 370 | /* Not first thread in subcore to wake up */ |
7cba160a SP |
371 | stwcx. r15,0,r14 |
372 | bne- lwarx_loop2 | |
373 | isync | |
374 | b common_exit | |
375 | ||
77b54e9f SP |
376 | first_thread_in_subcore: |
377 | /* First thread in subcore to wakeup */ | |
7cba160a SP |
378 | ori r15,r15,PNV_CORE_IDLE_LOCK_BIT |
379 | stwcx. r15,0,r14 | |
380 | bne- lwarx_loop2 | |
381 | isync | |
382 | ||
77b54e9f SP |
383 | /* |
384 | * If waking up from sleep, subcore state is not lost. Hence | |
385 | * skip subcore state restore | |
386 | */ | |
387 | bne cr4,subcore_state_restored | |
388 | ||
389 | /* Restore per-subcore state */ | |
390 | ld r4,_SDR1(r1) | |
391 | mtspr SPRN_SDR1,r4 | |
392 | ld r4,_RPR(r1) | |
393 | mtspr SPRN_RPR,r4 | |
394 | ld r4,_AMOR(r1) | |
395 | mtspr SPRN_AMOR,r4 | |
396 | ||
397 | subcore_state_restored: | |
398 | /* | |
399 | * Check if the thread is also the first thread in the core. If not, | |
400 | * skip to clear_lock. | |
401 | */ | |
402 | bne cr2,clear_lock | |
403 | ||
404 | first_thread_in_core: | |
405 | ||
7cba160a SP |
406 | /* |
407 | * First thread in the core waking up from fastsleep. It needs to | |
408 | * call the fastsleep workaround code if the platform requires it. | |
409 | * Call it unconditionally here. The below branch instruction will | |
410 | * be patched out when the idle states are discovered if platform | |
411 | * does not require workaround. | |
412 | */ | |
413 | .global pnv_fastsleep_workaround_at_exit | |
414 | pnv_fastsleep_workaround_at_exit: | |
415 | b fastsleep_workaround_at_exit | |
416 | ||
417 | timebase_resync: | |
418 | /* Do timebase resync if we are waking up from sleep. Use cr3 value | |
419 | * set in exceptions-64s.S */ | |
420 | ble cr3,clear_lock | |
97eb001f | 421 | /* Time base re-sync */ |
7cba160a | 422 | li r0,OPAL_RESYNC_TIMEBASE |
db97efff | 423 | bl opal_call_realmode; |
97eb001f VS |
424 | /* TODO: Check r3 for failure */ |
425 | ||
77b54e9f SP |
426 | /* |
427 | * If waking up from sleep, per core state is not lost, skip to | |
428 | * clear_lock. | |
429 | */ | |
430 | bne cr4,clear_lock | |
431 | ||
432 | /* Restore per core state */ | |
433 | ld r4,_TSCR(r1) | |
434 | mtspr SPRN_TSCR,r4 | |
435 | ld r4,_WORC(r1) | |
436 | mtspr SPRN_WORC,r4 | |
437 | ||
7cba160a SP |
438 | clear_lock: |
439 | andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS | |
440 | lwsync | |
441 | stw r15,0(r14) | |
442 | ||
443 | common_exit: | |
77b54e9f SP |
444 | /* |
445 | * Common to all threads. | |
446 | * | |
447 | * If waking up from sleep, hypervisor state is not lost. Hence | |
448 | * skip hypervisor state restore. | |
449 | */ | |
450 | bne cr4,hypervisor_state_restored | |
451 | ||
452 | /* Waking up from winkle */ | |
453 | ||
454 | /* Restore per thread state */ | |
455 | bl __restore_cpu_power8 | |
456 | ||
457 | /* Restore SLB from PACA */ | |
458 | ld r8,PACA_SLBSHADOWPTR(r13) | |
459 | ||
460 | .rept SLB_NUM_BOLTED | |
461 | li r3, SLBSHADOW_SAVEAREA | |
462 | LDX_BE r5, r8, r3 | |
463 | addi r3, r3, 8 | |
464 | LDX_BE r6, r8, r3 | |
465 | andis. r7,r5,SLB_ESID_V@h | |
466 | beq 1f | |
467 | slbmte r6,r5 | |
468 | 1: addi r8,r8,16 | |
469 | .endr | |
470 | ||
471 | ld r4,_SPURR(r1) | |
472 | mtspr SPRN_SPURR,r4 | |
473 | ld r4,_PURR(r1) | |
474 | mtspr SPRN_PURR,r4 | |
475 | ld r4,_DSCR(r1) | |
476 | mtspr SPRN_DSCR,r4 | |
477 | ld r4,_WORT(r1) | |
478 | mtspr SPRN_WORT,r4 | |
479 | ||
480 | hypervisor_state_restored: | |
481 | ||
7cba160a | 482 | mtspr SPRN_SRR1,r16 |
17065671 SP |
483 | mtlr r17 |
484 | blr /* Return back to System Reset vector from where | |
5fa6b6bd | 485 | pnv_restore_hyp_resource was invoked */ |
97eb001f | 486 | |
7cba160a SP |
487 | fastsleep_workaround_at_exit: |
488 | li r3,1 | |
489 | li r4,0 | |
490 | li r0,OPAL_CONFIG_CPU_IDLE_STATE | |
491 | bl opal_call_realmode | |
492 | b timebase_resync | |
493 | ||
56548fc0 PM |
494 | /* |
495 | * R3 here contains the value that will be returned to the caller | |
496 | * of power7_nap. | |
497 | */ | |
5fa6b6bd | 498 | _GLOBAL(pnv_wakeup_loss) |
948cf67c | 499 | ld r1,PACAR1(r13) |
bbdb760d MS |
500 | BEGIN_FTR_SECTION |
501 | CHECK_HMI_INTERRUPT | |
502 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
948cf67c BH |
503 | REST_NVGPRS(r1) |
504 | REST_GPR(2, r1) | |
56548fc0 | 505 | ld r6,_CCR(r1) |
948cf67c BH |
506 | ld r4,_MSR(r1) |
507 | ld r5,_NIP(r1) | |
508 | addi r1,r1,INT_FRAME_SIZE | |
56548fc0 | 509 | mtcr r6 |
948cf67c BH |
510 | mtspr SPRN_SRR1,r4 |
511 | mtspr SPRN_SRR0,r5 | |
512 | rfid | |
513 | ||
56548fc0 PM |
514 | /* |
515 | * R3 here contains the value that will be returned to the caller | |
516 | * of power7_nap. | |
517 | */ | |
5fa6b6bd | 518 | _GLOBAL(pnv_wakeup_noloss) |
2fde6d20 PM |
519 | lbz r0,PACA_NAPSTATELOST(r13) |
520 | cmpwi r0,0 | |
5fa6b6bd | 521 | bne pnv_wakeup_loss |
bbdb760d MS |
522 | BEGIN_FTR_SECTION |
523 | CHECK_HMI_INTERRUPT | |
524 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
948cf67c | 525 | ld r1,PACAR1(r13) |
0aab3747 | 526 | ld r6,_CCR(r1) |
948cf67c BH |
527 | ld r4,_MSR(r1) |
528 | ld r5,_NIP(r1) | |
529 | addi r1,r1,INT_FRAME_SIZE | |
0aab3747 | 530 | mtcr r6 |
948cf67c BH |
531 | mtspr SPRN_SRR1,r4 |
532 | mtspr SPRN_SRR0,r5 | |
533 | rfid |