Commit | Line | Data |
---|---|---|
948cf67c | 1 | /* |
bcef83a0 SP |
2 | * This file contains idle entry/exit functions for POWER7, |
3 | * POWER8 and POWER9 CPUs. | |
948cf67c BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | */ | |
10 | ||
11 | #include <linux/threads.h> | |
12 | #include <asm/processor.h> | |
13 | #include <asm/page.h> | |
14 | #include <asm/cputable.h> | |
15 | #include <asm/thread_info.h> | |
16 | #include <asm/ppc_asm.h> | |
17 | #include <asm/asm-offsets.h> | |
18 | #include <asm/ppc-opcode.h> | |
7230c564 | 19 | #include <asm/hw_irq.h> |
f0888f70 | 20 | #include <asm/kvm_book3s_asm.h> |
97eb001f | 21 | #include <asm/opal.h> |
7cba160a | 22 | #include <asm/cpuidle.h> |
bf0153c1 | 23 | #include <asm/exception-64s.h> |
f64e8084 | 24 | #include <asm/book3s/64/mmu-hash.h> |
bcef83a0 | 25 | #include <asm/mmu.h> |
948cf67c BH |
26 | |
27 | #undef DEBUG | |
28 | ||
77b54e9f SP |
29 | /* |
30 | * Use unused space in the interrupt stack to save and restore | |
31 | * registers for winkle support. | |
32 | */ | |
33 | #define _SDR1 GPR3 | |
cb0be7ec | 34 | #define _PTCR GPR3 |
77b54e9f SP |
35 | #define _RPR GPR4 |
36 | #define _SPURR GPR5 | |
37 | #define _PURR GPR6 | |
38 | #define _TSCR GPR7 | |
39 | #define _DSCR GPR8 | |
40 | #define _AMOR GPR9 | |
41 | #define _WORT GPR10 | |
42 | #define _WORC GPR11 | |
cb0be7ec | 43 | #define _LPCR GPR12 |
bcef83a0 | 44 | |
09206b60 | 45 | #define PSSCR_EC_ESL_MASK_SHIFTED (PSSCR_EC | PSSCR_ESL) >> 16 |
77b54e9f | 46 | |
aca79d2b VS |
47 | .text |
48 | ||
0dfffb48 SP |
49 | /* |
50 | * Used by threads before entering deep idle states. Saves SPRs | |
51 | * in interrupt stack frame | |
52 | */ | |
53 | save_sprs_to_stack: | |
54 | /* | |
55 | * Note all register i.e per-core, per-subcore or per-thread is saved | |
56 | * here since any thread in the core might wake up first | |
57 | */ | |
bcef83a0 | 58 | BEGIN_FTR_SECTION |
bcef83a0 SP |
59 | /* |
60 | * Note - SDR1 is dropped in Power ISA v3. Hence not restoring | |
61 | * SDR1 here | |
62 | */ | |
cb0be7ec GS |
63 | mfspr r3,SPRN_PTCR |
64 | std r3,_PTCR(r1) | |
65 | mfspr r3,SPRN_LPCR | |
66 | std r3,_LPCR(r1) | |
bcef83a0 | 67 | FTR_SECTION_ELSE |
0dfffb48 SP |
68 | mfspr r3,SPRN_SDR1 |
69 | std r3,_SDR1(r1) | |
bcef83a0 | 70 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300) |
0dfffb48 SP |
71 | mfspr r3,SPRN_RPR |
72 | std r3,_RPR(r1) | |
73 | mfspr r3,SPRN_SPURR | |
74 | std r3,_SPURR(r1) | |
75 | mfspr r3,SPRN_PURR | |
76 | std r3,_PURR(r1) | |
77 | mfspr r3,SPRN_TSCR | |
78 | std r3,_TSCR(r1) | |
79 | mfspr r3,SPRN_DSCR | |
80 | std r3,_DSCR(r1) | |
81 | mfspr r3,SPRN_AMOR | |
82 | std r3,_AMOR(r1) | |
83 | mfspr r3,SPRN_WORT | |
84 | std r3,_WORT(r1) | |
85 | mfspr r3,SPRN_WORC | |
86 | std r3,_WORC(r1) | |
87 | ||
88 | blr | |
89 | ||
b32aadc1 SP |
90 | /* |
91 | * Used by threads when the lock bit of core_idle_state is set. | |
92 | * Threads will spin in HMT_LOW until the lock bit is cleared. | |
93 | * r14 - pointer to core_idle_state | |
94 | * r15 - used to load contents of core_idle_state | |
09b7e37b | 95 | * r9 - used as a temporary variable |
b32aadc1 SP |
96 | */ |
97 | ||
98 | core_idle_lock_held: | |
99 | HMT_LOW | |
100 | 3: lwz r15,0(r14) | |
adbcf8d7 | 101 | andis. r15,r15,PNV_CORE_IDLE_LOCK_BIT@h |
b32aadc1 SP |
102 | bne 3b |
103 | HMT_MEDIUM | |
104 | lwarx r15,0,r14 | |
adbcf8d7 NP |
105 | andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h |
106 | bne- core_idle_lock_held | |
b32aadc1 SP |
107 | blr |
108 | ||
aca79d2b VS |
109 | /* |
110 | * Pass requested state in r3: | |
bcef83a0 SP |
111 | * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8 |
112 | * - Requested STOP state in POWER9 | |
8d6f7c5a ME |
113 | * |
114 | * To check IRQ_HAPPENED in r4 | |
115 | * 0 - don't check | |
116 | * 1 - check | |
4eae2c9a SP |
117 | * |
118 | * Address to 'rfid' to in r5 | |
aca79d2b | 119 | */ |
bf0153c1 | 120 | pnv_powersave_common: |
aca79d2b | 121 | /* Use r3 to pass state nap/sleep/winkle */ |
948cf67c BH |
122 | /* NAP is a state loss, we create a regs frame on the |
123 | * stack, fill it up with the state we care about and | |
124 | * stick a pointer to it in PACAR1. We really only | |
125 | * need to save PC, some CR bits and the NV GPRs, | |
126 | * but for now an interrupt frame will do. | |
127 | */ | |
128 | mflr r0 | |
129 | std r0,16(r1) | |
130 | stdu r1,-INT_FRAME_SIZE(r1) | |
131 | std r0,_LINK(r1) | |
132 | std r0,_NIP(r1) | |
133 | ||
948cf67c BH |
134 | /* Hard disable interrupts */ |
135 | mfmsr r9 | |
136 | rldicl r9,r9,48,1 | |
137 | rotldi r9,r9,16 | |
138 | mtmsrd r9,1 /* hard-disable interrupts */ | |
7230c564 BH |
139 | |
140 | /* Check if something happened while soft-disabled */ | |
141 | lbz r0,PACAIRQHAPPENED(r13) | |
d6a4f709 | 142 | andi. r0,r0,~PACA_IRQ_HARD_DIS@l |
7230c564 | 143 | beq 1f |
8d6f7c5a ME |
144 | cmpwi cr0,r4,0 |
145 | beq 1f | |
7230c564 BH |
146 | addi r1,r1,INT_FRAME_SIZE |
147 | ld r0,16(r1) | |
f57333a7 | 148 | li r3,0 /* Return 0 (no nap) */ |
7230c564 BH |
149 | mtlr r0 |
150 | blr | |
151 | ||
152 | 1: /* We mark irqs hard disabled as this is the state we'll | |
153 | * be in when returning and we need to tell arch_local_irq_restore() | |
154 | * about it | |
155 | */ | |
156 | li r0,PACA_IRQ_HARD_DIS | |
157 | stb r0,PACAIRQHAPPENED(r13) | |
158 | ||
159 | /* We haven't lost state ... yet */ | |
948cf67c | 160 | li r0,0 |
2fde6d20 | 161 | stb r0,PACA_NAPSTATELOST(r13) |
948cf67c BH |
162 | |
163 | /* Continue saving state */ | |
164 | SAVE_GPR(2, r1) | |
165 | SAVE_NVGPRS(r1) | |
aca79d2b VS |
166 | mfcr r4 |
167 | std r4,_CCR(r1) | |
948cf67c BH |
168 | std r9,_MSR(r1) |
169 | std r1,PACAR1(r13) | |
170 | ||
8117ac6a PM |
171 | /* |
172 | * Go to real mode to do the nap, as required by the architecture. | |
173 | * Also, we need to be in real mode before setting hwthread_state, | |
174 | * because as soon as we do that, another thread can switch | |
175 | * the MMU context to the guest. | |
176 | */ | |
4eae2c9a | 177 | LOAD_REG_IMMEDIATE(r7, MSR_IDLE) |
8117ac6a PM |
178 | li r6, MSR_RI |
179 | andc r6, r9, r6 | |
8117ac6a | 180 | mtmsrd r6, 1 /* clear RI before setting SRR0/1 */ |
4eae2c9a SP |
181 | mtspr SPRN_SRR0, r5 |
182 | mtspr SPRN_SRR1, r7 | |
8117ac6a PM |
183 | rfid |
184 | ||
5fa6b6bd SP |
185 | .globl pnv_enter_arch207_idle_mode |
186 | pnv_enter_arch207_idle_mode: | |
56c46222 PM |
187 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
188 | /* Tell KVM we're entering idle */ | |
189 | li r4,KVM_HWTHREAD_IN_IDLE | |
190 | /******************************************************/ | |
191 | /* N O T E W E L L ! ! ! N O T E W E L L */ | |
192 | /* The following store to HSTATE_HWTHREAD_STATE(r13) */ | |
193 | /* MUST occur in real mode, i.e. with the MMU off, */ | |
194 | /* and the MMU must stay off until we clear this flag */ | |
bf0153c1 NP |
195 | /* and test HSTATE_HWTHREAD_REQ(r13) in */ |
196 | /* pnv_powersave_wakeup in this file. */ | |
56c46222 PM |
197 | /* The reason is that another thread can switch the */ |
198 | /* MMU to a guest context whenever this flag is set */ | |
199 | /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */ | |
200 | /* that would potentially cause this thread to start */ | |
201 | /* executing instructions from guest memory in */ | |
202 | /* hypervisor mode, leading to a host crash or data */ | |
203 | /* corruption, or worse. */ | |
204 | /******************************************************/ | |
205 | stb r4,HSTATE_HWTHREAD_STATE(r13) | |
206 | #endif | |
7cba160a | 207 | stb r3,PACA_THREAD_IDLE_STATE(r13) |
77b54e9f SP |
208 | cmpwi cr3,r3,PNV_THREAD_SLEEP |
209 | bge cr3,2f | |
823b7bd5 | 210 | IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP) |
aca79d2b | 211 | /* No return */ |
7cba160a SP |
212 | 2: |
213 | /* Sleep or winkle */ | |
214 | lbz r7,PACA_THREAD_MASK(r13) | |
215 | ld r14,PACA_CORE_IDLE_STATE_PTR(r13) | |
0d7720a2 NP |
216 | li r5,0 |
217 | beq cr3,3f | |
218 | lis r5,PNV_CORE_IDLE_WINKLE_COUNT@h | |
219 | 3: | |
7cba160a SP |
220 | lwarx_loop1: |
221 | lwarx r15,0,r14 | |
b32aadc1 | 222 | |
adbcf8d7 NP |
223 | andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h |
224 | bnel- core_idle_lock_held | |
b32aadc1 | 225 | |
0d7720a2 | 226 | add r15,r15,r5 /* Add if winkle */ |
7cba160a SP |
227 | andc r15,r15,r7 /* Clear thread bit */ |
228 | ||
0d7720a2 | 229 | andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS |
7cba160a SP |
230 | |
231 | /* | |
232 | * If cr0 = 0, then current thread is the last thread of the core entering | |
233 | * sleep. Last thread needs to execute the hardware bug workaround code if | |
234 | * required by the platform. | |
235 | * Make the workaround call unconditionally here. The below branch call is | |
236 | * patched out when the idle states are discovered if the platform does not | |
237 | * require it. | |
238 | */ | |
239 | .global pnv_fastsleep_workaround_at_entry | |
240 | pnv_fastsleep_workaround_at_entry: | |
241 | beq fastsleep_workaround_at_entry | |
242 | ||
243 | stwcx. r15,0,r14 | |
244 | bne- lwarx_loop1 | |
245 | isync | |
246 | ||
77b54e9f SP |
247 | common_enter: /* common code for all the threads entering sleep or winkle */ |
248 | bgt cr3,enter_winkle | |
823b7bd5 | 249 | IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP) |
7cba160a SP |
250 | |
251 | fastsleep_workaround_at_entry: | |
adbcf8d7 | 252 | oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h |
7cba160a SP |
253 | stwcx. r15,0,r14 |
254 | bne- lwarx_loop1 | |
255 | isync | |
256 | ||
257 | /* Fast sleep workaround */ | |
258 | li r3,1 | |
259 | li r4,1 | |
ab9bad0e | 260 | bl opal_config_cpu_idle_state |
7cba160a | 261 | |
adbcf8d7 NP |
262 | /* Unlock */ |
263 | xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h | |
7cba160a | 264 | lwsync |
adbcf8d7 | 265 | stw r15,0(r14) |
7cba160a SP |
266 | b common_enter |
267 | ||
77b54e9f | 268 | enter_winkle: |
0dfffb48 SP |
269 | bl save_sprs_to_stack |
270 | ||
823b7bd5 | 271 | IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE) |
f0888f70 | 272 | |
bcef83a0 | 273 | /* |
09206b60 | 274 | * r3 - PSSCR value corresponding to the requested stop state. |
bcef83a0 SP |
275 | */ |
276 | power_enter_stop: | |
56c46222 PM |
277 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
278 | /* Tell KVM we're entering idle */ | |
279 | li r4,KVM_HWTHREAD_IN_IDLE | |
280 | /* DO THIS IN REAL MODE! See comment above. */ | |
281 | stb r4,HSTATE_HWTHREAD_STATE(r13) | |
282 | #endif | |
09206b60 GS |
283 | /* |
284 | * Check if we are executing the lite variant with ESL=EC=0 | |
285 | */ | |
286 | andis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED | |
287 | clrldi r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */ | |
424f8acd | 288 | bne .Lhandle_esl_ec_set |
09206b60 GS |
289 | IDLE_STATE_ENTER_SEQ(PPC_STOP) |
290 | li r3,0 /* Since we didn't lose state, return 0 */ | |
291 | b pnv_wakeup_noloss | |
424f8acd GS |
292 | |
293 | .Lhandle_esl_ec_set: | |
bcef83a0 SP |
294 | /* |
295 | * Check if the requested state is a deep idle state. | |
296 | */ | |
424f8acd | 297 | LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state) |
bcef83a0 SP |
298 | ld r4,ADDROFF(pnv_first_deep_stop_state)(r5) |
299 | cmpd r3,r4 | |
424f8acd | 300 | bge .Lhandle_deep_stop |
823b7bd5 | 301 | IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP) |
424f8acd | 302 | .Lhandle_deep_stop: |
bcef83a0 SP |
303 | /* |
304 | * Entering deep idle state. | |
305 | * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to | |
306 | * stack and enter stop | |
307 | */ | |
308 | lbz r7,PACA_THREAD_MASK(r13) | |
309 | ld r14,PACA_CORE_IDLE_STATE_PTR(r13) | |
310 | ||
311 | lwarx_loop_stop: | |
312 | lwarx r15,0,r14 | |
adbcf8d7 NP |
313 | andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h |
314 | bnel- core_idle_lock_held | |
bcef83a0 SP |
315 | andc r15,r15,r7 /* Clear thread bit */ |
316 | ||
317 | stwcx. r15,0,r14 | |
318 | bne- lwarx_loop_stop | |
319 | isync | |
320 | ||
321 | bl save_sprs_to_stack | |
322 | ||
823b7bd5 | 323 | IDLE_STATE_ENTER_SEQ_NORET(PPC_STOP) |
bcef83a0 | 324 | |
aca79d2b VS |
325 | _GLOBAL(power7_idle) |
326 | /* Now check if user or arch enabled NAP mode */ | |
327 | LOAD_REG_ADDRBASE(r3,powersave_nap) | |
328 | lwz r4,ADDROFF(powersave_nap)(r3) | |
329 | cmpwi 0,r4,0 | |
330 | beqlr | |
8d6f7c5a | 331 | li r3, 1 |
aca79d2b VS |
332 | /* fall through */ |
333 | ||
334 | _GLOBAL(power7_nap) | |
8d6f7c5a | 335 | mr r4,r3 |
7cba160a | 336 | li r3,PNV_THREAD_NAP |
4eae2c9a | 337 | LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode) |
5fa6b6bd | 338 | b pnv_powersave_common |
aca79d2b VS |
339 | /* No return */ |
340 | ||
341 | _GLOBAL(power7_sleep) | |
7cba160a | 342 | li r3,PNV_THREAD_SLEEP |
c733cf83 | 343 | li r4,1 |
4eae2c9a | 344 | LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode) |
5fa6b6bd | 345 | b pnv_powersave_common |
aca79d2b | 346 | /* No return */ |
948cf67c | 347 | |
77b54e9f | 348 | _GLOBAL(power7_winkle) |
bfd1b7ae | 349 | li r3,PNV_THREAD_WINKLE |
77b54e9f | 350 | li r4,1 |
4eae2c9a | 351 | LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode) |
5fa6b6bd | 352 | b pnv_powersave_common |
77b54e9f SP |
353 | /* No return */ |
354 | ||
bbdb760d MS |
355 | #define CHECK_HMI_INTERRUPT \ |
356 | mfspr r0,SPRN_SRR1; \ | |
357 | BEGIN_FTR_SECTION_NESTED(66); \ | |
358 | rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \ | |
359 | FTR_SECTION_ELSE_NESTED(66); \ | |
360 | rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \ | |
361 | ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \ | |
362 | cmpwi r0,0xa; /* Hypervisor maintenance ? */ \ | |
363 | bne 20f; \ | |
364 | /* Invoke opal call to handle hmi */ \ | |
365 | ld r2,PACATOC(r13); \ | |
366 | ld r1,PACAR1(r13); \ | |
367 | std r3,ORIG_GPR3(r1); /* Save original r3 */ \ | |
fd7bacbc MS |
368 | li r3,0; /* NULL argument */ \ |
369 | bl hmi_exception_realmode; \ | |
370 | nop; \ | |
bbdb760d MS |
371 | ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \ |
372 | 20: nop; | |
373 | ||
bcef83a0 | 374 | /* |
09206b60 GS |
375 | * r3 - The PSSCR value corresponding to the stop state. |
376 | * r4 - The PSSCR mask corrresonding to the stop state. | |
bcef83a0 SP |
377 | */ |
378 | _GLOBAL(power9_idle_stop) | |
09206b60 GS |
379 | mfspr r5,SPRN_PSSCR |
380 | andc r5,r5,r4 | |
381 | or r3,r3,r5 | |
22c6663d | 382 | std r3, PACA_REQ_PSSCR(r13) |
09206b60 | 383 | mtspr SPRN_PSSCR,r3 |
bcef83a0 | 384 | LOAD_REG_ADDR(r5,power_enter_stop) |
09206b60 | 385 | li r4,1 |
bcef83a0 SP |
386 | b pnv_powersave_common |
387 | /* No return */ | |
17ed4c8f | 388 | |
17065671 | 389 | /* |
17ed4c8f GS |
390 | * On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1, |
391 | * HSPRG0 will be set to the HSPRG0 value of one of the | |
392 | * threads in this core. Thus the value we have in r13 | |
393 | * may not be this thread's paca pointer. | |
394 | * | |
395 | * Fortunately, the TIR remains invariant. Since this thread's | |
396 | * paca pointer is recorded in all its sibling's paca, we can | |
397 | * correctly recover this thread's paca pointer if we | |
398 | * know the index of this thread in the core. | |
399 | * | |
400 | * This index can be obtained from the TIR. | |
17065671 | 401 | * |
17ed4c8f GS |
402 | * i.e, thread's position in the core = TIR. |
403 | * If this value is i, then this thread's paca is | |
404 | * paca->thread_sibling_pacas[i]. | |
405 | */ | |
406 | power9_dd1_recover_paca: | |
407 | mfspr r4, SPRN_TIR | |
408 | /* | |
409 | * Since each entry in thread_sibling_pacas is 8 bytes | |
410 | * we need to left-shift by 3 bits. Thus r4 = i * 8 | |
411 | */ | |
412 | sldi r4, r4, 3 | |
413 | /* Get &paca->thread_sibling_pacas[0] in r5 */ | |
414 | ld r5, PACA_SIBLING_PACA_PTRS(r13) | |
415 | /* Load paca->thread_sibling_pacas[i] into r13 */ | |
416 | ldx r13, r4, r5 | |
417 | SET_PACA(r13) | |
17ed4c8f GS |
418 | /* |
419 | * Indicate that we have lost NVGPR state | |
420 | * which needs to be restored from the stack. | |
421 | */ | |
422 | li r3, 1 | |
bbb075dd | 423 | stb r3,PACA_NAPSTATELOST(r13) |
17ed4c8f GS |
424 | blr |
425 | ||
1945bc45 NP |
426 | /* |
427 | * Called from machine check handler for powersave wakeups. | |
428 | * Low level machine check processing has already been done. Now just | |
429 | * go through the wake up path to get everything in order. | |
430 | * | |
431 | * r3 - The original SRR1 value. | |
432 | * Original SRR[01] have been clobbered. | |
433 | * MSR_RI is clear. | |
434 | */ | |
435 | .global pnv_powersave_wakeup_mce | |
436 | pnv_powersave_wakeup_mce: | |
437 | /* Set cr3 for pnv_powersave_wakeup */ | |
438 | rlwinm r11,r3,47-31,30,31 | |
439 | cmpwi cr3,r11,2 | |
440 | ||
441 | /* | |
442 | * Now put the original SRR1 with SRR1_WAKEMCE_RESVD as the wake | |
443 | * reason into SRR1, which allows reuse of the system reset wakeup | |
444 | * code without being mistaken for another type of wakeup. | |
445 | */ | |
446 | oris r3,r3,SRR1_WAKEMCE_RESVD@h | |
447 | mtspr SPRN_SRR1,r3 | |
448 | ||
449 | b pnv_powersave_wakeup | |
450 | ||
544686ca NP |
451 | /* |
452 | * Called from reset vector for powersave wakeups. | |
17065671 SP |
453 | * cr3 - set to gt if waking up with partial/complete hypervisor state loss |
454 | */ | |
bf0153c1 NP |
455 | .global pnv_powersave_wakeup |
456 | pnv_powersave_wakeup: | |
9cba253d NP |
457 | ld r2, PACATOC(r13) |
458 | ||
bcef83a0 | 459 | BEGIN_FTR_SECTION |
9cba253d NP |
460 | BEGIN_FTR_SECTION_NESTED(70) |
461 | bl power9_dd1_recover_paca | |
462 | END_FTR_SECTION_NESTED_IFSET(CPU_FTR_POWER9_DD1, 70) | |
10101aa9 NP |
463 | bl pnv_restore_hyp_resource_arch300 |
464 | FTR_SECTION_ELSE | |
465 | bl pnv_restore_hyp_resource_arch207 | |
466 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300) | |
bf0153c1 NP |
467 | |
468 | li r0,PNV_THREAD_RUNNING | |
469 | stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */ | |
470 | ||
471 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE | |
472 | li r0,KVM_HWTHREAD_IN_KERNEL | |
473 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
474 | /* Order setting hwthread_state vs. testing hwthread_req */ | |
475 | sync | |
476 | lbz r0,HSTATE_HWTHREAD_REQ(r13) | |
477 | cmpwi r0,0 | |
478 | beq 1f | |
479 | b kvm_start_guest | |
480 | 1: | |
481 | #endif | |
482 | ||
483 | /* Return SRR1 from power7_nap() */ | |
484 | mfspr r3,SPRN_SRR1 | |
485 | blt cr3,pnv_wakeup_noloss | |
486 | b pnv_wakeup_loss | |
487 | ||
17065671 | 488 | /* |
bf0153c1 NP |
489 | * Check whether we have woken up with hypervisor state loss. |
490 | * If yes, restore hypervisor state and return back to link. | |
17065671 | 491 | * |
17065671 SP |
492 | * cr3 - set to gt if waking up with partial/complete hypervisor state loss |
493 | */ | |
10101aa9 | 494 | pnv_restore_hyp_resource_arch300: |
bcef83a0 SP |
495 | /* |
496 | * POWER ISA 3. Use PSSCR to determine if we | |
497 | * are waking up from deep idle state | |
498 | */ | |
499 | LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state) | |
500 | ld r4,ADDROFF(pnv_first_deep_stop_state)(r5) | |
501 | ||
22c6663d GS |
502 | BEGIN_FTR_SECTION_NESTED(71) |
503 | /* | |
504 | * Assume that we are waking up from the state | |
505 | * same as the Requested Level (RL) in the PSSCR | |
506 | * which are Bits 60-63 | |
507 | */ | |
508 | ld r5,PACA_REQ_PSSCR(r13) | |
509 | rldicl r5,r5,0,60 | |
510 | FTR_SECTION_ELSE_NESTED(71) | |
17065671 | 511 | /* |
bcef83a0 SP |
512 | * 0-3 bits correspond to Power-Saving Level Status |
513 | * which indicates the idle state we are waking up from | |
514 | */ | |
22c6663d | 515 | mfspr r5, SPRN_PSSCR |
bcef83a0 | 516 | rldicl r5,r5,4,60 |
22c6663d | 517 | ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_POWER9_DD1, 71) |
bcef83a0 | 518 | cmpd cr4,r5,r4 |
bf0153c1 | 519 | bge cr4,pnv_wakeup_tb_loss /* returns to caller */ |
bcef83a0 | 520 | |
bf0153c1 | 521 | blr /* Waking up without hypervisor state loss. */ |
bcef83a0 | 522 | |
10101aa9 NP |
523 | /* Same calling convention as arch300 */ |
524 | pnv_restore_hyp_resource_arch207: | |
bcef83a0 SP |
525 | /* |
526 | * POWER ISA 2.07 or less. | |
0d7720a2 | 527 | * Check if we slept with sleep or winkle. |
17065671 | 528 | */ |
0d7720a2 NP |
529 | lbz r4,PACA_THREAD_IDLE_STATE(r13) |
530 | cmpwi cr2,r4,PNV_THREAD_NAP | |
531 | bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */ | |
17065671 SP |
532 | |
533 | /* | |
534 | * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking | |
535 | * up from nap. At this stage CR3 shouldn't contains 'gt' since that | |
536 | * indicates we are waking with hypervisor state loss from nap. | |
537 | */ | |
538 | bgt cr3,. | |
539 | ||
bf0153c1 | 540 | blr /* Waking up without hypervisor state loss */ |
17065671 | 541 | |
bcef83a0 SP |
542 | /* |
543 | * Called if waking up from idle state which can cause either partial or | |
544 | * complete hyp state loss. | |
545 | * In POWER8, called if waking up from fastsleep or winkle | |
546 | * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state | |
547 | * | |
548 | * r13 - PACA | |
549 | * cr3 - gt if waking up with partial/complete hypervisor state loss | |
0d7720a2 NP |
550 | * |
551 | * If ISA300: | |
bd00a240 | 552 | * cr4 - gt or eq if waking up from complete hypervisor state loss. |
0d7720a2 NP |
553 | * |
554 | * If ISA207: | |
555 | * r4 - PACA_THREAD_IDLE_STATE | |
bcef83a0 | 556 | */ |
bf0153c1 | 557 | pnv_wakeup_tb_loss: |
97eb001f | 558 | ld r1,PACAR1(r13) |
7cba160a | 559 | /* |
6d98ce0b NP |
560 | * Before entering any idle state, the NVGPRs are saved in the stack. |
561 | * If there was a state loss, or PACA_NAPSTATELOST was set, then the | |
562 | * NVGPRs are restored. If we are here, it is likely that state is lost, | |
563 | * but not guaranteed -- neither ISA207 nor ISA300 tests to reach | |
564 | * here are the same as the test to restore NVGPRS: | |
565 | * PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300, | |
566 | * and SRR1 test for restoring NVGPRs. | |
567 | * | |
568 | * We are about to clobber NVGPRs now, so set NAPSTATELOST to | |
569 | * guarantee they will always be restored. This might be tightened | |
570 | * with careful reading of specs (particularly for ISA300) but this | |
571 | * is already a slow wakeup path and it's simpler to be safe. | |
572 | */ | |
573 | li r0,1 | |
574 | stb r0,PACA_NAPSTATELOST(r13) | |
575 | ||
576 | /* | |
7cba160a | 577 | * |
17065671 | 578 | * Save SRR1 and LR in NVGPRs as they might be clobbered in |
69c592ed | 579 | * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required |
17065671 SP |
580 | * to determine the wakeup reason if we branch to kvm_start_guest. LR |
581 | * is required to return back to reset vector after hypervisor state | |
582 | * restore is complete. | |
7cba160a | 583 | */ |
0d7720a2 | 584 | mr r18,r4 |
17065671 | 585 | mflr r17 |
7cba160a | 586 | mfspr r16,SPRN_SRR1 |
bbdb760d MS |
587 | BEGIN_FTR_SECTION |
588 | CHECK_HMI_INTERRUPT | |
589 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
7cba160a | 590 | |
7cba160a | 591 | ld r14,PACA_CORE_IDLE_STATE_PTR(r13) |
e420249d NP |
592 | lbz r7,PACA_THREAD_MASK(r13) |
593 | ||
7cba160a | 594 | /* |
e420249d NP |
595 | * Take the core lock to synchronize against other threads. |
596 | * | |
7cba160a SP |
597 | * Lock bit is set in one of the 2 cases- |
598 | * a. In the sleep/winkle enter path, the last thread is executing | |
599 | * fastsleep workaround code. | |
600 | * b. In the wake up path, another thread is executing fastsleep | |
601 | * workaround undo code or resyncing timebase or restoring context | |
602 | * In either case loop until the lock bit is cleared. | |
603 | */ | |
e420249d NP |
604 | 1: |
605 | lwarx r15,0,r14 | |
606 | andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h | |
adbcf8d7 | 607 | bnel- core_idle_lock_held |
e420249d NP |
608 | oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h |
609 | stwcx. r15,0,r14 | |
610 | bne- 1b | |
611 | isync | |
7cba160a | 612 | |
adbcf8d7 NP |
613 | andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS |
614 | cmpwi cr2,r9,0 | |
77b54e9f SP |
615 | |
616 | /* | |
617 | * At this stage | |
bcef83a0 SP |
618 | * cr2 - eq if first thread to wakeup in core |
619 | * cr3- gt if waking up with partial/complete hypervisor state loss | |
0d7720a2 | 620 | * ISA300: |
bd00a240 | 621 | * cr4 - gt or eq if waking up from complete hypervisor state loss. |
77b54e9f SP |
622 | */ |
623 | ||
bcef83a0 | 624 | BEGIN_FTR_SECTION |
0d7720a2 NP |
625 | /* |
626 | * Were we in winkle? | |
627 | * If yes, check if all threads were in winkle, decrement our | |
628 | * winkle count, set all thread winkle bits if all were in winkle. | |
629 | * Check if our thread has a winkle bit set, and set cr4 accordingly | |
630 | * (to match ISA300, above). Pseudo-code for core idle state | |
631 | * transitions for ISA207 is as follows (everything happens atomically | |
632 | * due to store conditional and/or lock bit): | |
633 | * | |
634 | * nap_idle() { } | |
635 | * nap_wake() { } | |
636 | * | |
637 | * sleep_idle() | |
638 | * { | |
639 | * core_idle_state &= ~thread_in_core | |
640 | * } | |
641 | * | |
642 | * sleep_wake() | |
643 | * { | |
644 | * bool first_in_core, first_in_subcore; | |
645 | * | |
646 | * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0; | |
647 | * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0; | |
648 | * | |
649 | * core_idle_state |= thread_in_core; | |
650 | * } | |
651 | * | |
652 | * winkle_idle() | |
653 | * { | |
654 | * core_idle_state &= ~thread_in_core; | |
655 | * core_idle_state += 1 << WINKLE_COUNT_SHIFT; | |
656 | * } | |
657 | * | |
658 | * winkle_wake() | |
659 | * { | |
660 | * bool first_in_core, first_in_subcore, winkle_state_lost; | |
661 | * | |
662 | * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0; | |
663 | * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0; | |
664 | * | |
665 | * core_idle_state |= thread_in_core; | |
666 | * | |
667 | * if ((core_idle_state & WINKLE_MASK) == (8 << WINKLE_COUNT_SIHFT)) | |
668 | * core_idle_state |= THREAD_WINKLE_BITS; | |
669 | * core_idle_state -= 1 << WINKLE_COUNT_SHIFT; | |
670 | * | |
671 | * winkle_state_lost = core_idle_state & | |
672 | * (thread_in_core << WINKLE_THREAD_SHIFT); | |
673 | * core_idle_state &= ~(thread_in_core << WINKLE_THREAD_SHIFT); | |
674 | * } | |
675 | * | |
676 | */ | |
677 | cmpwi r18,PNV_THREAD_WINKLE | |
678 | bne 2f | |
679 | andis. r9,r15,PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT@h | |
680 | subis r15,r15,PNV_CORE_IDLE_WINKLE_COUNT@h | |
681 | beq 2f | |
682 | ori r15,r15,PNV_CORE_IDLE_THREAD_WINKLE_BITS /* all were winkle */ | |
683 | 2: | |
684 | /* Shift thread bit to winkle mask, then test if this thread is set, | |
685 | * and remove it from the winkle bits */ | |
686 | slwi r8,r7,8 | |
687 | and r8,r8,r15 | |
688 | andc r15,r15,r8 | |
689 | cmpwi cr4,r8,1 /* cr4 will be gt if our bit is set, lt if not */ | |
690 | ||
bcef83a0 SP |
691 | lbz r4,PACA_SUBCORE_SIBLING_MASK(r13) |
692 | and r4,r4,r15 | |
693 | cmpwi r4,0 /* Check if first in subcore */ | |
694 | ||
695 | or r15,r15,r7 /* Set thread bit */ | |
696 | beq first_thread_in_subcore | |
697 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) | |
698 | ||
699 | or r15,r15,r7 /* Set thread bit */ | |
700 | beq cr2,first_thread_in_core | |
701 | ||
702 | /* Not first thread in core or subcore to wake up */ | |
703 | b clear_lock | |
704 | ||
705 | first_thread_in_subcore: | |
77b54e9f SP |
706 | /* |
707 | * If waking up from sleep, subcore state is not lost. Hence | |
708 | * skip subcore state restore | |
709 | */ | |
bd00a240 | 710 | blt cr4,subcore_state_restored |
77b54e9f SP |
711 | |
712 | /* Restore per-subcore state */ | |
713 | ld r4,_SDR1(r1) | |
714 | mtspr SPRN_SDR1,r4 | |
bcef83a0 | 715 | |
77b54e9f SP |
716 | ld r4,_RPR(r1) |
717 | mtspr SPRN_RPR,r4 | |
718 | ld r4,_AMOR(r1) | |
719 | mtspr SPRN_AMOR,r4 | |
720 | ||
721 | subcore_state_restored: | |
722 | /* | |
723 | * Check if the thread is also the first thread in the core. If not, | |
724 | * skip to clear_lock. | |
725 | */ | |
726 | bne cr2,clear_lock | |
727 | ||
728 | first_thread_in_core: | |
729 | ||
7cba160a | 730 | /* |
bcef83a0 SP |
731 | * First thread in the core waking up from any state which can cause |
732 | * partial or complete hypervisor state loss. It needs to | |
7cba160a SP |
733 | * call the fastsleep workaround code if the platform requires it. |
734 | * Call it unconditionally here. The below branch instruction will | |
bcef83a0 SP |
735 | * be patched out if the platform does not have fastsleep or does not |
736 | * require the workaround. Patching will be performed during the | |
737 | * discovery of idle-states. | |
7cba160a SP |
738 | */ |
739 | .global pnv_fastsleep_workaround_at_exit | |
740 | pnv_fastsleep_workaround_at_exit: | |
741 | b fastsleep_workaround_at_exit | |
742 | ||
743 | timebase_resync: | |
bcef83a0 SP |
744 | /* |
745 | * Use cr3 which indicates that we are waking up with atleast partial | |
746 | * hypervisor state loss to determine if TIMEBASE RESYNC is needed. | |
747 | */ | |
ec486735 | 748 | ble cr3,.Ltb_resynced |
97eb001f | 749 | /* Time base re-sync */ |
ab9bad0e | 750 | bl opal_resync_timebase; |
77b54e9f | 751 | /* |
ec486735 GS |
752 | * If waking up from sleep (POWER8), per core state |
753 | * is not lost, skip to clear_lock. | |
77b54e9f | 754 | */ |
ec486735 | 755 | .Ltb_resynced: |
bd00a240 | 756 | blt cr4,clear_lock |
77b54e9f | 757 | |
bcef83a0 SP |
758 | /* |
759 | * First thread in the core to wake up and its waking up with | |
760 | * complete hypervisor state loss. Restore per core hypervisor | |
761 | * state. | |
762 | */ | |
763 | BEGIN_FTR_SECTION | |
764 | ld r4,_PTCR(r1) | |
765 | mtspr SPRN_PTCR,r4 | |
766 | ld r4,_RPR(r1) | |
767 | mtspr SPRN_RPR,r4 | |
768 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
769 | ||
77b54e9f SP |
770 | ld r4,_TSCR(r1) |
771 | mtspr SPRN_TSCR,r4 | |
772 | ld r4,_WORC(r1) | |
773 | mtspr SPRN_WORC,r4 | |
774 | ||
7cba160a | 775 | clear_lock: |
adbcf8d7 | 776 | xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h |
7cba160a SP |
777 | lwsync |
778 | stw r15,0(r14) | |
779 | ||
780 | common_exit: | |
77b54e9f SP |
781 | /* |
782 | * Common to all threads. | |
783 | * | |
784 | * If waking up from sleep, hypervisor state is not lost. Hence | |
785 | * skip hypervisor state restore. | |
786 | */ | |
bd00a240 | 787 | blt cr4,hypervisor_state_restored |
77b54e9f SP |
788 | |
789 | /* Waking up from winkle */ | |
790 | ||
bcef83a0 SP |
791 | BEGIN_MMU_FTR_SECTION |
792 | b no_segments | |
5a25b6f5 | 793 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX) |
77b54e9f SP |
794 | /* Restore SLB from PACA */ |
795 | ld r8,PACA_SLBSHADOWPTR(r13) | |
796 | ||
797 | .rept SLB_NUM_BOLTED | |
798 | li r3, SLBSHADOW_SAVEAREA | |
799 | LDX_BE r5, r8, r3 | |
800 | addi r3, r3, 8 | |
801 | LDX_BE r6, r8, r3 | |
802 | andis. r7,r5,SLB_ESID_V@h | |
803 | beq 1f | |
804 | slbmte r6,r5 | |
805 | 1: addi r8,r8,16 | |
806 | .endr | |
bcef83a0 SP |
807 | no_segments: |
808 | ||
809 | /* Restore per thread state */ | |
77b54e9f SP |
810 | |
811 | ld r4,_SPURR(r1) | |
812 | mtspr SPRN_SPURR,r4 | |
813 | ld r4,_PURR(r1) | |
814 | mtspr SPRN_PURR,r4 | |
815 | ld r4,_DSCR(r1) | |
816 | mtspr SPRN_DSCR,r4 | |
817 | ld r4,_WORT(r1) | |
818 | mtspr SPRN_WORT,r4 | |
819 | ||
bcef83a0 SP |
820 | /* Call cur_cpu_spec->cpu_restore() */ |
821 | LOAD_REG_ADDR(r4, cur_cpu_spec) | |
822 | ld r4,0(r4) | |
823 | ld r12,CPU_SPEC_RESTORE(r4) | |
824 | #ifdef PPC64_ELF_ABI_v1 | |
825 | ld r12,0(r12) | |
826 | #endif | |
827 | mtctr r12 | |
828 | bctrl | |
829 | ||
cb0be7ec GS |
830 | BEGIN_FTR_SECTION |
831 | ld r4,_LPCR(r1) | |
832 | mtspr SPRN_LPCR,r4 | |
833 | END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) | |
77b54e9f SP |
834 | hypervisor_state_restored: |
835 | ||
7cba160a | 836 | mtspr SPRN_SRR1,r16 |
17065671 | 837 | mtlr r17 |
bf0153c1 | 838 | blr /* return to pnv_powersave_wakeup */ |
97eb001f | 839 | |
7cba160a SP |
840 | fastsleep_workaround_at_exit: |
841 | li r3,1 | |
842 | li r4,0 | |
ab9bad0e | 843 | bl opal_config_cpu_idle_state |
7cba160a SP |
844 | b timebase_resync |
845 | ||
56548fc0 PM |
846 | /* |
847 | * R3 here contains the value that will be returned to the caller | |
848 | * of power7_nap. | |
849 | */ | |
bf0153c1 NP |
850 | .global pnv_wakeup_loss |
851 | pnv_wakeup_loss: | |
948cf67c | 852 | ld r1,PACAR1(r13) |
bbdb760d MS |
853 | BEGIN_FTR_SECTION |
854 | CHECK_HMI_INTERRUPT | |
855 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
948cf67c BH |
856 | REST_NVGPRS(r1) |
857 | REST_GPR(2, r1) | |
56548fc0 | 858 | ld r6,_CCR(r1) |
948cf67c BH |
859 | ld r4,_MSR(r1) |
860 | ld r5,_NIP(r1) | |
861 | addi r1,r1,INT_FRAME_SIZE | |
56548fc0 | 862 | mtcr r6 |
948cf67c BH |
863 | mtspr SPRN_SRR1,r4 |
864 | mtspr SPRN_SRR0,r5 | |
865 | rfid | |
866 | ||
56548fc0 PM |
867 | /* |
868 | * R3 here contains the value that will be returned to the caller | |
869 | * of power7_nap. | |
870 | */ | |
bf0153c1 | 871 | pnv_wakeup_noloss: |
2fde6d20 PM |
872 | lbz r0,PACA_NAPSTATELOST(r13) |
873 | cmpwi r0,0 | |
5fa6b6bd | 874 | bne pnv_wakeup_loss |
bbdb760d MS |
875 | BEGIN_FTR_SECTION |
876 | CHECK_HMI_INTERRUPT | |
877 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
948cf67c | 878 | ld r1,PACAR1(r13) |
0aab3747 | 879 | ld r6,_CCR(r1) |
948cf67c BH |
880 | ld r4,_MSR(r1) |
881 | ld r5,_NIP(r1) | |
882 | addi r1,r1,INT_FRAME_SIZE | |
0aab3747 | 883 | mtcr r6 |
948cf67c BH |
884 | mtspr SPRN_SRR1,r4 |
885 | mtspr SPRN_SRR0,r5 | |
886 | rfid |