[linux-2.6-block.git] / arch / powerpc / kernel / hw_breakpoint.c

/*
 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
 * using the CPU's debug registers. Derived from
 * "arch/x86/kernel/hw_breakpoint.c"
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Copyright 2010 IBM Corporation
 * Author: K.Prasad <prasad@linux.vnet.ibm.com>
 *
 */

#include <linux/hw_breakpoint.h>
#include <linux/notifier.h>
#include <linux/kprobes.h>
#include <linux/percpu.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/debugfs.h>
#include <linux/init.h>

#include <asm/hw_breakpoint.h>
#include <asm/processor.h>
#include <asm/sstep.h>
#include <asm/debug.h>
#include <asm/debugfs.h>
#include <asm/hvcall.h>
#include <linux/uaccess.h>

/*
 * Stores the breakpoints currently in use on each breakpoint address
 * register for every cpu
 */
static DEFINE_PER_CPU(struct perf_event *, bp_per_reg);

/*
 * Returns total number of data or instruction breakpoints available.
 */
int hw_breakpoint_slots(int type)
{
	if (type == TYPE_DATA)
		return HBP_NUM;
	return 0;		/* no instruction breakpoints available */
}

/*
 * Install a perf counter breakpoint.
 *
 * We seek a free debug address register and use it for this
 * breakpoint.
 *
 * Atomic: we hold the counter->ctx->lock and we only handle variables
 * and registers local to this cpu.
 */
int arch_install_hw_breakpoint(struct perf_event *bp)
{
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	struct perf_event **slot = this_cpu_ptr(&bp_per_reg);

	*slot = bp;

	/*
	 * Do not install DABR values if the instruction must be single-stepped.
	 * If so, DABR will be populated in single_step_dabr_instruction().
	 */
	if (current->thread.last_hit_ubp != bp)
		__set_breakpoint(info);

	return 0;
}

/*
 * Uninstall the breakpoint contained in the given counter.
 *
 * First we search the debug address register it uses and then we disable
 * it.
 *
 * Atomic: we hold the counter->ctx->lock and we only handle variables
 * and registers local to this cpu.
 */
void arch_uninstall_hw_breakpoint(struct perf_event *bp)
{
	struct perf_event **slot = this_cpu_ptr(&bp_per_reg);

	if (*slot != bp) {
		WARN_ONCE(1, "Can't find the breakpoint");
		return;
	}

	*slot = NULL;
	hw_breakpoint_disable();
}

/*
 * Perform cleanup of arch-specific counters during unregistration
 * of the perf-event
 */
void arch_unregister_hw_breakpoint(struct perf_event *bp)
{
	/*
	 * If the breakpoint is unregistered between a hw_breakpoint_handler()
	 * and the single_step_dabr_instruction(), then cleanup the breakpoint
	 * restoration variables to prevent dangling pointers.
	 * FIXME, this should not be using bp->ctx at all! Sayeth peterz.
	 */
	if (bp->ctx && bp->ctx->task && bp->ctx->task != ((void *)-1L))
		bp->ctx->task->thread.last_hit_ubp = NULL;
}

/*
 * Check for virtual address in kernel space.
 */
int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
{
	return is_kernel_addr(hw->address);
}

int arch_bp_generic_fields(int type, int *gen_bp_type)
{
	*gen_bp_type = 0;
	if (type & HW_BRK_TYPE_READ)
		*gen_bp_type |= HW_BREAKPOINT_R;
	if (type & HW_BRK_TYPE_WRITE)
		*gen_bp_type |= HW_BREAKPOINT_W;
	if (*gen_bp_type == 0)
		return -EINVAL;
	return 0;
}

/*
 * Validate the arch-specific HW Breakpoint register settings
 */
int hw_breakpoint_arch_parse(struct perf_event *bp,
			     const struct perf_event_attr *attr,
			     struct arch_hw_breakpoint *hw)
{
	int ret = -EINVAL, length_max;

	if (!bp)
		return ret;

	hw->type = HW_BRK_TYPE_TRANSLATE;
	if (attr->bp_type & HW_BREAKPOINT_R)
		hw->type |= HW_BRK_TYPE_READ;
	if (attr->bp_type & HW_BREAKPOINT_W)
		hw->type |= HW_BRK_TYPE_WRITE;
	if (hw->type == HW_BRK_TYPE_TRANSLATE)
		/* must set alteast read or write */
		return ret;
	if (!attr->exclude_user)
		hw->type |= HW_BRK_TYPE_USER;
	if (!attr->exclude_kernel)
		hw->type |= HW_BRK_TYPE_KERNEL;
	if (!attr->exclude_hv)
		hw->type |= HW_BRK_TYPE_HYP;
	hw->address = attr->bp_addr;
	hw->len = attr->bp_len;

	/*
	 * Since breakpoint length can be a maximum of HW_BREAKPOINT_LEN(8)
	 * and breakpoint addresses are aligned to nearest double-word
	 * HW_BREAKPOINT_ALIGN by rounding off to the lower address, the
	 * 'symbolsize' should satisfy the check below.
	 */
	if (!ppc_breakpoint_available())
		return -ENODEV;
	length_max = 8; /* DABR */
	if (dawr_enabled()) {
		length_max = 512 ; /* 64 doublewords */
		/* DAWR region can't cross 512 boundary */
		if ((attr->bp_addr >> 9) !=
		    ((attr->bp_addr + attr->bp_len - 1) >> 9))
			return -EINVAL;
	}
	if (hw->len >
	    (length_max - (hw->address & HW_BREAKPOINT_ALIGN)))
		return -EINVAL;
	return 0;
}

/*
 * Restores the breakpoint on the debug registers.
 * Invoke this function if it is known that the execution context is
 * about to change to cause loss of MSR_SE settings.
 */
void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs)
{
	struct arch_hw_breakpoint *info;

	if (likely(!tsk->thread.last_hit_ubp))
		return;

	info = counter_arch_bp(tsk->thread.last_hit_ubp);
	regs->msr &= ~MSR_SE;
	__set_breakpoint(info);
	tsk->thread.last_hit_ubp = NULL;
}

/*
 * Handle debug exception notifications.
 */
int hw_breakpoint_handler(struct die_args *args)
{
	int rc = NOTIFY_STOP;
	struct perf_event *bp;
	struct pt_regs *regs = args->regs;
#ifndef CONFIG_PPC_8xx
	int stepped = 1;
	unsigned int instr;
#endif
	struct arch_hw_breakpoint *info;
	unsigned long dar = regs->dar;

	/* Disable breakpoints during exception handling */
	hw_breakpoint_disable();

	/*
	 * The counter may be concurrently released but that can only
	 * occur from a call_rcu() path. We can then safely fetch
	 * the breakpoint, use its callback, touch its counter
	 * while we are in an rcu_read_lock() path.
	 */
	rcu_read_lock();

	bp = __this_cpu_read(bp_per_reg);
	if (!bp) {
		rc = NOTIFY_DONE;
		goto out;
	}
	info = counter_arch_bp(bp);

	/*
	 * Return early after invoking user-callback function without restoring
	 * DABR if the breakpoint is from ptrace which always operates in
	 * one-shot mode. The ptrace-ed process will receive the SIGTRAP signal
	 * generated in do_dabr().
	 */
	if (bp->overflow_handler == ptrace_triggered) {
		perf_bp_event(bp, regs);
		rc = NOTIFY_DONE;
		goto out;
	}

	/*
	 * Verify if dar lies within the address range occupied by the symbol
	 * being watched to filter extraneous exceptions.  If it doesn't,
	 * we still need to single-step the instruction, but we don't
	 * generate an event.
	 */
	info->type &= ~HW_BRK_TYPE_EXTRANEOUS_IRQ;
	if (!((bp->attr.bp_addr <= dar) &&
	      (dar - bp->attr.bp_addr < bp->attr.bp_len)))
		info->type |= HW_BRK_TYPE_EXTRANEOUS_IRQ;

#ifndef CONFIG_PPC_8xx
	/* Do not emulate user-space instructions, instead single-step them */
	if (user_mode(regs)) {
		current->thread.last_hit_ubp = bp;
		regs->msr |= MSR_SE;
		goto out;
	}

	stepped = 0;
	instr = 0;
	if (!__get_user_inatomic(instr, (unsigned int *) regs->nip))
		stepped = emulate_step(regs, instr);

	/*
	 * emulate_step() could not execute it. We've failed in reliably
	 * handling the hw-breakpoint. Unregister it and throw a warning
	 * message to let the user know about it.
	 */
	if (!stepped) {
		WARN(1, "Unable to handle hardware breakpoint. Breakpoint at "
			"0x%lx will be disabled.", info->address);
		perf_event_disable_inatomic(bp);
		goto out;
	}
#endif
	/*
	 * As a policy, the callback is invoked in a 'trigger-after-execute'
	 * fashion
	 */
	if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
		perf_bp_event(bp, regs);

	__set_breakpoint(info);
out:
	rcu_read_unlock();
	return rc;
}
NOKPROBE_SYMBOL(hw_breakpoint_handler);

/*
 * Handle single-step exceptions following a DABR hit.
 */
static int single_step_dabr_instruction(struct die_args *args)
{
	struct pt_regs *regs = args->regs;
	struct perf_event *bp = NULL;
	struct arch_hw_breakpoint *info;

	bp = current->thread.last_hit_ubp;
	/*
	 * Check if we are single-stepping as a result of a
	 * previous HW Breakpoint exception
	 */
	if (!bp)
		return NOTIFY_DONE;

	info = counter_arch_bp(bp);

	/*
	 * We shall invoke the user-defined callback function in the single
	 * stepping handler to confirm to 'trigger-after-execute' semantics
	 */
	if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
		perf_bp_event(bp, regs);

	__set_breakpoint(info);
	current->thread.last_hit_ubp = NULL;

	/*
	 * If the process was being single-stepped by ptrace, let the
	 * other single-step actions occur (e.g. generate SIGTRAP).
	 */
	if (test_thread_flag(TIF_SINGLESTEP))
		return NOTIFY_DONE;

	return NOTIFY_STOP;
}
NOKPROBE_SYMBOL(single_step_dabr_instruction);

/*
 * Handle debug exception notifications.
 */
int hw_breakpoint_exceptions_notify(
		struct notifier_block *unused, unsigned long val, void *data)
{
	int ret = NOTIFY_DONE;

	switch (val) {
	case DIE_DABR_MATCH:
		ret = hw_breakpoint_handler(data);
		break;
	case DIE_SSTEP:
		ret = single_step_dabr_instruction(data);
		break;
	}

	return ret;
}
NOKPROBE_SYMBOL(hw_breakpoint_exceptions_notify);

/*
 * Release the user breakpoints used by ptrace
 */
void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
{
	struct thread_struct *t = &tsk->thread;

	unregister_hw_breakpoint(t->ptrace_bps[0]);
	t->ptrace_bps[0] = NULL;
}

void hw_breakpoint_pmu_read(struct perf_event *bp)
{
	/* TODO */
}
Commit	Line	Data
5aae8a53 P	1	/*
	2	* HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
	3	* using the CPU's debug registers. Derived from
	4	* "arch/x86/kernel/hw_breakpoint.c"
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	19	*
	20	* Copyright 2010 IBM Corporation
	21	* Author: K.Prasad <prasad@linux.vnet.ibm.com>
	22	*
	23	*/
	24
	25	#include <linux/hw_breakpoint.h>
	26	#include <linux/notifier.h>
	27	#include <linux/kprobes.h>
	28	#include <linux/percpu.h>
	29	#include <linux/kernel.h>
5aae8a53	30	#include <linux/sched.h>
5aae8a53	31	#include <linux/smp.h>
c1fe190c MN	32	#include <linux/debugfs.h>
c1fe190c MN	33	#include <linux/init.h>
5aae8a53 P	34
	35	#include <asm/hw_breakpoint.h>
	36	#include <asm/processor.h>
	37	#include <asm/sstep.h>
85ce9a5d	38	#include <asm/debug.h>
c1fe190c MN	39	#include <asm/debugfs.h>
c1fe190c MN	40	#include <asm/hvcall.h>
7c0f6ba6	41	#include <linux/uaccess.h>
5aae8a53 P	42
	43	/*
	44	* Stores the breakpoints currently in use on each breakpoint address
	45	* register for every cpu
	46	*/
	47	static DEFINE_PER_CPU(struct perf_event *, bp_per_reg);
	48
d09ec738 PM	49	/*
	50	* Returns total number of data or instruction breakpoints available.
	51	*/
	52	int hw_breakpoint_slots(int type)
	53	{
	54	if (type == TYPE_DATA)
	55	return HBP_NUM;
	56	return 0; /* no instruction breakpoints available */
	57	}
	58
5aae8a53 P	59	/*
	60	* Install a perf counter breakpoint.
	61	*
	62	* We seek a free debug address register and use it for this
	63	* breakpoint.
	64	*
	65	* Atomic: we hold the counter->ctx->lock and we only handle variables
	66	* and registers local to this cpu.
	67	*/
	68	int arch_install_hw_breakpoint(struct perf_event *bp)
	69	{
	70	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
69111bac	71	struct perf_event **slot = this_cpu_ptr(&bp_per_reg);
5aae8a53 P	72
	73	*slot = bp;
	74
	75	/*
	76	* Do not install DABR values if the instruction must be single-stepped.
	77	* If so, DABR will be populated in single_step_dabr_instruction().
	78	*/
	79	if (current->thread.last_hit_ubp != bp)
21f58507	80	__set_breakpoint(info);
5aae8a53 P	81
	82	return 0;
	83	}
	84
	85	/*
	86	* Uninstall the breakpoint contained in the given counter.
	87	*
	88	* First we search the debug address register it uses and then we disable
	89	* it.
	90	*
	91	* Atomic: we hold the counter->ctx->lock and we only handle variables
	92	* and registers local to this cpu.
	93	*/
	94	void arch_uninstall_hw_breakpoint(struct perf_event *bp)
	95	{
69111bac	96	struct perf_event **slot = this_cpu_ptr(&bp_per_reg);
5aae8a53 P	97
	98	if (*slot != bp) {
	99	WARN_ONCE(1, "Can't find the breakpoint");
	100	return;
	101	}
	102
	103	*slot = NULL;
9422de3e	104	hw_breakpoint_disable();
5aae8a53 P	105	}
	106
	107	/*
	108	* Perform cleanup of arch-specific counters during unregistration
	109	* of the perf-event
	110	*/
	111	void arch_unregister_hw_breakpoint(struct perf_event *bp)
	112	{
	113	/*
	114	* If the breakpoint is unregistered between a hw_breakpoint_handler()
	115	* and the single_step_dabr_instruction(), then cleanup the breakpoint
	116	* restoration variables to prevent dangling pointers.
fb822e60	117	* FIXME, this should not be using bp->ctx at all! Sayeth peterz.
5aae8a53	118	*/
fb822e60	119	if (bp->ctx && bp->ctx->task && bp->ctx->task != ((void *)-1L))
5aae8a53 P	120	bp->ctx->task->thread.last_hit_ubp = NULL;
	121	}
	122
	123	/*
	124	* Check for virtual address in kernel space.
	125	*/
8e983ff9	126	int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
5aae8a53	127	{
8e983ff9	128	return is_kernel_addr(hw->address);
5aae8a53 P	129	}
	130
	131	int arch_bp_generic_fields(int type, int *gen_bp_type)
	132	{
9422de3e MN	133	*gen_bp_type = 0;
	134	if (type & HW_BRK_TYPE_READ)
	135	*gen_bp_type \|= HW_BREAKPOINT_R;
	136	if (type & HW_BRK_TYPE_WRITE)
	137	*gen_bp_type \|= HW_BREAKPOINT_W;
	138	if (*gen_bp_type == 0)
5aae8a53	139	return -EINVAL;
5aae8a53 P	140	return 0;
	141	}
	142
	143	/*
	144	* Validate the arch-specific HW Breakpoint register settings
	145	*/
5d5176ba FW	146	int hw_breakpoint_arch_parse(struct perf_event *bp,
	147	const struct perf_event_attr *attr,
	148	struct arch_hw_breakpoint *hw)
5aae8a53	149	{
4ae7ebe9	150	int ret = -EINVAL, length_max;
5aae8a53 P	151
	152	if (!bp)
	153	return ret;
	154
5d5176ba FW	155	hw->type = HW_BRK_TYPE_TRANSLATE;
	156	if (attr->bp_type & HW_BREAKPOINT_R)
	157	hw->type \|= HW_BRK_TYPE_READ;
	158	if (attr->bp_type & HW_BREAKPOINT_W)
	159	hw->type \|= HW_BRK_TYPE_WRITE;
	160	if (hw->type == HW_BRK_TYPE_TRANSLATE)
9422de3e	161	/* must set alteast read or write */
5aae8a53	162	return ret;
5d5176ba FW	163	if (!attr->exclude_user)
	164	hw->type \|= HW_BRK_TYPE_USER;
	165	if (!attr->exclude_kernel)
	166	hw->type \|= HW_BRK_TYPE_KERNEL;
	167	if (!attr->exclude_hv)
	168	hw->type \|= HW_BRK_TYPE_HYP;
	169	hw->address = attr->bp_addr;
	170	hw->len = attr->bp_len;
5aae8a53 P	171
	172	/*
	173	* Since breakpoint length can be a maximum of HW_BREAKPOINT_LEN(8)
	174	* and breakpoint addresses are aligned to nearest double-word
	175	* HW_BREAKPOINT_ALIGN by rounding off to the lower address, the
	176	* 'symbolsize' should satisfy the check below.
	177	*/
85ce9a5d MN	178	if (!ppc_breakpoint_available())
85ce9a5d MN	179	return -ENODEV;
4ae7ebe9	180	length_max = 8; /* DABR */
c1fe190c	181	if (dawr_enabled()) {
4ae7ebe9 MN	182	length_max = 512 ; /* 64 doublewords */
4ae7ebe9 MN	183	/* DAWR region can't cross 512 boundary */
5d5176ba FW	184	if ((attr->bp_addr >> 9) !=
5d5176ba FW	185	((attr->bp_addr + attr->bp_len - 1) >> 9))
4ae7ebe9 MN	186	return -EINVAL;
4ae7ebe9 MN	187	}
5d5176ba FW	188	if (hw->len >
5d5176ba FW	189	(length_max - (hw->address & HW_BREAKPOINT_ALIGN)))
5aae8a53 P	190	return -EINVAL;
	191	return 0;
	192	}
	193
06532a67 P	194	/*
	195	* Restores the breakpoint on the debug registers.
	196	* Invoke this function if it is known that the execution context is
	197	* about to change to cause loss of MSR_SE settings.
	198	*/
	199	void thread_change_pc(struct task_struct tsk, struct pt_regs regs)
	200	{
	201	struct arch_hw_breakpoint *info;
	202
	203	if (likely(!tsk->thread.last_hit_ubp))
	204	return;
	205
	206	info = counter_arch_bp(tsk->thread.last_hit_ubp);
	207	regs->msr &= ~MSR_SE;
21f58507	208	__set_breakpoint(info);
06532a67 P	209	tsk->thread.last_hit_ubp = NULL;
	210	}
	211
5aae8a53 P	212	/*
	213	* Handle debug exception notifications.
	214	*/
03465f89	215	int hw_breakpoint_handler(struct die_args *args)
5aae8a53	216	{
5aae8a53 P	217	int rc = NOTIFY_STOP;
	218	struct perf_event *bp;
	219	struct pt_regs *regs = args->regs;
4ad8622d	220	#ifndef CONFIG_PPC_8xx
5aae8a53	221	int stepped = 1;
5aae8a53	222	unsigned int instr;
4ad8622d CL	223	#endif
4ad8622d CL	224	struct arch_hw_breakpoint *info;
e3e94084	225	unsigned long dar = regs->dar;
5aae8a53 P	226
5aae8a53 P	227	/* Disable breakpoints during exception handling */
9422de3e	228	hw_breakpoint_disable();
574cb248	229
5aae8a53 P	230	/*
	231	* The counter may be concurrently released but that can only
	232	* occur from a call_rcu() path. We can then safely fetch
	233	* the breakpoint, use its callback, touch its counter
	234	* while we are in an rcu_read_lock() path.
	235	*/
	236	rcu_read_lock();
	237
69111bac	238	bp = __this_cpu_read(bp_per_reg);
c21a493a RB	239	if (!bp) {
c21a493a RB	240	rc = NOTIFY_DONE;
5aae8a53	241	goto out;
c21a493a	242	}
5aae8a53	243	info = counter_arch_bp(bp);
5aae8a53 P	244
	245	/*
	246	* Return early after invoking user-callback function without restoring
	247	* DABR if the breakpoint is from ptrace which always operates in
	248	* one-shot mode. The ptrace-ed process will receive the SIGTRAP signal
	249	* generated in do_dabr().
	250	*/
574cb248	251	if (bp->overflow_handler == ptrace_triggered) {
5aae8a53 P	252	perf_bp_event(bp, regs);
	253	rc = NOTIFY_DONE;
	254	goto out;
	255	}
	256
e3e94084 P	257	/*
e3e94084 P	258	* Verify if dar lies within the address range occupied by the symbol
574cb248 PM	259	* being watched to filter extraneous exceptions. If it doesn't,
	260	* we still need to single-step the instruction, but we don't
	261	* generate an event.
e3e94084	262	*/
540e07c6	263	info->type &= ~HW_BRK_TYPE_EXTRANEOUS_IRQ;
9422de3e MN	264	if (!((bp->attr.bp_addr <= dar) &&
	265	(dar - bp->attr.bp_addr < bp->attr.bp_len)))
	266	info->type \|= HW_BRK_TYPE_EXTRANEOUS_IRQ;
e3e94084	267
4ad8622d	268	#ifndef CONFIG_PPC_8xx
5aae8a53 P	269	/* Do not emulate user-space instructions, instead single-step them */
5aae8a53 P	270	if (user_mode(regs)) {
6d9c00c6	271	current->thread.last_hit_ubp = bp;
5aae8a53 P	272	regs->msr \|= MSR_SE;
	273	goto out;
	274	}
	275
	276	stepped = 0;
	277	instr = 0;
	278	if (!__get_user_inatomic(instr, (unsigned int *) regs->nip))
	279	stepped = emulate_step(regs, instr);
	280
	281	/*
	282	* emulate_step() could not execute it. We've failed in reliably
	283	* handling the hw-breakpoint. Unregister it and throw a warning
	284	* message to let the user know about it.
	285	*/
	286	if (!stepped) {
	287	WARN(1, "Unable to handle hardware breakpoint. Breakpoint at "
	288	"0x%lx will be disabled.", info->address);
5aab90ce	289	perf_event_disable_inatomic(bp);
5aae8a53 P	290	goto out;
5aae8a53 P	291	}
4ad8622d	292	#endif
5aae8a53 P	293	/*
	294	* As a policy, the callback is invoked in a 'trigger-after-execute'
	295	* fashion
	296	*/
9422de3e	297	if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
e3e94084	298	perf_bp_event(bp, regs);
5aae8a53	299
21f58507	300	__set_breakpoint(info);
5aae8a53 P	301	out:
	302	rcu_read_unlock();
	303	return rc;
	304	}
03465f89	305	NOKPROBE_SYMBOL(hw_breakpoint_handler);
5aae8a53 P	306
	307	/*
	308	* Handle single-step exceptions following a DABR hit.
	309	*/
03465f89	310	static int single_step_dabr_instruction(struct die_args *args)
5aae8a53 P	311	{
	312	struct pt_regs *regs = args->regs;
	313	struct perf_event *bp = NULL;
3f4693ee	314	struct arch_hw_breakpoint *info;
5aae8a53 P	315
	316	bp = current->thread.last_hit_ubp;
	317	/*
	318	* Check if we are single-stepping as a result of a
	319	* previous HW Breakpoint exception
	320	*/
	321	if (!bp)
	322	return NOTIFY_DONE;
	323
3f4693ee	324	info = counter_arch_bp(bp);
5aae8a53 P	325
	326	/*
	327	* We shall invoke the user-defined callback function in the single
	328	* stepping handler to confirm to 'trigger-after-execute' semantics
	329	*/
9422de3e	330	if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
e3e94084	331	perf_bp_event(bp, regs);
5aae8a53	332
21f58507	333	__set_breakpoint(info);
76b0f133 PM	334	current->thread.last_hit_ubp = NULL;
76b0f133 PM	335
5aae8a53	336	/*
76b0f133 PM	337	* If the process was being single-stepped by ptrace, let the
76b0f133 PM	338	* other single-step actions occur (e.g. generate SIGTRAP).
5aae8a53	339	*/
76b0f133 PM	340	if (test_thread_flag(TIF_SINGLESTEP))
76b0f133 PM	341	return NOTIFY_DONE;
5aae8a53	342
5aae8a53 P	343	return NOTIFY_STOP;
5aae8a53 P	344	}
03465f89	345	NOKPROBE_SYMBOL(single_step_dabr_instruction);
5aae8a53 P	346
	347	/*
	348	* Handle debug exception notifications.
	349	*/
03465f89	350	int hw_breakpoint_exceptions_notify(
5aae8a53 P	351	struct notifier_block unused, unsigned long val, void data)
	352	{
	353	int ret = NOTIFY_DONE;
	354
	355	switch (val) {
	356	case DIE_DABR_MATCH:
	357	ret = hw_breakpoint_handler(data);
	358	break;
	359	case DIE_SSTEP:
	360	ret = single_step_dabr_instruction(data);
	361	break;
	362	}
	363
	364	return ret;
	365	}
03465f89	366	NOKPROBE_SYMBOL(hw_breakpoint_exceptions_notify);
5aae8a53 P	367
	368	/*
	369	* Release the user breakpoints used by ptrace
	370	*/
	371	void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
	372	{
	373	struct thread_struct *t = &tsk->thread;
	374
	375	unregister_hw_breakpoint(t->ptrace_bps[0]);
	376	t->ptrace_bps[0] = NULL;
	377	}
	378
	379	void hw_breakpoint_pmu_read(struct perf_event *bp)
	380	{
	381	/* TODO */
	382	}