Commit | Line | Data |
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2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
14cf11af | 2 | /* |
14cf11af PM |
3 | * Kernel execution entry point code. |
4 | * | |
5 | * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> | |
3c5df5c2 | 6 | * Initial PowerPC version. |
14cf11af | 7 | * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> |
3c5df5c2 | 8 | * Rewritten for PReP |
14cf11af | 9 | * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> |
3c5df5c2 | 10 | * Low-level exception handers, MMU support, and rewrite. |
14cf11af | 11 | * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> |
3c5df5c2 | 12 | * PowerPC 8xx modifications. |
14cf11af | 13 | * Copyright (c) 1998-1999 TiVo, Inc. |
3c5df5c2 | 14 | * PowerPC 403GCX modifications. |
14cf11af | 15 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> |
3c5df5c2 | 16 | * PowerPC 403GCX/405GP modifications. |
14cf11af PM |
17 | * Copyright 2000 MontaVista Software Inc. |
18 | * PPC405 modifications | |
3c5df5c2 KG |
19 | * PowerPC 403GCX/405GP modifications. |
20 | * Author: MontaVista Software, Inc. | |
21 | * frank_rowand@mvista.com or source@mvista.com | |
22 | * debbie_chu@mvista.com | |
14cf11af | 23 | * Copyright 2002-2004 MontaVista Software, Inc. |
3c5df5c2 | 24 | * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org> |
14cf11af | 25 | * Copyright 2004 Freescale Semiconductor, Inc |
3c5df5c2 | 26 | * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org> |
14cf11af PM |
27 | */ |
28 | ||
e7039845 | 29 | #include <linux/init.h> |
14cf11af | 30 | #include <linux/threads.h> |
65fddcfc | 31 | #include <linux/pgtable.h> |
14cf11af PM |
32 | #include <asm/processor.h> |
33 | #include <asm/page.h> | |
34 | #include <asm/mmu.h> | |
14cf11af PM |
35 | #include <asm/cputable.h> |
36 | #include <asm/thread_info.h> | |
37 | #include <asm/ppc_asm.h> | |
38 | #include <asm/asm-offsets.h> | |
fc4033b2 | 39 | #include <asm/cache.h> |
46f52210 | 40 | #include <asm/ptrace.h> |
9445aa1a | 41 | #include <asm/export.h> |
2c86cd18 | 42 | #include <asm/feature-fixups.h> |
14cf11af PM |
43 | #include "head_booke.h" |
44 | ||
45 | /* As with the other PowerPC ports, it is expected that when code | |
46 | * execution begins here, the following registers contain valid, yet | |
47 | * optional, information: | |
48 | * | |
49 | * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) | |
50 | * r4 - Starting address of the init RAM disk | |
51 | * r5 - Ending address of the init RAM disk | |
52 | * r6 - Start of kernel command line string (e.g. "mem=128") | |
53 | * r7 - End of kernel command line string | |
54 | * | |
55 | */ | |
e7039845 | 56 | __HEAD |
748a7683 KG |
57 | _ENTRY(_stext); |
58 | _ENTRY(_start); | |
14cf11af PM |
59 | /* |
60 | * Reserve a word at a fixed location to store the address | |
61 | * of abatron_pteptrs | |
62 | */ | |
63 | nop | |
6dece0eb SW |
64 | |
65 | /* Translate device tree address to physical, save in r30/r31 */ | |
99739611 KH |
66 | bl get_phys_addr |
67 | mr r30,r3 | |
68 | mr r31,r4 | |
6dece0eb SW |
69 | |
70 | li r25,0 /* phys kernel start (low) */ | |
71 | li r24,0 /* CPU number */ | |
72 | li r23,0 /* phys kernel start (high) */ | |
14cf11af | 73 | |
dd189692 KH |
74 | #ifdef CONFIG_RELOCATABLE |
75 | LOAD_REG_ADDR_PIC(r3, _stext) /* Get our current runtime base */ | |
76 | ||
77 | /* Translate _stext address to physical, save in r23/r25 */ | |
78 | bl get_phys_addr | |
79 | mr r23,r3 | |
80 | mr r25,r4 | |
81 | ||
7d2471f9 KH |
82 | bl 0f |
83 | 0: mflr r8 | |
84 | addis r3,r8,(is_second_reloc - 0b)@ha | |
85 | lwz r19,(is_second_reloc - 0b)@l(r3) | |
86 | ||
87 | /* Check if this is the second relocation. */ | |
88 | cmpwi r19,1 | |
89 | bne 1f | |
90 | ||
91 | /* | |
92 | * For the second relocation, we already get the real memstart_addr | |
93 | * from device tree. So we will map PAGE_OFFSET to memstart_addr, | |
94 | * then the virtual address of start kernel should be: | |
95 | * PAGE_OFFSET + (kernstart_addr - memstart_addr) | |
96 | * Since the offset between kernstart_addr and memstart_addr should | |
97 | * never be beyond 1G, so we can just use the lower 32bit of them | |
98 | * for the calculation. | |
99 | */ | |
100 | lis r3,PAGE_OFFSET@h | |
101 | ||
102 | addis r4,r8,(kernstart_addr - 0b)@ha | |
103 | addi r4,r4,(kernstart_addr - 0b)@l | |
104 | lwz r5,4(r4) | |
105 | ||
106 | addis r6,r8,(memstart_addr - 0b)@ha | |
107 | addi r6,r6,(memstart_addr - 0b)@l | |
108 | lwz r7,4(r6) | |
109 | ||
110 | subf r5,r7,r5 | |
111 | add r3,r3,r5 | |
112 | b 2f | |
113 | ||
114 | 1: | |
dd189692 KH |
115 | /* |
116 | * We have the runtime (virutal) address of our base. | |
117 | * We calculate our shift of offset from a 64M page. | |
118 | * We could map the 64M page we belong to at PAGE_OFFSET and | |
119 | * get going from there. | |
120 | */ | |
121 | lis r4,KERNELBASE@h | |
122 | ori r4,r4,KERNELBASE@l | |
123 | rlwinm r6,r25,0,0x3ffffff /* r6 = PHYS_START % 64M */ | |
124 | rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */ | |
125 | subf r3,r5,r6 /* r3 = r6 - r5 */ | |
126 | add r3,r4,r3 /* Required Virtual Address */ | |
127 | ||
7d2471f9 KH |
128 | 2: bl relocate |
129 | ||
130 | /* | |
131 | * For the second relocation, we already set the right tlb entries | |
132 | * for the kernel space, so skip the code in fsl_booke_entry_mapping.S | |
133 | */ | |
134 | cmpwi r19,1 | |
135 | beq set_ivor | |
dd189692 KH |
136 | #endif |
137 | ||
14cf11af PM |
138 | /* We try to not make any assumptions about how the boot loader |
139 | * setup or used the TLBs. We invalidate all mappings from the | |
140 | * boot loader and load a single entry in TLB1[0] to map the | |
e8b63761 DF |
141 | * first 64M of kernel memory. Any boot info passed from the |
142 | * bootloader needs to live in this first 64M. | |
14cf11af PM |
143 | * |
144 | * Requirement on bootloader: | |
145 | * - The page we're executing in needs to reside in TLB1 and | |
146 | * have IPROT=1. If not an invalidate broadcast could | |
147 | * evict the entry we're currently executing in. | |
148 | * | |
149 | * r3 = Index of TLB1 were executing in | |
150 | * r4 = Current MSR[IS] | |
151 | * r5 = Index of TLB1 temp mapping | |
152 | * | |
153 | * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0] | |
154 | * if needed | |
155 | */ | |
156 | ||
d5b26db2 | 157 | _ENTRY(__early_start) |
2b0e86cc JY |
158 | LOAD_REG_ADDR_PIC(r20, kernstart_virt_addr) |
159 | lwz r20,0(r20) | |
105c31df | 160 | |
b3df895a | 161 | #define ENTRY_MAPPING_BOOT_SETUP |
7c08ce71 | 162 | #include "fsl_booke_entry_mapping.S" |
b3df895a | 163 | #undef ENTRY_MAPPING_BOOT_SETUP |
14cf11af | 164 | |
7d2471f9 | 165 | set_ivor: |
14cf11af PM |
166 | /* Establish the interrupt vector offsets */ |
167 | SET_IVOR(0, CriticalInput); | |
168 | SET_IVOR(1, MachineCheck); | |
169 | SET_IVOR(2, DataStorage); | |
170 | SET_IVOR(3, InstructionStorage); | |
171 | SET_IVOR(4, ExternalInput); | |
172 | SET_IVOR(5, Alignment); | |
173 | SET_IVOR(6, Program); | |
174 | SET_IVOR(7, FloatingPointUnavailable); | |
175 | SET_IVOR(8, SystemCall); | |
176 | SET_IVOR(9, AuxillaryProcessorUnavailable); | |
177 | SET_IVOR(10, Decrementer); | |
178 | SET_IVOR(11, FixedIntervalTimer); | |
179 | SET_IVOR(12, WatchdogTimer); | |
180 | SET_IVOR(13, DataTLBError); | |
181 | SET_IVOR(14, InstructionTLBError); | |
eb0cd5fd | 182 | SET_IVOR(15, DebugCrit); |
14cf11af PM |
183 | |
184 | /* Establish the interrupt vector base */ | |
185 | lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ | |
186 | mtspr SPRN_IVPR,r4 | |
187 | ||
188 | /* Setup the defaults for TLB entries */ | |
d66c82ea | 189 | li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l |
3c5df5c2 | 190 | mtspr SPRN_MAS4, r2 |
14cf11af | 191 | |
14cf11af PM |
192 | #if !defined(CONFIG_BDI_SWITCH) |
193 | /* | |
194 | * The Abatron BDI JTAG debugger does not tolerate others | |
195 | * mucking with the debug registers. | |
196 | */ | |
197 | lis r2,DBCR0_IDM@h | |
198 | mtspr SPRN_DBCR0,r2 | |
a7cb0337 | 199 | isync |
14cf11af PM |
200 | /* clear any residual debug events */ |
201 | li r2,-1 | |
202 | mtspr SPRN_DBSR,r2 | |
203 | #endif | |
204 | ||
d5b26db2 KG |
205 | #ifdef CONFIG_SMP |
206 | /* Check to see if we're the second processor, and jump | |
207 | * to the secondary_start code if so | |
208 | */ | |
0be7d969 | 209 | LOAD_REG_ADDR_PIC(r24, boot_cpuid) |
2ed38b23 MM |
210 | lwz r24, 0(r24) |
211 | cmpwi r24, -1 | |
212 | mfspr r24,SPRN_PIR | |
d5b26db2 KG |
213 | bne __secondary_start |
214 | #endif | |
215 | ||
14cf11af PM |
216 | /* |
217 | * This is where the main kernel code starts. | |
218 | */ | |
219 | ||
220 | /* ptr to current */ | |
221 | lis r2,init_task@h | |
222 | ori r2,r2,init_task@l | |
223 | ||
224 | /* ptr to current thread */ | |
225 | addi r4,r2,THREAD /* init task's THREAD */ | |
ee43eb78 | 226 | mtspr SPRN_SPRG_THREAD,r4 |
14cf11af PM |
227 | |
228 | /* stack */ | |
229 | lis r1,init_thread_union@h | |
230 | ori r1,r1,init_thread_union@l | |
231 | li r0,0 | |
232 | stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) | |
233 | ||
05486089 | 234 | #ifdef CONFIG_SMP |
f7354cca | 235 | stw r24, TASK_CPU(r2) |
05486089 | 236 | #endif |
2ed38b23 | 237 | |
14cf11af PM |
238 | bl early_init |
239 | ||
71eb40fc CL |
240 | #ifdef CONFIG_KASAN |
241 | bl kasan_early_init | |
242 | #endif | |
dd189692 | 243 | #ifdef CONFIG_RELOCATABLE |
7d2471f9 KH |
244 | mr r3,r30 |
245 | mr r4,r31 | |
dd189692 | 246 | #ifdef CONFIG_PHYS_64BIT |
7d2471f9 KH |
247 | mr r5,r23 |
248 | mr r6,r25 | |
dd189692 | 249 | #else |
7d2471f9 | 250 | mr r5,r25 |
dd189692 KH |
251 | #endif |
252 | bl relocate_init | |
253 | #endif | |
254 | ||
0f890c8d | 255 | #ifdef CONFIG_DYNAMIC_MEMSTART |
37dd2bad KG |
256 | lis r3,kernstart_addr@ha |
257 | la r3,kernstart_addr@l(r3) | |
258 | #ifdef CONFIG_PHYS_64BIT | |
259 | stw r23,0(r3) | |
260 | stw r25,4(r3) | |
261 | #else | |
262 | stw r25,0(r3) | |
263 | #endif | |
264 | #endif | |
265 | ||
14cf11af PM |
266 | /* |
267 | * Decide what sort of machine this is and initialize the MMU. | |
268 | */ | |
6dece0eb SW |
269 | mr r3,r30 |
270 | mr r4,r31 | |
14cf11af PM |
271 | bl machine_init |
272 | bl MMU_init | |
273 | ||
274 | /* Setup PTE pointers for the Abatron bdiGDB */ | |
275 | lis r6, swapper_pg_dir@h | |
276 | ori r6, r6, swapper_pg_dir@l | |
277 | lis r5, abatron_pteptrs@h | |
278 | ori r5, r5, abatron_pteptrs@l | |
2b0e86cc JY |
279 | lis r3, kernstart_virt_addr@ha |
280 | lwz r4, kernstart_virt_addr@l(r3) | |
14cf11af PM |
281 | stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ |
282 | stw r6, 0(r5) | |
283 | ||
284 | /* Let's move on */ | |
285 | lis r4,start_kernel@h | |
286 | ori r4,r4,start_kernel@l | |
287 | lis r3,MSR_KERNEL@h | |
288 | ori r3,r3,MSR_KERNEL@l | |
289 | mtspr SPRN_SRR0,r4 | |
290 | mtspr SPRN_SRR1,r3 | |
291 | rfi /* change context and jump to start_kernel */ | |
292 | ||
293 | /* Macros to hide the PTE size differences | |
294 | * | |
295 | * FIND_PTE -- walks the page tables given EA & pgdir pointer | |
296 | * r10 -- EA of fault | |
297 | * r11 -- PGDIR pointer | |
298 | * r12 -- free | |
299 | * label 2: is the bailout case | |
300 | * | |
301 | * if we find the pte (fall through): | |
302 | * r11 is low pte word | |
303 | * r12 is pointer to the pte | |
41151e77 | 304 | * r10 is the pshift from the PGD, if we're a hugepage |
14cf11af PM |
305 | */ |
306 | #ifdef CONFIG_PTE_64BIT | |
41151e77 BB |
307 | #ifdef CONFIG_HUGETLB_PAGE |
308 | #define FIND_PTE \ | |
309 | rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \ | |
310 | lwzx r11, r12, r11; /* Get pgd/pmd entry */ \ | |
311 | rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ | |
312 | blt 1000f; /* Normal non-huge page */ \ | |
313 | beq 2f; /* Bail if no table */ \ | |
314 | oris r11, r11, PD_HUGE@h; /* Put back address bit */ \ | |
315 | andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \ | |
316 | xor r12, r10, r11; /* drop size bits from pointer */ \ | |
317 | b 1001f; \ | |
318 | 1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \ | |
319 | li r10, 0; /* clear r10 */ \ | |
320 | 1001: lwz r11, 4(r12); /* Get pte entry */ | |
321 | #else | |
14cf11af | 322 | #define FIND_PTE \ |
3c5df5c2 | 323 | rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \ |
14cf11af PM |
324 | lwzx r11, r12, r11; /* Get pgd/pmd entry */ \ |
325 | rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ | |
326 | beq 2f; /* Bail if no table */ \ | |
327 | rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \ | |
328 | lwz r11, 4(r12); /* Get pte entry */ | |
41151e77 BB |
329 | #endif /* HUGEPAGE */ |
330 | #else /* !PTE_64BIT */ | |
14cf11af PM |
331 | #define FIND_PTE \ |
332 | rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \ | |
333 | lwz r11, 0(r11); /* Get L1 entry */ \ | |
334 | rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \ | |
335 | beq 2f; /* Bail if no table */ \ | |
336 | rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \ | |
337 | lwz r11, 0(r12); /* Get Linux PTE */ | |
338 | #endif | |
339 | ||
340 | /* | |
341 | * Interrupt vector entry code | |
342 | * | |
343 | * The Book E MMUs are always on so we don't need to handle | |
344 | * interrupts in real mode as with previous PPC processors. In | |
345 | * this case we handle interrupts in the kernel virtual address | |
346 | * space. | |
347 | * | |
348 | * Interrupt vectors are dynamically placed relative to the | |
349 | * interrupt prefix as determined by the address of interrupt_base. | |
350 | * The interrupt vectors offsets are programmed using the labels | |
351 | * for each interrupt vector entry. | |
352 | * | |
353 | * Interrupt vectors must be aligned on a 16 byte boundary. | |
354 | * We align on a 32 byte cache line boundary for good measure. | |
355 | */ | |
356 | ||
357 | interrupt_base: | |
358 | /* Critical Input Interrupt */ | |
cfac5784 | 359 | CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception) |
14cf11af PM |
360 | |
361 | /* Machine Check Interrupt */ | |
dc1c1ca3 | 362 | MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception) |
14cf11af PM |
363 | |
364 | /* Data Storage Interrupt */ | |
365 | START_EXCEPTION(DataStorage) | |
719e7e21 | 366 | NORMAL_EXCEPTION_PROLOG(0x300, DATA_STORAGE) |
b4ced803 | 367 | mfspr r5,SPRN_ESR /* Grab the ESR, save it */ |
6cfd8990 | 368 | stw r5,_ESR(r11) |
b4ced803 NP |
369 | mfspr r4,SPRN_DEAR /* Grab the DEAR, save it */ |
370 | stw r4, _DEAR(r11) | |
6cfd8990 KG |
371 | andis. r10,r5,(ESR_ILK|ESR_DLK)@h |
372 | bne 1f | |
af6f2ce8 | 373 | EXC_XFER_LITE(0x0300, do_page_fault) |
6cfd8990 | 374 | 1: |
642770dd | 375 | EXC_XFER_LITE(0x0300, CacheLockingException) |
14cf11af PM |
376 | |
377 | /* Instruction Storage Interrupt */ | |
378 | INSTRUCTION_STORAGE_EXCEPTION | |
379 | ||
380 | /* External Input Interrupt */ | |
cfac5784 | 381 | EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ, EXC_XFER_LITE) |
14cf11af PM |
382 | |
383 | /* Alignment Interrupt */ | |
384 | ALIGNMENT_EXCEPTION | |
385 | ||
386 | /* Program Interrupt */ | |
387 | PROGRAM_EXCEPTION | |
388 | ||
389 | /* Floating Point Unavailable Interrupt */ | |
390 | #ifdef CONFIG_PPC_FPU | |
391 | FP_UNAVAILABLE_EXCEPTION | |
14cf11af | 392 | #else |
cfac5784 | 393 | EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \ |
642770dd | 394 | unknown_exception, EXC_XFER_STD) |
14cf11af PM |
395 | #endif |
396 | ||
397 | /* System Call Interrupt */ | |
398 | START_EXCEPTION(SystemCall) | |
82f6e266 | 399 | SYSCALL_ENTRY 0xc00 BOOKE_INTERRUPT_SYSCALL SPRN_SRR1 |
14cf11af | 400 | |
25985edc | 401 | /* Auxiliary Processor Unavailable Interrupt */ |
cfac5784 | 402 | EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \ |
642770dd | 403 | unknown_exception, EXC_XFER_STD) |
14cf11af PM |
404 | |
405 | /* Decrementer Interrupt */ | |
406 | DECREMENTER_EXCEPTION | |
407 | ||
408 | /* Fixed Internal Timer Interrupt */ | |
409 | /* TODO: Add FIT support */ | |
cfac5784 | 410 | EXCEPTION(0x3100, FIT, FixedIntervalTimer, \ |
642770dd | 411 | unknown_exception, EXC_XFER_STD) |
14cf11af PM |
412 | |
413 | /* Watchdog Timer Interrupt */ | |
414 | #ifdef CONFIG_BOOKE_WDT | |
cfac5784 | 415 | CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException) |
14cf11af | 416 | #else |
cfac5784 | 417 | CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception) |
14cf11af PM |
418 | #endif |
419 | ||
420 | /* Data TLB Error Interrupt */ | |
421 | START_EXCEPTION(DataTLBError) | |
ee43eb78 | 422 | mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ |
1325a684 AK |
423 | mfspr r10, SPRN_SPRG_THREAD |
424 | stw r11, THREAD_NORMSAVE(0)(r10) | |
73196cd3 SW |
425 | #ifdef CONFIG_KVM_BOOKE_HV |
426 | BEGIN_FTR_SECTION | |
427 | mfspr r11, SPRN_SRR1 | |
428 | END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) | |
429 | #endif | |
1325a684 AK |
430 | stw r12, THREAD_NORMSAVE(1)(r10) |
431 | stw r13, THREAD_NORMSAVE(2)(r10) | |
432 | mfcr r13 | |
433 | stw r13, THREAD_NORMSAVE(3)(r10) | |
73196cd3 | 434 | DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1 |
7fef4362 DC |
435 | START_BTB_FLUSH_SECTION |
436 | mfspr r11, SPRN_SRR1 | |
437 | andi. r10,r11,MSR_PR | |
438 | beq 1f | |
439 | BTB_FLUSH(r10) | |
440 | 1: | |
441 | END_BTB_FLUSH_SECTION | |
14cf11af PM |
442 | mfspr r10, SPRN_DEAR /* Get faulting address */ |
443 | ||
444 | /* If we are faulting a kernel address, we have to use the | |
445 | * kernel page tables. | |
446 | */ | |
8a13c4f9 | 447 | lis r11, PAGE_OFFSET@h |
14cf11af PM |
448 | cmplw 5, r10, r11 |
449 | blt 5, 3f | |
450 | lis r11, swapper_pg_dir@h | |
451 | ori r11, r11, swapper_pg_dir@l | |
452 | ||
453 | mfspr r12,SPRN_MAS1 /* Set TID to 0 */ | |
454 | rlwinm r12,r12,0,16,1 | |
455 | mtspr SPRN_MAS1,r12 | |
456 | ||
457 | b 4f | |
458 | ||
459 | /* Get the PGD for the current thread */ | |
460 | 3: | |
ee43eb78 | 461 | mfspr r11,SPRN_SPRG_THREAD |
14cf11af PM |
462 | lwz r11,PGDIR(r11) |
463 | ||
464 | 4: | |
6cfd8990 KG |
465 | /* Mask of required permission bits. Note that while we |
466 | * do copy ESR:ST to _PAGE_RW position as trying to write | |
467 | * to an RO page is pretty common, we don't do it with | |
468 | * _PAGE_DIRTY. We could do it, but it's a fairly rare | |
469 | * event so I'd rather take the overhead when it happens | |
470 | * rather than adding an instruction here. We should measure | |
471 | * whether the whole thing is worth it in the first place | |
472 | * as we could avoid loading SPRN_ESR completely in the first | |
473 | * place... | |
474 | * | |
475 | * TODO: Is it worth doing that mfspr & rlwimi in the first | |
476 | * place or can we save a couple of instructions here ? | |
477 | */ | |
478 | mfspr r12,SPRN_ESR | |
76acc2c1 KG |
479 | #ifdef CONFIG_PTE_64BIT |
480 | li r13,_PAGE_PRESENT | |
481 | oris r13,r13,_PAGE_ACCESSED@h | |
482 | #else | |
6cfd8990 | 483 | li r13,_PAGE_PRESENT|_PAGE_ACCESSED |
76acc2c1 | 484 | #endif |
6cfd8990 KG |
485 | rlwimi r13,r12,11,29,29 |
486 | ||
14cf11af | 487 | FIND_PTE |
6cfd8990 | 488 | andc. r13,r13,r11 /* Check permission */ |
14cf11af PM |
489 | |
490 | #ifdef CONFIG_PTE_64BIT | |
b38fd42f | 491 | #ifdef CONFIG_SMP |
41151e77 BB |
492 | subf r13,r11,r12 /* create false data dep */ |
493 | lwzx r13,r11,r13 /* Get upper pte bits */ | |
b38fd42f KG |
494 | #else |
495 | lwz r13,0(r12) /* Get upper pte bits */ | |
496 | #endif | |
14cf11af | 497 | #endif |
14cf11af | 498 | |
b38fd42f KG |
499 | bne 2f /* Bail if permission/valid mismach */ |
500 | ||
501 | /* Jump to common tlb load */ | |
14cf11af PM |
502 | b finish_tlb_load |
503 | 2: | |
504 | /* The bailout. Restore registers to pre-exception conditions | |
505 | * and call the heavyweights to help us out. | |
506 | */ | |
1325a684 AK |
507 | mfspr r10, SPRN_SPRG_THREAD |
508 | lwz r11, THREAD_NORMSAVE(3)(r10) | |
14cf11af | 509 | mtcr r11 |
1325a684 AK |
510 | lwz r13, THREAD_NORMSAVE(2)(r10) |
511 | lwz r12, THREAD_NORMSAVE(1)(r10) | |
512 | lwz r11, THREAD_NORMSAVE(0)(r10) | |
ee43eb78 | 513 | mfspr r10, SPRN_SPRG_RSCRATCH0 |
6cfd8990 | 514 | b DataStorage |
14cf11af PM |
515 | |
516 | /* Instruction TLB Error Interrupt */ | |
517 | /* | |
518 | * Nearly the same as above, except we get our | |
519 | * information from different registers and bailout | |
520 | * to a different point. | |
521 | */ | |
522 | START_EXCEPTION(InstructionTLBError) | |
ee43eb78 | 523 | mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */ |
1325a684 AK |
524 | mfspr r10, SPRN_SPRG_THREAD |
525 | stw r11, THREAD_NORMSAVE(0)(r10) | |
73196cd3 SW |
526 | #ifdef CONFIG_KVM_BOOKE_HV |
527 | BEGIN_FTR_SECTION | |
528 | mfspr r11, SPRN_SRR1 | |
529 | END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV) | |
530 | #endif | |
1325a684 AK |
531 | stw r12, THREAD_NORMSAVE(1)(r10) |
532 | stw r13, THREAD_NORMSAVE(2)(r10) | |
533 | mfcr r13 | |
534 | stw r13, THREAD_NORMSAVE(3)(r10) | |
73196cd3 | 535 | DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1 |
7fef4362 DC |
536 | START_BTB_FLUSH_SECTION |
537 | mfspr r11, SPRN_SRR1 | |
538 | andi. r10,r11,MSR_PR | |
539 | beq 1f | |
540 | BTB_FLUSH(r10) | |
541 | 1: | |
542 | END_BTB_FLUSH_SECTION | |
543 | ||
14cf11af PM |
544 | mfspr r10, SPRN_SRR0 /* Get faulting address */ |
545 | ||
546 | /* If we are faulting a kernel address, we have to use the | |
547 | * kernel page tables. | |
548 | */ | |
8a13c4f9 | 549 | lis r11, PAGE_OFFSET@h |
14cf11af PM |
550 | cmplw 5, r10, r11 |
551 | blt 5, 3f | |
552 | lis r11, swapper_pg_dir@h | |
553 | ori r11, r11, swapper_pg_dir@l | |
554 | ||
555 | mfspr r12,SPRN_MAS1 /* Set TID to 0 */ | |
556 | rlwinm r12,r12,0,16,1 | |
557 | mtspr SPRN_MAS1,r12 | |
558 | ||
78e2e68a LY |
559 | /* Make up the required permissions for kernel code */ |
560 | #ifdef CONFIG_PTE_64BIT | |
561 | li r13,_PAGE_PRESENT | _PAGE_BAP_SX | |
562 | oris r13,r13,_PAGE_ACCESSED@h | |
563 | #else | |
564 | li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC | |
565 | #endif | |
14cf11af PM |
566 | b 4f |
567 | ||
568 | /* Get the PGD for the current thread */ | |
569 | 3: | |
ee43eb78 | 570 | mfspr r11,SPRN_SPRG_THREAD |
14cf11af PM |
571 | lwz r11,PGDIR(r11) |
572 | ||
78e2e68a | 573 | /* Make up the required permissions for user code */ |
76acc2c1 | 574 | #ifdef CONFIG_PTE_64BIT |
78e2e68a | 575 | li r13,_PAGE_PRESENT | _PAGE_BAP_UX |
76acc2c1 KG |
576 | oris r13,r13,_PAGE_ACCESSED@h |
577 | #else | |
ea3cc330 | 578 | li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC |
76acc2c1 | 579 | #endif |
6cfd8990 | 580 | |
78e2e68a | 581 | 4: |
14cf11af | 582 | FIND_PTE |
6cfd8990 | 583 | andc. r13,r13,r11 /* Check permission */ |
b38fd42f KG |
584 | |
585 | #ifdef CONFIG_PTE_64BIT | |
586 | #ifdef CONFIG_SMP | |
41151e77 BB |
587 | subf r13,r11,r12 /* create false data dep */ |
588 | lwzx r13,r11,r13 /* Get upper pte bits */ | |
b38fd42f KG |
589 | #else |
590 | lwz r13,0(r12) /* Get upper pte bits */ | |
591 | #endif | |
592 | #endif | |
593 | ||
6cfd8990 | 594 | bne 2f /* Bail if permission mismach */ |
14cf11af | 595 | |
14cf11af PM |
596 | /* Jump to common TLB load point */ |
597 | b finish_tlb_load | |
598 | ||
599 | 2: | |
600 | /* The bailout. Restore registers to pre-exception conditions | |
601 | * and call the heavyweights to help us out. | |
602 | */ | |
1325a684 AK |
603 | mfspr r10, SPRN_SPRG_THREAD |
604 | lwz r11, THREAD_NORMSAVE(3)(r10) | |
14cf11af | 605 | mtcr r11 |
1325a684 AK |
606 | lwz r13, THREAD_NORMSAVE(2)(r10) |
607 | lwz r12, THREAD_NORMSAVE(1)(r10) | |
608 | lwz r11, THREAD_NORMSAVE(0)(r10) | |
ee43eb78 | 609 | mfspr r10, SPRN_SPRG_RSCRATCH0 |
14cf11af PM |
610 | b InstructionStorage |
611 | ||
39c8bf2b | 612 | /* Define SPE handlers for e500v2 */ |
14cf11af PM |
613 | #ifdef CONFIG_SPE |
614 | /* SPE Unavailable */ | |
615 | START_EXCEPTION(SPEUnavailable) | |
719e7e21 | 616 | NORMAL_EXCEPTION_PROLOG(0x2010, SPE_UNAVAIL) |
2dc3d4cc LY |
617 | beq 1f |
618 | bl load_up_spe | |
619 | b fast_exception_return | |
e7291556 | 620 | 1: EXC_XFER_LITE(0x2010, KernelSPE) |
3477e71d | 621 | #elif defined(CONFIG_SPE_POSSIBLE) |
2b2695a8 | 622 | EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \ |
642770dd | 623 | unknown_exception, EXC_XFER_STD) |
3477e71d | 624 | #endif /* CONFIG_SPE_POSSIBLE */ |
14cf11af PM |
625 | |
626 | /* SPE Floating Point Data */ | |
627 | #ifdef CONFIG_SPE | |
8f6ff5bd CL |
628 | START_EXCEPTION(SPEFloatingPointData) |
629 | NORMAL_EXCEPTION_PROLOG(0x2030, SPE_FP_DATA) | |
630 | prepare_transfer_to_handler | |
631 | bl SPEFloatingPointException | |
632 | REST_NVGPRS(r1) | |
633 | b interrupt_return | |
14cf11af PM |
634 | |
635 | /* SPE Floating Point Round */ | |
8f6ff5bd CL |
636 | START_EXCEPTION(SPEFloatingPointRound) |
637 | NORMAL_EXCEPTION_PROLOG(0x2050, SPE_FP_ROUND) | |
638 | prepare_transfer_to_handler | |
639 | bl SPEFloatingPointRoundException | |
640 | REST_NVGPRS(r1) | |
641 | b interrupt_return | |
3477e71d | 642 | #elif defined(CONFIG_SPE_POSSIBLE) |
2b2695a8 | 643 | EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData, |
642770dd | 644 | unknown_exception, EXC_XFER_STD) |
cfac5784 | 645 | EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \ |
642770dd | 646 | unknown_exception, EXC_XFER_STD) |
3477e71d MC |
647 | #endif /* CONFIG_SPE_POSSIBLE */ |
648 | ||
14cf11af PM |
649 | |
650 | /* Performance Monitor */ | |
cfac5784 SW |
651 | EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \ |
652 | performance_monitor_exception, EXC_XFER_STD) | |
14cf11af | 653 | |
cfac5784 | 654 | EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception, EXC_XFER_STD) |
620165f9 | 655 | |
cfac5784 SW |
656 | CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \ |
657 | CriticalDoorbell, unknown_exception) | |
14cf11af PM |
658 | |
659 | /* Debug Interrupt */ | |
eb0cd5fd | 660 | DEBUG_DEBUG_EXCEPTION |
eb0cd5fd | 661 | DEBUG_CRIT_EXCEPTION |
14cf11af | 662 | |
73196cd3 SW |
663 | GUEST_DOORBELL_EXCEPTION |
664 | ||
665 | CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \ | |
666 | unknown_exception) | |
667 | ||
668 | /* Hypercall */ | |
642770dd | 669 | EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception, EXC_XFER_STD) |
73196cd3 SW |
670 | |
671 | /* Embedded Hypervisor Privilege */ | |
642770dd | 672 | EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_STD) |
73196cd3 | 673 | |
fc2a6cfe BB |
674 | interrupt_end: |
675 | ||
14cf11af PM |
676 | /* |
677 | * Local functions | |
678 | */ | |
679 | ||
14cf11af | 680 | /* |
14cf11af PM |
681 | * Both the instruction and data TLB miss get to this |
682 | * point to load the TLB. | |
41151e77 | 683 | * r10 - tsize encoding (if HUGETLB_PAGE) or available to use |
3c5df5c2 | 684 | * r11 - TLB (info from Linux PTE) |
6cfd8990 KG |
685 | * r12 - available to use |
686 | * r13 - upper bits of PTE (if PTE_64BIT) or available to use | |
8a13c4f9 | 687 | * CR5 - results of addr >= PAGE_OFFSET |
14cf11af PM |
688 | * MAS0, MAS1 - loaded with proper value when we get here |
689 | * MAS2, MAS3 - will need additional info from Linux PTE | |
690 | * Upon exit, we reload everything and RFI. | |
691 | */ | |
692 | finish_tlb_load: | |
41151e77 BB |
693 | #ifdef CONFIG_HUGETLB_PAGE |
694 | cmpwi 6, r10, 0 /* check for huge page */ | |
695 | beq 6, finish_tlb_load_cont /* !huge */ | |
696 | ||
697 | /* Alas, we need more scratch registers for hugepages */ | |
698 | mfspr r12, SPRN_SPRG_THREAD | |
699 | stw r14, THREAD_NORMSAVE(4)(r12) | |
700 | stw r15, THREAD_NORMSAVE(5)(r12) | |
701 | stw r16, THREAD_NORMSAVE(6)(r12) | |
702 | stw r17, THREAD_NORMSAVE(7)(r12) | |
703 | ||
704 | /* Get the next_tlbcam_idx percpu var */ | |
705 | #ifdef CONFIG_SMP | |
f7354cca | 706 | lwz r15, TASK_CPU-THREAD(r12) |
41151e77 BB |
707 | lis r14, __per_cpu_offset@h |
708 | ori r14, r14, __per_cpu_offset@l | |
709 | rlwinm r15, r15, 2, 0, 29 | |
710 | lwzx r16, r14, r15 | |
711 | #else | |
712 | li r16, 0 | |
713 | #endif | |
714 | lis r17, next_tlbcam_idx@h | |
715 | ori r17, r17, next_tlbcam_idx@l | |
716 | add r17, r17, r16 /* r17 = *next_tlbcam_idx */ | |
717 | lwz r15, 0(r17) /* r15 = next_tlbcam_idx */ | |
718 | ||
719 | lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */ | |
720 | rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */ | |
721 | mtspr SPRN_MAS0, r14 | |
722 | ||
723 | /* Extract TLB1CFG(NENTRY) */ | |
724 | mfspr r16, SPRN_TLB1CFG | |
725 | andi. r16, r16, 0xfff | |
726 | ||
727 | /* Update next_tlbcam_idx, wrapping when necessary */ | |
728 | addi r15, r15, 1 | |
729 | cmpw r15, r16 | |
730 | blt 100f | |
731 | lis r14, tlbcam_index@h | |
732 | ori r14, r14, tlbcam_index@l | |
733 | lwz r15, 0(r14) | |
734 | 100: stw r15, 0(r17) | |
735 | ||
736 | /* | |
737 | * Calc MAS1_TSIZE from r10 (which has pshift encoded) | |
738 | * tlb_enc = (pshift - 10). | |
739 | */ | |
740 | subi r15, r10, 10 | |
741 | mfspr r16, SPRN_MAS1 | |
742 | rlwimi r16, r15, 7, 20, 24 | |
743 | mtspr SPRN_MAS1, r16 | |
744 | ||
745 | /* copy the pshift for use later */ | |
746 | mr r14, r10 | |
747 | ||
748 | /* fall through */ | |
749 | ||
750 | #endif /* CONFIG_HUGETLB_PAGE */ | |
751 | ||
14cf11af PM |
752 | /* |
753 | * We set execute, because we don't have the granularity to | |
754 | * properly set this at the page level (Linux problem). | |
755 | * Many of these bits are software only. Bits we don't set | |
756 | * here we (properly should) assume have the appropriate value. | |
757 | */ | |
41151e77 | 758 | finish_tlb_load_cont: |
76acc2c1 KG |
759 | #ifdef CONFIG_PTE_64BIT |
760 | rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */ | |
761 | andi. r10, r11, _PAGE_DIRTY | |
762 | bne 1f | |
763 | li r10, MAS3_SW | MAS3_UW | |
764 | andc r12, r12, r10 | |
765 | 1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */ | |
766 | rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */ | |
41151e77 | 767 | 2: mtspr SPRN_MAS3, r12 |
76acc2c1 KG |
768 | BEGIN_MMU_FTR_SECTION |
769 | srwi r10, r13, 12 /* grab RPN[12:31] */ | |
770 | mtspr SPRN_MAS7, r10 | |
771 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS) | |
772 | #else | |
ea3cc330 | 773 | li r10, (_PAGE_EXEC | _PAGE_PRESENT) |
41151e77 | 774 | mr r13, r11 |
6cfd8990 KG |
775 | rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */ |
776 | and r12, r11, r10 | |
14cf11af | 777 | andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */ |
6cfd8990 KG |
778 | slwi r10, r12, 1 |
779 | or r10, r10, r12 | |
780 | iseleq r12, r12, r10 | |
41151e77 BB |
781 | rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */ |
782 | mtspr SPRN_MAS3, r13 | |
14cf11af | 783 | #endif |
41151e77 BB |
784 | |
785 | mfspr r12, SPRN_MAS2 | |
786 | #ifdef CONFIG_PTE_64BIT | |
787 | rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */ | |
788 | #else | |
789 | rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */ | |
790 | #endif | |
791 | #ifdef CONFIG_HUGETLB_PAGE | |
792 | beq 6, 3f /* don't mask if page isn't huge */ | |
793 | li r13, 1 | |
794 | slw r13, r13, r14 | |
795 | subi r13, r13, 1 | |
796 | rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */ | |
797 | andc r12, r12, r13 /* mask off ea bits within the page */ | |
798 | #endif | |
799 | 3: mtspr SPRN_MAS2, r12 | |
800 | ||
41151e77 | 801 | tlb_write_entry: |
14cf11af PM |
802 | tlbwe |
803 | ||
804 | /* Done...restore registers and get out of here. */ | |
1325a684 | 805 | mfspr r10, SPRN_SPRG_THREAD |
41151e77 BB |
806 | #ifdef CONFIG_HUGETLB_PAGE |
807 | beq 6, 8f /* skip restore for 4k page faults */ | |
808 | lwz r14, THREAD_NORMSAVE(4)(r10) | |
809 | lwz r15, THREAD_NORMSAVE(5)(r10) | |
810 | lwz r16, THREAD_NORMSAVE(6)(r10) | |
811 | lwz r17, THREAD_NORMSAVE(7)(r10) | |
812 | #endif | |
813 | 8: lwz r11, THREAD_NORMSAVE(3)(r10) | |
14cf11af | 814 | mtcr r11 |
1325a684 AK |
815 | lwz r13, THREAD_NORMSAVE(2)(r10) |
816 | lwz r12, THREAD_NORMSAVE(1)(r10) | |
817 | lwz r11, THREAD_NORMSAVE(0)(r10) | |
ee43eb78 | 818 | mfspr r10, SPRN_SPRG_RSCRATCH0 |
14cf11af PM |
819 | rfi /* Force context change */ |
820 | ||
821 | #ifdef CONFIG_SPE | |
822 | /* Note that the SPE support is closely modeled after the AltiVec | |
823 | * support. Changes to one are likely to be applicable to the | |
824 | * other! */ | |
2dc3d4cc | 825 | _GLOBAL(load_up_spe) |
14cf11af PM |
826 | /* |
827 | * Disable SPE for the task which had SPE previously, | |
828 | * and save its SPE registers in its thread_struct. | |
829 | * Enables SPE for use in the kernel on return. | |
830 | * On SMP we know the SPE units are free, since we give it up every | |
831 | * switch. -- Kumar | |
832 | */ | |
833 | mfmsr r5 | |
834 | oris r5,r5,MSR_SPE@h | |
835 | mtmsr r5 /* enable use of SPE now */ | |
836 | isync | |
14cf11af PM |
837 | /* enable use of SPE after return */ |
838 | oris r9,r9,MSR_SPE@h | |
ee43eb78 | 839 | mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ |
14cf11af PM |
840 | li r4,1 |
841 | li r10,THREAD_ACC | |
842 | stw r4,THREAD_USED_SPE(r5) | |
843 | evlddx evr4,r10,r5 | |
844 | evmra evr4,evr4 | |
c51584d5 | 845 | REST_32EVRS(0,r10,r5,THREAD_EVR0) |
2dc3d4cc | 846 | blr |
14cf11af PM |
847 | |
848 | /* | |
849 | * SPE unavailable trap from kernel - print a message, but let | |
850 | * the task use SPE in the kernel until it returns to user mode. | |
851 | */ | |
852 | KernelSPE: | |
853 | lwz r3,_MSR(r1) | |
854 | oris r3,r3,MSR_SPE@h | |
855 | stw r3,_MSR(r1) /* enable use of SPE after return */ | |
09156a7a | 856 | #ifdef CONFIG_PRINTK |
14cf11af PM |
857 | lis r3,87f@h |
858 | ori r3,r3,87f@l | |
859 | mr r4,r2 /* current */ | |
860 | lwz r5,_NIP(r1) | |
861 | bl printk | |
09156a7a | 862 | #endif |
14cf11af | 863 | b ret_from_except |
09156a7a | 864 | #ifdef CONFIG_PRINTK |
14cf11af | 865 | 87: .string "SPE used in kernel (task=%p, pc=%x) \n" |
09156a7a | 866 | #endif |
14cf11af PM |
867 | .align 4,0 |
868 | ||
869 | #endif /* CONFIG_SPE */ | |
870 | ||
99739611 KH |
871 | /* |
872 | * Translate the effec addr in r3 to phys addr. The phys addr will be put | |
873 | * into r3(higher 32bit) and r4(lower 32bit) | |
874 | */ | |
875 | get_phys_addr: | |
876 | mfmsr r8 | |
877 | mfspr r9,SPRN_PID | |
878 | rlwinm r9,r9,16,0x3fff0000 /* turn PID into MAS6[SPID] */ | |
879 | rlwimi r9,r8,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */ | |
880 | mtspr SPRN_MAS6,r9 | |
881 | ||
882 | tlbsx 0,r3 /* must succeed */ | |
883 | ||
884 | mfspr r8,SPRN_MAS1 | |
885 | mfspr r12,SPRN_MAS3 | |
886 | rlwinm r9,r8,25,0x1f /* r9 = log2(page size) */ | |
887 | li r10,1024 | |
888 | slw r10,r10,r9 /* r10 = page size */ | |
889 | addi r10,r10,-1 | |
890 | and r11,r3,r10 /* r11 = page offset */ | |
891 | andc r4,r12,r10 /* r4 = page base */ | |
892 | or r4,r4,r11 /* r4 = devtree phys addr */ | |
893 | #ifdef CONFIG_PHYS_64BIT | |
894 | mfspr r3,SPRN_MAS7 | |
895 | #endif | |
896 | blr | |
897 | ||
14cf11af PM |
898 | /* |
899 | * Global functions | |
900 | */ | |
901 | ||
3477e71d MC |
902 | #ifdef CONFIG_E500 |
903 | #ifndef CONFIG_PPC_E500MC | |
105c31df KG |
904 | /* Adjust or setup IVORs for e500v1/v2 */ |
905 | _GLOBAL(__setup_e500_ivors) | |
906 | li r3,DebugCrit@l | |
907 | mtspr SPRN_IVOR15,r3 | |
908 | li r3,SPEUnavailable@l | |
909 | mtspr SPRN_IVOR32,r3 | |
910 | li r3,SPEFloatingPointData@l | |
911 | mtspr SPRN_IVOR33,r3 | |
912 | li r3,SPEFloatingPointRound@l | |
913 | mtspr SPRN_IVOR34,r3 | |
914 | li r3,PerformanceMonitor@l | |
915 | mtspr SPRN_IVOR35,r3 | |
916 | sync | |
917 | blr | |
3477e71d | 918 | #else |
105c31df KG |
919 | /* Adjust or setup IVORs for e500mc */ |
920 | _GLOBAL(__setup_e500mc_ivors) | |
921 | li r3,DebugDebug@l | |
922 | mtspr SPRN_IVOR15,r3 | |
923 | li r3,PerformanceMonitor@l | |
924 | mtspr SPRN_IVOR35,r3 | |
925 | li r3,Doorbell@l | |
926 | mtspr SPRN_IVOR36,r3 | |
620165f9 KG |
927 | li r3,CriticalDoorbell@l |
928 | mtspr SPRN_IVOR37,r3 | |
7e0f4872 VS |
929 | sync |
930 | blr | |
73196cd3 | 931 | |
7e0f4872 VS |
932 | /* setup ehv ivors for */ |
933 | _GLOBAL(__setup_ehv_ivors) | |
73196cd3 SW |
934 | li r3,GuestDoorbell@l |
935 | mtspr SPRN_IVOR38,r3 | |
936 | li r3,CriticalGuestDoorbell@l | |
937 | mtspr SPRN_IVOR39,r3 | |
938 | li r3,Hypercall@l | |
939 | mtspr SPRN_IVOR40,r3 | |
940 | li r3,Ehvpriv@l | |
941 | mtspr SPRN_IVOR41,r3 | |
105c31df KG |
942 | sync |
943 | blr | |
3477e71d MC |
944 | #endif /* CONFIG_PPC_E500MC */ |
945 | #endif /* CONFIG_E500 */ | |
105c31df | 946 | |
14cf11af PM |
947 | #ifdef CONFIG_SPE |
948 | /* | |
98da581e | 949 | * extern void __giveup_spe(struct task_struct *prev) |
14cf11af PM |
950 | * |
951 | */ | |
98da581e | 952 | _GLOBAL(__giveup_spe) |
14cf11af PM |
953 | addi r3,r3,THREAD /* want THREAD of task */ |
954 | lwz r5,PT_REGS(r3) | |
955 | cmpi 0,r5,0 | |
c51584d5 | 956 | SAVE_32EVRS(0, r4, r3, THREAD_EVR0) |
3c5df5c2 | 957 | evxor evr6, evr6, evr6 /* clear out evr6 */ |
14cf11af PM |
958 | evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */ |
959 | li r4,THREAD_ACC | |
3c5df5c2 | 960 | evstddx evr6, r4, r3 /* save off accumulator */ |
14cf11af PM |
961 | beq 1f |
962 | lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
963 | lis r3,MSR_SPE@h | |
964 | andc r4,r4,r3 /* disable SPE for previous task */ | |
965 | stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
966 | 1: | |
14cf11af PM |
967 | blr |
968 | #endif /* CONFIG_SPE */ | |
969 | ||
14cf11af PM |
970 | /* |
971 | * extern void abort(void) | |
972 | * | |
973 | * At present, this routine just applies a system reset. | |
974 | */ | |
975 | _GLOBAL(abort) | |
976 | li r13,0 | |
3c5df5c2 | 977 | mtspr SPRN_DBCR0,r13 /* disable all debug events */ |
a7cb0337 | 978 | isync |
14cf11af PM |
979 | mfmsr r13 |
980 | ori r13,r13,MSR_DE@l /* Enable Debug Events */ | |
981 | mtmsr r13 | |
a7cb0337 | 982 | isync |
3c5df5c2 KG |
983 | mfspr r13,SPRN_DBCR0 |
984 | lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h | |
985 | mtspr SPRN_DBCR0,r13 | |
a7cb0337 | 986 | isync |
14cf11af PM |
987 | |
988 | _GLOBAL(set_context) | |
989 | ||
990 | #ifdef CONFIG_BDI_SWITCH | |
991 | /* Context switch the PTE pointer for the Abatron BDI2000. | |
992 | * The PGDIR is the second parameter. | |
993 | */ | |
994 | lis r5, abatron_pteptrs@h | |
995 | ori r5, r5, abatron_pteptrs@l | |
996 | stw r4, 0x4(r5) | |
997 | #endif | |
998 | mtspr SPRN_PID,r3 | |
999 | isync /* Force context change */ | |
1000 | blr | |
1001 | ||
d5b26db2 KG |
1002 | #ifdef CONFIG_SMP |
1003 | /* When we get here, r24 needs to hold the CPU # */ | |
1004 | .globl __secondary_start | |
1005 | __secondary_start: | |
0be7d969 KH |
1006 | LOAD_REG_ADDR_PIC(r3, tlbcam_index) |
1007 | lwz r3,0(r3) | |
d5b26db2 KG |
1008 | mtctr r3 |
1009 | li r26,0 /* r26 safe? */ | |
1010 | ||
0be7d969 KH |
1011 | bl switch_to_as1 |
1012 | mr r27,r3 /* tlb entry */ | |
d5b26db2 KG |
1013 | /* Load each CAM entry */ |
1014 | 1: mr r3,r26 | |
1015 | bl loadcam_entry | |
1016 | addi r26,r26,1 | |
1017 | bdnz 1b | |
0be7d969 KH |
1018 | mr r3,r27 /* tlb entry */ |
1019 | LOAD_REG_ADDR_PIC(r4, memstart_addr) | |
1020 | lwz r4,0(r4) | |
1021 | mr r5,r25 /* phys kernel start */ | |
1022 | rlwinm r5,r5,0,~0x3ffffff /* aligned 64M */ | |
1023 | subf r4,r5,r4 /* memstart_addr - phys kernel start */ | |
2b0e86cc JY |
1024 | lis r7,KERNELBASE@h |
1025 | ori r7,r7,KERNELBASE@l | |
1026 | cmpw r20,r7 /* if kernstart_virt_addr != KERNELBASE, randomized */ | |
1027 | beq 2f | |
1028 | li r4,0 | |
1029 | 2: li r5,0 /* no device tree */ | |
0be7d969 KH |
1030 | li r6,0 /* not boot cpu */ |
1031 | bl restore_to_as0 | |
1032 | ||
1033 | ||
1034 | lis r3,__secondary_hold_acknowledge@h | |
1035 | ori r3,r3,__secondary_hold_acknowledge@l | |
1036 | stw r24,0(r3) | |
1037 | ||
1038 | li r3,0 | |
1039 | mr r4,r24 /* Why? */ | |
1040 | bl call_setup_cpu | |
d5b26db2 | 1041 | |
4e67bfd7 | 1042 | /* get current's stack and current */ |
7c19c2e5 CL |
1043 | lis r2,secondary_current@ha |
1044 | lwz r2,secondary_current@l(r2) | |
ed1cd6de | 1045 | lwz r1,TASK_STACK(r2) |
d5b26db2 KG |
1046 | |
1047 | /* stack */ | |
1048 | addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD | |
1049 | li r0,0 | |
1050 | stw r0,0(r1) | |
1051 | ||
1052 | /* ptr to current thread */ | |
1053 | addi r4,r2,THREAD /* address of our thread_struct */ | |
ee43eb78 | 1054 | mtspr SPRN_SPRG_THREAD,r4 |
d5b26db2 KG |
1055 | |
1056 | /* Setup the defaults for TLB entries */ | |
d66c82ea | 1057 | li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l |
d5b26db2 KG |
1058 | mtspr SPRN_MAS4,r4 |
1059 | ||
1060 | /* Jump to start_secondary */ | |
1061 | lis r4,MSR_KERNEL@h | |
1062 | ori r4,r4,MSR_KERNEL@l | |
1063 | lis r3,start_secondary@h | |
1064 | ori r3,r3,start_secondary@l | |
1065 | mtspr SPRN_SRR0,r3 | |
1066 | mtspr SPRN_SRR1,r4 | |
1067 | sync | |
1068 | rfi | |
1069 | sync | |
1070 | ||
1071 | .globl __secondary_hold_acknowledge | |
1072 | __secondary_hold_acknowledge: | |
1073 | .long -1 | |
1074 | #endif | |
1075 | ||
aa1d2090 JY |
1076 | /* |
1077 | * Create a 64M tlb by address and entry | |
1078 | * r3 - entry | |
1079 | * r4 - virtual address | |
1080 | * r5/r6 - physical address | |
1081 | */ | |
1082 | _GLOBAL(create_kaslr_tlb_entry) | |
1083 | lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
1084 | rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ | |
1085 | mtspr SPRN_MAS0,r7 /* Write MAS0 */ | |
1086 | ||
1087 | lis r3,(MAS1_VALID|MAS1_IPROT)@h | |
1088 | ori r3,r3,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l | |
1089 | mtspr SPRN_MAS1,r3 /* Write MAS1 */ | |
1090 | ||
1091 | lis r3,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@h | |
1092 | ori r3,r3,MAS2_EPN_MASK(BOOK3E_PAGESZ_64M)@l | |
1093 | and r3,r3,r4 | |
1094 | ori r3,r3,MAS2_M_IF_NEEDED@l | |
1095 | mtspr SPRN_MAS2,r3 /* Write MAS2(EPN) */ | |
1096 | ||
1097 | #ifdef CONFIG_PHYS_64BIT | |
1098 | ori r8,r6,(MAS3_SW|MAS3_SR|MAS3_SX) | |
1099 | mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */ | |
1100 | mtspr SPRN_MAS7,r5 | |
1101 | #else | |
1102 | ori r8,r5,(MAS3_SW|MAS3_SR|MAS3_SX) | |
1103 | mtspr SPRN_MAS3,r8 /* Write MAS3(RPN) */ | |
1104 | #endif | |
1105 | ||
1106 | tlbwe /* Write TLB */ | |
1107 | isync | |
1108 | sync | |
1109 | blr | |
1110 | ||
c061b38a JY |
1111 | /* |
1112 | * Return to the start of the relocated kernel and run again | |
1113 | * r3 - virtual address of fdt | |
1114 | * r4 - entry of the kernel | |
1115 | */ | |
1116 | _GLOBAL(reloc_kernel_entry) | |
1117 | mfmsr r7 | |
1118 | rlwinm r7, r7, 0, ~(MSR_IS | MSR_DS) | |
1119 | ||
1120 | mtspr SPRN_SRR0,r4 | |
1121 | mtspr SPRN_SRR1,r7 | |
1122 | rfi | |
1123 | ||
78a235ef KH |
1124 | /* |
1125 | * Create a tlb entry with the same effective and physical address as | |
1126 | * the tlb entry used by the current running code. But set the TS to 1. | |
1127 | * Then switch to the address space 1. It will return with the r3 set to | |
1128 | * the ESEL of the new created tlb. | |
1129 | */ | |
1130 | _GLOBAL(switch_to_as1) | |
1131 | mflr r5 | |
1132 | ||
1133 | /* Find a entry not used */ | |
1134 | mfspr r3,SPRN_TLB1CFG | |
1135 | andi. r3,r3,0xfff | |
1136 | mfspr r4,SPRN_PID | |
1137 | rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */ | |
1138 | mtspr SPRN_MAS6,r4 | |
1139 | 1: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
1140 | addi r3,r3,-1 | |
1141 | rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ | |
1142 | mtspr SPRN_MAS0,r4 | |
1143 | tlbre | |
1144 | mfspr r4,SPRN_MAS1 | |
1145 | andis. r4,r4,MAS1_VALID@h | |
1146 | bne 1b | |
1147 | ||
1148 | /* Get the tlb entry used by the current running code */ | |
1149 | bl 0f | |
1150 | 0: mflr r4 | |
1151 | tlbsx 0,r4 | |
1152 | ||
1153 | mfspr r4,SPRN_MAS1 | |
1154 | ori r4,r4,MAS1_TS /* Set the TS = 1 */ | |
1155 | mtspr SPRN_MAS1,r4 | |
1156 | ||
1157 | mfspr r4,SPRN_MAS0 | |
1158 | rlwinm r4,r4,0,~MAS0_ESEL_MASK | |
1159 | rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ | |
1160 | mtspr SPRN_MAS0,r4 | |
1161 | tlbwe | |
1162 | isync | |
1163 | sync | |
1164 | ||
1165 | mfmsr r4 | |
1166 | ori r4,r4,MSR_IS | MSR_DS | |
1167 | mtspr SPRN_SRR0,r5 | |
1168 | mtspr SPRN_SRR1,r4 | |
1169 | sync | |
1170 | rfi | |
1171 | ||
1172 | /* | |
1173 | * Restore to the address space 0 and also invalidate the tlb entry created | |
1174 | * by switch_to_as1. | |
7d2471f9 KH |
1175 | * r3 - the tlb entry which should be invalidated |
1176 | * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0) | |
1177 | * r5 - device tree virtual address. If r4 is 0, r5 is ignored. | |
0be7d969 | 1178 | * r6 - boot cpu |
78a235ef KH |
1179 | */ |
1180 | _GLOBAL(restore_to_as0) | |
1181 | mflr r0 | |
1182 | ||
1183 | bl 0f | |
1184 | 0: mflr r9 | |
1185 | addi r9,r9,1f - 0b | |
1186 | ||
7d2471f9 KH |
1187 | /* |
1188 | * We may map the PAGE_OFFSET in AS0 to a different physical address, | |
1189 | * so we need calculate the right jump and device tree address based | |
1190 | * on the offset passed by r4. | |
1191 | */ | |
1192 | add r9,r9,r4 | |
1193 | add r5,r5,r4 | |
0be7d969 | 1194 | add r0,r0,r4 |
7d2471f9 KH |
1195 | |
1196 | 2: mfmsr r7 | |
78a235ef KH |
1197 | li r8,(MSR_IS | MSR_DS) |
1198 | andc r7,r7,r8 | |
1199 | ||
1200 | mtspr SPRN_SRR0,r9 | |
1201 | mtspr SPRN_SRR1,r7 | |
1202 | sync | |
1203 | rfi | |
1204 | ||
1205 | /* Invalidate the temporary tlb entry for AS1 */ | |
1206 | 1: lis r9,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
1207 | rlwimi r9,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ | |
1208 | mtspr SPRN_MAS0,r9 | |
1209 | tlbre | |
1210 | mfspr r9,SPRN_MAS1 | |
1211 | rlwinm r9,r9,0,2,31 /* Clear MAS1 Valid and IPPROT */ | |
1212 | mtspr SPRN_MAS1,r9 | |
1213 | tlbwe | |
1214 | isync | |
7d2471f9 KH |
1215 | |
1216 | cmpwi r4,0 | |
0be7d969 KH |
1217 | cmpwi cr1,r6,0 |
1218 | cror eq,4*cr1+eq,eq | |
1219 | bne 3f /* offset != 0 && is_boot_cpu */ | |
78a235ef KH |
1220 | mtlr r0 |
1221 | blr | |
1222 | ||
7d2471f9 KH |
1223 | /* |
1224 | * The PAGE_OFFSET will map to a different physical address, | |
1225 | * jump to _start to do another relocation again. | |
1226 | */ | |
1227 | 3: mr r3,r5 | |
1228 | bl _start | |
1229 | ||
14cf11af PM |
1230 | /* |
1231 | * We put a few things here that have to be page-aligned. This stuff | |
1232 | * goes at the beginning of the data segment, which is page-aligned. | |
1233 | */ | |
1234 | .data | |
ea703ce2 KG |
1235 | .align 12 |
1236 | .globl sdata | |
1237 | sdata: | |
1238 | .globl empty_zero_page | |
1239 | empty_zero_page: | |
14cf11af | 1240 | .space 4096 |
9445aa1a | 1241 | EXPORT_SYMBOL(empty_zero_page) |
ea703ce2 KG |
1242 | .globl swapper_pg_dir |
1243 | swapper_pg_dir: | |
bee86f14 | 1244 | .space PGD_TABLE_SIZE |
14cf11af | 1245 | |
14cf11af PM |
1246 | /* |
1247 | * Room for two PTE pointers, usually the kernel and current user pointers | |
1248 | * to their respective root page table. | |
1249 | */ | |
1250 | abatron_pteptrs: | |
1251 | .space 8 |