Commit | Line | Data |
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14cf11af | 1 | /* |
14cf11af PM |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
6 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
7 | * Adapted for Power Macintosh by Paul Mackerras. | |
8 | * Low-level exception handlers and MMU support | |
9 | * rewritten by Paul Mackerras. | |
10 | * Copyright (C) 1996 Paul Mackerras. | |
11 | * | |
12 | * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and | |
13 | * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com | |
14 | * | |
0ebc4cda BH |
15 | * This file contains the entry point for the 64-bit kernel along |
16 | * with some early initialization code common to all 64-bit powerpc | |
17 | * variants. | |
14cf11af PM |
18 | * |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License | |
21 | * as published by the Free Software Foundation; either version | |
22 | * 2 of the License, or (at your option) any later version. | |
23 | */ | |
24 | ||
14cf11af | 25 | #include <linux/threads.h> |
b5bbeb23 | 26 | #include <asm/reg.h> |
14cf11af PM |
27 | #include <asm/page.h> |
28 | #include <asm/mmu.h> | |
14cf11af PM |
29 | #include <asm/ppc_asm.h> |
30 | #include <asm/asm-offsets.h> | |
31 | #include <asm/bug.h> | |
32 | #include <asm/cputable.h> | |
33 | #include <asm/setup.h> | |
34 | #include <asm/hvcall.h> | |
6cb7bfeb | 35 | #include <asm/thread_info.h> |
3f639ee8 | 36 | #include <asm/firmware.h> |
16a15a30 | 37 | #include <asm/page_64.h> |
945feb17 | 38 | #include <asm/irqflags.h> |
2191d657 | 39 | #include <asm/kvm_book3s_asm.h> |
46f52210 | 40 | #include <asm/ptrace.h> |
7230c564 | 41 | #include <asm/hw_irq.h> |
14cf11af | 42 | |
25985edc | 43 | /* The physical memory is laid out such that the secondary processor |
0ebc4cda BH |
44 | * spin code sits at 0x0000...0x00ff. On server, the vectors follow |
45 | * using the layout described in exceptions-64s.S | |
14cf11af PM |
46 | */ |
47 | ||
48 | /* | |
49 | * Entering into this code we make the following assumptions: | |
0ebc4cda BH |
50 | * |
51 | * For pSeries or server processors: | |
14cf11af PM |
52 | * 1. The MMU is off & open firmware is running in real mode. |
53 | * 2. The kernel is entered at __start | |
27f44888 BH |
54 | * -or- For OPAL entry: |
55 | * 1. The MMU is off, processor in HV mode, primary CPU enters at 0 | |
daea1175 BH |
56 | * with device-tree in gpr3. We also get OPAL base in r8 and |
57 | * entry in r9 for debugging purposes | |
27f44888 | 58 | * 2. Secondary processors enter at 0x60 with PIR in gpr3 |
14cf11af | 59 | * |
0ebc4cda BH |
60 | * For Book3E processors: |
61 | * 1. The MMU is on running in AS0 in a state defined in ePAPR | |
62 | * 2. The kernel is entered at __start | |
14cf11af PM |
63 | */ |
64 | ||
65 | .text | |
66 | .globl _stext | |
67 | _stext: | |
14cf11af PM |
68 | _GLOBAL(__start) |
69 | /* NOP this out unconditionally */ | |
70 | BEGIN_FTR_SECTION | |
b85a046a | 71 | b .__start_initialization_multiplatform |
14cf11af | 72 | END_FTR_SECTION(0, 1) |
14cf11af PM |
73 | |
74 | /* Catch branch to 0 in real mode */ | |
75 | trap | |
76 | ||
1f6a93e4 PM |
77 | /* Secondary processors spin on this value until it becomes nonzero. |
78 | * When it does it contains the real address of the descriptor | |
79 | * of the function that the cpu should jump to to continue | |
80 | * initialization. | |
81 | */ | |
14cf11af PM |
82 | .globl __secondary_hold_spinloop |
83 | __secondary_hold_spinloop: | |
84 | .llong 0x0 | |
85 | ||
86 | /* Secondary processors write this value with their cpu # */ | |
87 | /* after they enter the spin loop immediately below. */ | |
88 | .globl __secondary_hold_acknowledge | |
89 | __secondary_hold_acknowledge: | |
90 | .llong 0x0 | |
91 | ||
928a3197 | 92 | #ifdef CONFIG_RELOCATABLE |
8b8b0cc1 MM |
93 | /* This flag is set to 1 by a loader if the kernel should run |
94 | * at the loaded address instead of the linked address. This | |
95 | * is used by kexec-tools to keep the the kdump kernel in the | |
96 | * crash_kernel region. The loader is responsible for | |
97 | * observing the alignment requirement. | |
98 | */ | |
99 | /* Do not move this variable as kexec-tools knows about it. */ | |
100 | . = 0x5c | |
101 | .globl __run_at_load | |
102 | __run_at_load: | |
103 | .long 0x72756e30 /* "run0" -- relocate to 0 by default */ | |
104 | #endif | |
105 | ||
14cf11af PM |
106 | . = 0x60 |
107 | /* | |
75423b7b GL |
108 | * The following code is used to hold secondary processors |
109 | * in a spin loop after they have entered the kernel, but | |
14cf11af PM |
110 | * before the bulk of the kernel has been relocated. This code |
111 | * is relocated to physical address 0x60 before prom_init is run. | |
112 | * All of it must fit below the first exception vector at 0x100. | |
1f6a93e4 PM |
113 | * Use .globl here not _GLOBAL because we want __secondary_hold |
114 | * to be the actual text address, not a descriptor. | |
14cf11af | 115 | */ |
1f6a93e4 PM |
116 | .globl __secondary_hold |
117 | __secondary_hold: | |
2d27cfd3 | 118 | #ifndef CONFIG_PPC_BOOK3E |
14cf11af PM |
119 | mfmsr r24 |
120 | ori r24,r24,MSR_RI | |
121 | mtmsrd r24 /* RI on */ | |
2d27cfd3 | 122 | #endif |
f1870f77 | 123 | /* Grab our physical cpu number */ |
14cf11af | 124 | mr r24,r3 |
96f013fe JX |
125 | /* stash r4 for book3e */ |
126 | mr r25,r4 | |
14cf11af PM |
127 | |
128 | /* Tell the master cpu we're here */ | |
129 | /* Relocation is off & we are located at an address less */ | |
130 | /* than 0x100, so only need to grab low order offset. */ | |
e31aa453 | 131 | std r24,__secondary_hold_acknowledge-_stext(0) |
14cf11af PM |
132 | sync |
133 | ||
96f013fe JX |
134 | li r26,0 |
135 | #ifdef CONFIG_PPC_BOOK3E | |
136 | tovirt(r26,r26) | |
137 | #endif | |
14cf11af | 138 | /* All secondary cpus wait here until told to start. */ |
96f013fe | 139 | 100: ld r4,__secondary_hold_spinloop-_stext(r26) |
1f6a93e4 PM |
140 | cmpdi 0,r4,0 |
141 | beq 100b | |
14cf11af | 142 | |
f1870f77 | 143 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) |
96f013fe JX |
144 | #ifdef CONFIG_PPC_BOOK3E |
145 | tovirt(r4,r4) | |
146 | #endif | |
1f6a93e4 | 147 | ld r4,0(r4) /* deref function descriptor */ |
758438a7 | 148 | mtctr r4 |
14cf11af | 149 | mr r3,r24 |
96f013fe JX |
150 | /* |
151 | * it may be the case that other platforms have r4 right to | |
152 | * begin with, this gives us some safety in case it is not | |
153 | */ | |
154 | #ifdef CONFIG_PPC_BOOK3E | |
155 | mr r4,r25 | |
156 | #else | |
2d27cfd3 | 157 | li r4,0 |
96f013fe | 158 | #endif |
dd797738 BH |
159 | /* Make sure that patched code is visible */ |
160 | isync | |
758438a7 | 161 | bctr |
14cf11af PM |
162 | #else |
163 | BUG_OPCODE | |
164 | #endif | |
14cf11af PM |
165 | |
166 | /* This value is used to mark exception frames on the stack. */ | |
167 | .section ".toc","aw" | |
168 | exception_marker: | |
169 | .tc ID_72656773_68657265[TC],0x7265677368657265 | |
170 | .text | |
171 | ||
14cf11af | 172 | /* |
0ebc4cda BH |
173 | * On server, we include the exception vectors code here as it |
174 | * relies on absolute addressing which is only possible within | |
175 | * this compilation unit | |
3c726f8d | 176 | */ |
0ebc4cda BH |
177 | #ifdef CONFIG_PPC_BOOK3S |
178 | #include "exceptions-64s.S" | |
1f6a93e4 | 179 | #endif |
3c726f8d | 180 | |
2d27cfd3 BH |
181 | _GLOBAL(generic_secondary_thread_init) |
182 | mr r24,r3 | |
183 | ||
184 | /* turn on 64-bit mode */ | |
185 | bl .enable_64b_mode | |
186 | ||
187 | /* get a valid TOC pointer, wherever we're mapped at */ | |
188 | bl .relative_toc | |
1fbe9cf2 | 189 | tovirt(r2,r2) |
2d27cfd3 BH |
190 | |
191 | #ifdef CONFIG_PPC_BOOK3E | |
192 | /* Book3E initialization */ | |
193 | mr r3,r24 | |
194 | bl .book3e_secondary_thread_init | |
195 | #endif | |
196 | b generic_secondary_common_init | |
14cf11af PM |
197 | |
198 | /* | |
f39b7a55 OJ |
199 | * On pSeries and most other platforms, secondary processors spin |
200 | * in the following code. | |
14cf11af | 201 | * At entry, r3 = this processor's number (physical cpu id) |
2d27cfd3 BH |
202 | * |
203 | * On Book3E, r4 = 1 to indicate that the initial TLB entry for | |
204 | * this core already exists (setup via some other mechanism such | |
205 | * as SCOM before entry). | |
14cf11af | 206 | */ |
f39b7a55 | 207 | _GLOBAL(generic_secondary_smp_init) |
14cf11af | 208 | mr r24,r3 |
2d27cfd3 BH |
209 | mr r25,r4 |
210 | ||
14cf11af PM |
211 | /* turn on 64-bit mode */ |
212 | bl .enable_64b_mode | |
14cf11af | 213 | |
2d27cfd3 | 214 | /* get a valid TOC pointer, wherever we're mapped at */ |
e31aa453 | 215 | bl .relative_toc |
1fbe9cf2 | 216 | tovirt(r2,r2) |
e31aa453 | 217 | |
2d27cfd3 BH |
218 | #ifdef CONFIG_PPC_BOOK3E |
219 | /* Book3E initialization */ | |
220 | mr r3,r24 | |
221 | mr r4,r25 | |
222 | bl .book3e_secondary_core_init | |
223 | #endif | |
224 | ||
225 | generic_secondary_common_init: | |
14cf11af PM |
226 | /* Set up a paca value for this processor. Since we have the |
227 | * physical cpu id in r24, we need to search the pacas to find | |
228 | * which logical id maps to our physical one. | |
229 | */ | |
1426d5a3 ME |
230 | LOAD_REG_ADDR(r13, paca) /* Load paca pointer */ |
231 | ld r13,0(r13) /* Get base vaddr of paca array */ | |
768d18ad MM |
232 | #ifndef CONFIG_SMP |
233 | addi r13,r13,PACA_SIZE /* know r13 if used accidentally */ | |
234 | b .kexec_wait /* wait for next kernel if !SMP */ | |
235 | #else | |
236 | LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */ | |
237 | lwz r7,0(r7) /* also the max paca allocated */ | |
14cf11af PM |
238 | li r5,0 /* logical cpu id */ |
239 | 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ | |
240 | cmpw r6,r24 /* Compare to our id */ | |
241 | beq 2f | |
242 | addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ | |
243 | addi r5,r5,1 | |
768d18ad | 244 | cmpw r5,r7 /* Check if more pacas exist */ |
14cf11af PM |
245 | blt 1b |
246 | ||
247 | mr r3,r24 /* not found, copy phys to r3 */ | |
248 | b .kexec_wait /* next kernel might do better */ | |
249 | ||
2dd60d79 | 250 | 2: SET_PACA(r13) |
2d27cfd3 BH |
251 | #ifdef CONFIG_PPC_BOOK3E |
252 | addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ | |
253 | mtspr SPRN_SPRG_TLB_EXFRAME,r12 | |
254 | #endif | |
255 | ||
14cf11af PM |
256 | /* From now on, r24 is expected to be logical cpuid */ |
257 | mr r24,r5 | |
b6f6b98a | 258 | |
f39b7a55 | 259 | /* See if we need to call a cpu state restore handler */ |
e31aa453 | 260 | LOAD_REG_ADDR(r23, cur_cpu_spec) |
f39b7a55 OJ |
261 | ld r23,0(r23) |
262 | ld r23,CPU_SPEC_RESTORE(r23) | |
263 | cmpdi 0,r23,0 | |
9d07bc84 | 264 | beq 3f |
f39b7a55 OJ |
265 | ld r23,0(r23) |
266 | mtctr r23 | |
267 | bctrl | |
268 | ||
7ac87abb | 269 | 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */ |
9d07bc84 BH |
270 | lwarx r4,0,r3 |
271 | subi r4,r4,1 | |
272 | stwcx. r4,0,r3 | |
273 | bne 3b | |
274 | isync | |
275 | ||
276 | 4: HMT_LOW | |
ad0693ee BH |
277 | lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ |
278 | /* start. */ | |
ad0693ee | 279 | cmpwi 0,r23,0 |
9d07bc84 | 280 | beq 4b /* Loop until told to go */ |
ad0693ee BH |
281 | |
282 | sync /* order paca.run and cur_cpu_spec */ | |
9d07bc84 | 283 | isync /* In case code patching happened */ |
ad0693ee | 284 | |
9d07bc84 | 285 | /* Create a temp kernel stack for use before relocation is on. */ |
14cf11af PM |
286 | ld r1,PACAEMERGSP(r13) |
287 | subi r1,r1,STACK_FRAME_OVERHEAD | |
288 | ||
c705677e | 289 | b __secondary_start |
768d18ad | 290 | #endif /* SMP */ |
14cf11af | 291 | |
e31aa453 PM |
292 | /* |
293 | * Turn the MMU off. | |
294 | * Assumes we're mapped EA == RA if the MMU is on. | |
295 | */ | |
2d27cfd3 | 296 | #ifdef CONFIG_PPC_BOOK3S |
14cf11af PM |
297 | _STATIC(__mmu_off) |
298 | mfmsr r3 | |
299 | andi. r0,r3,MSR_IR|MSR_DR | |
300 | beqlr | |
e31aa453 | 301 | mflr r4 |
14cf11af PM |
302 | andc r3,r3,r0 |
303 | mtspr SPRN_SRR0,r4 | |
304 | mtspr SPRN_SRR1,r3 | |
305 | sync | |
306 | rfid | |
307 | b . /* prevent speculative execution */ | |
2d27cfd3 | 308 | #endif |
14cf11af PM |
309 | |
310 | ||
311 | /* | |
312 | * Here is our main kernel entry point. We support currently 2 kind of entries | |
313 | * depending on the value of r5. | |
314 | * | |
315 | * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content | |
316 | * in r3...r7 | |
317 | * | |
318 | * r5 == NULL -> kexec style entry. r3 is a physical pointer to the | |
319 | * DT block, r4 is a physical pointer to the kernel itself | |
320 | * | |
321 | */ | |
322 | _GLOBAL(__start_initialization_multiplatform) | |
e31aa453 PM |
323 | /* Make sure we are running in 64 bits mode */ |
324 | bl .enable_64b_mode | |
325 | ||
326 | /* Get TOC pointer (current runtime address) */ | |
327 | bl .relative_toc | |
328 | ||
329 | /* find out where we are now */ | |
330 | bcl 20,31,$+4 | |
331 | 0: mflr r26 /* r26 = runtime addr here */ | |
332 | addis r26,r26,(_stext - 0b)@ha | |
333 | addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ | |
334 | ||
14cf11af PM |
335 | /* |
336 | * Are we booted from a PROM Of-type client-interface ? | |
337 | */ | |
338 | cmpldi cr0,r5,0 | |
939e60f6 SR |
339 | beq 1f |
340 | b .__boot_from_prom /* yes -> prom */ | |
341 | 1: | |
14cf11af PM |
342 | /* Save parameters */ |
343 | mr r31,r3 | |
344 | mr r30,r4 | |
daea1175 BH |
345 | #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL |
346 | /* Save OPAL entry */ | |
347 | mr r28,r8 | |
348 | mr r29,r9 | |
349 | #endif | |
14cf11af | 350 | |
2d27cfd3 BH |
351 | #ifdef CONFIG_PPC_BOOK3E |
352 | bl .start_initialization_book3e | |
353 | b .__after_prom_start | |
354 | #else | |
14cf11af | 355 | /* Setup some critical 970 SPRs before switching MMU off */ |
f39b7a55 OJ |
356 | mfspr r0,SPRN_PVR |
357 | srwi r0,r0,16 | |
358 | cmpwi r0,0x39 /* 970 */ | |
359 | beq 1f | |
360 | cmpwi r0,0x3c /* 970FX */ | |
361 | beq 1f | |
362 | cmpwi r0,0x44 /* 970MP */ | |
190a24f5 OJ |
363 | beq 1f |
364 | cmpwi r0,0x45 /* 970GX */ | |
f39b7a55 OJ |
365 | bne 2f |
366 | 1: bl .__cpu_preinit_ppc970 | |
367 | 2: | |
14cf11af | 368 | |
e31aa453 | 369 | /* Switch off MMU if not already off */ |
14cf11af PM |
370 | bl .__mmu_off |
371 | b .__after_prom_start | |
2d27cfd3 | 372 | #endif /* CONFIG_PPC_BOOK3E */ |
14cf11af | 373 | |
939e60f6 | 374 | _INIT_STATIC(__boot_from_prom) |
28794d34 | 375 | #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE |
14cf11af PM |
376 | /* Save parameters */ |
377 | mr r31,r3 | |
378 | mr r30,r4 | |
379 | mr r29,r5 | |
380 | mr r28,r6 | |
381 | mr r27,r7 | |
382 | ||
6088857b OH |
383 | /* |
384 | * Align the stack to 16-byte boundary | |
385 | * Depending on the size and layout of the ELF sections in the initial | |
e31aa453 | 386 | * boot binary, the stack pointer may be unaligned on PowerMac |
6088857b | 387 | */ |
c05b4770 LT |
388 | rldicr r1,r1,0,59 |
389 | ||
549e8152 PM |
390 | #ifdef CONFIG_RELOCATABLE |
391 | /* Relocate code for where we are now */ | |
392 | mr r3,r26 | |
393 | bl .relocate | |
394 | #endif | |
395 | ||
14cf11af PM |
396 | /* Restore parameters */ |
397 | mr r3,r31 | |
398 | mr r4,r30 | |
399 | mr r5,r29 | |
400 | mr r6,r28 | |
401 | mr r7,r27 | |
402 | ||
403 | /* Do all of the interaction with OF client interface */ | |
549e8152 | 404 | mr r8,r26 |
14cf11af | 405 | bl .prom_init |
28794d34 BH |
406 | #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ |
407 | ||
408 | /* We never return. We also hit that trap if trying to boot | |
409 | * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ | |
14cf11af PM |
410 | trap |
411 | ||
14cf11af | 412 | _STATIC(__after_prom_start) |
549e8152 PM |
413 | #ifdef CONFIG_RELOCATABLE |
414 | /* process relocations for the final address of the kernel */ | |
415 | lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ | |
416 | sldi r25,r25,32 | |
8b8b0cc1 | 417 | lwz r7,__run_at_load-_stext(r26) |
928a3197 | 418 | cmplwi cr0,r7,1 /* flagged to stay where we are ? */ |
54622f10 MK |
419 | bne 1f |
420 | add r25,r25,r26 | |
54622f10 | 421 | 1: mr r3,r25 |
549e8152 PM |
422 | bl .relocate |
423 | #endif | |
14cf11af PM |
424 | |
425 | /* | |
e31aa453 | 426 | * We need to run with _stext at physical address PHYSICAL_START. |
14cf11af PM |
427 | * This will leave some code in the first 256B of |
428 | * real memory, which are reserved for software use. | |
14cf11af PM |
429 | * |
430 | * Note: This process overwrites the OF exception vectors. | |
14cf11af | 431 | */ |
549e8152 | 432 | li r3,0 /* target addr */ |
2d27cfd3 BH |
433 | #ifdef CONFIG_PPC_BOOK3E |
434 | tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ | |
435 | #endif | |
549e8152 | 436 | mr. r4,r26 /* In some cases the loader may */ |
e31aa453 | 437 | beq 9f /* have already put us at zero */ |
14cf11af PM |
438 | li r6,0x100 /* Start offset, the first 0x100 */ |
439 | /* bytes were copied earlier. */ | |
2d27cfd3 BH |
440 | #ifdef CONFIG_PPC_BOOK3E |
441 | tovirt(r6,r6) /* on booke, we already run at PAGE_OFFSET */ | |
442 | #endif | |
14cf11af | 443 | |
11ee7e99 | 444 | #ifdef CONFIG_RELOCATABLE |
54622f10 MK |
445 | /* |
446 | * Check if the kernel has to be running as relocatable kernel based on the | |
8b8b0cc1 | 447 | * variable __run_at_load, if it is set the kernel is treated as relocatable |
54622f10 MK |
448 | * kernel, otherwise it will be moved to PHYSICAL_START |
449 | */ | |
8b8b0cc1 MM |
450 | lwz r7,__run_at_load-_stext(r26) |
451 | cmplwi cr0,r7,1 | |
54622f10 MK |
452 | bne 3f |
453 | ||
c1fb6816 MN |
454 | /* just copy interrupts */ |
455 | LOAD_REG_IMMEDIATE(r5, __end_interrupts - _stext) | |
54622f10 MK |
456 | b 5f |
457 | 3: | |
458 | #endif | |
459 | lis r5,(copy_to_here - _stext)@ha | |
460 | addi r5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */ | |
461 | ||
14cf11af PM |
462 | bl .copy_and_flush /* copy the first n bytes */ |
463 | /* this includes the code being */ | |
464 | /* executed here. */ | |
e31aa453 PM |
465 | addis r8,r3,(4f - _stext)@ha /* Jump to the copy of this code */ |
466 | addi r8,r8,(4f - _stext)@l /* that we just made */ | |
467 | mtctr r8 | |
14cf11af PM |
468 | bctr |
469 | ||
54622f10 MK |
470 | p_end: .llong _end - _stext |
471 | ||
e31aa453 PM |
472 | 4: /* Now copy the rest of the kernel up to _end */ |
473 | addis r5,r26,(p_end - _stext)@ha | |
474 | ld r5,(p_end - _stext)@l(r5) /* get _end */ | |
54622f10 | 475 | 5: bl .copy_and_flush /* copy the rest */ |
e31aa453 PM |
476 | |
477 | 9: b .start_here_multiplatform | |
478 | ||
14cf11af PM |
479 | /* |
480 | * Copy routine used to copy the kernel to start at physical address 0 | |
481 | * and flush and invalidate the caches as needed. | |
482 | * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset | |
483 | * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. | |
484 | * | |
485 | * Note: this routine *only* clobbers r0, r6 and lr | |
486 | */ | |
487 | _GLOBAL(copy_and_flush) | |
488 | addi r5,r5,-8 | |
489 | addi r6,r6,-8 | |
5a2fe38d | 490 | 4: li r0,8 /* Use the smallest common */ |
14cf11af PM |
491 | /* denominator cache line */ |
492 | /* size. This results in */ | |
493 | /* extra cache line flushes */ | |
494 | /* but operation is correct. */ | |
495 | /* Can't get cache line size */ | |
496 | /* from NACA as it is being */ | |
497 | /* moved too. */ | |
498 | ||
499 | mtctr r0 /* put # words/line in ctr */ | |
500 | 3: addi r6,r6,8 /* copy a cache line */ | |
501 | ldx r0,r6,r4 | |
502 | stdx r0,r6,r3 | |
503 | bdnz 3b | |
504 | dcbst r6,r3 /* write it to memory */ | |
505 | sync | |
506 | icbi r6,r3 /* flush the icache line */ | |
507 | cmpld 0,r6,r5 | |
508 | blt 4b | |
509 | sync | |
510 | addi r5,r5,8 | |
511 | addi r6,r6,8 | |
29ce3c50 | 512 | isync |
14cf11af PM |
513 | blr |
514 | ||
515 | .align 8 | |
516 | copy_to_here: | |
517 | ||
518 | #ifdef CONFIG_SMP | |
519 | #ifdef CONFIG_PPC_PMAC | |
520 | /* | |
521 | * On PowerMac, secondary processors starts from the reset vector, which | |
522 | * is temporarily turned into a call to one of the functions below. | |
523 | */ | |
524 | .section ".text"; | |
525 | .align 2 ; | |
526 | ||
35499c01 PM |
527 | .globl __secondary_start_pmac_0 |
528 | __secondary_start_pmac_0: | |
529 | /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ | |
530 | li r24,0 | |
531 | b 1f | |
532 | li r24,1 | |
533 | b 1f | |
534 | li r24,2 | |
535 | b 1f | |
536 | li r24,3 | |
537 | 1: | |
14cf11af PM |
538 | |
539 | _GLOBAL(pmac_secondary_start) | |
540 | /* turn on 64-bit mode */ | |
541 | bl .enable_64b_mode | |
14cf11af | 542 | |
c478b581 BH |
543 | li r0,0 |
544 | mfspr r3,SPRN_HID4 | |
545 | rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ | |
546 | sync | |
547 | mtspr SPRN_HID4,r3 | |
548 | isync | |
549 | sync | |
550 | slbia | |
551 | ||
e31aa453 PM |
552 | /* get TOC pointer (real address) */ |
553 | bl .relative_toc | |
1fbe9cf2 | 554 | tovirt(r2,r2) |
e31aa453 | 555 | |
14cf11af | 556 | /* Copy some CPU settings from CPU 0 */ |
f39b7a55 | 557 | bl .__restore_cpu_ppc970 |
14cf11af PM |
558 | |
559 | /* pSeries do that early though I don't think we really need it */ | |
560 | mfmsr r3 | |
561 | ori r3,r3,MSR_RI | |
562 | mtmsrd r3 /* RI on */ | |
563 | ||
564 | /* Set up a paca value for this processor. */ | |
1426d5a3 ME |
565 | LOAD_REG_ADDR(r4,paca) /* Load paca pointer */ |
566 | ld r4,0(r4) /* Get base vaddr of paca array */ | |
e31aa453 | 567 | mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ |
14cf11af | 568 | add r13,r13,r4 /* for this processor. */ |
2dd60d79 | 569 | SET_PACA(r13) /* Save vaddr of paca in an SPRG*/ |
14cf11af | 570 | |
62cc67b9 BH |
571 | /* Mark interrupts soft and hard disabled (they might be enabled |
572 | * in the PACA when doing hotplug) | |
573 | */ | |
574 | li r0,0 | |
575 | stb r0,PACASOFTIRQEN(r13) | |
7230c564 BH |
576 | li r0,PACA_IRQ_HARD_DIS |
577 | stb r0,PACAIRQHAPPENED(r13) | |
62cc67b9 | 578 | |
14cf11af PM |
579 | /* Create a temp kernel stack for use before relocation is on. */ |
580 | ld r1,PACAEMERGSP(r13) | |
581 | subi r1,r1,STACK_FRAME_OVERHEAD | |
582 | ||
c705677e | 583 | b __secondary_start |
14cf11af PM |
584 | |
585 | #endif /* CONFIG_PPC_PMAC */ | |
586 | ||
587 | /* | |
588 | * This function is called after the master CPU has released the | |
589 | * secondary processors. The execution environment is relocation off. | |
590 | * The paca for this processor has the following fields initialized at | |
591 | * this point: | |
592 | * 1. Processor number | |
593 | * 2. Segment table pointer (virtual address) | |
594 | * On entry the following are set: | |
4f8cf36f | 595 | * r1 = stack pointer (real addr of temp stack) |
ee43eb78 BH |
596 | * r24 = cpu# (in Linux terms) |
597 | * r13 = paca virtual address | |
598 | * SPRG_PACA = paca virtual address | |
14cf11af | 599 | */ |
2d27cfd3 BH |
600 | .section ".text"; |
601 | .align 2 ; | |
602 | ||
fc68e869 | 603 | .globl __secondary_start |
c705677e | 604 | __secondary_start: |
799d6046 PM |
605 | /* Set thread priority to MEDIUM */ |
606 | HMT_MEDIUM | |
14cf11af | 607 | |
4f8cf36f | 608 | /* Initialize the kernel stack */ |
e58c3495 | 609 | LOAD_REG_ADDR(r3, current_set) |
14cf11af | 610 | sldi r28,r24,3 /* get current_set[cpu#] */ |
54a83404 MN |
611 | ldx r14,r3,r28 |
612 | addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD | |
613 | std r14,PACAKSAVE(r13) | |
14cf11af | 614 | |
f761622e ME |
615 | /* Do early setup for that CPU (stab, slb, hash table pointer) */ |
616 | bl .early_setup_secondary | |
617 | ||
54a83404 MN |
618 | /* |
619 | * setup the new stack pointer, but *don't* use this until | |
620 | * translation is on. | |
621 | */ | |
622 | mr r1, r14 | |
623 | ||
799d6046 | 624 | /* Clear backchain so we get nice backtraces */ |
14cf11af PM |
625 | li r7,0 |
626 | mtlr r7 | |
627 | ||
7230c564 BH |
628 | /* Mark interrupts soft and hard disabled (they might be enabled |
629 | * in the PACA when doing hotplug) | |
630 | */ | |
4f8cf36f | 631 | stb r7,PACASOFTIRQEN(r13) |
7230c564 BH |
632 | li r0,PACA_IRQ_HARD_DIS |
633 | stb r0,PACAIRQHAPPENED(r13) | |
4f8cf36f | 634 | |
14cf11af | 635 | /* enable MMU and jump to start_secondary */ |
e58c3495 DG |
636 | LOAD_REG_ADDR(r3, .start_secondary_prolog) |
637 | LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) | |
d04c56f7 | 638 | |
b5bbeb23 PM |
639 | mtspr SPRN_SRR0,r3 |
640 | mtspr SPRN_SRR1,r4 | |
2d27cfd3 | 641 | RFI |
14cf11af PM |
642 | b . /* prevent speculative execution */ |
643 | ||
644 | /* | |
645 | * Running with relocation on at this point. All we want to do is | |
e31aa453 PM |
646 | * zero the stack back-chain pointer and get the TOC virtual address |
647 | * before going into C code. | |
14cf11af PM |
648 | */ |
649 | _GLOBAL(start_secondary_prolog) | |
e31aa453 | 650 | ld r2,PACATOC(r13) |
14cf11af PM |
651 | li r3,0 |
652 | std r3,0(r1) /* Zero the stack frame pointer */ | |
653 | bl .start_secondary | |
799d6046 | 654 | b . |
8dbce53c VS |
655 | /* |
656 | * Reset stack pointer and call start_secondary | |
657 | * to continue with online operation when woken up | |
658 | * from cede in cpu offline. | |
659 | */ | |
660 | _GLOBAL(start_secondary_resume) | |
661 | ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ | |
662 | li r3,0 | |
663 | std r3,0(r1) /* Zero the stack frame pointer */ | |
664 | bl .start_secondary | |
665 | b . | |
14cf11af PM |
666 | #endif |
667 | ||
668 | /* | |
669 | * This subroutine clobbers r11 and r12 | |
670 | */ | |
671 | _GLOBAL(enable_64b_mode) | |
672 | mfmsr r11 /* grab the current MSR */ | |
2d27cfd3 BH |
673 | #ifdef CONFIG_PPC_BOOK3E |
674 | oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ | |
675 | mtmsr r11 | |
676 | #else /* CONFIG_PPC_BOOK3E */ | |
9f0b0793 | 677 | li r12,(MSR_64BIT | MSR_ISF)@highest |
e31aa453 | 678 | sldi r12,r12,48 |
14cf11af PM |
679 | or r11,r11,r12 |
680 | mtmsrd r11 | |
681 | isync | |
2d27cfd3 | 682 | #endif |
14cf11af PM |
683 | blr |
684 | ||
e31aa453 PM |
685 | /* |
686 | * This puts the TOC pointer into r2, offset by 0x8000 (as expected | |
687 | * by the toolchain). It computes the correct value for wherever we | |
688 | * are running at the moment, using position-independent code. | |
1fbe9cf2 AB |
689 | * |
690 | * Note: The compiler constructs pointers using offsets from the | |
691 | * TOC in -mcmodel=medium mode. After we relocate to 0 but before | |
692 | * the MMU is on we need our TOC to be a virtual address otherwise | |
693 | * these pointers will be real addresses which may get stored and | |
694 | * accessed later with the MMU on. We use tovirt() at the call | |
695 | * sites to handle this. | |
e31aa453 PM |
696 | */ |
697 | _GLOBAL(relative_toc) | |
698 | mflr r0 | |
699 | bcl 20,31,$+4 | |
e550592e BH |
700 | 0: mflr r11 |
701 | ld r2,(p_toc - 0b)(r11) | |
702 | add r2,r2,r11 | |
e31aa453 PM |
703 | mtlr r0 |
704 | blr | |
705 | ||
706 | p_toc: .llong __toc_start + 0x8000 - 0b | |
707 | ||
14cf11af PM |
708 | /* |
709 | * This is where the main kernel code starts. | |
710 | */ | |
939e60f6 | 711 | _INIT_STATIC(start_here_multiplatform) |
1fbe9cf2 AB |
712 | /* set up the TOC */ |
713 | bl .relative_toc | |
714 | tovirt(r2,r2) | |
14cf11af PM |
715 | |
716 | /* Clear out the BSS. It may have been done in prom_init, | |
717 | * already but that's irrelevant since prom_init will soon | |
718 | * be detached from the kernel completely. Besides, we need | |
719 | * to clear it now for kexec-style entry. | |
720 | */ | |
e31aa453 PM |
721 | LOAD_REG_ADDR(r11,__bss_stop) |
722 | LOAD_REG_ADDR(r8,__bss_start) | |
14cf11af PM |
723 | sub r11,r11,r8 /* bss size */ |
724 | addi r11,r11,7 /* round up to an even double word */ | |
e31aa453 | 725 | srdi. r11,r11,3 /* shift right by 3 */ |
14cf11af PM |
726 | beq 4f |
727 | addi r8,r8,-8 | |
728 | li r0,0 | |
729 | mtctr r11 /* zero this many doublewords */ | |
730 | 3: stdu r0,8(r8) | |
731 | bdnz 3b | |
732 | 4: | |
733 | ||
daea1175 BH |
734 | #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL |
735 | /* Setup OPAL entry */ | |
ab7f961a | 736 | LOAD_REG_ADDR(r11, opal) |
daea1175 BH |
737 | std r28,0(r11); |
738 | std r29,8(r11); | |
739 | #endif | |
740 | ||
2d27cfd3 | 741 | #ifndef CONFIG_PPC_BOOK3E |
14cf11af PM |
742 | mfmsr r6 |
743 | ori r6,r6,MSR_RI | |
744 | mtmsrd r6 /* RI on */ | |
2d27cfd3 | 745 | #endif |
14cf11af | 746 | |
549e8152 PM |
747 | #ifdef CONFIG_RELOCATABLE |
748 | /* Save the physical address we're running at in kernstart_addr */ | |
749 | LOAD_REG_ADDR(r4, kernstart_addr) | |
750 | clrldi r0,r25,2 | |
751 | std r0,0(r4) | |
752 | #endif | |
753 | ||
e31aa453 | 754 | /* The following gets the stack set up with the regs */ |
14cf11af PM |
755 | /* pointing to the real addr of the kernel stack. This is */ |
756 | /* all done to support the C function call below which sets */ | |
757 | /* up the htab. This is done because we have relocated the */ | |
758 | /* kernel but are still running in real mode. */ | |
759 | ||
e31aa453 | 760 | LOAD_REG_ADDR(r3,init_thread_union) |
14cf11af | 761 | |
e31aa453 | 762 | /* set up a stack pointer */ |
14cf11af PM |
763 | addi r1,r3,THREAD_SIZE |
764 | li r0,0 | |
765 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
766 | ||
14cf11af PM |
767 | /* Do very early kernel initializations, including initial hash table, |
768 | * stab and slb setup before we turn on relocation. */ | |
769 | ||
770 | /* Restore parameters passed from prom_init/kexec */ | |
771 | mr r3,r31 | |
ee43eb78 | 772 | bl .early_setup /* also sets r13 and SPRG_PACA */ |
14cf11af | 773 | |
e31aa453 PM |
774 | LOAD_REG_ADDR(r3, .start_here_common) |
775 | ld r4,PACAKMSR(r13) | |
b5bbeb23 PM |
776 | mtspr SPRN_SRR0,r3 |
777 | mtspr SPRN_SRR1,r4 | |
2d27cfd3 | 778 | RFI |
14cf11af | 779 | b . /* prevent speculative execution */ |
14cf11af PM |
780 | |
781 | /* This is where all platforms converge execution */ | |
fc68e869 | 782 | _INIT_GLOBAL(start_here_common) |
14cf11af | 783 | /* relocation is on at this point */ |
e31aa453 | 784 | std r1,PACAKSAVE(r13) |
14cf11af | 785 | |
e31aa453 | 786 | /* Load the TOC (virtual address) */ |
14cf11af | 787 | ld r2,PACATOC(r13) |
14cf11af | 788 | |
7230c564 | 789 | /* Do more system initializations in virtual mode */ |
14cf11af PM |
790 | bl .setup_system |
791 | ||
7230c564 BH |
792 | /* Mark interrupts soft and hard disabled (they might be enabled |
793 | * in the PACA when doing hotplug) | |
794 | */ | |
795 | li r0,0 | |
796 | stb r0,PACASOFTIRQEN(r13) | |
797 | li r0,PACA_IRQ_HARD_DIS | |
798 | stb r0,PACAIRQHAPPENED(r13) | |
14cf11af | 799 | |
7230c564 | 800 | /* Generic kernel entry */ |
ff3da2e0 | 801 | bl .start_kernel |
14cf11af | 802 | |
f1870f77 AB |
803 | /* Not reached */ |
804 | BUG_OPCODE | |
14cf11af | 805 | |
14cf11af PM |
806 | /* |
807 | * We put a few things here that have to be page-aligned. | |
808 | * This stuff goes at the beginning of the bss, which is page-aligned. | |
809 | */ | |
810 | .section ".bss" | |
811 | ||
812 | .align PAGE_SHIFT | |
813 | ||
814 | .globl empty_zero_page | |
815 | empty_zero_page: | |
816 | .space PAGE_SIZE | |
817 | ||
818 | .globl swapper_pg_dir | |
819 | swapper_pg_dir: | |
ee7a76da | 820 | .space PGD_TABLE_SIZE |