Commit | Line | Data |
---|---|---|
14cf11af | 1 | /* |
14cf11af PM |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
6 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
7 | * Adapted for Power Macintosh by Paul Mackerras. | |
8 | * Low-level exception handlers and MMU support | |
9 | * rewritten by Paul Mackerras. | |
10 | * Copyright (C) 1996 Paul Mackerras. | |
11 | * | |
12 | * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and | |
13 | * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com | |
14 | * | |
0ebc4cda BH |
15 | * This file contains the entry point for the 64-bit kernel along |
16 | * with some early initialization code common to all 64-bit powerpc | |
17 | * variants. | |
14cf11af PM |
18 | * |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License | |
21 | * as published by the Free Software Foundation; either version | |
22 | * 2 of the License, or (at your option) any later version. | |
23 | */ | |
24 | ||
14cf11af | 25 | #include <linux/threads.h> |
b5bbeb23 | 26 | #include <asm/reg.h> |
14cf11af PM |
27 | #include <asm/page.h> |
28 | #include <asm/mmu.h> | |
14cf11af PM |
29 | #include <asm/ppc_asm.h> |
30 | #include <asm/asm-offsets.h> | |
31 | #include <asm/bug.h> | |
32 | #include <asm/cputable.h> | |
33 | #include <asm/setup.h> | |
34 | #include <asm/hvcall.h> | |
c43a55ff | 35 | #include <asm/iseries/lpar_map.h> |
6cb7bfeb | 36 | #include <asm/thread_info.h> |
3f639ee8 | 37 | #include <asm/firmware.h> |
16a15a30 | 38 | #include <asm/page_64.h> |
945feb17 | 39 | #include <asm/irqflags.h> |
2191d657 | 40 | #include <asm/kvm_book3s_asm.h> |
46f52210 | 41 | #include <asm/ptrace.h> |
14cf11af | 42 | |
25985edc | 43 | /* The physical memory is laid out such that the secondary processor |
0ebc4cda BH |
44 | * spin code sits at 0x0000...0x00ff. On server, the vectors follow |
45 | * using the layout described in exceptions-64s.S | |
14cf11af PM |
46 | */ |
47 | ||
48 | /* | |
49 | * Entering into this code we make the following assumptions: | |
0ebc4cda BH |
50 | * |
51 | * For pSeries or server processors: | |
14cf11af PM |
52 | * 1. The MMU is off & open firmware is running in real mode. |
53 | * 2. The kernel is entered at __start | |
27f44888 BH |
54 | * -or- For OPAL entry: |
55 | * 1. The MMU is off, processor in HV mode, primary CPU enters at 0 | |
56 | * with device-tree in gpr3 | |
57 | * 2. Secondary processors enter at 0x60 with PIR in gpr3 | |
14cf11af PM |
58 | * |
59 | * For iSeries: | |
60 | * 1. The MMU is on (as it always is for iSeries) | |
61 | * 2. The kernel is entered at system_reset_iSeries | |
0ebc4cda BH |
62 | * |
63 | * For Book3E processors: | |
64 | * 1. The MMU is on running in AS0 in a state defined in ePAPR | |
65 | * 2. The kernel is entered at __start | |
14cf11af PM |
66 | */ |
67 | ||
68 | .text | |
69 | .globl _stext | |
70 | _stext: | |
14cf11af PM |
71 | _GLOBAL(__start) |
72 | /* NOP this out unconditionally */ | |
73 | BEGIN_FTR_SECTION | |
b85a046a | 74 | b .__start_initialization_multiplatform |
14cf11af | 75 | END_FTR_SECTION(0, 1) |
14cf11af PM |
76 | |
77 | /* Catch branch to 0 in real mode */ | |
78 | trap | |
79 | ||
1f6a93e4 PM |
80 | /* Secondary processors spin on this value until it becomes nonzero. |
81 | * When it does it contains the real address of the descriptor | |
82 | * of the function that the cpu should jump to to continue | |
83 | * initialization. | |
84 | */ | |
14cf11af PM |
85 | .globl __secondary_hold_spinloop |
86 | __secondary_hold_spinloop: | |
87 | .llong 0x0 | |
88 | ||
89 | /* Secondary processors write this value with their cpu # */ | |
90 | /* after they enter the spin loop immediately below. */ | |
91 | .globl __secondary_hold_acknowledge | |
92 | __secondary_hold_acknowledge: | |
93 | .llong 0x0 | |
94 | ||
1dce0e30 ME |
95 | #ifdef CONFIG_PPC_ISERIES |
96 | /* | |
97 | * At offset 0x20, there is a pointer to iSeries LPAR data. | |
98 | * This is required by the hypervisor | |
99 | */ | |
100 | . = 0x20 | |
101 | .llong hvReleaseData-KERNELBASE | |
102 | #endif /* CONFIG_PPC_ISERIES */ | |
103 | ||
928a3197 | 104 | #ifdef CONFIG_RELOCATABLE |
8b8b0cc1 MM |
105 | /* This flag is set to 1 by a loader if the kernel should run |
106 | * at the loaded address instead of the linked address. This | |
107 | * is used by kexec-tools to keep the the kdump kernel in the | |
108 | * crash_kernel region. The loader is responsible for | |
109 | * observing the alignment requirement. | |
110 | */ | |
111 | /* Do not move this variable as kexec-tools knows about it. */ | |
112 | . = 0x5c | |
113 | .globl __run_at_load | |
114 | __run_at_load: | |
115 | .long 0x72756e30 /* "run0" -- relocate to 0 by default */ | |
116 | #endif | |
117 | ||
14cf11af PM |
118 | . = 0x60 |
119 | /* | |
75423b7b GL |
120 | * The following code is used to hold secondary processors |
121 | * in a spin loop after they have entered the kernel, but | |
14cf11af PM |
122 | * before the bulk of the kernel has been relocated. This code |
123 | * is relocated to physical address 0x60 before prom_init is run. | |
124 | * All of it must fit below the first exception vector at 0x100. | |
1f6a93e4 PM |
125 | * Use .globl here not _GLOBAL because we want __secondary_hold |
126 | * to be the actual text address, not a descriptor. | |
14cf11af | 127 | */ |
1f6a93e4 PM |
128 | .globl __secondary_hold |
129 | __secondary_hold: | |
2d27cfd3 | 130 | #ifndef CONFIG_PPC_BOOK3E |
14cf11af PM |
131 | mfmsr r24 |
132 | ori r24,r24,MSR_RI | |
133 | mtmsrd r24 /* RI on */ | |
2d27cfd3 | 134 | #endif |
f1870f77 | 135 | /* Grab our physical cpu number */ |
14cf11af PM |
136 | mr r24,r3 |
137 | ||
138 | /* Tell the master cpu we're here */ | |
139 | /* Relocation is off & we are located at an address less */ | |
140 | /* than 0x100, so only need to grab low order offset. */ | |
e31aa453 | 141 | std r24,__secondary_hold_acknowledge-_stext(0) |
14cf11af PM |
142 | sync |
143 | ||
144 | /* All secondary cpus wait here until told to start. */ | |
e31aa453 | 145 | 100: ld r4,__secondary_hold_spinloop-_stext(0) |
1f6a93e4 PM |
146 | cmpdi 0,r4,0 |
147 | beq 100b | |
14cf11af | 148 | |
f1870f77 | 149 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) |
1f6a93e4 | 150 | ld r4,0(r4) /* deref function descriptor */ |
758438a7 | 151 | mtctr r4 |
14cf11af | 152 | mr r3,r24 |
2d27cfd3 | 153 | li r4,0 |
dd797738 BH |
154 | /* Make sure that patched code is visible */ |
155 | isync | |
758438a7 | 156 | bctr |
14cf11af PM |
157 | #else |
158 | BUG_OPCODE | |
159 | #endif | |
14cf11af PM |
160 | |
161 | /* This value is used to mark exception frames on the stack. */ | |
162 | .section ".toc","aw" | |
163 | exception_marker: | |
164 | .tc ID_72656773_68657265[TC],0x7265677368657265 | |
165 | .text | |
166 | ||
14cf11af | 167 | /* |
0ebc4cda BH |
168 | * On server, we include the exception vectors code here as it |
169 | * relies on absolute addressing which is only possible within | |
170 | * this compilation unit | |
3c726f8d | 171 | */ |
0ebc4cda BH |
172 | #ifdef CONFIG_PPC_BOOK3S |
173 | #include "exceptions-64s.S" | |
1f6a93e4 | 174 | #endif |
3c726f8d | 175 | |
2d27cfd3 BH |
176 | _GLOBAL(generic_secondary_thread_init) |
177 | mr r24,r3 | |
178 | ||
179 | /* turn on 64-bit mode */ | |
180 | bl .enable_64b_mode | |
181 | ||
182 | /* get a valid TOC pointer, wherever we're mapped at */ | |
183 | bl .relative_toc | |
184 | ||
185 | #ifdef CONFIG_PPC_BOOK3E | |
186 | /* Book3E initialization */ | |
187 | mr r3,r24 | |
188 | bl .book3e_secondary_thread_init | |
189 | #endif | |
190 | b generic_secondary_common_init | |
14cf11af PM |
191 | |
192 | /* | |
f39b7a55 OJ |
193 | * On pSeries and most other platforms, secondary processors spin |
194 | * in the following code. | |
14cf11af | 195 | * At entry, r3 = this processor's number (physical cpu id) |
2d27cfd3 BH |
196 | * |
197 | * On Book3E, r4 = 1 to indicate that the initial TLB entry for | |
198 | * this core already exists (setup via some other mechanism such | |
199 | * as SCOM before entry). | |
14cf11af | 200 | */ |
f39b7a55 | 201 | _GLOBAL(generic_secondary_smp_init) |
14cf11af | 202 | mr r24,r3 |
2d27cfd3 BH |
203 | mr r25,r4 |
204 | ||
14cf11af PM |
205 | /* turn on 64-bit mode */ |
206 | bl .enable_64b_mode | |
14cf11af | 207 | |
2d27cfd3 | 208 | /* get a valid TOC pointer, wherever we're mapped at */ |
e31aa453 PM |
209 | bl .relative_toc |
210 | ||
2d27cfd3 BH |
211 | #ifdef CONFIG_PPC_BOOK3E |
212 | /* Book3E initialization */ | |
213 | mr r3,r24 | |
214 | mr r4,r25 | |
215 | bl .book3e_secondary_core_init | |
216 | #endif | |
217 | ||
218 | generic_secondary_common_init: | |
14cf11af PM |
219 | /* Set up a paca value for this processor. Since we have the |
220 | * physical cpu id in r24, we need to search the pacas to find | |
221 | * which logical id maps to our physical one. | |
222 | */ | |
1426d5a3 ME |
223 | LOAD_REG_ADDR(r13, paca) /* Load paca pointer */ |
224 | ld r13,0(r13) /* Get base vaddr of paca array */ | |
768d18ad MM |
225 | #ifndef CONFIG_SMP |
226 | addi r13,r13,PACA_SIZE /* know r13 if used accidentally */ | |
227 | b .kexec_wait /* wait for next kernel if !SMP */ | |
228 | #else | |
229 | LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */ | |
230 | lwz r7,0(r7) /* also the max paca allocated */ | |
14cf11af PM |
231 | li r5,0 /* logical cpu id */ |
232 | 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ | |
233 | cmpw r6,r24 /* Compare to our id */ | |
234 | beq 2f | |
235 | addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ | |
236 | addi r5,r5,1 | |
768d18ad | 237 | cmpw r5,r7 /* Check if more pacas exist */ |
14cf11af PM |
238 | blt 1b |
239 | ||
240 | mr r3,r24 /* not found, copy phys to r3 */ | |
241 | b .kexec_wait /* next kernel might do better */ | |
242 | ||
2dd60d79 | 243 | 2: SET_PACA(r13) |
2d27cfd3 BH |
244 | #ifdef CONFIG_PPC_BOOK3E |
245 | addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ | |
246 | mtspr SPRN_SPRG_TLB_EXFRAME,r12 | |
247 | #endif | |
248 | ||
14cf11af PM |
249 | /* From now on, r24 is expected to be logical cpuid */ |
250 | mr r24,r5 | |
b6f6b98a | 251 | |
f39b7a55 | 252 | /* See if we need to call a cpu state restore handler */ |
e31aa453 | 253 | LOAD_REG_ADDR(r23, cur_cpu_spec) |
f39b7a55 OJ |
254 | ld r23,0(r23) |
255 | ld r23,CPU_SPEC_RESTORE(r23) | |
256 | cmpdi 0,r23,0 | |
9d07bc84 | 257 | beq 3f |
f39b7a55 OJ |
258 | ld r23,0(r23) |
259 | mtctr r23 | |
260 | bctrl | |
261 | ||
7ac87abb | 262 | 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */ |
9d07bc84 BH |
263 | lwarx r4,0,r3 |
264 | subi r4,r4,1 | |
265 | stwcx. r4,0,r3 | |
266 | bne 3b | |
267 | isync | |
268 | ||
269 | 4: HMT_LOW | |
ad0693ee BH |
270 | lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ |
271 | /* start. */ | |
ad0693ee | 272 | cmpwi 0,r23,0 |
9d07bc84 | 273 | beq 4b /* Loop until told to go */ |
ad0693ee BH |
274 | |
275 | sync /* order paca.run and cur_cpu_spec */ | |
9d07bc84 | 276 | isync /* In case code patching happened */ |
ad0693ee | 277 | |
9d07bc84 | 278 | /* Create a temp kernel stack for use before relocation is on. */ |
14cf11af PM |
279 | ld r1,PACAEMERGSP(r13) |
280 | subi r1,r1,STACK_FRAME_OVERHEAD | |
281 | ||
c705677e | 282 | b __secondary_start |
768d18ad | 283 | #endif /* SMP */ |
14cf11af | 284 | |
e31aa453 PM |
285 | /* |
286 | * Turn the MMU off. | |
287 | * Assumes we're mapped EA == RA if the MMU is on. | |
288 | */ | |
2d27cfd3 | 289 | #ifdef CONFIG_PPC_BOOK3S |
14cf11af PM |
290 | _STATIC(__mmu_off) |
291 | mfmsr r3 | |
292 | andi. r0,r3,MSR_IR|MSR_DR | |
293 | beqlr | |
e31aa453 | 294 | mflr r4 |
14cf11af PM |
295 | andc r3,r3,r0 |
296 | mtspr SPRN_SRR0,r4 | |
297 | mtspr SPRN_SRR1,r3 | |
298 | sync | |
299 | rfid | |
300 | b . /* prevent speculative execution */ | |
2d27cfd3 | 301 | #endif |
14cf11af PM |
302 | |
303 | ||
304 | /* | |
305 | * Here is our main kernel entry point. We support currently 2 kind of entries | |
306 | * depending on the value of r5. | |
307 | * | |
308 | * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content | |
309 | * in r3...r7 | |
310 | * | |
311 | * r5 == NULL -> kexec style entry. r3 is a physical pointer to the | |
312 | * DT block, r4 is a physical pointer to the kernel itself | |
313 | * | |
314 | */ | |
315 | _GLOBAL(__start_initialization_multiplatform) | |
e31aa453 PM |
316 | /* Make sure we are running in 64 bits mode */ |
317 | bl .enable_64b_mode | |
318 | ||
319 | /* Get TOC pointer (current runtime address) */ | |
320 | bl .relative_toc | |
321 | ||
322 | /* find out where we are now */ | |
323 | bcl 20,31,$+4 | |
324 | 0: mflr r26 /* r26 = runtime addr here */ | |
325 | addis r26,r26,(_stext - 0b)@ha | |
326 | addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ | |
327 | ||
14cf11af PM |
328 | /* |
329 | * Are we booted from a PROM Of-type client-interface ? | |
330 | */ | |
331 | cmpldi cr0,r5,0 | |
939e60f6 SR |
332 | beq 1f |
333 | b .__boot_from_prom /* yes -> prom */ | |
334 | 1: | |
14cf11af PM |
335 | /* Save parameters */ |
336 | mr r31,r3 | |
337 | mr r30,r4 | |
338 | ||
2d27cfd3 BH |
339 | #ifdef CONFIG_PPC_BOOK3E |
340 | bl .start_initialization_book3e | |
341 | b .__after_prom_start | |
342 | #else | |
14cf11af | 343 | /* Setup some critical 970 SPRs before switching MMU off */ |
f39b7a55 OJ |
344 | mfspr r0,SPRN_PVR |
345 | srwi r0,r0,16 | |
346 | cmpwi r0,0x39 /* 970 */ | |
347 | beq 1f | |
348 | cmpwi r0,0x3c /* 970FX */ | |
349 | beq 1f | |
350 | cmpwi r0,0x44 /* 970MP */ | |
190a24f5 OJ |
351 | beq 1f |
352 | cmpwi r0,0x45 /* 970GX */ | |
f39b7a55 OJ |
353 | bne 2f |
354 | 1: bl .__cpu_preinit_ppc970 | |
355 | 2: | |
14cf11af | 356 | |
e31aa453 | 357 | /* Switch off MMU if not already off */ |
14cf11af PM |
358 | bl .__mmu_off |
359 | b .__after_prom_start | |
2d27cfd3 | 360 | #endif /* CONFIG_PPC_BOOK3E */ |
14cf11af | 361 | |
939e60f6 | 362 | _INIT_STATIC(__boot_from_prom) |
28794d34 | 363 | #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE |
14cf11af PM |
364 | /* Save parameters */ |
365 | mr r31,r3 | |
366 | mr r30,r4 | |
367 | mr r29,r5 | |
368 | mr r28,r6 | |
369 | mr r27,r7 | |
370 | ||
6088857b OH |
371 | /* |
372 | * Align the stack to 16-byte boundary | |
373 | * Depending on the size and layout of the ELF sections in the initial | |
e31aa453 | 374 | * boot binary, the stack pointer may be unaligned on PowerMac |
6088857b | 375 | */ |
c05b4770 LT |
376 | rldicr r1,r1,0,59 |
377 | ||
549e8152 PM |
378 | #ifdef CONFIG_RELOCATABLE |
379 | /* Relocate code for where we are now */ | |
380 | mr r3,r26 | |
381 | bl .relocate | |
382 | #endif | |
383 | ||
14cf11af PM |
384 | /* Restore parameters */ |
385 | mr r3,r31 | |
386 | mr r4,r30 | |
387 | mr r5,r29 | |
388 | mr r6,r28 | |
389 | mr r7,r27 | |
390 | ||
391 | /* Do all of the interaction with OF client interface */ | |
549e8152 | 392 | mr r8,r26 |
14cf11af | 393 | bl .prom_init |
28794d34 BH |
394 | #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ |
395 | ||
396 | /* We never return. We also hit that trap if trying to boot | |
397 | * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ | |
14cf11af PM |
398 | trap |
399 | ||
14cf11af | 400 | _STATIC(__after_prom_start) |
549e8152 PM |
401 | #ifdef CONFIG_RELOCATABLE |
402 | /* process relocations for the final address of the kernel */ | |
403 | lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ | |
404 | sldi r25,r25,32 | |
8b8b0cc1 | 405 | lwz r7,__run_at_load-_stext(r26) |
928a3197 | 406 | cmplwi cr0,r7,1 /* flagged to stay where we are ? */ |
54622f10 MK |
407 | bne 1f |
408 | add r25,r25,r26 | |
54622f10 | 409 | 1: mr r3,r25 |
549e8152 PM |
410 | bl .relocate |
411 | #endif | |
14cf11af PM |
412 | |
413 | /* | |
e31aa453 | 414 | * We need to run with _stext at physical address PHYSICAL_START. |
14cf11af PM |
415 | * This will leave some code in the first 256B of |
416 | * real memory, which are reserved for software use. | |
14cf11af PM |
417 | * |
418 | * Note: This process overwrites the OF exception vectors. | |
14cf11af | 419 | */ |
549e8152 | 420 | li r3,0 /* target addr */ |
2d27cfd3 BH |
421 | #ifdef CONFIG_PPC_BOOK3E |
422 | tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ | |
423 | #endif | |
549e8152 | 424 | mr. r4,r26 /* In some cases the loader may */ |
e31aa453 | 425 | beq 9f /* have already put us at zero */ |
14cf11af PM |
426 | li r6,0x100 /* Start offset, the first 0x100 */ |
427 | /* bytes were copied earlier. */ | |
2d27cfd3 BH |
428 | #ifdef CONFIG_PPC_BOOK3E |
429 | tovirt(r6,r6) /* on booke, we already run at PAGE_OFFSET */ | |
430 | #endif | |
14cf11af | 431 | |
54622f10 MK |
432 | #ifdef CONFIG_CRASH_DUMP |
433 | /* | |
434 | * Check if the kernel has to be running as relocatable kernel based on the | |
8b8b0cc1 | 435 | * variable __run_at_load, if it is set the kernel is treated as relocatable |
54622f10 MK |
436 | * kernel, otherwise it will be moved to PHYSICAL_START |
437 | */ | |
8b8b0cc1 MM |
438 | lwz r7,__run_at_load-_stext(r26) |
439 | cmplwi cr0,r7,1 | |
54622f10 MK |
440 | bne 3f |
441 | ||
442 | li r5,__end_interrupts - _stext /* just copy interrupts */ | |
443 | b 5f | |
444 | 3: | |
445 | #endif | |
446 | lis r5,(copy_to_here - _stext)@ha | |
447 | addi r5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */ | |
448 | ||
14cf11af PM |
449 | bl .copy_and_flush /* copy the first n bytes */ |
450 | /* this includes the code being */ | |
451 | /* executed here. */ | |
e31aa453 PM |
452 | addis r8,r3,(4f - _stext)@ha /* Jump to the copy of this code */ |
453 | addi r8,r8,(4f - _stext)@l /* that we just made */ | |
454 | mtctr r8 | |
14cf11af PM |
455 | bctr |
456 | ||
54622f10 MK |
457 | p_end: .llong _end - _stext |
458 | ||
e31aa453 PM |
459 | 4: /* Now copy the rest of the kernel up to _end */ |
460 | addis r5,r26,(p_end - _stext)@ha | |
461 | ld r5,(p_end - _stext)@l(r5) /* get _end */ | |
54622f10 | 462 | 5: bl .copy_and_flush /* copy the rest */ |
e31aa453 PM |
463 | |
464 | 9: b .start_here_multiplatform | |
465 | ||
14cf11af PM |
466 | /* |
467 | * Copy routine used to copy the kernel to start at physical address 0 | |
468 | * and flush and invalidate the caches as needed. | |
469 | * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset | |
470 | * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. | |
471 | * | |
472 | * Note: this routine *only* clobbers r0, r6 and lr | |
473 | */ | |
474 | _GLOBAL(copy_and_flush) | |
475 | addi r5,r5,-8 | |
476 | addi r6,r6,-8 | |
5a2fe38d | 477 | 4: li r0,8 /* Use the smallest common */ |
14cf11af PM |
478 | /* denominator cache line */ |
479 | /* size. This results in */ | |
480 | /* extra cache line flushes */ | |
481 | /* but operation is correct. */ | |
482 | /* Can't get cache line size */ | |
483 | /* from NACA as it is being */ | |
484 | /* moved too. */ | |
485 | ||
486 | mtctr r0 /* put # words/line in ctr */ | |
487 | 3: addi r6,r6,8 /* copy a cache line */ | |
488 | ldx r0,r6,r4 | |
489 | stdx r0,r6,r3 | |
490 | bdnz 3b | |
491 | dcbst r6,r3 /* write it to memory */ | |
492 | sync | |
493 | icbi r6,r3 /* flush the icache line */ | |
494 | cmpld 0,r6,r5 | |
495 | blt 4b | |
496 | sync | |
497 | addi r5,r5,8 | |
498 | addi r6,r6,8 | |
499 | blr | |
500 | ||
501 | .align 8 | |
502 | copy_to_here: | |
503 | ||
504 | #ifdef CONFIG_SMP | |
505 | #ifdef CONFIG_PPC_PMAC | |
506 | /* | |
507 | * On PowerMac, secondary processors starts from the reset vector, which | |
508 | * is temporarily turned into a call to one of the functions below. | |
509 | */ | |
510 | .section ".text"; | |
511 | .align 2 ; | |
512 | ||
35499c01 PM |
513 | .globl __secondary_start_pmac_0 |
514 | __secondary_start_pmac_0: | |
515 | /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ | |
516 | li r24,0 | |
517 | b 1f | |
518 | li r24,1 | |
519 | b 1f | |
520 | li r24,2 | |
521 | b 1f | |
522 | li r24,3 | |
523 | 1: | |
14cf11af PM |
524 | |
525 | _GLOBAL(pmac_secondary_start) | |
526 | /* turn on 64-bit mode */ | |
527 | bl .enable_64b_mode | |
14cf11af | 528 | |
c478b581 BH |
529 | li r0,0 |
530 | mfspr r3,SPRN_HID4 | |
531 | rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ | |
532 | sync | |
533 | mtspr SPRN_HID4,r3 | |
534 | isync | |
535 | sync | |
536 | slbia | |
537 | ||
e31aa453 PM |
538 | /* get TOC pointer (real address) */ |
539 | bl .relative_toc | |
540 | ||
14cf11af | 541 | /* Copy some CPU settings from CPU 0 */ |
f39b7a55 | 542 | bl .__restore_cpu_ppc970 |
14cf11af PM |
543 | |
544 | /* pSeries do that early though I don't think we really need it */ | |
545 | mfmsr r3 | |
546 | ori r3,r3,MSR_RI | |
547 | mtmsrd r3 /* RI on */ | |
548 | ||
549 | /* Set up a paca value for this processor. */ | |
1426d5a3 ME |
550 | LOAD_REG_ADDR(r4,paca) /* Load paca pointer */ |
551 | ld r4,0(r4) /* Get base vaddr of paca array */ | |
e31aa453 | 552 | mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ |
14cf11af | 553 | add r13,r13,r4 /* for this processor. */ |
2dd60d79 | 554 | SET_PACA(r13) /* Save vaddr of paca in an SPRG*/ |
14cf11af | 555 | |
62cc67b9 BH |
556 | /* Mark interrupts soft and hard disabled (they might be enabled |
557 | * in the PACA when doing hotplug) | |
558 | */ | |
559 | li r0,0 | |
560 | stb r0,PACASOFTIRQEN(r13) | |
561 | stb r0,PACAHARDIRQEN(r13) | |
562 | ||
14cf11af PM |
563 | /* Create a temp kernel stack for use before relocation is on. */ |
564 | ld r1,PACAEMERGSP(r13) | |
565 | subi r1,r1,STACK_FRAME_OVERHEAD | |
566 | ||
c705677e | 567 | b __secondary_start |
14cf11af PM |
568 | |
569 | #endif /* CONFIG_PPC_PMAC */ | |
570 | ||
571 | /* | |
572 | * This function is called after the master CPU has released the | |
573 | * secondary processors. The execution environment is relocation off. | |
574 | * The paca for this processor has the following fields initialized at | |
575 | * this point: | |
576 | * 1. Processor number | |
577 | * 2. Segment table pointer (virtual address) | |
578 | * On entry the following are set: | |
ee43eb78 BH |
579 | * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries |
580 | * r24 = cpu# (in Linux terms) | |
581 | * r13 = paca virtual address | |
582 | * SPRG_PACA = paca virtual address | |
14cf11af | 583 | */ |
2d27cfd3 BH |
584 | .section ".text"; |
585 | .align 2 ; | |
586 | ||
fc68e869 | 587 | .globl __secondary_start |
c705677e | 588 | __secondary_start: |
799d6046 PM |
589 | /* Set thread priority to MEDIUM */ |
590 | HMT_MEDIUM | |
14cf11af | 591 | |
14cf11af | 592 | /* Initialize the kernel stack. Just a repeat for iSeries. */ |
e58c3495 | 593 | LOAD_REG_ADDR(r3, current_set) |
14cf11af | 594 | sldi r28,r24,3 /* get current_set[cpu#] */ |
54a83404 MN |
595 | ldx r14,r3,r28 |
596 | addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD | |
597 | std r14,PACAKSAVE(r13) | |
14cf11af | 598 | |
f761622e ME |
599 | /* Do early setup for that CPU (stab, slb, hash table pointer) */ |
600 | bl .early_setup_secondary | |
601 | ||
54a83404 MN |
602 | /* |
603 | * setup the new stack pointer, but *don't* use this until | |
604 | * translation is on. | |
605 | */ | |
606 | mr r1, r14 | |
607 | ||
799d6046 | 608 | /* Clear backchain so we get nice backtraces */ |
14cf11af PM |
609 | li r7,0 |
610 | mtlr r7 | |
611 | ||
612 | /* enable MMU and jump to start_secondary */ | |
e58c3495 DG |
613 | LOAD_REG_ADDR(r3, .start_secondary_prolog) |
614 | LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) | |
d04c56f7 | 615 | #ifdef CONFIG_PPC_ISERIES |
3f639ee8 | 616 | BEGIN_FW_FTR_SECTION |
14cf11af | 617 | ori r4,r4,MSR_EE |
ff3da2e0 BH |
618 | li r8,1 |
619 | stb r8,PACAHARDIRQEN(r13) | |
3f639ee8 | 620 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) |
14cf11af | 621 | #endif |
d04c56f7 | 622 | BEGIN_FW_FTR_SECTION |
d04c56f7 PM |
623 | stb r7,PACAHARDIRQEN(r13) |
624 | END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES) | |
ff3da2e0 | 625 | stb r7,PACASOFTIRQEN(r13) |
d04c56f7 | 626 | |
b5bbeb23 PM |
627 | mtspr SPRN_SRR0,r3 |
628 | mtspr SPRN_SRR1,r4 | |
2d27cfd3 | 629 | RFI |
14cf11af PM |
630 | b . /* prevent speculative execution */ |
631 | ||
632 | /* | |
633 | * Running with relocation on at this point. All we want to do is | |
e31aa453 PM |
634 | * zero the stack back-chain pointer and get the TOC virtual address |
635 | * before going into C code. | |
14cf11af PM |
636 | */ |
637 | _GLOBAL(start_secondary_prolog) | |
e31aa453 | 638 | ld r2,PACATOC(r13) |
14cf11af PM |
639 | li r3,0 |
640 | std r3,0(r1) /* Zero the stack frame pointer */ | |
641 | bl .start_secondary | |
799d6046 | 642 | b . |
8dbce53c VS |
643 | /* |
644 | * Reset stack pointer and call start_secondary | |
645 | * to continue with online operation when woken up | |
646 | * from cede in cpu offline. | |
647 | */ | |
648 | _GLOBAL(start_secondary_resume) | |
649 | ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ | |
650 | li r3,0 | |
651 | std r3,0(r1) /* Zero the stack frame pointer */ | |
652 | bl .start_secondary | |
653 | b . | |
14cf11af PM |
654 | #endif |
655 | ||
656 | /* | |
657 | * This subroutine clobbers r11 and r12 | |
658 | */ | |
659 | _GLOBAL(enable_64b_mode) | |
660 | mfmsr r11 /* grab the current MSR */ | |
2d27cfd3 BH |
661 | #ifdef CONFIG_PPC_BOOK3E |
662 | oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ | |
663 | mtmsr r11 | |
664 | #else /* CONFIG_PPC_BOOK3E */ | |
9f0b0793 | 665 | li r12,(MSR_64BIT | MSR_ISF)@highest |
e31aa453 | 666 | sldi r12,r12,48 |
14cf11af PM |
667 | or r11,r11,r12 |
668 | mtmsrd r11 | |
669 | isync | |
2d27cfd3 | 670 | #endif |
14cf11af PM |
671 | blr |
672 | ||
e31aa453 PM |
673 | /* |
674 | * This puts the TOC pointer into r2, offset by 0x8000 (as expected | |
675 | * by the toolchain). It computes the correct value for wherever we | |
676 | * are running at the moment, using position-independent code. | |
677 | */ | |
678 | _GLOBAL(relative_toc) | |
679 | mflr r0 | |
680 | bcl 20,31,$+4 | |
e550592e BH |
681 | 0: mflr r11 |
682 | ld r2,(p_toc - 0b)(r11) | |
683 | add r2,r2,r11 | |
e31aa453 PM |
684 | mtlr r0 |
685 | blr | |
686 | ||
687 | p_toc: .llong __toc_start + 0x8000 - 0b | |
688 | ||
14cf11af PM |
689 | /* |
690 | * This is where the main kernel code starts. | |
691 | */ | |
939e60f6 | 692 | _INIT_STATIC(start_here_multiplatform) |
e31aa453 PM |
693 | /* set up the TOC (real address) */ |
694 | bl .relative_toc | |
14cf11af PM |
695 | |
696 | /* Clear out the BSS. It may have been done in prom_init, | |
697 | * already but that's irrelevant since prom_init will soon | |
698 | * be detached from the kernel completely. Besides, we need | |
699 | * to clear it now for kexec-style entry. | |
700 | */ | |
e31aa453 PM |
701 | LOAD_REG_ADDR(r11,__bss_stop) |
702 | LOAD_REG_ADDR(r8,__bss_start) | |
14cf11af PM |
703 | sub r11,r11,r8 /* bss size */ |
704 | addi r11,r11,7 /* round up to an even double word */ | |
e31aa453 | 705 | srdi. r11,r11,3 /* shift right by 3 */ |
14cf11af PM |
706 | beq 4f |
707 | addi r8,r8,-8 | |
708 | li r0,0 | |
709 | mtctr r11 /* zero this many doublewords */ | |
710 | 3: stdu r0,8(r8) | |
711 | bdnz 3b | |
712 | 4: | |
713 | ||
2d27cfd3 | 714 | #ifndef CONFIG_PPC_BOOK3E |
14cf11af PM |
715 | mfmsr r6 |
716 | ori r6,r6,MSR_RI | |
717 | mtmsrd r6 /* RI on */ | |
2d27cfd3 | 718 | #endif |
14cf11af | 719 | |
549e8152 PM |
720 | #ifdef CONFIG_RELOCATABLE |
721 | /* Save the physical address we're running at in kernstart_addr */ | |
722 | LOAD_REG_ADDR(r4, kernstart_addr) | |
723 | clrldi r0,r25,2 | |
724 | std r0,0(r4) | |
725 | #endif | |
726 | ||
e31aa453 | 727 | /* The following gets the stack set up with the regs */ |
14cf11af PM |
728 | /* pointing to the real addr of the kernel stack. This is */ |
729 | /* all done to support the C function call below which sets */ | |
730 | /* up the htab. This is done because we have relocated the */ | |
731 | /* kernel but are still running in real mode. */ | |
732 | ||
e31aa453 | 733 | LOAD_REG_ADDR(r3,init_thread_union) |
14cf11af | 734 | |
e31aa453 | 735 | /* set up a stack pointer */ |
14cf11af PM |
736 | addi r1,r3,THREAD_SIZE |
737 | li r0,0 | |
738 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
739 | ||
14cf11af PM |
740 | /* Do very early kernel initializations, including initial hash table, |
741 | * stab and slb setup before we turn on relocation. */ | |
742 | ||
743 | /* Restore parameters passed from prom_init/kexec */ | |
744 | mr r3,r31 | |
ee43eb78 | 745 | bl .early_setup /* also sets r13 and SPRG_PACA */ |
14cf11af | 746 | |
e31aa453 PM |
747 | LOAD_REG_ADDR(r3, .start_here_common) |
748 | ld r4,PACAKMSR(r13) | |
b5bbeb23 PM |
749 | mtspr SPRN_SRR0,r3 |
750 | mtspr SPRN_SRR1,r4 | |
2d27cfd3 | 751 | RFI |
14cf11af | 752 | b . /* prevent speculative execution */ |
14cf11af PM |
753 | |
754 | /* This is where all platforms converge execution */ | |
fc68e869 | 755 | _INIT_GLOBAL(start_here_common) |
14cf11af | 756 | /* relocation is on at this point */ |
e31aa453 | 757 | std r1,PACAKSAVE(r13) |
14cf11af | 758 | |
e31aa453 | 759 | /* Load the TOC (virtual address) */ |
14cf11af | 760 | ld r2,PACATOC(r13) |
14cf11af PM |
761 | |
762 | bl .setup_system | |
763 | ||
764 | /* Load up the kernel context */ | |
765 | 5: | |
14cf11af | 766 | li r5,0 |
d04c56f7 PM |
767 | stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */ |
768 | #ifdef CONFIG_PPC_ISERIES | |
769 | BEGIN_FW_FTR_SECTION | |
14cf11af | 770 | mfmsr r5 |
ff3da2e0 | 771 | ori r5,r5,MSR_EE /* Hard Enabled on iSeries*/ |
14cf11af | 772 | mtmsrd r5 |
ff3da2e0 | 773 | li r5,1 |
3f639ee8 | 774 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES) |
14cf11af | 775 | #endif |
ff3da2e0 | 776 | stb r5,PACAHARDIRQEN(r13) /* Hard Disabled on others */ |
14cf11af | 777 | |
ff3da2e0 | 778 | bl .start_kernel |
14cf11af | 779 | |
f1870f77 AB |
780 | /* Not reached */ |
781 | BUG_OPCODE | |
14cf11af | 782 | |
14cf11af PM |
783 | /* |
784 | * We put a few things here that have to be page-aligned. | |
785 | * This stuff goes at the beginning of the bss, which is page-aligned. | |
786 | */ | |
787 | .section ".bss" | |
788 | ||
789 | .align PAGE_SHIFT | |
790 | ||
791 | .globl empty_zero_page | |
792 | empty_zero_page: | |
793 | .space PAGE_SIZE | |
794 | ||
795 | .globl swapper_pg_dir | |
796 | swapper_pg_dir: | |
ee7a76da | 797 | .space PGD_TABLE_SIZE |