Commit | Line | Data |
---|---|---|
14cf11af | 1 | /* |
14cf11af PM |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
6 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
7 | * Adapted for Power Macintosh by Paul Mackerras. | |
8 | * Low-level exception handlers and MMU support | |
9 | * rewritten by Paul Mackerras. | |
10 | * Copyright (C) 1996 Paul Mackerras. | |
11 | * | |
12 | * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and | |
13 | * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com | |
14 | * | |
0ebc4cda BH |
15 | * This file contains the entry point for the 64-bit kernel along |
16 | * with some early initialization code common to all 64-bit powerpc | |
17 | * variants. | |
14cf11af PM |
18 | * |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License | |
21 | * as published by the Free Software Foundation; either version | |
22 | * 2 of the License, or (at your option) any later version. | |
23 | */ | |
24 | ||
14cf11af | 25 | #include <linux/threads.h> |
c141611f | 26 | #include <linux/init.h> |
b5bbeb23 | 27 | #include <asm/reg.h> |
14cf11af PM |
28 | #include <asm/page.h> |
29 | #include <asm/mmu.h> | |
14cf11af | 30 | #include <asm/ppc_asm.h> |
57f26649 | 31 | #include <asm/head-64.h> |
14cf11af PM |
32 | #include <asm/asm-offsets.h> |
33 | #include <asm/bug.h> | |
34 | #include <asm/cputable.h> | |
35 | #include <asm/setup.h> | |
36 | #include <asm/hvcall.h> | |
6cb7bfeb | 37 | #include <asm/thread_info.h> |
3f639ee8 | 38 | #include <asm/firmware.h> |
16a15a30 | 39 | #include <asm/page_64.h> |
945feb17 | 40 | #include <asm/irqflags.h> |
2191d657 | 41 | #include <asm/kvm_book3s_asm.h> |
46f52210 | 42 | #include <asm/ptrace.h> |
7230c564 | 43 | #include <asm/hw_irq.h> |
6becef7e | 44 | #include <asm/cputhreads.h> |
7a25d912 | 45 | #include <asm/ppc-opcode.h> |
9445aa1a | 46 | #include <asm/export.h> |
14cf11af | 47 | |
25985edc | 48 | /* The physical memory is laid out such that the secondary processor |
0ebc4cda BH |
49 | * spin code sits at 0x0000...0x00ff. On server, the vectors follow |
50 | * using the layout described in exceptions-64s.S | |
14cf11af PM |
51 | */ |
52 | ||
53 | /* | |
54 | * Entering into this code we make the following assumptions: | |
0ebc4cda BH |
55 | * |
56 | * For pSeries or server processors: | |
14cf11af PM |
57 | * 1. The MMU is off & open firmware is running in real mode. |
58 | * 2. The kernel is entered at __start | |
27f44888 BH |
59 | * -or- For OPAL entry: |
60 | * 1. The MMU is off, processor in HV mode, primary CPU enters at 0 | |
daea1175 BH |
61 | * with device-tree in gpr3. We also get OPAL base in r8 and |
62 | * entry in r9 for debugging purposes | |
27f44888 | 63 | * 2. Secondary processors enter at 0x60 with PIR in gpr3 |
14cf11af | 64 | * |
0ebc4cda BH |
65 | * For Book3E processors: |
66 | * 1. The MMU is on running in AS0 in a state defined in ePAPR | |
67 | * 2. The kernel is entered at __start | |
14cf11af PM |
68 | */ |
69 | ||
57f26649 NP |
70 | OPEN_FIXED_SECTION(first_256B, 0x0, 0x100) |
71 | USE_FIXED_SECTION(first_256B) | |
72 | /* | |
73 | * Offsets are relative from the start of fixed section, and | |
74 | * first_256B starts at 0. Offsets are a bit easier to use here | |
75 | * than the fixed section entry macros. | |
76 | */ | |
77 | . = 0x0 | |
14cf11af PM |
78 | _GLOBAL(__start) |
79 | /* NOP this out unconditionally */ | |
80 | BEGIN_FTR_SECTION | |
5c0484e2 | 81 | FIXUP_ENDIAN |
b1576fec | 82 | b __start_initialization_multiplatform |
14cf11af | 83 | END_FTR_SECTION(0, 1) |
14cf11af PM |
84 | |
85 | /* Catch branch to 0 in real mode */ | |
86 | trap | |
87 | ||
2751b628 AB |
88 | /* Secondary processors spin on this value until it becomes non-zero. |
89 | * When non-zero, it contains the real address of the function the cpu | |
90 | * should jump to. | |
1f6a93e4 | 91 | */ |
7d4151b5 | 92 | .balign 8 |
14cf11af PM |
93 | .globl __secondary_hold_spinloop |
94 | __secondary_hold_spinloop: | |
95 | .llong 0x0 | |
96 | ||
97 | /* Secondary processors write this value with their cpu # */ | |
98 | /* after they enter the spin loop immediately below. */ | |
99 | .globl __secondary_hold_acknowledge | |
100 | __secondary_hold_acknowledge: | |
101 | .llong 0x0 | |
102 | ||
928a3197 | 103 | #ifdef CONFIG_RELOCATABLE |
8b8b0cc1 MM |
104 | /* This flag is set to 1 by a loader if the kernel should run |
105 | * at the loaded address instead of the linked address. This | |
106 | * is used by kexec-tools to keep the the kdump kernel in the | |
107 | * crash_kernel region. The loader is responsible for | |
108 | * observing the alignment requirement. | |
109 | */ | |
110 | /* Do not move this variable as kexec-tools knows about it. */ | |
111 | . = 0x5c | |
112 | .globl __run_at_load | |
113 | __run_at_load: | |
57f26649 | 114 | DEFINE_FIXED_SYMBOL(__run_at_load) |
8b8b0cc1 MM |
115 | .long 0x72756e30 /* "run0" -- relocate to 0 by default */ |
116 | #endif | |
117 | ||
14cf11af PM |
118 | . = 0x60 |
119 | /* | |
75423b7b GL |
120 | * The following code is used to hold secondary processors |
121 | * in a spin loop after they have entered the kernel, but | |
14cf11af PM |
122 | * before the bulk of the kernel has been relocated. This code |
123 | * is relocated to physical address 0x60 before prom_init is run. | |
124 | * All of it must fit below the first exception vector at 0x100. | |
1f6a93e4 PM |
125 | * Use .globl here not _GLOBAL because we want __secondary_hold |
126 | * to be the actual text address, not a descriptor. | |
14cf11af | 127 | */ |
1f6a93e4 PM |
128 | .globl __secondary_hold |
129 | __secondary_hold: | |
5c0484e2 | 130 | FIXUP_ENDIAN |
2d27cfd3 | 131 | #ifndef CONFIG_PPC_BOOK3E |
14cf11af PM |
132 | mfmsr r24 |
133 | ori r24,r24,MSR_RI | |
134 | mtmsrd r24 /* RI on */ | |
2d27cfd3 | 135 | #endif |
f1870f77 | 136 | /* Grab our physical cpu number */ |
14cf11af | 137 | mr r24,r3 |
96f013fe JX |
138 | /* stash r4 for book3e */ |
139 | mr r25,r4 | |
14cf11af PM |
140 | |
141 | /* Tell the master cpu we're here */ | |
142 | /* Relocation is off & we are located at an address less */ | |
143 | /* than 0x100, so only need to grab low order offset. */ | |
57f26649 | 144 | std r24,(ABS_ADDR(__secondary_hold_acknowledge))(0) |
14cf11af PM |
145 | sync |
146 | ||
96f013fe JX |
147 | li r26,0 |
148 | #ifdef CONFIG_PPC_BOOK3E | |
149 | tovirt(r26,r26) | |
150 | #endif | |
14cf11af | 151 | /* All secondary cpus wait here until told to start. */ |
57f26649 | 152 | 100: ld r12,(ABS_ADDR(__secondary_hold_spinloop))(r26) |
cc7efbf9 | 153 | cmpdi 0,r12,0 |
1f6a93e4 | 154 | beq 100b |
14cf11af | 155 | |
f1870f77 | 156 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC) |
96f013fe | 157 | #ifdef CONFIG_PPC_BOOK3E |
cc7efbf9 | 158 | tovirt(r12,r12) |
cc7efbf9 AB |
159 | #endif |
160 | mtctr r12 | |
14cf11af | 161 | mr r3,r24 |
96f013fe JX |
162 | /* |
163 | * it may be the case that other platforms have r4 right to | |
164 | * begin with, this gives us some safety in case it is not | |
165 | */ | |
166 | #ifdef CONFIG_PPC_BOOK3E | |
167 | mr r4,r25 | |
168 | #else | |
2d27cfd3 | 169 | li r4,0 |
96f013fe | 170 | #endif |
dd797738 BH |
171 | /* Make sure that patched code is visible */ |
172 | isync | |
758438a7 | 173 | bctr |
14cf11af PM |
174 | #else |
175 | BUG_OPCODE | |
176 | #endif | |
57f26649 | 177 | CLOSE_FIXED_SECTION(first_256B) |
14cf11af PM |
178 | |
179 | /* This value is used to mark exception frames on the stack. */ | |
180 | .section ".toc","aw" | |
181 | exception_marker: | |
182 | .tc ID_72656773_68657265[TC],0x7265677368657265 | |
57f26649 | 183 | .previous |
14cf11af | 184 | |
14cf11af | 185 | /* |
0ebc4cda BH |
186 | * On server, we include the exception vectors code here as it |
187 | * relies on absolute addressing which is only possible within | |
188 | * this compilation unit | |
3c726f8d | 189 | */ |
0ebc4cda BH |
190 | #ifdef CONFIG_PPC_BOOK3S |
191 | #include "exceptions-64s.S" | |
57f26649 NP |
192 | #else |
193 | OPEN_TEXT_SECTION(0x100) | |
1f6a93e4 | 194 | #endif |
3c726f8d | 195 | |
57f26649 NP |
196 | USE_TEXT_SECTION() |
197 | ||
e16c8765 | 198 | #ifdef CONFIG_PPC_BOOK3E |
6becef7e | 199 | /* |
200 | * The booting_thread_hwid holds the thread id we want to boot in cpu | |
201 | * hotplug case. It is set by cpu hotplug code, and is invalid by default. | |
202 | * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID] | |
203 | * bit field. | |
204 | */ | |
205 | .globl booting_thread_hwid | |
206 | booting_thread_hwid: | |
207 | .long INVALID_THREAD_HWID | |
208 | .align 3 | |
209 | /* | |
210 | * start a thread in the same core | |
211 | * input parameters: | |
212 | * r3 = the thread physical id | |
213 | * r4 = the entry point where thread starts | |
214 | */ | |
215 | _GLOBAL(book3e_start_thread) | |
216 | LOAD_REG_IMMEDIATE(r5, MSR_KERNEL) | |
217 | cmpi 0, r3, 0 | |
218 | beq 10f | |
219 | cmpi 0, r3, 1 | |
220 | beq 11f | |
221 | /* If the thread id is invalid, just exit. */ | |
222 | b 13f | |
223 | 10: | |
7a25d912 SW |
224 | MTTMR(TMRN_IMSR0, 5) |
225 | MTTMR(TMRN_INIA0, 4) | |
6becef7e | 226 | b 12f |
227 | 11: | |
7a25d912 SW |
228 | MTTMR(TMRN_IMSR1, 5) |
229 | MTTMR(TMRN_INIA1, 4) | |
6becef7e | 230 | 12: |
231 | isync | |
232 | li r6, 1 | |
233 | sld r6, r6, r3 | |
234 | mtspr SPRN_TENS, r6 | |
235 | 13: | |
236 | blr | |
237 | ||
d17799f9 | 238 | /* |
239 | * stop a thread in the same core | |
240 | * input parameter: | |
241 | * r3 = the thread physical id | |
242 | */ | |
243 | _GLOBAL(book3e_stop_thread) | |
244 | cmpi 0, r3, 0 | |
245 | beq 10f | |
246 | cmpi 0, r3, 1 | |
247 | beq 10f | |
248 | /* If the thread id is invalid, just exit. */ | |
249 | b 13f | |
250 | 10: | |
251 | li r4, 1 | |
252 | sld r4, r4, r3 | |
253 | mtspr SPRN_TENC, r4 | |
254 | 13: | |
255 | blr | |
256 | ||
e16c8765 | 257 | _GLOBAL(fsl_secondary_thread_init) |
f34b3e19 SW |
258 | mfspr r4,SPRN_BUCSR |
259 | ||
e16c8765 AF |
260 | /* Enable branch prediction */ |
261 | lis r3,BUCSR_INIT@h | |
262 | ori r3,r3,BUCSR_INIT@l | |
263 | mtspr SPRN_BUCSR,r3 | |
264 | isync | |
265 | ||
266 | /* | |
267 | * Fix PIR to match the linear numbering in the device tree. | |
268 | * | |
269 | * On e6500, the reset value of PIR uses the low three bits for | |
270 | * the thread within a core, and the upper bits for the core | |
271 | * number. There are two threads per core, so shift everything | |
272 | * but the low bit right by two bits so that the cpu numbering is | |
273 | * continuous. | |
f34b3e19 SW |
274 | * |
275 | * If the old value of BUCSR is non-zero, this thread has run | |
276 | * before. Thus, we assume we are coming from kexec or a similar | |
277 | * scenario, and PIR is already set to the correct value. This | |
278 | * is a bit of a hack, but there are limited opportunities for | |
279 | * getting information into the thread and the alternatives | |
280 | * seemed like they'd be overkill. We can't tell just by looking | |
281 | * at the old PIR value which state it's in, since the same value | |
282 | * could be valid for one thread out of reset and for a different | |
283 | * thread in Linux. | |
e16c8765 | 284 | */ |
f34b3e19 | 285 | |
e16c8765 | 286 | mfspr r3, SPRN_PIR |
f34b3e19 SW |
287 | cmpwi r4,0 |
288 | bne 1f | |
e16c8765 AF |
289 | rlwimi r3, r3, 30, 2, 30 |
290 | mtspr SPRN_PIR, r3 | |
f34b3e19 | 291 | 1: |
e16c8765 AF |
292 | #endif |
293 | ||
2d27cfd3 BH |
294 | _GLOBAL(generic_secondary_thread_init) |
295 | mr r24,r3 | |
296 | ||
297 | /* turn on 64-bit mode */ | |
b1576fec | 298 | bl enable_64b_mode |
2d27cfd3 BH |
299 | |
300 | /* get a valid TOC pointer, wherever we're mapped at */ | |
b1576fec | 301 | bl relative_toc |
1fbe9cf2 | 302 | tovirt(r2,r2) |
2d27cfd3 BH |
303 | |
304 | #ifdef CONFIG_PPC_BOOK3E | |
305 | /* Book3E initialization */ | |
306 | mr r3,r24 | |
b1576fec | 307 | bl book3e_secondary_thread_init |
2d27cfd3 BH |
308 | #endif |
309 | b generic_secondary_common_init | |
14cf11af PM |
310 | |
311 | /* | |
f39b7a55 OJ |
312 | * On pSeries and most other platforms, secondary processors spin |
313 | * in the following code. | |
14cf11af | 314 | * At entry, r3 = this processor's number (physical cpu id) |
2d27cfd3 BH |
315 | * |
316 | * On Book3E, r4 = 1 to indicate that the initial TLB entry for | |
317 | * this core already exists (setup via some other mechanism such | |
318 | * as SCOM before entry). | |
14cf11af | 319 | */ |
f39b7a55 | 320 | _GLOBAL(generic_secondary_smp_init) |
5c0484e2 | 321 | FIXUP_ENDIAN |
14cf11af | 322 | mr r24,r3 |
2d27cfd3 BH |
323 | mr r25,r4 |
324 | ||
14cf11af | 325 | /* turn on 64-bit mode */ |
b1576fec | 326 | bl enable_64b_mode |
14cf11af | 327 | |
2d27cfd3 | 328 | /* get a valid TOC pointer, wherever we're mapped at */ |
b1576fec | 329 | bl relative_toc |
1fbe9cf2 | 330 | tovirt(r2,r2) |
e31aa453 | 331 | |
2d27cfd3 BH |
332 | #ifdef CONFIG_PPC_BOOK3E |
333 | /* Book3E initialization */ | |
334 | mr r3,r24 | |
335 | mr r4,r25 | |
b1576fec | 336 | bl book3e_secondary_core_init |
6becef7e | 337 | |
338 | /* | |
339 | * After common core init has finished, check if the current thread is the | |
340 | * one we wanted to boot. If not, start the specified thread and stop the | |
341 | * current thread. | |
342 | */ | |
343 | LOAD_REG_ADDR(r4, booting_thread_hwid) | |
344 | lwz r3, 0(r4) | |
345 | li r5, INVALID_THREAD_HWID | |
346 | cmpw r3, r5 | |
347 | beq 20f | |
348 | ||
349 | /* | |
350 | * The value of booting_thread_hwid has been stored in r3, | |
351 | * so make it invalid. | |
352 | */ | |
353 | stw r5, 0(r4) | |
354 | ||
355 | /* | |
356 | * Get the current thread id and check if it is the one we wanted. | |
357 | * If not, start the one specified in booting_thread_hwid and stop | |
358 | * the current thread. | |
359 | */ | |
360 | mfspr r8, SPRN_TIR | |
361 | cmpw r3, r8 | |
362 | beq 20f | |
363 | ||
364 | /* start the specified thread */ | |
365 | LOAD_REG_ADDR(r5, fsl_secondary_thread_init) | |
366 | ld r4, 0(r5) | |
367 | bl book3e_start_thread | |
368 | ||
369 | /* stop the current thread */ | |
370 | mr r3, r8 | |
371 | bl book3e_stop_thread | |
372 | 10: | |
373 | b 10b | |
374 | 20: | |
2d27cfd3 BH |
375 | #endif |
376 | ||
377 | generic_secondary_common_init: | |
14cf11af PM |
378 | /* Set up a paca value for this processor. Since we have the |
379 | * physical cpu id in r24, we need to search the pacas to find | |
380 | * which logical id maps to our physical one. | |
381 | */ | |
1426d5a3 ME |
382 | LOAD_REG_ADDR(r13, paca) /* Load paca pointer */ |
383 | ld r13,0(r13) /* Get base vaddr of paca array */ | |
768d18ad MM |
384 | #ifndef CONFIG_SMP |
385 | addi r13,r13,PACA_SIZE /* know r13 if used accidentally */ | |
b1576fec | 386 | b kexec_wait /* wait for next kernel if !SMP */ |
768d18ad MM |
387 | #else |
388 | LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */ | |
389 | lwz r7,0(r7) /* also the max paca allocated */ | |
14cf11af PM |
390 | li r5,0 /* logical cpu id */ |
391 | 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ | |
392 | cmpw r6,r24 /* Compare to our id */ | |
393 | beq 2f | |
394 | addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ | |
395 | addi r5,r5,1 | |
768d18ad | 396 | cmpw r5,r7 /* Check if more pacas exist */ |
14cf11af PM |
397 | blt 1b |
398 | ||
399 | mr r3,r24 /* not found, copy phys to r3 */ | |
b1576fec | 400 | b kexec_wait /* next kernel might do better */ |
14cf11af | 401 | |
2dd60d79 | 402 | 2: SET_PACA(r13) |
2d27cfd3 BH |
403 | #ifdef CONFIG_PPC_BOOK3E |
404 | addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ | |
405 | mtspr SPRN_SPRG_TLB_EXFRAME,r12 | |
406 | #endif | |
407 | ||
14cf11af PM |
408 | /* From now on, r24 is expected to be logical cpuid */ |
409 | mr r24,r5 | |
b6f6b98a | 410 | |
f39b7a55 | 411 | /* See if we need to call a cpu state restore handler */ |
e31aa453 | 412 | LOAD_REG_ADDR(r23, cur_cpu_spec) |
f39b7a55 | 413 | ld r23,0(r23) |
2751b628 AB |
414 | ld r12,CPU_SPEC_RESTORE(r23) |
415 | cmpdi 0,r12,0 | |
9d07bc84 | 416 | beq 3f |
f55d9665 | 417 | #ifdef PPC64_ELF_ABI_v1 |
2751b628 AB |
418 | ld r12,0(r12) |
419 | #endif | |
cc7efbf9 | 420 | mtctr r12 |
f39b7a55 OJ |
421 | bctrl |
422 | ||
7ac87abb | 423 | 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */ |
9d07bc84 BH |
424 | lwarx r4,0,r3 |
425 | subi r4,r4,1 | |
426 | stwcx. r4,0,r3 | |
427 | bne 3b | |
428 | isync | |
429 | ||
430 | 4: HMT_LOW | |
ad0693ee BH |
431 | lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ |
432 | /* start. */ | |
ad0693ee | 433 | cmpwi 0,r23,0 |
9d07bc84 | 434 | beq 4b /* Loop until told to go */ |
ad0693ee BH |
435 | |
436 | sync /* order paca.run and cur_cpu_spec */ | |
9d07bc84 | 437 | isync /* In case code patching happened */ |
ad0693ee | 438 | |
9d07bc84 | 439 | /* Create a temp kernel stack for use before relocation is on. */ |
14cf11af PM |
440 | ld r1,PACAEMERGSP(r13) |
441 | subi r1,r1,STACK_FRAME_OVERHEAD | |
442 | ||
c705677e | 443 | b __secondary_start |
768d18ad | 444 | #endif /* SMP */ |
14cf11af | 445 | |
e31aa453 PM |
446 | /* |
447 | * Turn the MMU off. | |
448 | * Assumes we're mapped EA == RA if the MMU is on. | |
449 | */ | |
2d27cfd3 | 450 | #ifdef CONFIG_PPC_BOOK3S |
6a3bab90 | 451 | __mmu_off: |
14cf11af PM |
452 | mfmsr r3 |
453 | andi. r0,r3,MSR_IR|MSR_DR | |
454 | beqlr | |
e31aa453 | 455 | mflr r4 |
14cf11af PM |
456 | andc r3,r3,r0 |
457 | mtspr SPRN_SRR0,r4 | |
458 | mtspr SPRN_SRR1,r3 | |
459 | sync | |
460 | rfid | |
461 | b . /* prevent speculative execution */ | |
2d27cfd3 | 462 | #endif |
14cf11af PM |
463 | |
464 | ||
465 | /* | |
466 | * Here is our main kernel entry point. We support currently 2 kind of entries | |
467 | * depending on the value of r5. | |
468 | * | |
469 | * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content | |
470 | * in r3...r7 | |
471 | * | |
472 | * r5 == NULL -> kexec style entry. r3 is a physical pointer to the | |
473 | * DT block, r4 is a physical pointer to the kernel itself | |
474 | * | |
475 | */ | |
6a3bab90 | 476 | __start_initialization_multiplatform: |
e31aa453 | 477 | /* Make sure we are running in 64 bits mode */ |
b1576fec | 478 | bl enable_64b_mode |
e31aa453 PM |
479 | |
480 | /* Get TOC pointer (current runtime address) */ | |
b1576fec | 481 | bl relative_toc |
e31aa453 PM |
482 | |
483 | /* find out where we are now */ | |
484 | bcl 20,31,$+4 | |
485 | 0: mflr r26 /* r26 = runtime addr here */ | |
486 | addis r26,r26,(_stext - 0b)@ha | |
487 | addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ | |
488 | ||
14cf11af PM |
489 | /* |
490 | * Are we booted from a PROM Of-type client-interface ? | |
491 | */ | |
492 | cmpldi cr0,r5,0 | |
939e60f6 | 493 | beq 1f |
b1576fec | 494 | b __boot_from_prom /* yes -> prom */ |
939e60f6 | 495 | 1: |
14cf11af PM |
496 | /* Save parameters */ |
497 | mr r31,r3 | |
498 | mr r30,r4 | |
daea1175 BH |
499 | #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL |
500 | /* Save OPAL entry */ | |
501 | mr r28,r8 | |
502 | mr r29,r9 | |
503 | #endif | |
14cf11af | 504 | |
2d27cfd3 | 505 | #ifdef CONFIG_PPC_BOOK3E |
b1576fec AB |
506 | bl start_initialization_book3e |
507 | b __after_prom_start | |
2d27cfd3 | 508 | #else |
14cf11af | 509 | /* Setup some critical 970 SPRs before switching MMU off */ |
f39b7a55 OJ |
510 | mfspr r0,SPRN_PVR |
511 | srwi r0,r0,16 | |
512 | cmpwi r0,0x39 /* 970 */ | |
513 | beq 1f | |
514 | cmpwi r0,0x3c /* 970FX */ | |
515 | beq 1f | |
516 | cmpwi r0,0x44 /* 970MP */ | |
190a24f5 OJ |
517 | beq 1f |
518 | cmpwi r0,0x45 /* 970GX */ | |
f39b7a55 | 519 | bne 2f |
b1576fec | 520 | 1: bl __cpu_preinit_ppc970 |
f39b7a55 | 521 | 2: |
14cf11af | 522 | |
e31aa453 | 523 | /* Switch off MMU if not already off */ |
b1576fec AB |
524 | bl __mmu_off |
525 | b __after_prom_start | |
2d27cfd3 | 526 | #endif /* CONFIG_PPC_BOOK3E */ |
14cf11af | 527 | |
6a3bab90 | 528 | __boot_from_prom: |
28794d34 | 529 | #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE |
14cf11af PM |
530 | /* Save parameters */ |
531 | mr r31,r3 | |
532 | mr r30,r4 | |
533 | mr r29,r5 | |
534 | mr r28,r6 | |
535 | mr r27,r7 | |
536 | ||
6088857b OH |
537 | /* |
538 | * Align the stack to 16-byte boundary | |
539 | * Depending on the size and layout of the ELF sections in the initial | |
e31aa453 | 540 | * boot binary, the stack pointer may be unaligned on PowerMac |
6088857b | 541 | */ |
c05b4770 LT |
542 | rldicr r1,r1,0,59 |
543 | ||
549e8152 PM |
544 | #ifdef CONFIG_RELOCATABLE |
545 | /* Relocate code for where we are now */ | |
546 | mr r3,r26 | |
b1576fec | 547 | bl relocate |
549e8152 PM |
548 | #endif |
549 | ||
14cf11af PM |
550 | /* Restore parameters */ |
551 | mr r3,r31 | |
552 | mr r4,r30 | |
553 | mr r5,r29 | |
554 | mr r6,r28 | |
555 | mr r7,r27 | |
556 | ||
557 | /* Do all of the interaction with OF client interface */ | |
549e8152 | 558 | mr r8,r26 |
b1576fec | 559 | bl prom_init |
28794d34 BH |
560 | #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ |
561 | ||
562 | /* We never return. We also hit that trap if trying to boot | |
563 | * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ | |
14cf11af PM |
564 | trap |
565 | ||
6a3bab90 | 566 | __after_prom_start: |
549e8152 PM |
567 | #ifdef CONFIG_RELOCATABLE |
568 | /* process relocations for the final address of the kernel */ | |
569 | lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ | |
570 | sldi r25,r25,32 | |
1cb6e064 TC |
571 | #if defined(CONFIG_PPC_BOOK3E) |
572 | tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ | |
573 | #endif | |
57f26649 | 574 | lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) |
1cb6e064 TC |
575 | #if defined(CONFIG_PPC_BOOK3E) |
576 | tophys(r26,r26) | |
577 | #endif | |
928a3197 | 578 | cmplwi cr0,r7,1 /* flagged to stay where we are ? */ |
54622f10 MK |
579 | bne 1f |
580 | add r25,r25,r26 | |
54622f10 | 581 | 1: mr r3,r25 |
b1576fec | 582 | bl relocate |
1cb6e064 TC |
583 | #if defined(CONFIG_PPC_BOOK3E) |
584 | /* IVPR needs to be set after relocation. */ | |
585 | bl init_core_book3e | |
586 | #endif | |
549e8152 | 587 | #endif |
14cf11af PM |
588 | |
589 | /* | |
e31aa453 | 590 | * We need to run with _stext at physical address PHYSICAL_START. |
14cf11af PM |
591 | * This will leave some code in the first 256B of |
592 | * real memory, which are reserved for software use. | |
14cf11af PM |
593 | * |
594 | * Note: This process overwrites the OF exception vectors. | |
14cf11af | 595 | */ |
549e8152 | 596 | li r3,0 /* target addr */ |
2d27cfd3 | 597 | #ifdef CONFIG_PPC_BOOK3E |
835c031c | 598 | tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ |
2d27cfd3 | 599 | #endif |
549e8152 | 600 | mr. r4,r26 /* In some cases the loader may */ |
835c031c TC |
601 | #if defined(CONFIG_PPC_BOOK3E) |
602 | tovirt(r4,r4) | |
603 | #endif | |
e31aa453 | 604 | beq 9f /* have already put us at zero */ |
14cf11af PM |
605 | li r6,0x100 /* Start offset, the first 0x100 */ |
606 | /* bytes were copied earlier. */ | |
607 | ||
11ee7e99 | 608 | #ifdef CONFIG_RELOCATABLE |
54622f10 MK |
609 | /* |
610 | * Check if the kernel has to be running as relocatable kernel based on the | |
8b8b0cc1 | 611 | * variable __run_at_load, if it is set the kernel is treated as relocatable |
54622f10 MK |
612 | * kernel, otherwise it will be moved to PHYSICAL_START |
613 | */ | |
1cb6e064 TC |
614 | #if defined(CONFIG_PPC_BOOK3E) |
615 | tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ | |
616 | #endif | |
57f26649 | 617 | lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) |
8b8b0cc1 | 618 | cmplwi cr0,r7,1 |
54622f10 MK |
619 | bne 3f |
620 | ||
1cb6e064 TC |
621 | #ifdef CONFIG_PPC_BOOK3E |
622 | LOAD_REG_ADDR(r5, __end_interrupts) | |
623 | LOAD_REG_ADDR(r11, _stext) | |
624 | sub r5,r5,r11 | |
625 | #else | |
c1fb6816 | 626 | /* just copy interrupts */ |
57f26649 | 627 | LOAD_REG_IMMEDIATE(r5, FIXED_SYMBOL_ABS_ADDR(__end_interrupts)) |
1cb6e064 | 628 | #endif |
54622f10 MK |
629 | b 5f |
630 | 3: | |
631 | #endif | |
57f26649 NP |
632 | /* # bytes of memory to copy */ |
633 | lis r5,(ABS_ADDR(copy_to_here))@ha | |
634 | addi r5,r5,(ABS_ADDR(copy_to_here))@l | |
54622f10 | 635 | |
b1576fec | 636 | bl copy_and_flush /* copy the first n bytes */ |
14cf11af PM |
637 | /* this includes the code being */ |
638 | /* executed here. */ | |
57f26649 NP |
639 | /* Jump to the copy of this code that we just made */ |
640 | addis r8,r3,(ABS_ADDR(4f))@ha | |
641 | addi r12,r8,(ABS_ADDR(4f))@l | |
cc7efbf9 | 642 | mtctr r12 |
14cf11af PM |
643 | bctr |
644 | ||
286e4f90 | 645 | .balign 8 |
573819e3 | 646 | p_end: .llong _end - copy_to_here |
54622f10 | 647 | |
573819e3 NP |
648 | 4: |
649 | /* | |
650 | * Now copy the rest of the kernel up to _end, add | |
651 | * _end - copy_to_here to the copy limit and run again. | |
652 | */ | |
57f26649 NP |
653 | addis r8,r26,(ABS_ADDR(p_end))@ha |
654 | ld r8,(ABS_ADDR(p_end))@l(r8) | |
573819e3 | 655 | add r5,r5,r8 |
b1576fec | 656 | 5: bl copy_and_flush /* copy the rest */ |
e31aa453 | 657 | |
b1576fec | 658 | 9: b start_here_multiplatform |
e31aa453 | 659 | |
14cf11af PM |
660 | /* |
661 | * Copy routine used to copy the kernel to start at physical address 0 | |
662 | * and flush and invalidate the caches as needed. | |
663 | * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset | |
664 | * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. | |
665 | * | |
666 | * Note: this routine *only* clobbers r0, r6 and lr | |
667 | */ | |
668 | _GLOBAL(copy_and_flush) | |
669 | addi r5,r5,-8 | |
670 | addi r6,r6,-8 | |
5a2fe38d | 671 | 4: li r0,8 /* Use the smallest common */ |
14cf11af PM |
672 | /* denominator cache line */ |
673 | /* size. This results in */ | |
674 | /* extra cache line flushes */ | |
675 | /* but operation is correct. */ | |
676 | /* Can't get cache line size */ | |
677 | /* from NACA as it is being */ | |
678 | /* moved too. */ | |
679 | ||
680 | mtctr r0 /* put # words/line in ctr */ | |
681 | 3: addi r6,r6,8 /* copy a cache line */ | |
682 | ldx r0,r6,r4 | |
683 | stdx r0,r6,r3 | |
684 | bdnz 3b | |
685 | dcbst r6,r3 /* write it to memory */ | |
686 | sync | |
687 | icbi r6,r3 /* flush the icache line */ | |
688 | cmpld 0,r6,r5 | |
689 | blt 4b | |
690 | sync | |
691 | addi r5,r5,8 | |
692 | addi r6,r6,8 | |
29ce3c50 | 693 | isync |
14cf11af PM |
694 | blr |
695 | ||
696 | .align 8 | |
697 | copy_to_here: | |
698 | ||
699 | #ifdef CONFIG_SMP | |
700 | #ifdef CONFIG_PPC_PMAC | |
701 | /* | |
702 | * On PowerMac, secondary processors starts from the reset vector, which | |
703 | * is temporarily turned into a call to one of the functions below. | |
704 | */ | |
705 | .section ".text"; | |
706 | .align 2 ; | |
707 | ||
35499c01 PM |
708 | .globl __secondary_start_pmac_0 |
709 | __secondary_start_pmac_0: | |
710 | /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ | |
711 | li r24,0 | |
712 | b 1f | |
713 | li r24,1 | |
714 | b 1f | |
715 | li r24,2 | |
716 | b 1f | |
717 | li r24,3 | |
718 | 1: | |
14cf11af PM |
719 | |
720 | _GLOBAL(pmac_secondary_start) | |
721 | /* turn on 64-bit mode */ | |
b1576fec | 722 | bl enable_64b_mode |
14cf11af | 723 | |
c478b581 BH |
724 | li r0,0 |
725 | mfspr r3,SPRN_HID4 | |
726 | rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ | |
727 | sync | |
728 | mtspr SPRN_HID4,r3 | |
729 | isync | |
730 | sync | |
731 | slbia | |
732 | ||
e31aa453 | 733 | /* get TOC pointer (real address) */ |
b1576fec | 734 | bl relative_toc |
1fbe9cf2 | 735 | tovirt(r2,r2) |
e31aa453 | 736 | |
14cf11af | 737 | /* Copy some CPU settings from CPU 0 */ |
b1576fec | 738 | bl __restore_cpu_ppc970 |
14cf11af PM |
739 | |
740 | /* pSeries do that early though I don't think we really need it */ | |
741 | mfmsr r3 | |
742 | ori r3,r3,MSR_RI | |
743 | mtmsrd r3 /* RI on */ | |
744 | ||
745 | /* Set up a paca value for this processor. */ | |
1426d5a3 ME |
746 | LOAD_REG_ADDR(r4,paca) /* Load paca pointer */ |
747 | ld r4,0(r4) /* Get base vaddr of paca array */ | |
e31aa453 | 748 | mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ |
14cf11af | 749 | add r13,r13,r4 /* for this processor. */ |
2dd60d79 | 750 | SET_PACA(r13) /* Save vaddr of paca in an SPRG*/ |
14cf11af | 751 | |
62cc67b9 BH |
752 | /* Mark interrupts soft and hard disabled (they might be enabled |
753 | * in the PACA when doing hotplug) | |
754 | */ | |
755 | li r0,0 | |
756 | stb r0,PACASOFTIRQEN(r13) | |
7230c564 BH |
757 | li r0,PACA_IRQ_HARD_DIS |
758 | stb r0,PACAIRQHAPPENED(r13) | |
62cc67b9 | 759 | |
14cf11af PM |
760 | /* Create a temp kernel stack for use before relocation is on. */ |
761 | ld r1,PACAEMERGSP(r13) | |
762 | subi r1,r1,STACK_FRAME_OVERHEAD | |
763 | ||
c705677e | 764 | b __secondary_start |
14cf11af PM |
765 | |
766 | #endif /* CONFIG_PPC_PMAC */ | |
767 | ||
768 | /* | |
769 | * This function is called after the master CPU has released the | |
770 | * secondary processors. The execution environment is relocation off. | |
771 | * The paca for this processor has the following fields initialized at | |
772 | * this point: | |
773 | * 1. Processor number | |
774 | * 2. Segment table pointer (virtual address) | |
775 | * On entry the following are set: | |
4f8cf36f | 776 | * r1 = stack pointer (real addr of temp stack) |
ee43eb78 BH |
777 | * r24 = cpu# (in Linux terms) |
778 | * r13 = paca virtual address | |
779 | * SPRG_PACA = paca virtual address | |
14cf11af | 780 | */ |
2d27cfd3 BH |
781 | .section ".text"; |
782 | .align 2 ; | |
783 | ||
fc68e869 | 784 | .globl __secondary_start |
c705677e | 785 | __secondary_start: |
799d6046 PM |
786 | /* Set thread priority to MEDIUM */ |
787 | HMT_MEDIUM | |
14cf11af | 788 | |
4f8cf36f | 789 | /* Initialize the kernel stack */ |
e58c3495 | 790 | LOAD_REG_ADDR(r3, current_set) |
14cf11af | 791 | sldi r28,r24,3 /* get current_set[cpu#] */ |
54a83404 MN |
792 | ldx r14,r3,r28 |
793 | addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD | |
794 | std r14,PACAKSAVE(r13) | |
14cf11af | 795 | |
376af594 | 796 | /* Do early setup for that CPU (SLB and hash table pointer) */ |
b1576fec | 797 | bl early_setup_secondary |
f761622e | 798 | |
54a83404 MN |
799 | /* |
800 | * setup the new stack pointer, but *don't* use this until | |
801 | * translation is on. | |
802 | */ | |
803 | mr r1, r14 | |
804 | ||
799d6046 | 805 | /* Clear backchain so we get nice backtraces */ |
14cf11af PM |
806 | li r7,0 |
807 | mtlr r7 | |
808 | ||
7230c564 BH |
809 | /* Mark interrupts soft and hard disabled (they might be enabled |
810 | * in the PACA when doing hotplug) | |
811 | */ | |
4f8cf36f | 812 | stb r7,PACASOFTIRQEN(r13) |
7230c564 BH |
813 | li r0,PACA_IRQ_HARD_DIS |
814 | stb r0,PACAIRQHAPPENED(r13) | |
4f8cf36f | 815 | |
14cf11af | 816 | /* enable MMU and jump to start_secondary */ |
ad0289e4 | 817 | LOAD_REG_ADDR(r3, start_secondary_prolog) |
e58c3495 | 818 | LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) |
d04c56f7 | 819 | |
b5bbeb23 PM |
820 | mtspr SPRN_SRR0,r3 |
821 | mtspr SPRN_SRR1,r4 | |
2d27cfd3 | 822 | RFI |
14cf11af PM |
823 | b . /* prevent speculative execution */ |
824 | ||
825 | /* | |
826 | * Running with relocation on at this point. All we want to do is | |
e31aa453 PM |
827 | * zero the stack back-chain pointer and get the TOC virtual address |
828 | * before going into C code. | |
14cf11af | 829 | */ |
ad0289e4 | 830 | start_secondary_prolog: |
e31aa453 | 831 | ld r2,PACATOC(r13) |
14cf11af PM |
832 | li r3,0 |
833 | std r3,0(r1) /* Zero the stack frame pointer */ | |
b1576fec | 834 | bl start_secondary |
799d6046 | 835 | b . |
8dbce53c VS |
836 | /* |
837 | * Reset stack pointer and call start_secondary | |
838 | * to continue with online operation when woken up | |
839 | * from cede in cpu offline. | |
840 | */ | |
841 | _GLOBAL(start_secondary_resume) | |
842 | ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ | |
843 | li r3,0 | |
844 | std r3,0(r1) /* Zero the stack frame pointer */ | |
b1576fec | 845 | bl start_secondary |
8dbce53c | 846 | b . |
14cf11af PM |
847 | #endif |
848 | ||
849 | /* | |
850 | * This subroutine clobbers r11 and r12 | |
851 | */ | |
6a3bab90 | 852 | enable_64b_mode: |
14cf11af | 853 | mfmsr r11 /* grab the current MSR */ |
2d27cfd3 BH |
854 | #ifdef CONFIG_PPC_BOOK3E |
855 | oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ | |
856 | mtmsr r11 | |
857 | #else /* CONFIG_PPC_BOOK3E */ | |
9f0b0793 | 858 | li r12,(MSR_64BIT | MSR_ISF)@highest |
e31aa453 | 859 | sldi r12,r12,48 |
14cf11af PM |
860 | or r11,r11,r12 |
861 | mtmsrd r11 | |
862 | isync | |
2d27cfd3 | 863 | #endif |
14cf11af PM |
864 | blr |
865 | ||
e31aa453 PM |
866 | /* |
867 | * This puts the TOC pointer into r2, offset by 0x8000 (as expected | |
868 | * by the toolchain). It computes the correct value for wherever we | |
869 | * are running at the moment, using position-independent code. | |
1fbe9cf2 AB |
870 | * |
871 | * Note: The compiler constructs pointers using offsets from the | |
872 | * TOC in -mcmodel=medium mode. After we relocate to 0 but before | |
873 | * the MMU is on we need our TOC to be a virtual address otherwise | |
874 | * these pointers will be real addresses which may get stored and | |
875 | * accessed later with the MMU on. We use tovirt() at the call | |
876 | * sites to handle this. | |
e31aa453 PM |
877 | */ |
878 | _GLOBAL(relative_toc) | |
879 | mflr r0 | |
880 | bcl 20,31,$+4 | |
e550592e BH |
881 | 0: mflr r11 |
882 | ld r2,(p_toc - 0b)(r11) | |
883 | add r2,r2,r11 | |
e31aa453 PM |
884 | mtlr r0 |
885 | blr | |
886 | ||
5b63fee1 | 887 | .balign 8 |
e31aa453 PM |
888 | p_toc: .llong __toc_start + 0x8000 - 0b |
889 | ||
14cf11af PM |
890 | /* |
891 | * This is where the main kernel code starts. | |
892 | */ | |
6a3bab90 | 893 | start_here_multiplatform: |
1fbe9cf2 | 894 | /* set up the TOC */ |
b1576fec | 895 | bl relative_toc |
1fbe9cf2 | 896 | tovirt(r2,r2) |
14cf11af PM |
897 | |
898 | /* Clear out the BSS. It may have been done in prom_init, | |
899 | * already but that's irrelevant since prom_init will soon | |
900 | * be detached from the kernel completely. Besides, we need | |
901 | * to clear it now for kexec-style entry. | |
902 | */ | |
e31aa453 PM |
903 | LOAD_REG_ADDR(r11,__bss_stop) |
904 | LOAD_REG_ADDR(r8,__bss_start) | |
14cf11af PM |
905 | sub r11,r11,r8 /* bss size */ |
906 | addi r11,r11,7 /* round up to an even double word */ | |
e31aa453 | 907 | srdi. r11,r11,3 /* shift right by 3 */ |
14cf11af PM |
908 | beq 4f |
909 | addi r8,r8,-8 | |
910 | li r0,0 | |
911 | mtctr r11 /* zero this many doublewords */ | |
912 | 3: stdu r0,8(r8) | |
913 | bdnz 3b | |
914 | 4: | |
915 | ||
daea1175 BH |
916 | #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL |
917 | /* Setup OPAL entry */ | |
ab7f961a | 918 | LOAD_REG_ADDR(r11, opal) |
daea1175 BH |
919 | std r28,0(r11); |
920 | std r29,8(r11); | |
921 | #endif | |
922 | ||
2d27cfd3 | 923 | #ifndef CONFIG_PPC_BOOK3E |
14cf11af PM |
924 | mfmsr r6 |
925 | ori r6,r6,MSR_RI | |
926 | mtmsrd r6 /* RI on */ | |
2d27cfd3 | 927 | #endif |
14cf11af | 928 | |
549e8152 PM |
929 | #ifdef CONFIG_RELOCATABLE |
930 | /* Save the physical address we're running at in kernstart_addr */ | |
931 | LOAD_REG_ADDR(r4, kernstart_addr) | |
932 | clrldi r0,r25,2 | |
933 | std r0,0(r4) | |
934 | #endif | |
935 | ||
e31aa453 | 936 | /* The following gets the stack set up with the regs */ |
14cf11af PM |
937 | /* pointing to the real addr of the kernel stack. This is */ |
938 | /* all done to support the C function call below which sets */ | |
939 | /* up the htab. This is done because we have relocated the */ | |
940 | /* kernel but are still running in real mode. */ | |
941 | ||
e31aa453 | 942 | LOAD_REG_ADDR(r3,init_thread_union) |
14cf11af | 943 | |
e31aa453 | 944 | /* set up a stack pointer */ |
14cf11af PM |
945 | addi r1,r3,THREAD_SIZE |
946 | li r0,0 | |
947 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
948 | ||
376af594 ME |
949 | /* |
950 | * Do very early kernel initializations, including initial hash table | |
951 | * and SLB setup before we turn on relocation. | |
952 | */ | |
14cf11af PM |
953 | |
954 | /* Restore parameters passed from prom_init/kexec */ | |
955 | mr r3,r31 | |
b1576fec | 956 | bl early_setup /* also sets r13 and SPRG_PACA */ |
14cf11af | 957 | |
ad0289e4 | 958 | LOAD_REG_ADDR(r3, start_here_common) |
e31aa453 | 959 | ld r4,PACAKMSR(r13) |
b5bbeb23 PM |
960 | mtspr SPRN_SRR0,r3 |
961 | mtspr SPRN_SRR1,r4 | |
2d27cfd3 | 962 | RFI |
14cf11af | 963 | b . /* prevent speculative execution */ |
fa745a12 | 964 | |
14cf11af | 965 | /* This is where all platforms converge execution */ |
ad0289e4 AB |
966 | |
967 | start_here_common: | |
14cf11af | 968 | /* relocation is on at this point */ |
e31aa453 | 969 | std r1,PACAKSAVE(r13) |
14cf11af | 970 | |
e31aa453 | 971 | /* Load the TOC (virtual address) */ |
14cf11af | 972 | ld r2,PACATOC(r13) |
14cf11af | 973 | |
7230c564 BH |
974 | /* Mark interrupts soft and hard disabled (they might be enabled |
975 | * in the PACA when doing hotplug) | |
976 | */ | |
977 | li r0,0 | |
978 | stb r0,PACASOFTIRQEN(r13) | |
979 | li r0,PACA_IRQ_HARD_DIS | |
980 | stb r0,PACAIRQHAPPENED(r13) | |
14cf11af | 981 | |
7230c564 | 982 | /* Generic kernel entry */ |
b1576fec | 983 | bl start_kernel |
14cf11af | 984 | |
f1870f77 AB |
985 | /* Not reached */ |
986 | BUG_OPCODE | |
14cf11af | 987 | |
14cf11af PM |
988 | /* |
989 | * We put a few things here that have to be page-aligned. | |
990 | * This stuff goes at the beginning of the bss, which is page-aligned. | |
991 | */ | |
992 | .section ".bss" | |
43a5c684 AK |
993 | /* |
994 | * pgd dir should be aligned to PGD_TABLE_SIZE which is 64K. | |
995 | * We will need to find a better way to fix this | |
996 | */ | |
997 | .align 16 | |
14cf11af | 998 | |
43a5c684 AK |
999 | .globl swapper_pg_dir |
1000 | swapper_pg_dir: | |
1001 | .space PGD_TABLE_SIZE | |
14cf11af PM |
1002 | |
1003 | .globl empty_zero_page | |
1004 | empty_zero_page: | |
1005 | .space PAGE_SIZE | |
9445aa1a | 1006 | EXPORT_SYMBOL(empty_zero_page) |