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14cf11af PM |
1 | /* |
2 | * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> | |
3 | * Initial PowerPC version. | |
4 | * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> | |
5 | * Rewritten for PReP | |
6 | * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> | |
7 | * Low-level exception handers, MMU support, and rewrite. | |
8 | * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> | |
9 | * PowerPC 8xx modifications. | |
10 | * Copyright (c) 1998-1999 TiVo, Inc. | |
11 | * PowerPC 403GCX modifications. | |
12 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> | |
13 | * PowerPC 403GCX/405GP modifications. | |
14 | * Copyright 2000 MontaVista Software Inc. | |
15 | * PPC405 modifications | |
16 | * PowerPC 403GCX/405GP modifications. | |
17 | * Author: MontaVista Software, Inc. | |
18 | * frank_rowand@mvista.com or source@mvista.com | |
19 | * debbie_chu@mvista.com | |
20 | * | |
21 | * | |
22 | * Module name: head_4xx.S | |
23 | * | |
24 | * Description: | |
25 | * Kernel execution entry point code. | |
26 | * | |
27 | * This program is free software; you can redistribute it and/or | |
28 | * modify it under the terms of the GNU General Public License | |
29 | * as published by the Free Software Foundation; either version | |
30 | * 2 of the License, or (at your option) any later version. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <linux/config.h> | |
35 | #include <asm/processor.h> | |
36 | #include <asm/page.h> | |
37 | #include <asm/mmu.h> | |
38 | #include <asm/pgtable.h> | |
39 | #include <asm/ibm4xx.h> | |
40 | #include <asm/cputable.h> | |
41 | #include <asm/thread_info.h> | |
42 | #include <asm/ppc_asm.h> | |
43 | #include <asm/asm-offsets.h> | |
44 | ||
45 | /* As with the other PowerPC ports, it is expected that when code | |
46 | * execution begins here, the following registers contain valid, yet | |
47 | * optional, information: | |
48 | * | |
49 | * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) | |
50 | * r4 - Starting address of the init RAM disk | |
51 | * r5 - Ending address of the init RAM disk | |
52 | * r6 - Start of kernel command line string (e.g. "mem=96m") | |
53 | * r7 - End of kernel command line string | |
54 | * | |
55 | * This is all going to change RSN when we add bi_recs....... -- Dan | |
56 | */ | |
57 | .text | |
58 | _GLOBAL(_stext) | |
59 | _GLOBAL(_start) | |
60 | ||
61 | /* Save parameters we are passed. | |
62 | */ | |
63 | mr r31,r3 | |
64 | mr r30,r4 | |
65 | mr r29,r5 | |
66 | mr r28,r6 | |
67 | mr r27,r7 | |
68 | ||
69 | /* We have to turn on the MMU right away so we get cache modes | |
70 | * set correctly. | |
71 | */ | |
72 | bl initial_mmu | |
73 | ||
74 | /* We now have the lower 16 Meg mapped into TLB entries, and the caches | |
75 | * ready to work. | |
76 | */ | |
77 | turn_on_mmu: | |
78 | lis r0,MSR_KERNEL@h | |
79 | ori r0,r0,MSR_KERNEL@l | |
80 | mtspr SPRN_SRR1,r0 | |
81 | lis r0,start_here@h | |
82 | ori r0,r0,start_here@l | |
83 | mtspr SPRN_SRR0,r0 | |
84 | SYNC | |
85 | rfi /* enables MMU */ | |
86 | b . /* prevent prefetch past rfi */ | |
87 | ||
88 | /* | |
89 | * This area is used for temporarily saving registers during the | |
90 | * critical exception prolog. | |
91 | */ | |
92 | . = 0xc0 | |
93 | crit_save: | |
94 | _GLOBAL(crit_r10) | |
95 | .space 4 | |
96 | _GLOBAL(crit_r11) | |
97 | .space 4 | |
98 | ||
99 | /* | |
100 | * Exception vector entry code. This code runs with address translation | |
101 | * turned off (i.e. using physical addresses). We assume SPRG3 has the | |
102 | * physical address of the current task thread_struct. | |
103 | * Note that we have to have decremented r1 before we write to any fields | |
104 | * of the exception frame, since a critical interrupt could occur at any | |
105 | * time, and it will write to the area immediately below the current r1. | |
106 | */ | |
107 | #define NORMAL_EXCEPTION_PROLOG \ | |
108 | mtspr SPRN_SPRG0,r10; /* save two registers to work with */\ | |
109 | mtspr SPRN_SPRG1,r11; \ | |
110 | mtspr SPRN_SPRG2,r1; \ | |
111 | mfcr r10; /* save CR in r10 for now */\ | |
112 | mfspr r11,SPRN_SRR1; /* check whether user or kernel */\ | |
113 | andi. r11,r11,MSR_PR; \ | |
114 | beq 1f; \ | |
115 | mfspr r1,SPRN_SPRG3; /* if from user, start at top of */\ | |
116 | lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\ | |
117 | addi r1,r1,THREAD_SIZE; \ | |
118 | 1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\ | |
119 | tophys(r11,r1); \ | |
120 | stw r10,_CCR(r11); /* save various registers */\ | |
121 | stw r12,GPR12(r11); \ | |
122 | stw r9,GPR9(r11); \ | |
123 | mfspr r10,SPRN_SPRG0; \ | |
124 | stw r10,GPR10(r11); \ | |
125 | mfspr r12,SPRN_SPRG1; \ | |
126 | stw r12,GPR11(r11); \ | |
127 | mflr r10; \ | |
128 | stw r10,_LINK(r11); \ | |
129 | mfspr r10,SPRN_SPRG2; \ | |
130 | mfspr r12,SPRN_SRR0; \ | |
131 | stw r10,GPR1(r11); \ | |
132 | mfspr r9,SPRN_SRR1; \ | |
133 | stw r10,0(r11); \ | |
134 | rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ | |
135 | stw r0,GPR0(r11); \ | |
136 | SAVE_4GPRS(3, r11); \ | |
137 | SAVE_2GPRS(7, r11) | |
138 | ||
139 | /* | |
140 | * Exception prolog for critical exceptions. This is a little different | |
141 | * from the normal exception prolog above since a critical exception | |
142 | * can potentially occur at any point during normal exception processing. | |
143 | * Thus we cannot use the same SPRG registers as the normal prolog above. | |
144 | * Instead we use a couple of words of memory at low physical addresses. | |
145 | * This is OK since we don't support SMP on these processors. | |
146 | */ | |
147 | #define CRITICAL_EXCEPTION_PROLOG \ | |
148 | stw r10,crit_r10@l(0); /* save two registers to work with */\ | |
149 | stw r11,crit_r11@l(0); \ | |
150 | mfcr r10; /* save CR in r10 for now */\ | |
151 | mfspr r11,SPRN_SRR3; /* check whether user or kernel */\ | |
152 | andi. r11,r11,MSR_PR; \ | |
153 | lis r11,critical_stack_top@h; \ | |
154 | ori r11,r11,critical_stack_top@l; \ | |
155 | beq 1f; \ | |
156 | /* COMING FROM USER MODE */ \ | |
157 | mfspr r11,SPRN_SPRG3; /* if from user, start at top of */\ | |
158 | lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ | |
159 | addi r11,r11,THREAD_SIZE; \ | |
160 | 1: subi r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame */\ | |
161 | tophys(r11,r11); \ | |
162 | stw r10,_CCR(r11); /* save various registers */\ | |
163 | stw r12,GPR12(r11); \ | |
164 | stw r9,GPR9(r11); \ | |
165 | mflr r10; \ | |
166 | stw r10,_LINK(r11); \ | |
167 | mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\ | |
168 | stw r12,_DEAR(r11); /* since they may have had stuff */\ | |
169 | mfspr r9,SPRN_ESR; /* in them at the point where the */\ | |
170 | stw r9,_ESR(r11); /* exception was taken */\ | |
171 | mfspr r12,SPRN_SRR2; \ | |
172 | stw r1,GPR1(r11); \ | |
173 | mfspr r9,SPRN_SRR3; \ | |
174 | stw r1,0(r11); \ | |
175 | tovirt(r1,r11); \ | |
176 | rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ | |
177 | stw r0,GPR0(r11); \ | |
178 | SAVE_4GPRS(3, r11); \ | |
179 | SAVE_2GPRS(7, r11) | |
180 | ||
181 | /* | |
182 | * State at this point: | |
183 | * r9 saved in stack frame, now saved SRR3 & ~MSR_WE | |
184 | * r10 saved in crit_r10 and in stack frame, trashed | |
185 | * r11 saved in crit_r11 and in stack frame, | |
186 | * now phys stack/exception frame pointer | |
187 | * r12 saved in stack frame, now saved SRR2 | |
188 | * CR saved in stack frame, CR0.EQ = !SRR3.PR | |
189 | * LR, DEAR, ESR in stack frame | |
190 | * r1 saved in stack frame, now virt stack/excframe pointer | |
191 | * r0, r3-r8 saved in stack frame | |
192 | */ | |
193 | ||
194 | /* | |
195 | * Exception vectors. | |
196 | */ | |
197 | #define START_EXCEPTION(n, label) \ | |
198 | . = n; \ | |
199 | label: | |
200 | ||
201 | #define EXCEPTION(n, label, hdlr, xfer) \ | |
202 | START_EXCEPTION(n, label); \ | |
203 | NORMAL_EXCEPTION_PROLOG; \ | |
204 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | |
205 | xfer(n, hdlr) | |
206 | ||
207 | #define CRITICAL_EXCEPTION(n, label, hdlr) \ | |
208 | START_EXCEPTION(n, label); \ | |
209 | CRITICAL_EXCEPTION_PROLOG; \ | |
210 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | |
211 | EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ | |
212 | NOCOPY, crit_transfer_to_handler, \ | |
213 | ret_from_crit_exc) | |
214 | ||
215 | #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \ | |
216 | li r10,trap; \ | |
217 | stw r10,TRAP(r11); \ | |
218 | lis r10,msr@h; \ | |
219 | ori r10,r10,msr@l; \ | |
220 | copyee(r10, r9); \ | |
221 | bl tfer; \ | |
222 | .long hdlr; \ | |
223 | .long ret | |
224 | ||
225 | #define COPY_EE(d, s) rlwimi d,s,0,16,16 | |
226 | #define NOCOPY(d, s) | |
227 | ||
228 | #define EXC_XFER_STD(n, hdlr) \ | |
229 | EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \ | |
230 | ret_from_except_full) | |
231 | ||
232 | #define EXC_XFER_LITE(n, hdlr) \ | |
233 | EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \ | |
234 | ret_from_except) | |
235 | ||
236 | #define EXC_XFER_EE(n, hdlr) \ | |
237 | EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \ | |
238 | ret_from_except_full) | |
239 | ||
240 | #define EXC_XFER_EE_LITE(n, hdlr) \ | |
241 | EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \ | |
242 | ret_from_except) | |
243 | ||
244 | ||
245 | /* | |
246 | * 0x0100 - Critical Interrupt Exception | |
247 | */ | |
dc1c1ca3 | 248 | CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception) |
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249 | |
250 | /* | |
251 | * 0x0200 - Machine Check Exception | |
252 | */ | |
dc1c1ca3 | 253 | CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception) |
14cf11af PM |
254 | |
255 | /* | |
256 | * 0x0300 - Data Storage Exception | |
257 | * This happens for just a few reasons. U0 set (but we don't do that), | |
258 | * or zone protection fault (user violation, write to protected page). | |
259 | * If this is just an update of modified status, we do that quickly | |
260 | * and exit. Otherwise, we call heavywight functions to do the work. | |
261 | */ | |
262 | START_EXCEPTION(0x0300, DataStorage) | |
263 | mtspr SPRN_SPRG0, r10 /* Save some working registers */ | |
264 | mtspr SPRN_SPRG1, r11 | |
265 | #ifdef CONFIG_403GCX | |
266 | stw r12, 0(r0) | |
267 | stw r9, 4(r0) | |
268 | mfcr r11 | |
269 | mfspr r12, SPRN_PID | |
270 | stw r11, 8(r0) | |
271 | stw r12, 12(r0) | |
272 | #else | |
273 | mtspr SPRN_SPRG4, r12 | |
274 | mtspr SPRN_SPRG5, r9 | |
275 | mfcr r11 | |
276 | mfspr r12, SPRN_PID | |
277 | mtspr SPRN_SPRG7, r11 | |
278 | mtspr SPRN_SPRG6, r12 | |
279 | #endif | |
280 | ||
281 | /* First, check if it was a zone fault (which means a user | |
282 | * tried to access a kernel or read-protected page - always | |
283 | * a SEGV). All other faults here must be stores, so no | |
284 | * need to check ESR_DST as well. */ | |
285 | mfspr r10, SPRN_ESR | |
286 | andis. r10, r10, ESR_DIZ@h | |
287 | bne 2f | |
288 | ||
289 | mfspr r10, SPRN_DEAR /* Get faulting address */ | |
290 | ||
291 | /* If we are faulting a kernel address, we have to use the | |
292 | * kernel page tables. | |
293 | */ | |
294 | lis r11, TASK_SIZE@h | |
295 | cmplw r10, r11 | |
296 | blt+ 3f | |
297 | lis r11, swapper_pg_dir@h | |
298 | ori r11, r11, swapper_pg_dir@l | |
299 | li r9, 0 | |
300 | mtspr SPRN_PID, r9 /* TLB will have 0 TID */ | |
301 | b 4f | |
302 | ||
303 | /* Get the PGD for the current thread. | |
304 | */ | |
305 | 3: | |
306 | mfspr r11,SPRN_SPRG3 | |
307 | lwz r11,PGDIR(r11) | |
308 | 4: | |
309 | tophys(r11, r11) | |
310 | rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ | |
311 | lwz r11, 0(r11) /* Get L1 entry */ | |
312 | rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */ | |
313 | beq 2f /* Bail if no table */ | |
314 | ||
315 | rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ | |
316 | lwz r11, 0(r12) /* Get Linux PTE */ | |
317 | ||
318 | andi. r9, r11, _PAGE_RW /* Is it writeable? */ | |
319 | beq 2f /* Bail if not */ | |
320 | ||
321 | /* Update 'changed'. | |
322 | */ | |
323 | ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE | |
324 | stw r11, 0(r12) /* Update Linux page table */ | |
325 | ||
326 | /* Most of the Linux PTE is ready to load into the TLB LO. | |
327 | * We set ZSEL, where only the LS-bit determines user access. | |
328 | * We set execute, because we don't have the granularity to | |
329 | * properly set this at the page level (Linux problem). | |
330 | * If shared is set, we cause a zero PID->TID load. | |
331 | * Many of these bits are software only. Bits we don't set | |
332 | * here we (properly should) assume have the appropriate value. | |
333 | */ | |
334 | li r12, 0x0ce2 | |
335 | andc r11, r11, r12 /* Make sure 20, 21 are zero */ | |
336 | ||
337 | /* find the TLB index that caused the fault. It has to be here. | |
338 | */ | |
339 | tlbsx r9, 0, r10 | |
340 | ||
341 | tlbwe r11, r9, TLB_DATA /* Load TLB LO */ | |
342 | ||
343 | /* Done...restore registers and get out of here. | |
344 | */ | |
345 | #ifdef CONFIG_403GCX | |
346 | lwz r12, 12(r0) | |
347 | lwz r11, 8(r0) | |
348 | mtspr SPRN_PID, r12 | |
349 | mtcr r11 | |
350 | lwz r9, 4(r0) | |
351 | lwz r12, 0(r0) | |
352 | #else | |
353 | mfspr r12, SPRN_SPRG6 | |
354 | mfspr r11, SPRN_SPRG7 | |
355 | mtspr SPRN_PID, r12 | |
356 | mtcr r11 | |
357 | mfspr r9, SPRN_SPRG5 | |
358 | mfspr r12, SPRN_SPRG4 | |
359 | #endif | |
360 | mfspr r11, SPRN_SPRG1 | |
361 | mfspr r10, SPRN_SPRG0 | |
362 | PPC405_ERR77_SYNC | |
363 | rfi /* Should sync shadow TLBs */ | |
364 | b . /* prevent prefetch past rfi */ | |
365 | ||
366 | 2: | |
367 | /* The bailout. Restore registers to pre-exception conditions | |
368 | * and call the heavyweights to help us out. | |
369 | */ | |
370 | #ifdef CONFIG_403GCX | |
371 | lwz r12, 12(r0) | |
372 | lwz r11, 8(r0) | |
373 | mtspr SPRN_PID, r12 | |
374 | mtcr r11 | |
375 | lwz r9, 4(r0) | |
376 | lwz r12, 0(r0) | |
377 | #else | |
378 | mfspr r12, SPRN_SPRG6 | |
379 | mfspr r11, SPRN_SPRG7 | |
380 | mtspr SPRN_PID, r12 | |
381 | mtcr r11 | |
382 | mfspr r9, SPRN_SPRG5 | |
383 | mfspr r12, SPRN_SPRG4 | |
384 | #endif | |
385 | mfspr r11, SPRN_SPRG1 | |
386 | mfspr r10, SPRN_SPRG0 | |
387 | b DataAccess | |
388 | ||
389 | /* | |
390 | * 0x0400 - Instruction Storage Exception | |
391 | * This is caused by a fetch from non-execute or guarded pages. | |
392 | */ | |
393 | START_EXCEPTION(0x0400, InstructionAccess) | |
394 | NORMAL_EXCEPTION_PROLOG | |
395 | mr r4,r12 /* Pass SRR0 as arg2 */ | |
396 | li r5,0 /* Pass zero as arg3 */ | |
397 | EXC_XFER_EE_LITE(0x400, handle_page_fault) | |
398 | ||
399 | /* 0x0500 - External Interrupt Exception */ | |
400 | EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) | |
401 | ||
402 | /* 0x0600 - Alignment Exception */ | |
403 | START_EXCEPTION(0x0600, Alignment) | |
404 | NORMAL_EXCEPTION_PROLOG | |
405 | mfspr r4,SPRN_DEAR /* Grab the DEAR and save it */ | |
406 | stw r4,_DEAR(r11) | |
407 | addi r3,r1,STACK_FRAME_OVERHEAD | |
dc1c1ca3 | 408 | EXC_XFER_EE(0x600, alignment_exception) |
14cf11af PM |
409 | |
410 | /* 0x0700 - Program Exception */ | |
411 | START_EXCEPTION(0x0700, ProgramCheck) | |
412 | NORMAL_EXCEPTION_PROLOG | |
413 | mfspr r4,SPRN_ESR /* Grab the ESR and save it */ | |
414 | stw r4,_ESR(r11) | |
415 | addi r3,r1,STACK_FRAME_OVERHEAD | |
dc1c1ca3 | 416 | EXC_XFER_STD(0x700, program_check_exception) |
14cf11af | 417 | |
dc1c1ca3 SR |
418 | EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE) |
419 | EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE) | |
420 | EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE) | |
421 | EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
422 | |
423 | /* 0x0C00 - System Call Exception */ | |
424 | START_EXCEPTION(0x0C00, SystemCall) | |
425 | NORMAL_EXCEPTION_PROLOG | |
426 | EXC_XFER_EE_LITE(0xc00, DoSyscall) | |
427 | ||
dc1c1ca3 SR |
428 | EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_EE) |
429 | EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_EE) | |
430 | EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_EE) | |
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431 | |
432 | /* 0x1000 - Programmable Interval Timer (PIT) Exception */ | |
433 | START_EXCEPTION(0x1000, Decrementer) | |
434 | NORMAL_EXCEPTION_PROLOG | |
435 | lis r0,TSR_PIS@h | |
436 | mtspr SPRN_TSR,r0 /* Clear the PIT exception */ | |
437 | addi r3,r1,STACK_FRAME_OVERHEAD | |
438 | EXC_XFER_LITE(0x1000, timer_interrupt) | |
439 | ||
440 | #if 0 | |
441 | /* NOTE: | |
442 | * FIT and WDT handlers are not implemented yet. | |
443 | */ | |
444 | ||
445 | /* 0x1010 - Fixed Interval Timer (FIT) Exception | |
446 | */ | |
dc1c1ca3 | 447 | STND_EXCEPTION(0x1010, FITException, unknown_exception) |
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448 | |
449 | /* 0x1020 - Watchdog Timer (WDT) Exception | |
450 | */ | |
451 | #ifdef CONFIG_BOOKE_WDT | |
452 | CRITICAL_EXCEPTION(0x1020, WDTException, WatchdogException) | |
453 | #else | |
dc1c1ca3 | 454 | CRITICAL_EXCEPTION(0x1020, WDTException, unknown_exception) |
14cf11af PM |
455 | #endif |
456 | #endif | |
457 | ||
458 | /* 0x1100 - Data TLB Miss Exception | |
459 | * As the name implies, translation is not in the MMU, so search the | |
460 | * page tables and fix it. The only purpose of this function is to | |
461 | * load TLB entries from the page table if they exist. | |
462 | */ | |
463 | START_EXCEPTION(0x1100, DTLBMiss) | |
464 | mtspr SPRN_SPRG0, r10 /* Save some working registers */ | |
465 | mtspr SPRN_SPRG1, r11 | |
466 | #ifdef CONFIG_403GCX | |
467 | stw r12, 0(r0) | |
468 | stw r9, 4(r0) | |
469 | mfcr r11 | |
470 | mfspr r12, SPRN_PID | |
471 | stw r11, 8(r0) | |
472 | stw r12, 12(r0) | |
473 | #else | |
474 | mtspr SPRN_SPRG4, r12 | |
475 | mtspr SPRN_SPRG5, r9 | |
476 | mfcr r11 | |
477 | mfspr r12, SPRN_PID | |
478 | mtspr SPRN_SPRG7, r11 | |
479 | mtspr SPRN_SPRG6, r12 | |
480 | #endif | |
481 | mfspr r10, SPRN_DEAR /* Get faulting address */ | |
482 | ||
483 | /* If we are faulting a kernel address, we have to use the | |
484 | * kernel page tables. | |
485 | */ | |
486 | lis r11, TASK_SIZE@h | |
487 | cmplw r10, r11 | |
488 | blt+ 3f | |
489 | lis r11, swapper_pg_dir@h | |
490 | ori r11, r11, swapper_pg_dir@l | |
491 | li r9, 0 | |
492 | mtspr SPRN_PID, r9 /* TLB will have 0 TID */ | |
493 | b 4f | |
494 | ||
495 | /* Get the PGD for the current thread. | |
496 | */ | |
497 | 3: | |
498 | mfspr r11,SPRN_SPRG3 | |
499 | lwz r11,PGDIR(r11) | |
500 | 4: | |
501 | tophys(r11, r11) | |
502 | rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ | |
503 | lwz r12, 0(r11) /* Get L1 entry */ | |
504 | andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */ | |
505 | beq 2f /* Bail if no table */ | |
506 | ||
507 | rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ | |
508 | lwz r11, 0(r12) /* Get Linux PTE */ | |
509 | andi. r9, r11, _PAGE_PRESENT | |
510 | beq 5f | |
511 | ||
512 | ori r11, r11, _PAGE_ACCESSED | |
513 | stw r11, 0(r12) | |
514 | ||
515 | /* Create TLB tag. This is the faulting address plus a static | |
516 | * set of bits. These are size, valid, E, U0. | |
517 | */ | |
518 | li r12, 0x00c0 | |
519 | rlwimi r10, r12, 0, 20, 31 | |
520 | ||
521 | b finish_tlb_load | |
522 | ||
523 | 2: /* Check for possible large-page pmd entry */ | |
524 | rlwinm. r9, r12, 2, 22, 24 | |
525 | beq 5f | |
526 | ||
527 | /* Create TLB tag. This is the faulting address, plus a static | |
528 | * set of bits (valid, E, U0) plus the size from the PMD. | |
529 | */ | |
530 | ori r9, r9, 0x40 | |
531 | rlwimi r10, r9, 0, 20, 31 | |
532 | mr r11, r12 | |
533 | ||
534 | b finish_tlb_load | |
535 | ||
536 | 5: | |
537 | /* The bailout. Restore registers to pre-exception conditions | |
538 | * and call the heavyweights to help us out. | |
539 | */ | |
540 | #ifdef CONFIG_403GCX | |
541 | lwz r12, 12(r0) | |
542 | lwz r11, 8(r0) | |
543 | mtspr SPRN_PID, r12 | |
544 | mtcr r11 | |
545 | lwz r9, 4(r0) | |
546 | lwz r12, 0(r0) | |
547 | #else | |
548 | mfspr r12, SPRN_SPRG6 | |
549 | mfspr r11, SPRN_SPRG7 | |
550 | mtspr SPRN_PID, r12 | |
551 | mtcr r11 | |
552 | mfspr r9, SPRN_SPRG5 | |
553 | mfspr r12, SPRN_SPRG4 | |
554 | #endif | |
555 | mfspr r11, SPRN_SPRG1 | |
556 | mfspr r10, SPRN_SPRG0 | |
557 | b DataAccess | |
558 | ||
559 | /* 0x1200 - Instruction TLB Miss Exception | |
560 | * Nearly the same as above, except we get our information from different | |
561 | * registers and bailout to a different point. | |
562 | */ | |
563 | START_EXCEPTION(0x1200, ITLBMiss) | |
564 | mtspr SPRN_SPRG0, r10 /* Save some working registers */ | |
565 | mtspr SPRN_SPRG1, r11 | |
566 | #ifdef CONFIG_403GCX | |
567 | stw r12, 0(r0) | |
568 | stw r9, 4(r0) | |
569 | mfcr r11 | |
570 | mfspr r12, SPRN_PID | |
571 | stw r11, 8(r0) | |
572 | stw r12, 12(r0) | |
573 | #else | |
574 | mtspr SPRN_SPRG4, r12 | |
575 | mtspr SPRN_SPRG5, r9 | |
576 | mfcr r11 | |
577 | mfspr r12, SPRN_PID | |
578 | mtspr SPRN_SPRG7, r11 | |
579 | mtspr SPRN_SPRG6, r12 | |
580 | #endif | |
581 | mfspr r10, SPRN_SRR0 /* Get faulting address */ | |
582 | ||
583 | /* If we are faulting a kernel address, we have to use the | |
584 | * kernel page tables. | |
585 | */ | |
586 | lis r11, TASK_SIZE@h | |
587 | cmplw r10, r11 | |
588 | blt+ 3f | |
589 | lis r11, swapper_pg_dir@h | |
590 | ori r11, r11, swapper_pg_dir@l | |
591 | li r9, 0 | |
592 | mtspr SPRN_PID, r9 /* TLB will have 0 TID */ | |
593 | b 4f | |
594 | ||
595 | /* Get the PGD for the current thread. | |
596 | */ | |
597 | 3: | |
598 | mfspr r11,SPRN_SPRG3 | |
599 | lwz r11,PGDIR(r11) | |
600 | 4: | |
601 | tophys(r11, r11) | |
602 | rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ | |
603 | lwz r12, 0(r11) /* Get L1 entry */ | |
604 | andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */ | |
605 | beq 2f /* Bail if no table */ | |
606 | ||
607 | rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ | |
608 | lwz r11, 0(r12) /* Get Linux PTE */ | |
609 | andi. r9, r11, _PAGE_PRESENT | |
610 | beq 5f | |
611 | ||
612 | ori r11, r11, _PAGE_ACCESSED | |
613 | stw r11, 0(r12) | |
614 | ||
615 | /* Create TLB tag. This is the faulting address plus a static | |
616 | * set of bits. These are size, valid, E, U0. | |
617 | */ | |
618 | li r12, 0x00c0 | |
619 | rlwimi r10, r12, 0, 20, 31 | |
620 | ||
621 | b finish_tlb_load | |
622 | ||
623 | 2: /* Check for possible large-page pmd entry */ | |
624 | rlwinm. r9, r12, 2, 22, 24 | |
625 | beq 5f | |
626 | ||
627 | /* Create TLB tag. This is the faulting address, plus a static | |
628 | * set of bits (valid, E, U0) plus the size from the PMD. | |
629 | */ | |
630 | ori r9, r9, 0x40 | |
631 | rlwimi r10, r9, 0, 20, 31 | |
632 | mr r11, r12 | |
633 | ||
634 | b finish_tlb_load | |
635 | ||
636 | 5: | |
637 | /* The bailout. Restore registers to pre-exception conditions | |
638 | * and call the heavyweights to help us out. | |
639 | */ | |
640 | #ifdef CONFIG_403GCX | |
641 | lwz r12, 12(r0) | |
642 | lwz r11, 8(r0) | |
643 | mtspr SPRN_PID, r12 | |
644 | mtcr r11 | |
645 | lwz r9, 4(r0) | |
646 | lwz r12, 0(r0) | |
647 | #else | |
648 | mfspr r12, SPRN_SPRG6 | |
649 | mfspr r11, SPRN_SPRG7 | |
650 | mtspr SPRN_PID, r12 | |
651 | mtcr r11 | |
652 | mfspr r9, SPRN_SPRG5 | |
653 | mfspr r12, SPRN_SPRG4 | |
654 | #endif | |
655 | mfspr r11, SPRN_SPRG1 | |
656 | mfspr r10, SPRN_SPRG0 | |
657 | b InstructionAccess | |
658 | ||
dc1c1ca3 SR |
659 | EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_EE) |
660 | EXCEPTION(0x1400, Trap_14, unknown_exception, EXC_XFER_EE) | |
661 | EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) | |
662 | EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
663 | #ifdef CONFIG_IBM405_ERR51 |
664 | /* 405GP errata 51 */ | |
665 | START_EXCEPTION(0x1700, Trap_17) | |
666 | b DTLBMiss | |
667 | #else | |
dc1c1ca3 | 668 | EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) |
14cf11af | 669 | #endif |
dc1c1ca3 SR |
670 | EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) |
671 | EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) | |
672 | EXCEPTION(0x1A00, Trap_1A, unknown_exception, EXC_XFER_EE) | |
673 | EXCEPTION(0x1B00, Trap_1B, unknown_exception, EXC_XFER_EE) | |
674 | EXCEPTION(0x1C00, Trap_1C, unknown_exception, EXC_XFER_EE) | |
675 | EXCEPTION(0x1D00, Trap_1D, unknown_exception, EXC_XFER_EE) | |
676 | EXCEPTION(0x1E00, Trap_1E, unknown_exception, EXC_XFER_EE) | |
677 | EXCEPTION(0x1F00, Trap_1F, unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
678 | |
679 | /* Check for a single step debug exception while in an exception | |
680 | * handler before state has been saved. This is to catch the case | |
681 | * where an instruction that we are trying to single step causes | |
682 | * an exception (eg ITLB/DTLB miss) and thus the first instruction of | |
683 | * the exception handler generates a single step debug exception. | |
684 | * | |
685 | * If we get a debug trap on the first instruction of an exception handler, | |
686 | * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is | |
687 | * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). | |
688 | * The exception handler was handling a non-critical interrupt, so it will | |
689 | * save (and later restore) the MSR via SPRN_SRR1, which will still have | |
690 | * the MSR_DE bit set. | |
691 | */ | |
692 | /* 0x2000 - Debug Exception */ | |
693 | START_EXCEPTION(0x2000, DebugTrap) | |
694 | CRITICAL_EXCEPTION_PROLOG | |
695 | ||
696 | /* | |
697 | * If this is a single step or branch-taken exception in an | |
698 | * exception entry sequence, it was probably meant to apply to | |
699 | * the code where the exception occurred (since exception entry | |
700 | * doesn't turn off DE automatically). We simulate the effect | |
701 | * of turning off DE on entry to an exception handler by turning | |
702 | * off DE in the SRR3 value and clearing the debug status. | |
703 | */ | |
704 | mfspr r10,SPRN_DBSR /* check single-step/branch taken */ | |
705 | andis. r10,r10,DBSR_IC@h | |
706 | beq+ 2f | |
707 | ||
708 | andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */ | |
709 | beq 1f /* branch and fix it up */ | |
710 | ||
711 | mfspr r10,SPRN_SRR2 /* Faulting instruction address */ | |
712 | cmplwi r10,0x2100 | |
713 | bgt+ 2f /* address above exception vectors */ | |
714 | ||
715 | /* here it looks like we got an inappropriate debug exception. */ | |
716 | 1: rlwinm r9,r9,0,~MSR_DE /* clear DE in the SRR3 value */ | |
717 | lis r10,DBSR_IC@h /* clear the IC event */ | |
718 | mtspr SPRN_DBSR,r10 | |
719 | /* restore state and get out */ | |
720 | lwz r10,_CCR(r11) | |
721 | lwz r0,GPR0(r11) | |
722 | lwz r1,GPR1(r11) | |
723 | mtcrf 0x80,r10 | |
724 | mtspr SPRN_SRR2,r12 | |
725 | mtspr SPRN_SRR3,r9 | |
726 | lwz r9,GPR9(r11) | |
727 | lwz r12,GPR12(r11) | |
728 | lwz r10,crit_r10@l(0) | |
729 | lwz r11,crit_r11@l(0) | |
730 | PPC405_ERR77_SYNC | |
731 | rfci | |
732 | b . | |
733 | ||
734 | /* continue normal handling for a critical exception... */ | |
735 | 2: mfspr r4,SPRN_DBSR | |
736 | addi r3,r1,STACK_FRAME_OVERHEAD | |
737 | EXC_XFER_TEMPLATE(DebugException, 0x2002, \ | |
738 | (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ | |
739 | NOCOPY, crit_transfer_to_handler, ret_from_crit_exc) | |
740 | ||
741 | /* | |
742 | * The other Data TLB exceptions bail out to this point | |
743 | * if they can't resolve the lightweight TLB fault. | |
744 | */ | |
745 | DataAccess: | |
746 | NORMAL_EXCEPTION_PROLOG | |
747 | mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ | |
748 | stw r5,_ESR(r11) | |
749 | mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ | |
750 | EXC_XFER_EE_LITE(0x300, handle_page_fault) | |
751 | ||
752 | /* Other PowerPC processors, namely those derived from the 6xx-series | |
753 | * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved. | |
754 | * However, for the 4xx-series processors these are neither defined nor | |
755 | * reserved. | |
756 | */ | |
757 | ||
758 | /* Damn, I came up one instruction too many to fit into the | |
759 | * exception space :-). Both the instruction and data TLB | |
760 | * miss get to this point to load the TLB. | |
761 | * r10 - TLB_TAG value | |
762 | * r11 - Linux PTE | |
763 | * r12, r9 - avilable to use | |
764 | * PID - loaded with proper value when we get here | |
765 | * Upon exit, we reload everything and RFI. | |
766 | * Actually, it will fit now, but oh well.....a common place | |
767 | * to load the TLB. | |
768 | */ | |
769 | tlb_4xx_index: | |
770 | .long 0 | |
771 | finish_tlb_load: | |
772 | /* load the next available TLB index. | |
773 | */ | |
774 | lwz r9, tlb_4xx_index@l(0) | |
775 | addi r9, r9, 1 | |
776 | andi. r9, r9, (PPC4XX_TLB_SIZE-1) | |
777 | stw r9, tlb_4xx_index@l(0) | |
778 | ||
779 | 6: | |
780 | /* | |
781 | * Clear out the software-only bits in the PTE to generate the | |
782 | * TLB_DATA value. These are the bottom 2 bits of the RPM, the | |
783 | * top 3 bits of the zone field, and M. | |
784 | */ | |
785 | li r12, 0x0ce2 | |
786 | andc r11, r11, r12 | |
787 | ||
788 | tlbwe r11, r9, TLB_DATA /* Load TLB LO */ | |
789 | tlbwe r10, r9, TLB_TAG /* Load TLB HI */ | |
790 | ||
791 | /* Done...restore registers and get out of here. | |
792 | */ | |
793 | #ifdef CONFIG_403GCX | |
794 | lwz r12, 12(r0) | |
795 | lwz r11, 8(r0) | |
796 | mtspr SPRN_PID, r12 | |
797 | mtcr r11 | |
798 | lwz r9, 4(r0) | |
799 | lwz r12, 0(r0) | |
800 | #else | |
801 | mfspr r12, SPRN_SPRG6 | |
802 | mfspr r11, SPRN_SPRG7 | |
803 | mtspr SPRN_PID, r12 | |
804 | mtcr r11 | |
805 | mfspr r9, SPRN_SPRG5 | |
806 | mfspr r12, SPRN_SPRG4 | |
807 | #endif | |
808 | mfspr r11, SPRN_SPRG1 | |
809 | mfspr r10, SPRN_SPRG0 | |
810 | PPC405_ERR77_SYNC | |
811 | rfi /* Should sync shadow TLBs */ | |
812 | b . /* prevent prefetch past rfi */ | |
813 | ||
814 | /* extern void giveup_fpu(struct task_struct *prev) | |
815 | * | |
816 | * The PowerPC 4xx family of processors do not have an FPU, so this just | |
817 | * returns. | |
818 | */ | |
819 | _GLOBAL(giveup_fpu) | |
820 | blr | |
821 | ||
822 | /* This is where the main kernel code starts. | |
823 | */ | |
824 | start_here: | |
825 | ||
826 | /* ptr to current */ | |
827 | lis r2,init_task@h | |
828 | ori r2,r2,init_task@l | |
829 | ||
830 | /* ptr to phys current thread */ | |
831 | tophys(r4,r2) | |
832 | addi r4,r4,THREAD /* init task's THREAD */ | |
833 | mtspr SPRN_SPRG3,r4 | |
834 | ||
835 | /* stack */ | |
836 | lis r1,init_thread_union@ha | |
837 | addi r1,r1,init_thread_union@l | |
838 | li r0,0 | |
839 | stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) | |
840 | ||
841 | bl early_init /* We have to do this with MMU on */ | |
842 | ||
843 | /* | |
844 | * Decide what sort of machine this is and initialize the MMU. | |
845 | */ | |
846 | mr r3,r31 | |
847 | mr r4,r30 | |
848 | mr r5,r29 | |
849 | mr r6,r28 | |
850 | mr r7,r27 | |
851 | bl machine_init | |
852 | bl MMU_init | |
853 | ||
854 | /* Go back to running unmapped so we can load up new values | |
855 | * and change to using our exception vectors. | |
856 | * On the 4xx, all we have to do is invalidate the TLB to clear | |
857 | * the old 16M byte TLB mappings. | |
858 | */ | |
859 | lis r4,2f@h | |
860 | ori r4,r4,2f@l | |
861 | tophys(r4,r4) | |
862 | lis r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h | |
863 | ori r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l | |
864 | mtspr SPRN_SRR0,r4 | |
865 | mtspr SPRN_SRR1,r3 | |
866 | rfi | |
867 | b . /* prevent prefetch past rfi */ | |
868 | ||
869 | /* Load up the kernel context */ | |
870 | 2: | |
871 | sync /* Flush to memory before changing TLB */ | |
872 | tlbia | |
873 | isync /* Flush shadow TLBs */ | |
874 | ||
875 | /* set up the PTE pointers for the Abatron bdiGDB. | |
876 | */ | |
877 | lis r6, swapper_pg_dir@h | |
878 | ori r6, r6, swapper_pg_dir@l | |
879 | lis r5, abatron_pteptrs@h | |
880 | ori r5, r5, abatron_pteptrs@l | |
881 | stw r5, 0xf0(r0) /* Must match your Abatron config file */ | |
882 | tophys(r5,r5) | |
883 | stw r6, 0(r5) | |
884 | ||
885 | /* Now turn on the MMU for real! */ | |
886 | lis r4,MSR_KERNEL@h | |
887 | ori r4,r4,MSR_KERNEL@l | |
888 | lis r3,start_kernel@h | |
889 | ori r3,r3,start_kernel@l | |
890 | mtspr SPRN_SRR0,r3 | |
891 | mtspr SPRN_SRR1,r4 | |
892 | rfi /* enable MMU and jump to start_kernel */ | |
893 | b . /* prevent prefetch past rfi */ | |
894 | ||
895 | /* Set up the initial MMU state so we can do the first level of | |
896 | * kernel initialization. This maps the first 16 MBytes of memory 1:1 | |
897 | * virtual to physical and more importantly sets the cache mode. | |
898 | */ | |
899 | initial_mmu: | |
900 | tlbia /* Invalidate all TLB entries */ | |
901 | isync | |
902 | ||
903 | /* We should still be executing code at physical address 0x0000xxxx | |
904 | * at this point. However, start_here is at virtual address | |
905 | * 0xC000xxxx. So, set up a TLB mapping to cover this once | |
906 | * translation is enabled. | |
907 | */ | |
908 | ||
909 | lis r3,KERNELBASE@h /* Load the kernel virtual address */ | |
910 | ori r3,r3,KERNELBASE@l | |
911 | tophys(r4,r3) /* Load the kernel physical address */ | |
912 | ||
913 | iccci r0,r3 /* Invalidate the i-cache before use */ | |
914 | ||
915 | /* Load the kernel PID. | |
916 | */ | |
917 | li r0,0 | |
918 | mtspr SPRN_PID,r0 | |
919 | sync | |
920 | ||
921 | /* Configure and load two entries into TLB slots 62 and 63. | |
922 | * In case we are pinning TLBs, these are reserved in by the | |
923 | * other TLB functions. If not reserving, then it doesn't | |
924 | * matter where they are loaded. | |
925 | */ | |
926 | clrrwi r4,r4,10 /* Mask off the real page number */ | |
927 | ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ | |
928 | ||
929 | clrrwi r3,r3,10 /* Mask off the effective page number */ | |
930 | ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M)) | |
931 | ||
932 | li r0,63 /* TLB slot 63 */ | |
933 | ||
934 | tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */ | |
935 | tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */ | |
936 | ||
937 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(SERIAL_DEBUG_IO_BASE) | |
938 | ||
939 | /* Load a TLB entry for the UART, so that ppc4xx_progress() can use | |
940 | * the UARTs nice and early. We use a 4k real==virtual mapping. */ | |
941 | ||
942 | lis r3,SERIAL_DEBUG_IO_BASE@h | |
943 | ori r3,r3,SERIAL_DEBUG_IO_BASE@l | |
944 | mr r4,r3 | |
945 | clrrwi r4,r4,12 | |
946 | ori r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G) | |
947 | ||
948 | clrrwi r3,r3,12 | |
949 | ori r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K)) | |
950 | ||
951 | li r0,0 /* TLB slot 0 */ | |
952 | tlbwe r4,r0,TLB_DATA | |
953 | tlbwe r3,r0,TLB_TAG | |
954 | #endif /* CONFIG_SERIAL_DEBUG_TEXT && SERIAL_DEBUG_IO_BASE */ | |
955 | ||
956 | isync | |
957 | ||
958 | /* Establish the exception vector base | |
959 | */ | |
960 | lis r4,KERNELBASE@h /* EVPR only uses the high 16-bits */ | |
961 | tophys(r0,r4) /* Use the physical address */ | |
962 | mtspr SPRN_EVPR,r0 | |
963 | ||
964 | blr | |
965 | ||
966 | _GLOBAL(abort) | |
967 | mfspr r13,SPRN_DBCR0 | |
968 | oris r13,r13,DBCR0_RST_SYSTEM@h | |
969 | mtspr SPRN_DBCR0,r13 | |
970 | ||
971 | _GLOBAL(set_context) | |
972 | ||
973 | #ifdef CONFIG_BDI_SWITCH | |
974 | /* Context switch the PTE pointer for the Abatron BDI2000. | |
975 | * The PGDIR is the second parameter. | |
976 | */ | |
977 | lis r5, KERNELBASE@h | |
978 | lwz r5, 0xf0(r5) | |
979 | stw r4, 0x4(r5) | |
980 | #endif | |
981 | sync | |
982 | mtspr SPRN_PID,r3 | |
983 | isync /* Need an isync to flush shadow */ | |
984 | /* TLBs after changing PID */ | |
985 | blr | |
986 | ||
987 | /* We put a few things here that have to be page-aligned. This stuff | |
988 | * goes at the beginning of the data segment, which is page-aligned. | |
989 | */ | |
990 | .data | |
991 | _GLOBAL(sdata) | |
992 | _GLOBAL(empty_zero_page) | |
993 | .space 4096 | |
994 | _GLOBAL(swapper_pg_dir) | |
995 | .space 4096 | |
996 | ||
997 | ||
998 | /* Stack for handling critical exceptions from kernel mode */ | |
999 | .section .bss | |
1000 | .align 12 | |
1001 | exception_stack_bottom: | |
1002 | .space 4096 | |
1003 | critical_stack_top: | |
1004 | _GLOBAL(exception_stack_top) | |
1005 | ||
1006 | /* This space gets a copy of optional info passed to us by the bootstrap | |
1007 | * which is used to pass parameters into the kernel like root=/dev/sda1, etc. | |
1008 | */ | |
1009 | _GLOBAL(cmd_line) | |
1010 | .space 512 | |
1011 | ||
1012 | /* Room for two PTE pointers, usually the kernel and current user pointers | |
1013 | * to their respective root page table. | |
1014 | */ | |
1015 | abatron_pteptrs: | |
1016 | .space 8 |