projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[POWERPC] Fix device-tree locking vs. interrupts
[linux-block.git] / arch / powerpc / kernel / head_32.S
CommitLineData
14cf11af
PM		 1/*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
14cf11af
PM		 12 *
13 * This file contains the low-level support and setup for the
14 * PowerPC platform, including trap and interrupt dispatch.
15 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License
19 * as published by the Free Software Foundation; either version
20 * 2 of the License, or (at your option) any later version.
21 *
22 */
23
b3b8dc6c 24#include <asm/reg.h>
14cf11af
PM		 25#include <asm/page.h>
26#include <asm/mmu.h>
27#include <asm/pgtable.h>
28#include <asm/cputable.h>
29#include <asm/cache.h>
30#include <asm/thread_info.h>
31#include <asm/ppc_asm.h>
32#include <asm/asm-offsets.h>
33
14cf11af
PM		 34/* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
35#define LOAD_BAT(n, reg, RA, RB) \
36 /* see the comment for clear_bats() -- Cort */ \
37 li RA,0; \
38 mtspr SPRN_IBAT##n##U,RA; \
39 mtspr SPRN_DBAT##n##U,RA; \
40 lwz RA,(n*16)+0(reg); \
41 lwz RB,(n*16)+4(reg); \
42 mtspr SPRN_IBAT##n##U,RA; \
43 mtspr SPRN_IBAT##n##L,RB; \
44 beq 1f; \
45 lwz RA,(n*16)+8(reg); \
46 lwz RB,(n*16)+12(reg); \
47 mtspr SPRN_DBAT##n##U,RA; \
48 mtspr SPRN_DBAT##n##L,RB; \
491:
14cf11af 50
748a7683 51 .section .text.head, "ax"
b3b8dc6c
PM		 52 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
53 .stabs "head_32.S",N_SO,0,0,0f
14cf11af 540:
748a7683 55_ENTRY(_stext);
14cf11af
PM		 56
57/*
58 * _start is defined this way because the XCOFF loader in the OpenFirmware
59 * on the powermac expects the entry point to be a procedure descriptor.
60 */
748a7683 61_ENTRY(_start);
14cf11af
PM		 62 /*
63 * These are here for legacy reasons, the kernel used to
64 * need to look like a coff function entry for the pmac
65 * but we're always started by some kind of bootloader now.
66 * -- Cort
67 */
68 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
69 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
70 nop
71
72/* PMAC
73 * Enter here with the kernel text, data and bss loaded starting at
74 * 0, running with virtual == physical mapping.
75 * r5 points to the prom entry point (the client interface handler
76 * address). Address translation is turned on, with the prom
77 * managing the hash table. Interrupts are disabled. The stack
78 * pointer (r1) points to just below the end of the half-meg region
79 * from 0x380000 - 0x400000, which is mapped in already.
80 *
81 * If we are booted from MacOS via BootX, we enter with the kernel
82 * image loaded somewhere, and the following values in registers:
83 * r3: 'BooX' (0x426f6f58)
84 * r4: virtual address of boot_infos_t
85 * r5: 0
86 *
14cf11af
PM		 87 * PREP
88 * This is jumped to on prep systems right after the kernel is relocated
89 * to its proper place in memory by the boot loader. The expected layout
90 * of the regs is:
91 * r3: ptr to residual data
92 * r4: initrd_start or if no initrd then 0
93 * r5: initrd_end - unused if r4 is 0
94 * r6: Start of command line string
95 * r7: End of command line string
96 *
97 * This just gets a minimal mmu environment setup so we can call
98 * start_here() to do the real work.
99 * -- Cort
100 */
101
102 .globl __start
103__start:
104/*
105 * We have to do any OF calls before we map ourselves to KERNELBASE,
106 * because OF may have I/O devices mapped into that area
107 * (particularly on CHRP).
108 */
0a498d96 109#ifdef CONFIG_PPC_MULTIPLATFORM
9b6b563c
PM		 110 cmpwi 0,r5,0
111 beq 1f
112 bl prom_init
113 trap
0a498d96 114#endif
9b6b563c 115
d7f39454
BH		 116/*
117 * Check for BootX signature when supporting PowerMac and branch to
118 * appropriate trampoline if it's present
119 */
120#ifdef CONFIG_PPC_PMAC
1211: lis r31,0x426f
122 ori r31,r31,0x6f58
123 cmpw 0,r3,r31
124 bne 1f
125 bl bootx_init
126 trap
127#endif /* CONFIG_PPC_PMAC */
128
9b6b563c 1291: mr r31,r3 /* save parameters */
14cf11af 130 mr r30,r4
14cf11af
PM		 131 li r24,0 /* cpu # */
132
133/*
134 * early_init() does the early machine identification and does
135 * the necessary low-level setup and clears the BSS
136 * -- Cort <cort@fsmlabs.com>
137 */
138 bl early_init
139
14cf11af
PM		 140/* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
141 * the physical address we are running at, returned by early_init()
142 */
143 bl mmu_off
144__after_mmu_off:
14cf11af
PM		 145 bl clear_bats
146 bl flush_tlbs
147
148 bl initial_bats
f21f49ea 149#if defined(CONFIG_BOOTX_TEXT)
51d3082f
BH		 150 bl setup_disp_bat
151#endif
c374e00e
SW		 152#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
153 bl setup_cpm_bat
154#endif
14cf11af
PM		 155
156/*
157 * Call setup_cpu for CPU 0 and initialize 6xx Idle
158 */
159 bl reloc_offset
160 li r24,0 /* cpu# */
161 bl call_setup_cpu /* Call setup_cpu for this CPU */
162#ifdef CONFIG_6xx
163 bl reloc_offset
164 bl init_idle_6xx
165#endif /* CONFIG_6xx */
14cf11af
PM		 166
167
14cf11af
PM		 168/*
169 * We need to run with _start at physical address 0.
170 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
171 * the exception vectors at 0 (and therefore this copy
172 * overwrites OF's exception vectors with our own).
9b6b563c 173 * The MMU is off at this point.
14cf11af
PM		 174 */
175 bl reloc_offset
176 mr r26,r3
177 addis r4,r3,KERNELBASE@h /* current address of _start */
178 cmpwi 0,r4,0 /* are we already running at 0? */
179 bne relocate_kernel
14cf11af
PM		 180/*
181 * we now have the 1st 16M of ram mapped with the bats.
182 * prep needs the mmu to be turned on here, but pmac already has it on.
183 * this shouldn't bother the pmac since it just gets turned on again
184 * as we jump to our code at KERNELBASE. -- Cort
185 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
186 * off, and in other cases, we now turn it off before changing BATs above.
187 */
188turn_on_mmu:
189 mfmsr r0
190 ori r0,r0,MSR_DR|MSR_IR
191 mtspr SPRN_SRR1,r0
192 lis r0,start_here@h
193 ori r0,r0,start_here@l
194 mtspr SPRN_SRR0,r0
195 SYNC
196 RFI /* enables MMU */
197
198/*
199 * We need __secondary_hold as a place to hold the other cpus on
200 * an SMP machine, even when we are running a UP kernel.
201 */
202 . = 0xc0 /* for prep bootloader */
203 li r3,1 /* MTX only has 1 cpu */
204 .globl __secondary_hold
205__secondary_hold:
206 /* tell the master we're here */
bbd0abda 207 stw r3,__secondary_hold_acknowledge@l(0)
14cf11af
PM		 208#ifdef CONFIG_SMP
209100: lwz r4,0(0)
210 /* wait until we're told to start */
211 cmpw 0,r4,r3
212 bne 100b
213 /* our cpu # was at addr 0 - go */
214 mr r24,r3 /* cpu # */
215 b __secondary_start
216#else
217 b .
218#endif /* CONFIG_SMP */
219
bbd0abda
PM		 220 .globl __secondary_hold_spinloop
221__secondary_hold_spinloop:
222 .long 0
223 .globl __secondary_hold_acknowledge
224__secondary_hold_acknowledge:
225 .long -1
226
14cf11af
PM		 227/*
228 * Exception entry code. This code runs with address translation
229 * turned off, i.e. using physical addresses.
230 * We assume sprg3 has the physical address of the current
231 * task's thread_struct.
232 */
233#define EXCEPTION_PROLOG \
234 mtspr SPRN_SPRG0,r10; \
235 mtspr SPRN_SPRG1,r11; \
236 mfcr r10; \
237 EXCEPTION_PROLOG_1; \
238 EXCEPTION_PROLOG_2
239
240#define EXCEPTION_PROLOG_1 \
241 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
242 andi. r11,r11,MSR_PR; \
243 tophys(r11,r1); /* use tophys(r1) if kernel */ \
244 beq 1f; \
245 mfspr r11,SPRN_SPRG3; \
246 lwz r11,THREAD_INFO-THREAD(r11); \
247 addi r11,r11,THREAD_SIZE; \
248 tophys(r11,r11); \
2491: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
250
251
252#define EXCEPTION_PROLOG_2 \
253 CLR_TOP32(r11); \
254 stw r10,_CCR(r11); /* save registers */ \
255 stw r12,GPR12(r11); \
256 stw r9,GPR9(r11); \
257 mfspr r10,SPRN_SPRG0; \
258 stw r10,GPR10(r11); \
259 mfspr r12,SPRN_SPRG1; \
260 stw r12,GPR11(r11); \
261 mflr r10; \
262 stw r10,_LINK(r11); \
263 mfspr r12,SPRN_SRR0; \
264 mfspr r9,SPRN_SRR1; \
265 stw r1,GPR1(r11); \
266 stw r1,0(r11); \
267 tovirt(r1,r11); /* set new kernel sp */ \
268 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
269 MTMSRD(r10); /* (except for mach check in rtas) */ \
270 stw r0,GPR0(r11); \
f78541dc
PM		 271 lis r10,0x7265; /* put exception frame marker */ \
272 addi r10,r10,0x6773; \
273 stw r10,8(r11); \
14cf11af
PM		 274 SAVE_4GPRS(3, r11); \
275 SAVE_2GPRS(7, r11)
276
277/*
278 * Note: code which follows this uses cr0.eq (set if from kernel),
279 * r11, r12 (SRR0), and r9 (SRR1).
280 *
281 * Note2: once we have set r1 we are in a position to take exceptions
282 * again, and we could thus set MSR:RI at that point.
283 */
284
285/*
286 * Exception vectors.
287 */
288#define EXCEPTION(n, label, hdlr, xfer) \
289 . = n; \
290label: \
291 EXCEPTION_PROLOG; \
292 addi r3,r1,STACK_FRAME_OVERHEAD; \
293 xfer(n, hdlr)
294
295#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
296 li r10,trap; \
d73e0c99 297 stw r10,_TRAP(r11); \
14cf11af
PM		 298 li r10,MSR_KERNEL; \
299 copyee(r10, r9); \
300 bl tfer; \
301i##n: \
302 .long hdlr; \
303 .long ret
304
305#define COPY_EE(d, s) rlwimi d,s,0,16,16
306#define NOCOPY(d, s)
307
308#define EXC_XFER_STD(n, hdlr) \
309 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
310 ret_from_except_full)
311
312#define EXC_XFER_LITE(n, hdlr) \
313 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
314 ret_from_except)
315
316#define EXC_XFER_EE(n, hdlr) \
317 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
318 ret_from_except_full)
319
320#define EXC_XFER_EE_LITE(n, hdlr) \
321 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
322 ret_from_except)
323
324/* System reset */
325/* core99 pmac starts the seconary here by changing the vector, and
dc1c1ca3 326 putting it back to what it was (unknown_exception) when done. */
dc1c1ca3 327 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
14cf11af
PM		 328
329/* Machine check */
330/*
331 * On CHRP, this is complicated by the fact that we could get a
332 * machine check inside RTAS, and we have no guarantee that certain
333 * critical registers will have the values we expect. The set of
334 * registers that might have bad values includes all the GPRs
335 * and all the BATs. We indicate that we are in RTAS by putting
336 * a non-zero value, the address of the exception frame to use,
337 * in SPRG2. The machine check handler checks SPRG2 and uses its
338 * value if it is non-zero. If we ever needed to free up SPRG2,
339 * we could use a field in the thread_info or thread_struct instead.
340 * (Other exception handlers assume that r1 is a valid kernel stack
341 * pointer when we take an exception from supervisor mode.)
342 * -- paulus.
343 */
344 . = 0x200
345 mtspr SPRN_SPRG0,r10
346 mtspr SPRN_SPRG1,r11
347 mfcr r10
348#ifdef CONFIG_PPC_CHRP
349 mfspr r11,SPRN_SPRG2
350 cmpwi 0,r11,0
351 bne 7f
352#endif /* CONFIG_PPC_CHRP */
353 EXCEPTION_PROLOG_1
3547: EXCEPTION_PROLOG_2
355 addi r3,r1,STACK_FRAME_OVERHEAD
356#ifdef CONFIG_PPC_CHRP
357 mfspr r4,SPRN_SPRG2
358 cmpwi cr1,r4,0
359 bne cr1,1f
360#endif
dc1c1ca3 361 EXC_XFER_STD(0x200, machine_check_exception)
14cf11af
PM		 362#ifdef CONFIG_PPC_CHRP
3631: b machine_check_in_rtas
364#endif
365
366/* Data access exception. */
367 . = 0x300
14cf11af
PM		 368DataAccess:
369 EXCEPTION_PROLOG
14cf11af
PM		 370 mfspr r10,SPRN_DSISR
371 andis. r0,r10,0xa470 /* weird error? */
372 bne 1f /* if not, try to put a PTE */
373 mfspr r4,SPRN_DAR /* into the hash table */
374 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
375 bl hash_page
3761: stw r10,_DSISR(r11)
377 mr r5,r10
378 mfspr r4,SPRN_DAR
379 EXC_XFER_EE_LITE(0x300, handle_page_fault)
380
14cf11af
PM		 381
382/* Instruction access exception. */
383 . = 0x400
14cf11af
PM		 384InstructionAccess:
385 EXCEPTION_PROLOG
14cf11af
PM		 386 andis. r0,r9,0x4000 /* no pte found? */
387 beq 1f /* if so, try to put a PTE */
388 li r3,0 /* into the hash table */
389 mr r4,r12 /* SRR0 is fault address */
390 bl hash_page
3911: mr r4,r12
392 mr r5,r9
393 EXC_XFER_EE_LITE(0x400, handle_page_fault)
394
14cf11af
PM		 395/* External interrupt */
396 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
397
398/* Alignment exception */
399 . = 0x600
400Alignment:
401 EXCEPTION_PROLOG
402 mfspr r4,SPRN_DAR
403 stw r4,_DAR(r11)
404 mfspr r5,SPRN_DSISR
405 stw r5,_DSISR(r11)
406 addi r3,r1,STACK_FRAME_OVERHEAD
dc1c1ca3 407 EXC_XFER_EE(0x600, alignment_exception)
14cf11af
PM		 408
409/* Program check exception */
dc1c1ca3 410 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
14cf11af
PM		 411
412/* Floating-point unavailable */
413 . = 0x800
414FPUnavailable:
aa42c69c
KP		 415BEGIN_FTR_SECTION
416/*
417 * Certain Freescale cores don't have a FPU and treat fp instructions
418 * as a FP Unavailable exception. Redirect to illegal/emulation handling.
419 */
420 b ProgramCheck
421END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
14cf11af
PM		 422 EXCEPTION_PROLOG
423 bne load_up_fpu /* if from user, just load it up */
424 addi r3,r1,STACK_FRAME_OVERHEAD
8dad3f92 425 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
14cf11af
PM		 426
427/* Decrementer */
428 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
429
dc1c1ca3
SR		 430 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
431 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
14cf11af
PM		 432
433/* System call */
434 . = 0xc00
435SystemCall:
436 EXCEPTION_PROLOG
437 EXC_XFER_EE_LITE(0xc00, DoSyscall)
438
439/* Single step - not used on 601 */
dc1c1ca3
SR		 440 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
441 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
14cf11af
PM		 442
443/*
444 * The Altivec unavailable trap is at 0x0f20. Foo.
445 * We effectively remap it to 0x3000.
446 * We include an altivec unavailable exception vector even if
447 * not configured for Altivec, so that you can't panic a
448 * non-altivec kernel running on a machine with altivec just
449 * by executing an altivec instruction.
450 */
451 . = 0xf00
555d97ac 452 b PerformanceMonitor
14cf11af
PM		 453
454 . = 0xf20
455 b AltiVecUnavailable
456
14cf11af
PM		 457/*
458 * Handle TLB miss for instruction on 603/603e.
459 * Note: we get an alternate set of r0 - r3 to use automatically.
460 */
461 . = 0x1000
462InstructionTLBMiss:
463/*
464 * r0: stored ctr
465 * r1: linux style pte ( later becomes ppc hardware pte )
466 * r2: ptr to linux-style pte
467 * r3: scratch
468 */
469 mfctr r0
470 /* Get PTE (linux-style) and check access */
471 mfspr r3,SPRN_IMISS
8a13c4f9
KG		 472 lis r1,PAGE_OFFSET@h /* check if kernel address */
473 cmplw 0,r1,r3
14cf11af
PM		 474 mfspr r2,SPRN_SPRG3
475 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
476 lwz r2,PGDIR(r2)
8a13c4f9 477 bge- 112f
bde6c6e1
SW		 478 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
479 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
14cf11af
PM		 480 lis r2,swapper_pg_dir@ha /* if kernel address, use */
481 addi r2,r2,swapper_pg_dir@l /* kernel page table */
14cf11af
PM		 482112: tophys(r2,r2)
483 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
484 lwz r2,0(r2) /* get pmd entry */
485 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
486 beq- InstructionAddressInvalid /* return if no mapping */
487 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
488 lwz r3,0(r2) /* get linux-style pte */
489 andc. r1,r1,r3 /* check access & ~permission */
490 bne- InstructionAddressInvalid /* return if access not permitted */
491 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
492 /*
493 * NOTE! We are assuming this is not an SMP system, otherwise
494 * we would need to update the pte atomically with lwarx/stwcx.
495 */
496 stw r3,0(r2) /* update PTE (accessed bit) */
497 /* Convert linux-style PTE to low word of PPC-style PTE */
498 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
499 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
500 and r1,r1,r2 /* writable if _RW and _DIRTY */
501 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
502 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
503 ori r1,r1,0xe14 /* clear out reserved bits and M */
504 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
505 mtspr SPRN_RPA,r1
506 mfspr r3,SPRN_IMISS
507 tlbli r3
508 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
509 mtcrf 0x80,r3
510 rfi
511InstructionAddressInvalid:
512 mfspr r3,SPRN_SRR1
513 rlwinm r1,r3,9,6,6 /* Get load/store bit */
514
515 addis r1,r1,0x2000
516 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
517 mtctr r0 /* Restore CTR */
518 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
519 or r2,r2,r1
520 mtspr SPRN_SRR1,r2
521 mfspr r1,SPRN_IMISS /* Get failing address */
522 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
523 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
524 xor r1,r1,r2
525 mtspr SPRN_DAR,r1 /* Set fault address */
526 mfmsr r0 /* Restore "normal" registers */
527 xoris r0,r0,MSR_TGPR>>16
528 mtcrf 0x80,r3 /* Restore CR0 */
529 mtmsr r0
530 b InstructionAccess
531
532/*
533 * Handle TLB miss for DATA Load operation on 603/603e
534 */
535 . = 0x1100
536DataLoadTLBMiss:
537/*
538 * r0: stored ctr
539 * r1: linux style pte ( later becomes ppc hardware pte )
540 * r2: ptr to linux-style pte
541 * r3: scratch
542 */
543 mfctr r0
544 /* Get PTE (linux-style) and check access */
545 mfspr r3,SPRN_DMISS
8a13c4f9
KG		 546 lis r1,PAGE_OFFSET@h /* check if kernel address */
547 cmplw 0,r1,r3
14cf11af
PM		 548 mfspr r2,SPRN_SPRG3
549 li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
550 lwz r2,PGDIR(r2)
8a13c4f9 551 bge- 112f
bde6c6e1
SW		 552 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
553 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
14cf11af
PM		 554 lis r2,swapper_pg_dir@ha /* if kernel address, use */
555 addi r2,r2,swapper_pg_dir@l /* kernel page table */
14cf11af
PM		 556112: tophys(r2,r2)
557 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
558 lwz r2,0(r2) /* get pmd entry */
559 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
560 beq- DataAddressInvalid /* return if no mapping */
561 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
562 lwz r3,0(r2) /* get linux-style pte */
563 andc. r1,r1,r3 /* check access & ~permission */
564 bne- DataAddressInvalid /* return if access not permitted */
565 ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */
566 /*
567 * NOTE! We are assuming this is not an SMP system, otherwise
568 * we would need to update the pte atomically with lwarx/stwcx.
569 */
570 stw r3,0(r2) /* update PTE (accessed bit) */
571 /* Convert linux-style PTE to low word of PPC-style PTE */
572 rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */
573 rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
574 and r1,r1,r2 /* writable if _RW and _DIRTY */
575 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
576 rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */
577 ori r1,r1,0xe14 /* clear out reserved bits and M */
578 andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */
579 mtspr SPRN_RPA,r1
580 mfspr r3,SPRN_DMISS
581 tlbld r3
582 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
583 mtcrf 0x80,r3
584 rfi
585DataAddressInvalid:
586 mfspr r3,SPRN_SRR1
587 rlwinm r1,r3,9,6,6 /* Get load/store bit */
588 addis r1,r1,0x2000
589 mtspr SPRN_DSISR,r1
590 mtctr r0 /* Restore CTR */
591 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
592 mtspr SPRN_SRR1,r2
593 mfspr r1,SPRN_DMISS /* Get failing address */
594 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
595 beq 20f /* Jump if big endian */
596 xori r1,r1,3
59720: mtspr SPRN_DAR,r1 /* Set fault address */
598 mfmsr r0 /* Restore "normal" registers */
599 xoris r0,r0,MSR_TGPR>>16
600 mtcrf 0x80,r3 /* Restore CR0 */
601 mtmsr r0
602 b DataAccess
603
604/*
605 * Handle TLB miss for DATA Store on 603/603e
606 */
607 . = 0x1200
608DataStoreTLBMiss:
609/*
610 * r0: stored ctr
611 * r1: linux style pte ( later becomes ppc hardware pte )
612 * r2: ptr to linux-style pte
613 * r3: scratch
614 */
615 mfctr r0
616 /* Get PTE (linux-style) and check access */
617 mfspr r3,SPRN_DMISS
8a13c4f9
KG		 618 lis r1,PAGE_OFFSET@h /* check if kernel address */
619 cmplw 0,r1,r3
14cf11af
PM		 620 mfspr r2,SPRN_SPRG3
621 li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
622 lwz r2,PGDIR(r2)
8a13c4f9 623 bge- 112f
bde6c6e1
SW		 624 mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */
625 rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */
14cf11af
PM		 626 lis r2,swapper_pg_dir@ha /* if kernel address, use */
627 addi r2,r2,swapper_pg_dir@l /* kernel page table */
14cf11af
PM		 628112: tophys(r2,r2)
629 rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
630 lwz r2,0(r2) /* get pmd entry */
631 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
632 beq- DataAddressInvalid /* return if no mapping */
633 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
634 lwz r3,0(r2) /* get linux-style pte */
635 andc. r1,r1,r3 /* check access & ~permission */
636 bne- DataAddressInvalid /* return if access not permitted */
637 ori r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY
638 /*
639 * NOTE! We are assuming this is not an SMP system, otherwise
640 * we would need to update the pte atomically with lwarx/stwcx.
641 */
642 stw r3,0(r2) /* update PTE (accessed/dirty bits) */
643 /* Convert linux-style PTE to low word of PPC-style PTE */
644 rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */
645 li r1,0xe15 /* clear out reserved bits and M */
646 andc r1,r3,r1 /* PP = user? 2: 0 */
647 mtspr SPRN_RPA,r1
648 mfspr r3,SPRN_DMISS
649 tlbld r3
650 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
651 mtcrf 0x80,r3
652 rfi
653
654#ifndef CONFIG_ALTIVEC
dc1c1ca3 655#define altivec_assist_exception unknown_exception
14cf11af
PM		 656#endif
657
dc1c1ca3 658 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE)
14cf11af 659 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
dc1c1ca3 660 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
dc1c1ca3 661 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE)
14cf11af 662 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
dc1c1ca3 663 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
dc1c1ca3
SR		 664 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
665 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
666 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
667 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
668 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
669 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
670 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
14cf11af 671 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
dc1c1ca3
SR		 672 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE)
673 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE)
674 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE)
675 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE)
676 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE)
677 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE)
678 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE)
679 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE)
680 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE)
681 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE)
682 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE)
683 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE)
684 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE)
685 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE)
686 EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE)
14cf11af
PM		 687
688 .globl mol_trampoline
689 .set mol_trampoline, i0x2f00
690
691 . = 0x3000
692
693AltiVecUnavailable:
694 EXCEPTION_PROLOG
695#ifdef CONFIG_ALTIVEC
696 bne load_up_altivec /* if from user, just load it up */
697#endif /* CONFIG_ALTIVEC */
f1434a48 698 addi r3,r1,STACK_FRAME_OVERHEAD
dc1c1ca3 699 EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
14cf11af 700
555d97ac
AF		 701PerformanceMonitor:
702 EXCEPTION_PROLOG
703 addi r3,r1,STACK_FRAME_OVERHEAD
704 EXC_XFER_STD(0xf00, performance_monitor_exception)
705
14cf11af
PM		 706#ifdef CONFIG_ALTIVEC
707/* Note that the AltiVec support is closely modeled after the FP
708 * support. Changes to one are likely to be applicable to the
709 * other! */
710load_up_altivec:
711/*
712 * Disable AltiVec for the task which had AltiVec previously,
713 * and save its AltiVec registers in its thread_struct.
714 * Enables AltiVec for use in the kernel on return.
715 * On SMP we know the AltiVec units are free, since we give it up every
716 * switch. -- Kumar
717 */
718 mfmsr r5
719 oris r5,r5,MSR_VEC@h
720 MTMSRD(r5) /* enable use of AltiVec now */
721 isync
722/*
723 * For SMP, we don't do lazy AltiVec switching because it just gets too
724 * horrendously complex, especially when a task switches from one CPU
725 * to another. Instead we call giveup_altivec in switch_to.
726 */
727#ifndef CONFIG_SMP
728 tophys(r6,0)
729 addis r3,r6,last_task_used_altivec@ha
730 lwz r4,last_task_used_altivec@l(r3)
731 cmpwi 0,r4,0
732 beq 1f
733 add r4,r4,r6
734 addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */
735 SAVE_32VRS(0,r10,r4)
736 mfvscr vr0
737 li r10,THREAD_VSCR
738 stvx vr0,r10,r4
739 lwz r5,PT_REGS(r4)
740 add r5,r5,r6
741 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
742 lis r10,MSR_VEC@h
743 andc r4,r4,r10 /* disable altivec for previous task */
744 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
7451:
746#endif /* CONFIG_SMP */
747 /* enable use of AltiVec after return */
748 oris r9,r9,MSR_VEC@h
749 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
750 li r4,1
751 li r10,THREAD_VSCR
752 stw r4,THREAD_USED_VR(r5)
753 lvx vr0,r10,r5
754 mtvscr vr0
755 REST_32VRS(0,r10,r5)
756#ifndef CONFIG_SMP
757 subi r4,r5,THREAD
758 sub r4,r4,r6
759 stw r4,last_task_used_altivec@l(r3)
760#endif /* CONFIG_SMP */
761 /* restore registers and return */
762 /* we haven't used ctr or xer or lr */
763 b fast_exception_return
764
14cf11af
PM		 765/*
766 * giveup_altivec(tsk)
767 * Disable AltiVec for the task given as the argument,
768 * and save the AltiVec registers in its thread_struct.
769 * Enables AltiVec for use in the kernel on return.
770 */
771
772 .globl giveup_altivec
773giveup_altivec:
774 mfmsr r5
775 oris r5,r5,MSR_VEC@h
776 SYNC
777 MTMSRD(r5) /* enable use of AltiVec now */
778 isync
779 cmpwi 0,r3,0
780 beqlr- /* if no previous owner, done */
781 addi r3,r3,THREAD /* want THREAD of task */
782 lwz r5,PT_REGS(r3)
783 cmpwi 0,r5,0
784 SAVE_32VRS(0, r4, r3)
785 mfvscr vr0
786 li r4,THREAD_VSCR
787 stvx vr0,r4,r3
788 beq 1f
789 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
790 lis r3,MSR_VEC@h
791 andc r4,r4,r3 /* disable AltiVec for previous task */
792 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
7931:
794#ifndef CONFIG_SMP
795 li r5,0
796 lis r4,last_task_used_altivec@ha
797 stw r5,last_task_used_altivec@l(r4)
798#endif /* CONFIG_SMP */
799 blr
800#endif /* CONFIG_ALTIVEC */
801
802/*
803 * This code is jumped to from the startup code to copy
804 * the kernel image to physical address 0.
805 */
806relocate_kernel:
807 addis r9,r26,klimit@ha /* fetch klimit */
808 lwz r25,klimit@l(r9)
809 addis r25,r25,-KERNELBASE@h
810 li r3,0 /* Destination base address */
811 li r6,0 /* Destination offset */
812 li r5,0x4000 /* # bytes of memory to copy */
813 bl copy_and_flush /* copy the first 0x4000 bytes */
814 addi r0,r3,4f@l /* jump to the address of 4f */
815 mtctr r0 /* in copy and do the rest. */
816 bctr /* jump to the copy */
8174: mr r5,r25
818 bl copy_and_flush /* copy the rest */
819 b turn_on_mmu
820
821/*
822 * Copy routine used to copy the kernel to start at physical address 0
823 * and flush and invalidate the caches as needed.
824 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
825 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
826 */
748a7683 827_ENTRY(copy_and_flush)
14cf11af
PM		 828 addi r5,r5,-4
829 addi r6,r6,-4
7dffb720 8304: li r0,L1_CACHE_BYTES/4
14cf11af
PM		 831 mtctr r0
8323: addi r6,r6,4 /* copy a cache line */
833 lwzx r0,r6,r4
834 stwx r0,r6,r3
835 bdnz 3b
836 dcbst r6,r3 /* write it to memory */
837 sync
838 icbi r6,r3 /* flush the icache line */
839 cmplw 0,r6,r5
840 blt 4b
841 sync /* additional sync needed on g4 */
842 isync
843 addi r5,r5,4
844 addi r6,r6,4
845 blr
846
14cf11af
PM		 847#ifdef CONFIG_SMP
848#ifdef CONFIG_GEMINI
849 .globl __secondary_start_gemini
850__secondary_start_gemini:
851 mfspr r4,SPRN_HID0
852 ori r4,r4,HID0_ICFI
853 li r3,0
854 ori r3,r3,HID0_ICE
855 andc r4,r4,r3
856 mtspr SPRN_HID0,r4
857 sync
858 b __secondary_start
859#endif /* CONFIG_GEMINI */
860
ee0339f2
JL		 861 .globl __secondary_start_mpc86xx
862__secondary_start_mpc86xx:
863 mfspr r3, SPRN_PIR
864 stw r3, __secondary_hold_acknowledge@l(0)
865 mr r24, r3 /* cpu # */
866 b __secondary_start
867
14cf11af
PM		 868 .globl __secondary_start_pmac_0
869__secondary_start_pmac_0:
870 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
871 li r24,0
872 b 1f
873 li r24,1
874 b 1f
875 li r24,2
876 b 1f
877 li r24,3
8781:
879 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
880 set to map the 0xf0000000 - 0xffffffff region */
881 mfmsr r0
882 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
883 SYNC
884 mtmsr r0
885 isync
886
887 .globl __secondary_start
888__secondary_start:
14cf11af
PM		 889 /* Copy some CPU settings from CPU 0 */
890 bl __restore_cpu_setup
891
892 lis r3,-KERNELBASE@h
893 mr r4,r24
14cf11af
PM		 894 bl call_setup_cpu /* Call setup_cpu for this CPU */
895#ifdef CONFIG_6xx
896 lis r3,-KERNELBASE@h
897 bl init_idle_6xx
898#endif /* CONFIG_6xx */
14cf11af
PM		 899
900 /* get current_thread_info and current */
901 lis r1,secondary_ti@ha
902 tophys(r1,r1)
903 lwz r1,secondary_ti@l(r1)
904 tophys(r2,r1)
905 lwz r2,TI_TASK(r2)
906
907 /* stack */
908 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
909 li r0,0
910 tophys(r3,r1)
911 stw r0,0(r3)
912
913 /* load up the MMU */
914 bl load_up_mmu
915
916 /* ptr to phys current thread */
917 tophys(r4,r2)
918 addi r4,r4,THREAD /* phys address of our thread_struct */
919 CLR_TOP32(r4)
920 mtspr SPRN_SPRG3,r4
921 li r3,0
922 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
923
924 /* enable MMU and jump to start_secondary */
925 li r4,MSR_KERNEL
926 FIX_SRR1(r4,r5)
927 lis r3,start_secondary@h
928 ori r3,r3,start_secondary@l
929 mtspr SPRN_SRR0,r3
930 mtspr SPRN_SRR1,r4
931 SYNC
932 RFI
933#endif /* CONFIG_SMP */
934
935/*
936 * Those generic dummy functions are kept for CPUs not
937 * included in CONFIG_6xx
938 */
187a0067 939#if !defined(CONFIG_6xx)
748a7683 940_ENTRY(__save_cpu_setup)
14cf11af 941 blr
748a7683 942_ENTRY(__restore_cpu_setup)
14cf11af 943 blr
187a0067 944#endif /* !defined(CONFIG_6xx) */
14cf11af
PM		 945
946
947/*
948 * Load stuff into the MMU. Intended to be called with
949 * IR=0 and DR=0.
950 */
951load_up_mmu:
952 sync /* Force all PTE updates to finish */
953 isync
954 tlbia /* Clear all TLB entries */
955 sync /* wait for tlbia/tlbie to finish */
956 TLBSYNC /* ... on all CPUs */
957 /* Load the SDR1 register (hash table base & size) */
958 lis r6,_SDR1@ha
959 tophys(r6,r6)
960 lwz r6,_SDR1@l(r6)
961 mtspr SPRN_SDR1,r6
14cf11af
PM		 962 li r0,16 /* load up segment register values */
963 mtctr r0 /* for context 0 */
964 lis r3,0x2000 /* Ku = 1, VSID = 0 */
965 li r4,0
9663: mtsrin r3,r4
967 addi r3,r3,0x111 /* increment VSID */
968 addis r4,r4,0x1000 /* address of next segment */
969 bdnz 3b
187a0067 970
14cf11af
PM		 971/* Load the BAT registers with the values set up by MMU_init.
972 MMU_init takes care of whether we're on a 601 or not. */
973 mfpvr r3
974 srwi r3,r3,16
975 cmpwi r3,1
976 lis r3,BATS@ha
977 addi r3,r3,BATS@l
978 tophys(r3,r3)
979 LOAD_BAT(0,r3,r4,r5)
980 LOAD_BAT(1,r3,r4,r5)
981 LOAD_BAT(2,r3,r4,r5)
982 LOAD_BAT(3,r3,r4,r5)
ee0339f2
JL		 983BEGIN_FTR_SECTION
984 LOAD_BAT(4,r3,r4,r5)
985 LOAD_BAT(5,r3,r4,r5)
986 LOAD_BAT(6,r3,r4,r5)
987 LOAD_BAT(7,r3,r4,r5)
988END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
14cf11af
PM		 989 blr
990
991/*
992 * This is where the main kernel code starts.
993 */
994start_here:
995 /* ptr to current */
996 lis r2,init_task@h
997 ori r2,r2,init_task@l
998 /* Set up for using our exception vectors */
999 /* ptr to phys current thread */
1000 tophys(r4,r2)
1001 addi r4,r4,THREAD /* init task's THREAD */
1002 CLR_TOP32(r4)
1003 mtspr SPRN_SPRG3,r4
1004 li r3,0
1005 mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */
1006
1007 /* stack */
1008 lis r1,init_thread_union@ha
1009 addi r1,r1,init_thread_union@l
1010 li r0,0
1011 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
1012/*
187a0067 1013 * Do early platform-specific initialization,
14cf11af
PM		 1014 * and set up the MMU.
1015 */
1016 mr r3,r31
1017 mr r4,r30
14cf11af 1018 bl machine_init
22c841c9 1019 bl __save_cpu_setup
14cf11af
PM		 1020 bl MMU_init
1021
14cf11af
PM		 1022/*
1023 * Go back to running unmapped so we can load up new values
1024 * for SDR1 (hash table pointer) and the segment registers
1025 * and change to using our exception vectors.
1026 */
1027 lis r4,2f@h
1028 ori r4,r4,2f@l
1029 tophys(r4,r4)
1030 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1031 FIX_SRR1(r3,r5)
1032 mtspr SPRN_SRR0,r4
1033 mtspr SPRN_SRR1,r3
1034 SYNC
1035 RFI
1036/* Load up the kernel context */
10372: bl load_up_mmu
1038
1039#ifdef CONFIG_BDI_SWITCH
1040 /* Add helper information for the Abatron bdiGDB debugger.
1041 * We do this here because we know the mmu is disabled, and
1042 * will be enabled for real in just a few instructions.
1043 */
1044 lis r5, abatron_pteptrs@h
1045 ori r5, r5, abatron_pteptrs@l
1046 stw r5, 0xf0(r0) /* This much match your Abatron config */
1047 lis r6, swapper_pg_dir@h
1048 ori r6, r6, swapper_pg_dir@l
1049 tophys(r5, r5)
1050 stw r6, 0(r5)
1051#endif /* CONFIG_BDI_SWITCH */
1052
1053/* Now turn on the MMU for real! */
1054 li r4,MSR_KERNEL
1055 FIX_SRR1(r4,r5)
1056 lis r3,start_kernel@h
1057 ori r3,r3,start_kernel@l
1058 mtspr SPRN_SRR0,r3
1059 mtspr SPRN_SRR1,r4
1060 SYNC
1061 RFI
1062
1063/*
1064 * Set up the segment registers for a new context.
1065 */
748a7683 1066_ENTRY(set_context)
14cf11af
PM		 1067 mulli r3,r3,897 /* multiply context by skew factor */
1068 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1069 addis r3,r3,0x6000 /* Set Ks, Ku bits */
1070 li r0,NUM_USER_SEGMENTS
1071 mtctr r0
1072
1073#ifdef CONFIG_BDI_SWITCH
1074 /* Context switch the PTE pointer for the Abatron BDI2000.
1075 * The PGDIR is passed as second argument.
1076 */
1077 lis r5, KERNELBASE@h
1078 lwz r5, 0xf0(r5)
1079 stw r4, 0x4(r5)
1080#endif
1081 li r4,0
1082 isync
10833:
14cf11af
PM		 1084 mtsrin r3,r4
1085 addi r3,r3,0x111 /* next VSID */
1086 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1087 addis r4,r4,0x1000 /* address of next segment */
1088 bdnz 3b
1089 sync
1090 isync
1091 blr
1092
1093/*
1094 * An undocumented "feature" of 604e requires that the v bit
1095 * be cleared before changing BAT values.
1096 *
1097 * Also, newer IBM firmware does not clear bat3 and 4 so
1098 * this makes sure it's done.
1099 * -- Cort
1100 */
1101clear_bats:
1102 li r10,0
1103 mfspr r9,SPRN_PVR
1104 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1105 cmpwi r9, 1
1106 beq 1f
1107
1108 mtspr SPRN_DBAT0U,r10
1109 mtspr SPRN_DBAT0L,r10
1110 mtspr SPRN_DBAT1U,r10
1111 mtspr SPRN_DBAT1L,r10
1112 mtspr SPRN_DBAT2U,r10
1113 mtspr SPRN_DBAT2L,r10
1114 mtspr SPRN_DBAT3U,r10
1115 mtspr SPRN_DBAT3L,r10
11161:
1117 mtspr SPRN_IBAT0U,r10
1118 mtspr SPRN_IBAT0L,r10
1119 mtspr SPRN_IBAT1U,r10
1120 mtspr SPRN_IBAT1L,r10
1121 mtspr SPRN_IBAT2U,r10
1122 mtspr SPRN_IBAT2L,r10
1123 mtspr SPRN_IBAT3U,r10
1124 mtspr SPRN_IBAT3L,r10
1125BEGIN_FTR_SECTION
1126 /* Here's a tweak: at this point, CPU setup have
1127 * not been called yet, so HIGH_BAT_EN may not be
1128 * set in HID0 for the 745x processors. However, it
1129 * seems that doesn't affect our ability to actually
1130 * write to these SPRs.
1131 */
1132 mtspr SPRN_DBAT4U,r10
1133 mtspr SPRN_DBAT4L,r10
1134 mtspr SPRN_DBAT5U,r10
1135 mtspr SPRN_DBAT5L,r10
1136 mtspr SPRN_DBAT6U,r10
1137 mtspr SPRN_DBAT6L,r10
1138 mtspr SPRN_DBAT7U,r10
1139 mtspr SPRN_DBAT7L,r10
1140 mtspr SPRN_IBAT4U,r10
1141 mtspr SPRN_IBAT4L,r10
1142 mtspr SPRN_IBAT5U,r10
1143 mtspr SPRN_IBAT5L,r10
1144 mtspr SPRN_IBAT6U,r10
1145 mtspr SPRN_IBAT6L,r10
1146 mtspr SPRN_IBAT7U,r10
1147 mtspr SPRN_IBAT7L,r10
1148END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
1149 blr
1150
1151flush_tlbs:
1152 lis r10, 0x40
11531: addic. r10, r10, -0x1000
1154 tlbie r10
1155 blt 1b
1156 sync
1157 blr
1158
1159mmu_off:
1160 addi r4, r3, __after_mmu_off - _start
1161 mfmsr r3
1162 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1163 beqlr
1164 andc r3,r3,r0
1165 mtspr SPRN_SRR0,r4
1166 mtspr SPRN_SRR1,r3
1167 sync
1168 RFI
1169
14cf11af
PM		 1170/*
1171 * Use the first pair of BAT registers to map the 1st 16MB
1172 * of RAM to KERNELBASE. From this point on we can't safely
1173 * call OF any more.
1174 */
1175initial_bats:
1176 lis r11,KERNELBASE@h
14cf11af
PM		 1177 mfspr r9,SPRN_PVR
1178 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1179 cmpwi 0,r9,1
1180 bne 4f
1181 ori r11,r11,4 /* set up BAT registers for 601 */
1182 li r8,0x7f /* valid, block length = 8MB */
1183 oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */
1184 oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */
1185 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1186 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
1187 mtspr SPRN_IBAT1U,r9
1188 mtspr SPRN_IBAT1L,r10
1189 isync
1190 blr
14cf11af
PM		 1191
11924: tophys(r8,r11)
1193#ifdef CONFIG_SMP
1194 ori r8,r8,0x12 /* R/W access, M=1 */
1195#else
1196 ori r8,r8,2 /* R/W access */
1197#endif /* CONFIG_SMP */
14cf11af 1198 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
14cf11af 1199
14cf11af
PM		 1200 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1201 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1202 mtspr SPRN_IBAT0L,r8
1203 mtspr SPRN_IBAT0U,r11
1204 isync
1205 blr
1206
14cf11af 1207
f21f49ea 1208#ifdef CONFIG_BOOTX_TEXT
51d3082f
BH		 1209setup_disp_bat:
1210 /*
1211 * setup the display bat prepared for us in prom.c
1212 */
1213 mflr r8
1214 bl reloc_offset
1215 mtlr r8
1216 addis r8,r3,disp_BAT@ha
1217 addi r8,r8,disp_BAT@l
1218 cmpwi cr0,r8,0
1219 beqlr
1220 lwz r11,0(r8)
1221 lwz r8,4(r8)
1222 mfspr r9,SPRN_PVR
1223 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1224 cmpwi 0,r9,1
1225 beq 1f
1226 mtspr SPRN_DBAT3L,r8
1227 mtspr SPRN_DBAT3U,r11
1228 blr
12291: mtspr SPRN_IBAT3L,r8
1230 mtspr SPRN_IBAT3U,r11
1231 blr
f21f49ea 1232#endif /* CONFIG_BOOTX_TEXT */
51d3082f 1233
c374e00e
SW		 1234#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1235setup_cpm_bat:
1236 lis r8, 0xf000
1237 ori r8, r8, 0x002a
1238 mtspr SPRN_DBAT1L, r8
1239
1240 lis r11, 0xf000
1241 ori r11, r11, (BL_1M << 2) | 2
1242 mtspr SPRN_DBAT1U, r11
1243
1244 blr
1245#endif
1246
14cf11af
PM		 1247#ifdef CONFIG_8260
1248/* Jump into the system reset for the rom.
1249 * We first disable the MMU, and then jump to the ROM reset address.
1250 *
1251 * r3 is the board info structure, r4 is the location for starting.
1252 * I use this for building a small kernel that can load other kernels,
1253 * rather than trying to write or rely on a rom monitor that can tftp load.
1254 */
1255 .globl m8260_gorom
1256m8260_gorom:
1257 mfmsr r0
1258 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1259 sync
1260 mtmsr r0
1261 sync
1262 mfspr r11, SPRN_HID0
1263 lis r10, 0
1264 ori r10,r10,HID0_ICE|HID0_DCE
1265 andc r11, r11, r10
1266 mtspr SPRN_HID0, r11
1267 isync
1268 li r5, MSR_ME|MSR_RI
1269 lis r6,2f@h
1270 addis r6,r6,-KERNELBASE@h
1271 ori r6,r6,2f@l
1272 mtspr SPRN_SRR0,r6
1273 mtspr SPRN_SRR1,r5
1274 isync
1275 sync
1276 rfi
12772:
1278 mtlr r4
1279 blr
1280#endif
1281
1282
1283/*
1284 * We put a few things here that have to be page-aligned.
1285 * This stuff goes at the beginning of the data segment,
1286 * which is page-aligned.
1287 */
1288 .data
1289 .globl sdata
1290sdata:
1291 .globl empty_zero_page
1292empty_zero_page:
1293 .space 4096
1294
1295 .globl swapper_pg_dir
1296swapper_pg_dir:
bee86f14 1297 .space PGD_TABLE_SIZE
14cf11af 1298
14cf11af
PM		 1299 .globl intercept_table
1300intercept_table:
1301 .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700
1302 .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0
1303 .long 0, 0, 0, i0x1300, 0, 0, 0, 0
1304 .long 0, 0, 0, 0, 0, 0, 0, 0
1305 .long 0, 0, 0, 0, 0, 0, 0, 0
1306 .long 0, 0, 0, 0, 0, 0, 0, 0
1307
1308/* Room for two PTE pointers, usually the kernel and current user pointers
1309 * to their respective root page table.
1310 */
1311abatron_pteptrs:
1312 .space 8
Linux 6.x block layer and io_uring tree(s)