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14cf11af PM |
1 | /* |
2 | * PowerPC version | |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
6 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
7 | * Adapted for Power Macintosh by Paul Mackerras. | |
8 | * Low-level exception handlers and MMU support | |
9 | * rewritten by Paul Mackerras. | |
10 | * Copyright (C) 1996 Paul Mackerras. | |
11 | * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). | |
14cf11af PM |
12 | * |
13 | * This file contains the low-level support and setup for the | |
14 | * PowerPC platform, including trap and interrupt dispatch. | |
15 | * (The PPC 8xx embedded CPUs use head_8xx.S instead.) | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or | |
18 | * modify it under the terms of the GNU General Public License | |
19 | * as published by the Free Software Foundation; either version | |
20 | * 2 of the License, or (at your option) any later version. | |
21 | * | |
22 | */ | |
23 | ||
e7039845 | 24 | #include <linux/init.h> |
b3b8dc6c | 25 | #include <asm/reg.h> |
14cf11af PM |
26 | #include <asm/page.h> |
27 | #include <asm/mmu.h> | |
28 | #include <asm/pgtable.h> | |
29 | #include <asm/cputable.h> | |
30 | #include <asm/cache.h> | |
31 | #include <asm/thread_info.h> | |
32 | #include <asm/ppc_asm.h> | |
33 | #include <asm/asm-offsets.h> | |
ec2b36b9 | 34 | #include <asm/ptrace.h> |
5e696617 | 35 | #include <asm/bug.h> |
14cf11af | 36 | |
14cf11af PM |
37 | /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */ |
38 | #define LOAD_BAT(n, reg, RA, RB) \ | |
39 | /* see the comment for clear_bats() -- Cort */ \ | |
40 | li RA,0; \ | |
41 | mtspr SPRN_IBAT##n##U,RA; \ | |
42 | mtspr SPRN_DBAT##n##U,RA; \ | |
43 | lwz RA,(n*16)+0(reg); \ | |
44 | lwz RB,(n*16)+4(reg); \ | |
45 | mtspr SPRN_IBAT##n##U,RA; \ | |
46 | mtspr SPRN_IBAT##n##L,RB; \ | |
47 | beq 1f; \ | |
48 | lwz RA,(n*16)+8(reg); \ | |
49 | lwz RB,(n*16)+12(reg); \ | |
50 | mtspr SPRN_DBAT##n##U,RA; \ | |
51 | mtspr SPRN_DBAT##n##L,RB; \ | |
52 | 1: | |
14cf11af | 53 | |
e7039845 | 54 | __HEAD |
b3b8dc6c PM |
55 | .stabs "arch/powerpc/kernel/",N_SO,0,0,0f |
56 | .stabs "head_32.S",N_SO,0,0,0f | |
14cf11af | 57 | 0: |
748a7683 | 58 | _ENTRY(_stext); |
14cf11af PM |
59 | |
60 | /* | |
61 | * _start is defined this way because the XCOFF loader in the OpenFirmware | |
62 | * on the powermac expects the entry point to be a procedure descriptor. | |
63 | */ | |
748a7683 | 64 | _ENTRY(_start); |
14cf11af PM |
65 | /* |
66 | * These are here for legacy reasons, the kernel used to | |
67 | * need to look like a coff function entry for the pmac | |
68 | * but we're always started by some kind of bootloader now. | |
69 | * -- Cort | |
70 | */ | |
71 | nop /* used by __secondary_hold on prep (mtx) and chrp smp */ | |
72 | nop /* used by __secondary_hold on prep (mtx) and chrp smp */ | |
73 | nop | |
74 | ||
75 | /* PMAC | |
76 | * Enter here with the kernel text, data and bss loaded starting at | |
77 | * 0, running with virtual == physical mapping. | |
78 | * r5 points to the prom entry point (the client interface handler | |
79 | * address). Address translation is turned on, with the prom | |
80 | * managing the hash table. Interrupts are disabled. The stack | |
81 | * pointer (r1) points to just below the end of the half-meg region | |
82 | * from 0x380000 - 0x400000, which is mapped in already. | |
83 | * | |
84 | * If we are booted from MacOS via BootX, we enter with the kernel | |
85 | * image loaded somewhere, and the following values in registers: | |
86 | * r3: 'BooX' (0x426f6f58) | |
87 | * r4: virtual address of boot_infos_t | |
88 | * r5: 0 | |
89 | * | |
14cf11af PM |
90 | * PREP |
91 | * This is jumped to on prep systems right after the kernel is relocated | |
92 | * to its proper place in memory by the boot loader. The expected layout | |
93 | * of the regs is: | |
94 | * r3: ptr to residual data | |
95 | * r4: initrd_start or if no initrd then 0 | |
96 | * r5: initrd_end - unused if r4 is 0 | |
97 | * r6: Start of command line string | |
98 | * r7: End of command line string | |
99 | * | |
100 | * This just gets a minimal mmu environment setup so we can call | |
101 | * start_here() to do the real work. | |
102 | * -- Cort | |
103 | */ | |
104 | ||
105 | .globl __start | |
106 | __start: | |
107 | /* | |
108 | * We have to do any OF calls before we map ourselves to KERNELBASE, | |
109 | * because OF may have I/O devices mapped into that area | |
110 | * (particularly on CHRP). | |
111 | */ | |
9b6b563c PM |
112 | cmpwi 0,r5,0 |
113 | beq 1f | |
2bda347b | 114 | |
28794d34 | 115 | #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE |
2bda347b BH |
116 | /* find out where we are now */ |
117 | bcl 20,31,$+4 | |
118 | 0: mflr r8 /* r8 = runtime addr here */ | |
119 | addis r8,r8,(_stext - 0b)@ha | |
120 | addi r8,r8,(_stext - 0b)@l /* current runtime base addr */ | |
9b6b563c | 121 | bl prom_init |
28794d34 BH |
122 | #endif /* CONFIG_PPC_OF_BOOT_TRAMPOLINE */ |
123 | ||
124 | /* We never return. We also hit that trap if trying to boot | |
125 | * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ | |
9b6b563c PM |
126 | trap |
127 | ||
d7f39454 BH |
128 | /* |
129 | * Check for BootX signature when supporting PowerMac and branch to | |
130 | * appropriate trampoline if it's present | |
131 | */ | |
132 | #ifdef CONFIG_PPC_PMAC | |
133 | 1: lis r31,0x426f | |
134 | ori r31,r31,0x6f58 | |
135 | cmpw 0,r3,r31 | |
136 | bne 1f | |
137 | bl bootx_init | |
138 | trap | |
139 | #endif /* CONFIG_PPC_PMAC */ | |
140 | ||
9b6b563c | 141 | 1: mr r31,r3 /* save parameters */ |
14cf11af | 142 | mr r30,r4 |
14cf11af PM |
143 | li r24,0 /* cpu # */ |
144 | ||
145 | /* | |
146 | * early_init() does the early machine identification and does | |
147 | * the necessary low-level setup and clears the BSS | |
148 | * -- Cort <cort@fsmlabs.com> | |
149 | */ | |
150 | bl early_init | |
151 | ||
14cf11af PM |
152 | /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains |
153 | * the physical address we are running at, returned by early_init() | |
154 | */ | |
155 | bl mmu_off | |
156 | __after_mmu_off: | |
14cf11af PM |
157 | bl clear_bats |
158 | bl flush_tlbs | |
159 | ||
160 | bl initial_bats | |
f21f49ea | 161 | #if defined(CONFIG_BOOTX_TEXT) |
51d3082f BH |
162 | bl setup_disp_bat |
163 | #endif | |
c374e00e SW |
164 | #ifdef CONFIG_PPC_EARLY_DEBUG_CPM |
165 | bl setup_cpm_bat | |
166 | #endif | |
14cf11af PM |
167 | |
168 | /* | |
169 | * Call setup_cpu for CPU 0 and initialize 6xx Idle | |
170 | */ | |
171 | bl reloc_offset | |
172 | li r24,0 /* cpu# */ | |
173 | bl call_setup_cpu /* Call setup_cpu for this CPU */ | |
174 | #ifdef CONFIG_6xx | |
175 | bl reloc_offset | |
176 | bl init_idle_6xx | |
177 | #endif /* CONFIG_6xx */ | |
14cf11af PM |
178 | |
179 | ||
14cf11af PM |
180 | /* |
181 | * We need to run with _start at physical address 0. | |
182 | * On CHRP, we are loaded at 0x10000 since OF on CHRP uses | |
183 | * the exception vectors at 0 (and therefore this copy | |
184 | * overwrites OF's exception vectors with our own). | |
9b6b563c | 185 | * The MMU is off at this point. |
14cf11af PM |
186 | */ |
187 | bl reloc_offset | |
188 | mr r26,r3 | |
189 | addis r4,r3,KERNELBASE@h /* current address of _start */ | |
ccdcef72 DF |
190 | lis r5,PHYSICAL_START@h |
191 | cmplw 0,r4,r5 /* already running at PHYSICAL_START? */ | |
14cf11af | 192 | bne relocate_kernel |
14cf11af PM |
193 | /* |
194 | * we now have the 1st 16M of ram mapped with the bats. | |
195 | * prep needs the mmu to be turned on here, but pmac already has it on. | |
196 | * this shouldn't bother the pmac since it just gets turned on again | |
197 | * as we jump to our code at KERNELBASE. -- Cort | |
198 | * Actually no, pmac doesn't have it on any more. BootX enters with MMU | |
199 | * off, and in other cases, we now turn it off before changing BATs above. | |
200 | */ | |
201 | turn_on_mmu: | |
202 | mfmsr r0 | |
203 | ori r0,r0,MSR_DR|MSR_IR | |
204 | mtspr SPRN_SRR1,r0 | |
205 | lis r0,start_here@h | |
206 | ori r0,r0,start_here@l | |
207 | mtspr SPRN_SRR0,r0 | |
208 | SYNC | |
209 | RFI /* enables MMU */ | |
210 | ||
211 | /* | |
212 | * We need __secondary_hold as a place to hold the other cpus on | |
213 | * an SMP machine, even when we are running a UP kernel. | |
214 | */ | |
215 | . = 0xc0 /* for prep bootloader */ | |
216 | li r3,1 /* MTX only has 1 cpu */ | |
217 | .globl __secondary_hold | |
218 | __secondary_hold: | |
219 | /* tell the master we're here */ | |
bbd0abda | 220 | stw r3,__secondary_hold_acknowledge@l(0) |
14cf11af PM |
221 | #ifdef CONFIG_SMP |
222 | 100: lwz r4,0(0) | |
223 | /* wait until we're told to start */ | |
224 | cmpw 0,r4,r3 | |
225 | bne 100b | |
226 | /* our cpu # was at addr 0 - go */ | |
227 | mr r24,r3 /* cpu # */ | |
228 | b __secondary_start | |
229 | #else | |
230 | b . | |
231 | #endif /* CONFIG_SMP */ | |
232 | ||
bbd0abda PM |
233 | .globl __secondary_hold_spinloop |
234 | __secondary_hold_spinloop: | |
235 | .long 0 | |
236 | .globl __secondary_hold_acknowledge | |
237 | __secondary_hold_acknowledge: | |
238 | .long -1 | |
239 | ||
14cf11af PM |
240 | /* |
241 | * Exception entry code. This code runs with address translation | |
242 | * turned off, i.e. using physical addresses. | |
243 | * We assume sprg3 has the physical address of the current | |
244 | * task's thread_struct. | |
245 | */ | |
246 | #define EXCEPTION_PROLOG \ | |
ee43eb78 BH |
247 | mtspr SPRN_SPRG_SCRATCH0,r10; \ |
248 | mtspr SPRN_SPRG_SCRATCH1,r11; \ | |
14cf11af PM |
249 | mfcr r10; \ |
250 | EXCEPTION_PROLOG_1; \ | |
251 | EXCEPTION_PROLOG_2 | |
252 | ||
253 | #define EXCEPTION_PROLOG_1 \ | |
254 | mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ | |
255 | andi. r11,r11,MSR_PR; \ | |
256 | tophys(r11,r1); /* use tophys(r1) if kernel */ \ | |
257 | beq 1f; \ | |
ee43eb78 | 258 | mfspr r11,SPRN_SPRG_THREAD; \ |
14cf11af PM |
259 | lwz r11,THREAD_INFO-THREAD(r11); \ |
260 | addi r11,r11,THREAD_SIZE; \ | |
261 | tophys(r11,r11); \ | |
262 | 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ | |
263 | ||
264 | ||
265 | #define EXCEPTION_PROLOG_2 \ | |
266 | CLR_TOP32(r11); \ | |
267 | stw r10,_CCR(r11); /* save registers */ \ | |
268 | stw r12,GPR12(r11); \ | |
269 | stw r9,GPR9(r11); \ | |
ee43eb78 | 270 | mfspr r10,SPRN_SPRG_SCRATCH0; \ |
14cf11af | 271 | stw r10,GPR10(r11); \ |
ee43eb78 | 272 | mfspr r12,SPRN_SPRG_SCRATCH1; \ |
14cf11af PM |
273 | stw r12,GPR11(r11); \ |
274 | mflr r10; \ | |
275 | stw r10,_LINK(r11); \ | |
276 | mfspr r12,SPRN_SRR0; \ | |
277 | mfspr r9,SPRN_SRR1; \ | |
278 | stw r1,GPR1(r11); \ | |
279 | stw r1,0(r11); \ | |
280 | tovirt(r1,r11); /* set new kernel sp */ \ | |
281 | li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ | |
282 | MTMSRD(r10); /* (except for mach check in rtas) */ \ | |
283 | stw r0,GPR0(r11); \ | |
ec2b36b9 BH |
284 | lis r10,STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */ \ |
285 | addi r10,r10,STACK_FRAME_REGS_MARKER@l; \ | |
f78541dc | 286 | stw r10,8(r11); \ |
14cf11af PM |
287 | SAVE_4GPRS(3, r11); \ |
288 | SAVE_2GPRS(7, r11) | |
289 | ||
290 | /* | |
291 | * Note: code which follows this uses cr0.eq (set if from kernel), | |
292 | * r11, r12 (SRR0), and r9 (SRR1). | |
293 | * | |
294 | * Note2: once we have set r1 we are in a position to take exceptions | |
295 | * again, and we could thus set MSR:RI at that point. | |
296 | */ | |
297 | ||
298 | /* | |
299 | * Exception vectors. | |
300 | */ | |
301 | #define EXCEPTION(n, label, hdlr, xfer) \ | |
302 | . = n; \ | |
303 | label: \ | |
304 | EXCEPTION_PROLOG; \ | |
305 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | |
306 | xfer(n, hdlr) | |
307 | ||
308 | #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ | |
309 | li r10,trap; \ | |
d73e0c99 | 310 | stw r10,_TRAP(r11); \ |
14cf11af PM |
311 | li r10,MSR_KERNEL; \ |
312 | copyee(r10, r9); \ | |
313 | bl tfer; \ | |
314 | i##n: \ | |
315 | .long hdlr; \ | |
316 | .long ret | |
317 | ||
318 | #define COPY_EE(d, s) rlwimi d,s,0,16,16 | |
319 | #define NOCOPY(d, s) | |
320 | ||
321 | #define EXC_XFER_STD(n, hdlr) \ | |
322 | EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ | |
323 | ret_from_except_full) | |
324 | ||
325 | #define EXC_XFER_LITE(n, hdlr) \ | |
326 | EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ | |
327 | ret_from_except) | |
328 | ||
329 | #define EXC_XFER_EE(n, hdlr) \ | |
330 | EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ | |
331 | ret_from_except_full) | |
332 | ||
333 | #define EXC_XFER_EE_LITE(n, hdlr) \ | |
334 | EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ | |
335 | ret_from_except) | |
336 | ||
337 | /* System reset */ | |
338 | /* core99 pmac starts the seconary here by changing the vector, and | |
dc1c1ca3 | 339 | putting it back to what it was (unknown_exception) when done. */ |
dc1c1ca3 | 340 | EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD) |
14cf11af PM |
341 | |
342 | /* Machine check */ | |
343 | /* | |
344 | * On CHRP, this is complicated by the fact that we could get a | |
345 | * machine check inside RTAS, and we have no guarantee that certain | |
346 | * critical registers will have the values we expect. The set of | |
347 | * registers that might have bad values includes all the GPRs | |
348 | * and all the BATs. We indicate that we are in RTAS by putting | |
349 | * a non-zero value, the address of the exception frame to use, | |
350 | * in SPRG2. The machine check handler checks SPRG2 and uses its | |
351 | * value if it is non-zero. If we ever needed to free up SPRG2, | |
352 | * we could use a field in the thread_info or thread_struct instead. | |
353 | * (Other exception handlers assume that r1 is a valid kernel stack | |
354 | * pointer when we take an exception from supervisor mode.) | |
355 | * -- paulus. | |
356 | */ | |
357 | . = 0x200 | |
ee43eb78 BH |
358 | mtspr SPRN_SPRG_SCRATCH0,r10 |
359 | mtspr SPRN_SPRG_SCRATCH1,r11 | |
14cf11af PM |
360 | mfcr r10 |
361 | #ifdef CONFIG_PPC_CHRP | |
ee43eb78 | 362 | mfspr r11,SPRN_SPRG_RTAS |
14cf11af PM |
363 | cmpwi 0,r11,0 |
364 | bne 7f | |
365 | #endif /* CONFIG_PPC_CHRP */ | |
366 | EXCEPTION_PROLOG_1 | |
367 | 7: EXCEPTION_PROLOG_2 | |
368 | addi r3,r1,STACK_FRAME_OVERHEAD | |
369 | #ifdef CONFIG_PPC_CHRP | |
ee43eb78 | 370 | mfspr r4,SPRN_SPRG_RTAS |
14cf11af PM |
371 | cmpwi cr1,r4,0 |
372 | bne cr1,1f | |
373 | #endif | |
dc1c1ca3 | 374 | EXC_XFER_STD(0x200, machine_check_exception) |
14cf11af PM |
375 | #ifdef CONFIG_PPC_CHRP |
376 | 1: b machine_check_in_rtas | |
377 | #endif | |
378 | ||
379 | /* Data access exception. */ | |
380 | . = 0x300 | |
14cf11af PM |
381 | DataAccess: |
382 | EXCEPTION_PROLOG | |
14cf11af | 383 | mfspr r10,SPRN_DSISR |
4ee7084e | 384 | stw r10,_DSISR(r11) |
14cf11af PM |
385 | andis. r0,r10,0xa470 /* weird error? */ |
386 | bne 1f /* if not, try to put a PTE */ | |
387 | mfspr r4,SPRN_DAR /* into the hash table */ | |
388 | rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */ | |
389 | bl hash_page | |
4ee7084e | 390 | 1: lwz r5,_DSISR(r11) /* get DSISR value */ |
14cf11af PM |
391 | mfspr r4,SPRN_DAR |
392 | EXC_XFER_EE_LITE(0x300, handle_page_fault) | |
393 | ||
14cf11af PM |
394 | |
395 | /* Instruction access exception. */ | |
396 | . = 0x400 | |
14cf11af PM |
397 | InstructionAccess: |
398 | EXCEPTION_PROLOG | |
14cf11af PM |
399 | andis. r0,r9,0x4000 /* no pte found? */ |
400 | beq 1f /* if so, try to put a PTE */ | |
401 | li r3,0 /* into the hash table */ | |
402 | mr r4,r12 /* SRR0 is fault address */ | |
403 | bl hash_page | |
404 | 1: mr r4,r12 | |
405 | mr r5,r9 | |
406 | EXC_XFER_EE_LITE(0x400, handle_page_fault) | |
407 | ||
14cf11af PM |
408 | /* External interrupt */ |
409 | EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) | |
410 | ||
411 | /* Alignment exception */ | |
412 | . = 0x600 | |
413 | Alignment: | |
414 | EXCEPTION_PROLOG | |
415 | mfspr r4,SPRN_DAR | |
416 | stw r4,_DAR(r11) | |
417 | mfspr r5,SPRN_DSISR | |
418 | stw r5,_DSISR(r11) | |
419 | addi r3,r1,STACK_FRAME_OVERHEAD | |
dc1c1ca3 | 420 | EXC_XFER_EE(0x600, alignment_exception) |
14cf11af PM |
421 | |
422 | /* Program check exception */ | |
dc1c1ca3 | 423 | EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) |
14cf11af PM |
424 | |
425 | /* Floating-point unavailable */ | |
426 | . = 0x800 | |
427 | FPUnavailable: | |
aa42c69c KP |
428 | BEGIN_FTR_SECTION |
429 | /* | |
430 | * Certain Freescale cores don't have a FPU and treat fp instructions | |
431 | * as a FP Unavailable exception. Redirect to illegal/emulation handling. | |
432 | */ | |
433 | b ProgramCheck | |
434 | END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE) | |
14cf11af | 435 | EXCEPTION_PROLOG |
6f3d8e69 MN |
436 | beq 1f |
437 | bl load_up_fpu /* if from user, just load it up */ | |
438 | b fast_exception_return | |
439 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
8dad3f92 | 440 | EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) |
14cf11af PM |
441 | |
442 | /* Decrementer */ | |
443 | EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) | |
444 | ||
dc1c1ca3 SR |
445 | EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) |
446 | EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
447 | |
448 | /* System call */ | |
449 | . = 0xc00 | |
450 | SystemCall: | |
451 | EXCEPTION_PROLOG | |
452 | EXC_XFER_EE_LITE(0xc00, DoSyscall) | |
453 | ||
454 | /* Single step - not used on 601 */ | |
dc1c1ca3 SR |
455 | EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) |
456 | EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
457 | |
458 | /* | |
459 | * The Altivec unavailable trap is at 0x0f20. Foo. | |
460 | * We effectively remap it to 0x3000. | |
461 | * We include an altivec unavailable exception vector even if | |
462 | * not configured for Altivec, so that you can't panic a | |
463 | * non-altivec kernel running on a machine with altivec just | |
464 | * by executing an altivec instruction. | |
465 | */ | |
466 | . = 0xf00 | |
555d97ac | 467 | b PerformanceMonitor |
14cf11af PM |
468 | |
469 | . = 0xf20 | |
470 | b AltiVecUnavailable | |
471 | ||
14cf11af PM |
472 | /* |
473 | * Handle TLB miss for instruction on 603/603e. | |
474 | * Note: we get an alternate set of r0 - r3 to use automatically. | |
475 | */ | |
476 | . = 0x1000 | |
477 | InstructionTLBMiss: | |
478 | /* | |
00fcb147 | 479 | * r0: scratch |
14cf11af PM |
480 | * r1: linux style pte ( later becomes ppc hardware pte ) |
481 | * r2: ptr to linux-style pte | |
482 | * r3: scratch | |
483 | */ | |
14cf11af PM |
484 | /* Get PTE (linux-style) and check access */ |
485 | mfspr r3,SPRN_IMISS | |
8a13c4f9 KG |
486 | lis r1,PAGE_OFFSET@h /* check if kernel address */ |
487 | cmplw 0,r1,r3 | |
ee43eb78 | 488 | mfspr r2,SPRN_SPRG_THREAD |
14cf11af PM |
489 | li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */ |
490 | lwz r2,PGDIR(r2) | |
8a13c4f9 | 491 | bge- 112f |
bde6c6e1 SW |
492 | mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ |
493 | rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ | |
14cf11af PM |
494 | lis r2,swapper_pg_dir@ha /* if kernel address, use */ |
495 | addi r2,r2,swapper_pg_dir@l /* kernel page table */ | |
14cf11af PM |
496 | 112: tophys(r2,r2) |
497 | rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ | |
498 | lwz r2,0(r2) /* get pmd entry */ | |
499 | rlwinm. r2,r2,0,0,19 /* extract address of pte page */ | |
500 | beq- InstructionAddressInvalid /* return if no mapping */ | |
501 | rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ | |
eb3436a0 KG |
502 | lwz r0,0(r2) /* get linux-style pte */ |
503 | andc. r1,r1,r0 /* check access & ~permission */ | |
14cf11af | 504 | bne- InstructionAddressInvalid /* return if access not permitted */ |
eb3436a0 | 505 | ori r0,r0,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */ |
14cf11af PM |
506 | /* |
507 | * NOTE! We are assuming this is not an SMP system, otherwise | |
508 | * we would need to update the pte atomically with lwarx/stwcx. | |
509 | */ | |
eb3436a0 | 510 | stw r0,0(r2) /* update PTE (accessed bit) */ |
14cf11af | 511 | /* Convert linux-style PTE to low word of PPC-style PTE */ |
eb3436a0 KG |
512 | rlwinm r1,r0,32-10,31,31 /* _PAGE_RW -> PP lsb */ |
513 | rlwinm r2,r0,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */ | |
14cf11af | 514 | and r1,r1,r2 /* writable if _RW and _DIRTY */ |
eb3436a0 KG |
515 | rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */ |
516 | rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */ | |
a4bd6a93 | 517 | ori r1,r1,0xe04 /* clear out reserved bits */ |
eb3436a0 | 518 | andc r1,r0,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ |
345953cf KG |
519 | BEGIN_FTR_SECTION |
520 | rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */ | |
521 | END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) | |
14cf11af | 522 | mtspr SPRN_RPA,r1 |
14cf11af PM |
523 | tlbli r3 |
524 | mfspr r3,SPRN_SRR1 /* Need to restore CR0 */ | |
525 | mtcrf 0x80,r3 | |
526 | rfi | |
527 | InstructionAddressInvalid: | |
528 | mfspr r3,SPRN_SRR1 | |
529 | rlwinm r1,r3,9,6,6 /* Get load/store bit */ | |
530 | ||
531 | addis r1,r1,0x2000 | |
532 | mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */ | |
14cf11af PM |
533 | andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */ |
534 | or r2,r2,r1 | |
535 | mtspr SPRN_SRR1,r2 | |
536 | mfspr r1,SPRN_IMISS /* Get failing address */ | |
537 | rlwinm. r2,r2,0,31,31 /* Check for little endian access */ | |
538 | rlwimi r2,r2,1,30,30 /* change 1 -> 3 */ | |
539 | xor r1,r1,r2 | |
540 | mtspr SPRN_DAR,r1 /* Set fault address */ | |
541 | mfmsr r0 /* Restore "normal" registers */ | |
542 | xoris r0,r0,MSR_TGPR>>16 | |
543 | mtcrf 0x80,r3 /* Restore CR0 */ | |
544 | mtmsr r0 | |
545 | b InstructionAccess | |
546 | ||
547 | /* | |
548 | * Handle TLB miss for DATA Load operation on 603/603e | |
549 | */ | |
550 | . = 0x1100 | |
551 | DataLoadTLBMiss: | |
552 | /* | |
00fcb147 | 553 | * r0: scratch |
14cf11af PM |
554 | * r1: linux style pte ( later becomes ppc hardware pte ) |
555 | * r2: ptr to linux-style pte | |
556 | * r3: scratch | |
557 | */ | |
14cf11af PM |
558 | /* Get PTE (linux-style) and check access */ |
559 | mfspr r3,SPRN_DMISS | |
8a13c4f9 KG |
560 | lis r1,PAGE_OFFSET@h /* check if kernel address */ |
561 | cmplw 0,r1,r3 | |
ee43eb78 | 562 | mfspr r2,SPRN_SPRG_THREAD |
14cf11af PM |
563 | li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */ |
564 | lwz r2,PGDIR(r2) | |
8a13c4f9 | 565 | bge- 112f |
bde6c6e1 SW |
566 | mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ |
567 | rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ | |
14cf11af PM |
568 | lis r2,swapper_pg_dir@ha /* if kernel address, use */ |
569 | addi r2,r2,swapper_pg_dir@l /* kernel page table */ | |
14cf11af PM |
570 | 112: tophys(r2,r2) |
571 | rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ | |
572 | lwz r2,0(r2) /* get pmd entry */ | |
573 | rlwinm. r2,r2,0,0,19 /* extract address of pte page */ | |
574 | beq- DataAddressInvalid /* return if no mapping */ | |
575 | rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ | |
eb3436a0 KG |
576 | lwz r0,0(r2) /* get linux-style pte */ |
577 | andc. r1,r1,r0 /* check access & ~permission */ | |
14cf11af | 578 | bne- DataAddressInvalid /* return if access not permitted */ |
eb3436a0 | 579 | ori r0,r0,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */ |
14cf11af PM |
580 | /* |
581 | * NOTE! We are assuming this is not an SMP system, otherwise | |
582 | * we would need to update the pte atomically with lwarx/stwcx. | |
583 | */ | |
eb3436a0 | 584 | stw r0,0(r2) /* update PTE (accessed bit) */ |
14cf11af | 585 | /* Convert linux-style PTE to low word of PPC-style PTE */ |
eb3436a0 KG |
586 | rlwinm r1,r0,32-10,31,31 /* _PAGE_RW -> PP lsb */ |
587 | rlwinm r2,r0,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */ | |
14cf11af | 588 | and r1,r1,r2 /* writable if _RW and _DIRTY */ |
eb3436a0 KG |
589 | rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */ |
590 | rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */ | |
a4bd6a93 | 591 | ori r1,r1,0xe04 /* clear out reserved bits */ |
eb3436a0 | 592 | andc r1,r0,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ |
345953cf KG |
593 | BEGIN_FTR_SECTION |
594 | rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */ | |
595 | END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) | |
14cf11af | 596 | mtspr SPRN_RPA,r1 |
2319f123 KG |
597 | mfspr r2,SPRN_SRR1 /* Need to restore CR0 */ |
598 | mtcrf 0x80,r2 | |
599 | BEGIN_MMU_FTR_SECTION | |
600 | li r0,1 | |
ee43eb78 | 601 | mfspr r1,SPRN_SPRG_603_LRU |
2319f123 KG |
602 | rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */ |
603 | slw r0,r0,r2 | |
604 | xor r1,r0,r1 | |
605 | srw r0,r1,r2 | |
ee43eb78 | 606 | mtspr SPRN_SPRG_603_LRU,r1 |
2319f123 KG |
607 | mfspr r2,SPRN_SRR1 |
608 | rlwimi r2,r0,31-14,14,14 | |
609 | mtspr SPRN_SRR1,r2 | |
610 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU) | |
14cf11af | 611 | tlbld r3 |
14cf11af PM |
612 | rfi |
613 | DataAddressInvalid: | |
614 | mfspr r3,SPRN_SRR1 | |
615 | rlwinm r1,r3,9,6,6 /* Get load/store bit */ | |
616 | addis r1,r1,0x2000 | |
617 | mtspr SPRN_DSISR,r1 | |
14cf11af PM |
618 | andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */ |
619 | mtspr SPRN_SRR1,r2 | |
620 | mfspr r1,SPRN_DMISS /* Get failing address */ | |
621 | rlwinm. r2,r2,0,31,31 /* Check for little endian access */ | |
622 | beq 20f /* Jump if big endian */ | |
623 | xori r1,r1,3 | |
624 | 20: mtspr SPRN_DAR,r1 /* Set fault address */ | |
625 | mfmsr r0 /* Restore "normal" registers */ | |
626 | xoris r0,r0,MSR_TGPR>>16 | |
627 | mtcrf 0x80,r3 /* Restore CR0 */ | |
628 | mtmsr r0 | |
629 | b DataAccess | |
630 | ||
631 | /* | |
632 | * Handle TLB miss for DATA Store on 603/603e | |
633 | */ | |
634 | . = 0x1200 | |
635 | DataStoreTLBMiss: | |
636 | /* | |
00fcb147 | 637 | * r0: scratch |
14cf11af PM |
638 | * r1: linux style pte ( later becomes ppc hardware pte ) |
639 | * r2: ptr to linux-style pte | |
640 | * r3: scratch | |
641 | */ | |
14cf11af PM |
642 | /* Get PTE (linux-style) and check access */ |
643 | mfspr r3,SPRN_DMISS | |
8a13c4f9 KG |
644 | lis r1,PAGE_OFFSET@h /* check if kernel address */ |
645 | cmplw 0,r1,r3 | |
ee43eb78 | 646 | mfspr r2,SPRN_SPRG_THREAD |
14cf11af PM |
647 | li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */ |
648 | lwz r2,PGDIR(r2) | |
8a13c4f9 | 649 | bge- 112f |
bde6c6e1 SW |
650 | mfspr r2,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ |
651 | rlwimi r1,r2,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ | |
14cf11af PM |
652 | lis r2,swapper_pg_dir@ha /* if kernel address, use */ |
653 | addi r2,r2,swapper_pg_dir@l /* kernel page table */ | |
14cf11af PM |
654 | 112: tophys(r2,r2) |
655 | rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ | |
656 | lwz r2,0(r2) /* get pmd entry */ | |
657 | rlwinm. r2,r2,0,0,19 /* extract address of pte page */ | |
658 | beq- DataAddressInvalid /* return if no mapping */ | |
659 | rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ | |
eb3436a0 KG |
660 | lwz r0,0(r2) /* get linux-style pte */ |
661 | andc. r1,r1,r0 /* check access & ~permission */ | |
14cf11af | 662 | bne- DataAddressInvalid /* return if access not permitted */ |
eb3436a0 | 663 | ori r0,r0,_PAGE_ACCESSED|_PAGE_DIRTY |
14cf11af PM |
664 | /* |
665 | * NOTE! We are assuming this is not an SMP system, otherwise | |
666 | * we would need to update the pte atomically with lwarx/stwcx. | |
667 | */ | |
eb3436a0 | 668 | stw r0,0(r2) /* update PTE (accessed/dirty bits) */ |
14cf11af | 669 | /* Convert linux-style PTE to low word of PPC-style PTE */ |
eb3436a0 | 670 | rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */ |
a4bd6a93 | 671 | li r1,0xe05 /* clear out reserved bits & PP lsb */ |
eb3436a0 | 672 | andc r1,r0,r1 /* PP = user? 2: 0 */ |
345953cf KG |
673 | BEGIN_FTR_SECTION |
674 | rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */ | |
675 | END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) | |
14cf11af | 676 | mtspr SPRN_RPA,r1 |
2319f123 KG |
677 | mfspr r2,SPRN_SRR1 /* Need to restore CR0 */ |
678 | mtcrf 0x80,r2 | |
679 | BEGIN_MMU_FTR_SECTION | |
680 | li r0,1 | |
ee43eb78 | 681 | mfspr r1,SPRN_SPRG_603_LRU |
2319f123 KG |
682 | rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */ |
683 | slw r0,r0,r2 | |
684 | xor r1,r0,r1 | |
685 | srw r0,r1,r2 | |
ee43eb78 | 686 | mtspr SPRN_SPRG_603_LRU,r1 |
2319f123 KG |
687 | mfspr r2,SPRN_SRR1 |
688 | rlwimi r2,r0,31-14,14,14 | |
689 | mtspr SPRN_SRR1,r2 | |
690 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU) | |
14cf11af | 691 | tlbld r3 |
14cf11af PM |
692 | rfi |
693 | ||
694 | #ifndef CONFIG_ALTIVEC | |
dc1c1ca3 | 695 | #define altivec_assist_exception unknown_exception |
14cf11af PM |
696 | #endif |
697 | ||
dc1c1ca3 | 698 | EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE) |
14cf11af | 699 | EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE) |
dc1c1ca3 | 700 | EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) |
dc1c1ca3 | 701 | EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE) |
14cf11af | 702 | EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD) |
dc1c1ca3 | 703 | EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) |
dc1c1ca3 SR |
704 | EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) |
705 | EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) | |
706 | EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) | |
707 | EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) | |
708 | EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) | |
709 | EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) | |
710 | EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) | |
14cf11af | 711 | EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE) |
dc1c1ca3 SR |
712 | EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE) |
713 | EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE) | |
714 | EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE) | |
715 | EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE) | |
716 | EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE) | |
717 | EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE) | |
718 | EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE) | |
719 | EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE) | |
720 | EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE) | |
721 | EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE) | |
722 | EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE) | |
723 | EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE) | |
724 | EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE) | |
725 | EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE) | |
726 | EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE) | |
14cf11af PM |
727 | |
728 | .globl mol_trampoline | |
729 | .set mol_trampoline, i0x2f00 | |
730 | ||
731 | . = 0x3000 | |
732 | ||
733 | AltiVecUnavailable: | |
734 | EXCEPTION_PROLOG | |
735 | #ifdef CONFIG_ALTIVEC | |
37f9ef55 BH |
736 | beq 1f |
737 | bl load_up_altivec /* if from user, just load it up */ | |
738 | b fast_exception_return | |
14cf11af | 739 | #endif /* CONFIG_ALTIVEC */ |
37f9ef55 | 740 | 1: addi r3,r1,STACK_FRAME_OVERHEAD |
dc1c1ca3 | 741 | EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception) |
14cf11af | 742 | |
555d97ac AF |
743 | PerformanceMonitor: |
744 | EXCEPTION_PROLOG | |
745 | addi r3,r1,STACK_FRAME_OVERHEAD | |
746 | EXC_XFER_STD(0xf00, performance_monitor_exception) | |
747 | ||
14cf11af PM |
748 | |
749 | /* | |
750 | * This code is jumped to from the startup code to copy | |
ccdcef72 | 751 | * the kernel image to physical address PHYSICAL_START. |
14cf11af PM |
752 | */ |
753 | relocate_kernel: | |
754 | addis r9,r26,klimit@ha /* fetch klimit */ | |
755 | lwz r25,klimit@l(r9) | |
756 | addis r25,r25,-KERNELBASE@h | |
ccdcef72 | 757 | lis r3,PHYSICAL_START@h /* Destination base address */ |
14cf11af PM |
758 | li r6,0 /* Destination offset */ |
759 | li r5,0x4000 /* # bytes of memory to copy */ | |
760 | bl copy_and_flush /* copy the first 0x4000 bytes */ | |
761 | addi r0,r3,4f@l /* jump to the address of 4f */ | |
762 | mtctr r0 /* in copy and do the rest. */ | |
763 | bctr /* jump to the copy */ | |
764 | 4: mr r5,r25 | |
765 | bl copy_and_flush /* copy the rest */ | |
766 | b turn_on_mmu | |
767 | ||
768 | /* | |
769 | * Copy routine used to copy the kernel to start at physical address 0 | |
770 | * and flush and invalidate the caches as needed. | |
771 | * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset | |
772 | * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. | |
773 | */ | |
748a7683 | 774 | _ENTRY(copy_and_flush) |
14cf11af PM |
775 | addi r5,r5,-4 |
776 | addi r6,r6,-4 | |
7dffb720 | 777 | 4: li r0,L1_CACHE_BYTES/4 |
14cf11af PM |
778 | mtctr r0 |
779 | 3: addi r6,r6,4 /* copy a cache line */ | |
780 | lwzx r0,r6,r4 | |
781 | stwx r0,r6,r3 | |
782 | bdnz 3b | |
783 | dcbst r6,r3 /* write it to memory */ | |
784 | sync | |
785 | icbi r6,r3 /* flush the icache line */ | |
786 | cmplw 0,r6,r5 | |
787 | blt 4b | |
788 | sync /* additional sync needed on g4 */ | |
789 | isync | |
790 | addi r5,r5,4 | |
791 | addi r6,r6,4 | |
792 | blr | |
793 | ||
14cf11af PM |
794 | #ifdef CONFIG_SMP |
795 | #ifdef CONFIG_GEMINI | |
796 | .globl __secondary_start_gemini | |
797 | __secondary_start_gemini: | |
798 | mfspr r4,SPRN_HID0 | |
799 | ori r4,r4,HID0_ICFI | |
800 | li r3,0 | |
801 | ori r3,r3,HID0_ICE | |
802 | andc r4,r4,r3 | |
803 | mtspr SPRN_HID0,r4 | |
804 | sync | |
805 | b __secondary_start | |
806 | #endif /* CONFIG_GEMINI */ | |
807 | ||
ee0339f2 JL |
808 | .globl __secondary_start_mpc86xx |
809 | __secondary_start_mpc86xx: | |
810 | mfspr r3, SPRN_PIR | |
811 | stw r3, __secondary_hold_acknowledge@l(0) | |
812 | mr r24, r3 /* cpu # */ | |
813 | b __secondary_start | |
814 | ||
14cf11af PM |
815 | .globl __secondary_start_pmac_0 |
816 | __secondary_start_pmac_0: | |
817 | /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ | |
818 | li r24,0 | |
819 | b 1f | |
820 | li r24,1 | |
821 | b 1f | |
822 | li r24,2 | |
823 | b 1f | |
824 | li r24,3 | |
825 | 1: | |
826 | /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0 | |
827 | set to map the 0xf0000000 - 0xffffffff region */ | |
828 | mfmsr r0 | |
829 | rlwinm r0,r0,0,28,26 /* clear DR (0x10) */ | |
830 | SYNC | |
831 | mtmsr r0 | |
832 | isync | |
833 | ||
834 | .globl __secondary_start | |
835 | __secondary_start: | |
14cf11af PM |
836 | /* Copy some CPU settings from CPU 0 */ |
837 | bl __restore_cpu_setup | |
838 | ||
839 | lis r3,-KERNELBASE@h | |
840 | mr r4,r24 | |
14cf11af PM |
841 | bl call_setup_cpu /* Call setup_cpu for this CPU */ |
842 | #ifdef CONFIG_6xx | |
843 | lis r3,-KERNELBASE@h | |
844 | bl init_idle_6xx | |
845 | #endif /* CONFIG_6xx */ | |
14cf11af PM |
846 | |
847 | /* get current_thread_info and current */ | |
848 | lis r1,secondary_ti@ha | |
849 | tophys(r1,r1) | |
850 | lwz r1,secondary_ti@l(r1) | |
851 | tophys(r2,r1) | |
852 | lwz r2,TI_TASK(r2) | |
853 | ||
854 | /* stack */ | |
855 | addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD | |
856 | li r0,0 | |
857 | tophys(r3,r1) | |
858 | stw r0,0(r3) | |
859 | ||
860 | /* load up the MMU */ | |
861 | bl load_up_mmu | |
862 | ||
863 | /* ptr to phys current thread */ | |
864 | tophys(r4,r2) | |
865 | addi r4,r4,THREAD /* phys address of our thread_struct */ | |
866 | CLR_TOP32(r4) | |
ee43eb78 | 867 | mtspr SPRN_SPRG_THREAD,r4 |
14cf11af | 868 | li r3,0 |
ee43eb78 | 869 | mtspr SPRN_SPRG_RTAS,r3 /* 0 => not in RTAS */ |
14cf11af PM |
870 | |
871 | /* enable MMU and jump to start_secondary */ | |
872 | li r4,MSR_KERNEL | |
873 | FIX_SRR1(r4,r5) | |
874 | lis r3,start_secondary@h | |
875 | ori r3,r3,start_secondary@l | |
876 | mtspr SPRN_SRR0,r3 | |
877 | mtspr SPRN_SRR1,r4 | |
878 | SYNC | |
879 | RFI | |
880 | #endif /* CONFIG_SMP */ | |
881 | ||
882 | /* | |
883 | * Those generic dummy functions are kept for CPUs not | |
884 | * included in CONFIG_6xx | |
885 | */ | |
187a0067 | 886 | #if !defined(CONFIG_6xx) |
748a7683 | 887 | _ENTRY(__save_cpu_setup) |
14cf11af | 888 | blr |
748a7683 | 889 | _ENTRY(__restore_cpu_setup) |
14cf11af | 890 | blr |
187a0067 | 891 | #endif /* !defined(CONFIG_6xx) */ |
14cf11af PM |
892 | |
893 | ||
894 | /* | |
895 | * Load stuff into the MMU. Intended to be called with | |
896 | * IR=0 and DR=0. | |
897 | */ | |
898 | load_up_mmu: | |
899 | sync /* Force all PTE updates to finish */ | |
900 | isync | |
901 | tlbia /* Clear all TLB entries */ | |
902 | sync /* wait for tlbia/tlbie to finish */ | |
903 | TLBSYNC /* ... on all CPUs */ | |
904 | /* Load the SDR1 register (hash table base & size) */ | |
905 | lis r6,_SDR1@ha | |
906 | tophys(r6,r6) | |
907 | lwz r6,_SDR1@l(r6) | |
908 | mtspr SPRN_SDR1,r6 | |
14cf11af PM |
909 | li r0,16 /* load up segment register values */ |
910 | mtctr r0 /* for context 0 */ | |
911 | lis r3,0x2000 /* Ku = 1, VSID = 0 */ | |
912 | li r4,0 | |
913 | 3: mtsrin r3,r4 | |
914 | addi r3,r3,0x111 /* increment VSID */ | |
915 | addis r4,r4,0x1000 /* address of next segment */ | |
916 | bdnz 3b | |
187a0067 | 917 | |
14cf11af PM |
918 | /* Load the BAT registers with the values set up by MMU_init. |
919 | MMU_init takes care of whether we're on a 601 or not. */ | |
920 | mfpvr r3 | |
921 | srwi r3,r3,16 | |
922 | cmpwi r3,1 | |
923 | lis r3,BATS@ha | |
924 | addi r3,r3,BATS@l | |
925 | tophys(r3,r3) | |
926 | LOAD_BAT(0,r3,r4,r5) | |
927 | LOAD_BAT(1,r3,r4,r5) | |
928 | LOAD_BAT(2,r3,r4,r5) | |
929 | LOAD_BAT(3,r3,r4,r5) | |
7c03d653 | 930 | BEGIN_MMU_FTR_SECTION |
ee0339f2 JL |
931 | LOAD_BAT(4,r3,r4,r5) |
932 | LOAD_BAT(5,r3,r4,r5) | |
933 | LOAD_BAT(6,r3,r4,r5) | |
934 | LOAD_BAT(7,r3,r4,r5) | |
7c03d653 | 935 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) |
14cf11af PM |
936 | blr |
937 | ||
938 | /* | |
939 | * This is where the main kernel code starts. | |
940 | */ | |
941 | start_here: | |
942 | /* ptr to current */ | |
943 | lis r2,init_task@h | |
944 | ori r2,r2,init_task@l | |
945 | /* Set up for using our exception vectors */ | |
946 | /* ptr to phys current thread */ | |
947 | tophys(r4,r2) | |
948 | addi r4,r4,THREAD /* init task's THREAD */ | |
949 | CLR_TOP32(r4) | |
ee43eb78 | 950 | mtspr SPRN_SPRG_THREAD,r4 |
14cf11af | 951 | li r3,0 |
ee43eb78 | 952 | mtspr SPRN_SPRG_RTAS,r3 /* 0 => not in RTAS */ |
14cf11af PM |
953 | |
954 | /* stack */ | |
955 | lis r1,init_thread_union@ha | |
956 | addi r1,r1,init_thread_union@l | |
957 | li r0,0 | |
958 | stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) | |
959 | /* | |
187a0067 | 960 | * Do early platform-specific initialization, |
14cf11af PM |
961 | * and set up the MMU. |
962 | */ | |
963 | mr r3,r31 | |
964 | mr r4,r30 | |
14cf11af | 965 | bl machine_init |
22c841c9 | 966 | bl __save_cpu_setup |
14cf11af PM |
967 | bl MMU_init |
968 | ||
14cf11af PM |
969 | /* |
970 | * Go back to running unmapped so we can load up new values | |
971 | * for SDR1 (hash table pointer) and the segment registers | |
972 | * and change to using our exception vectors. | |
973 | */ | |
974 | lis r4,2f@h | |
975 | ori r4,r4,2f@l | |
976 | tophys(r4,r4) | |
977 | li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) | |
978 | FIX_SRR1(r3,r5) | |
979 | mtspr SPRN_SRR0,r4 | |
980 | mtspr SPRN_SRR1,r3 | |
981 | SYNC | |
982 | RFI | |
983 | /* Load up the kernel context */ | |
984 | 2: bl load_up_mmu | |
985 | ||
986 | #ifdef CONFIG_BDI_SWITCH | |
987 | /* Add helper information for the Abatron bdiGDB debugger. | |
988 | * We do this here because we know the mmu is disabled, and | |
989 | * will be enabled for real in just a few instructions. | |
990 | */ | |
991 | lis r5, abatron_pteptrs@h | |
992 | ori r5, r5, abatron_pteptrs@l | |
993 | stw r5, 0xf0(r0) /* This much match your Abatron config */ | |
994 | lis r6, swapper_pg_dir@h | |
995 | ori r6, r6, swapper_pg_dir@l | |
996 | tophys(r5, r5) | |
997 | stw r6, 0(r5) | |
998 | #endif /* CONFIG_BDI_SWITCH */ | |
999 | ||
1000 | /* Now turn on the MMU for real! */ | |
1001 | li r4,MSR_KERNEL | |
1002 | FIX_SRR1(r4,r5) | |
1003 | lis r3,start_kernel@h | |
1004 | ori r3,r3,start_kernel@l | |
1005 | mtspr SPRN_SRR0,r3 | |
1006 | mtspr SPRN_SRR1,r4 | |
1007 | SYNC | |
1008 | RFI | |
1009 | ||
1010 | /* | |
5e696617 BH |
1011 | * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next); |
1012 | * | |
14cf11af PM |
1013 | * Set up the segment registers for a new context. |
1014 | */ | |
5e696617 BH |
1015 | _ENTRY(switch_mmu_context) |
1016 | lwz r3,MMCONTEXTID(r4) | |
1017 | cmpwi cr0,r3,0 | |
1018 | blt- 4f | |
14cf11af PM |
1019 | mulli r3,r3,897 /* multiply context by skew factor */ |
1020 | rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */ | |
1021 | addis r3,r3,0x6000 /* Set Ks, Ku bits */ | |
1022 | li r0,NUM_USER_SEGMENTS | |
1023 | mtctr r0 | |
1024 | ||
1025 | #ifdef CONFIG_BDI_SWITCH | |
1026 | /* Context switch the PTE pointer for the Abatron BDI2000. | |
1027 | * The PGDIR is passed as second argument. | |
1028 | */ | |
5e696617 | 1029 | lwz r4,MM_PGD(r4) |
14cf11af PM |
1030 | lis r5, KERNELBASE@h |
1031 | lwz r5, 0xf0(r5) | |
1032 | stw r4, 0x4(r5) | |
1033 | #endif | |
1034 | li r4,0 | |
1035 | isync | |
1036 | 3: | |
14cf11af PM |
1037 | mtsrin r3,r4 |
1038 | addi r3,r3,0x111 /* next VSID */ | |
1039 | rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */ | |
1040 | addis r4,r4,0x1000 /* address of next segment */ | |
1041 | bdnz 3b | |
1042 | sync | |
1043 | isync | |
1044 | blr | |
5e696617 BH |
1045 | 4: trap |
1046 | EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0 | |
1047 | blr | |
14cf11af PM |
1048 | |
1049 | /* | |
1050 | * An undocumented "feature" of 604e requires that the v bit | |
1051 | * be cleared before changing BAT values. | |
1052 | * | |
1053 | * Also, newer IBM firmware does not clear bat3 and 4 so | |
1054 | * this makes sure it's done. | |
1055 | * -- Cort | |
1056 | */ | |
1057 | clear_bats: | |
1058 | li r10,0 | |
1059 | mfspr r9,SPRN_PVR | |
1060 | rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ | |
1061 | cmpwi r9, 1 | |
1062 | beq 1f | |
1063 | ||
1064 | mtspr SPRN_DBAT0U,r10 | |
1065 | mtspr SPRN_DBAT0L,r10 | |
1066 | mtspr SPRN_DBAT1U,r10 | |
1067 | mtspr SPRN_DBAT1L,r10 | |
1068 | mtspr SPRN_DBAT2U,r10 | |
1069 | mtspr SPRN_DBAT2L,r10 | |
1070 | mtspr SPRN_DBAT3U,r10 | |
1071 | mtspr SPRN_DBAT3L,r10 | |
1072 | 1: | |
1073 | mtspr SPRN_IBAT0U,r10 | |
1074 | mtspr SPRN_IBAT0L,r10 | |
1075 | mtspr SPRN_IBAT1U,r10 | |
1076 | mtspr SPRN_IBAT1L,r10 | |
1077 | mtspr SPRN_IBAT2U,r10 | |
1078 | mtspr SPRN_IBAT2L,r10 | |
1079 | mtspr SPRN_IBAT3U,r10 | |
1080 | mtspr SPRN_IBAT3L,r10 | |
7c03d653 | 1081 | BEGIN_MMU_FTR_SECTION |
14cf11af PM |
1082 | /* Here's a tweak: at this point, CPU setup have |
1083 | * not been called yet, so HIGH_BAT_EN may not be | |
1084 | * set in HID0 for the 745x processors. However, it | |
1085 | * seems that doesn't affect our ability to actually | |
1086 | * write to these SPRs. | |
1087 | */ | |
1088 | mtspr SPRN_DBAT4U,r10 | |
1089 | mtspr SPRN_DBAT4L,r10 | |
1090 | mtspr SPRN_DBAT5U,r10 | |
1091 | mtspr SPRN_DBAT5L,r10 | |
1092 | mtspr SPRN_DBAT6U,r10 | |
1093 | mtspr SPRN_DBAT6L,r10 | |
1094 | mtspr SPRN_DBAT7U,r10 | |
1095 | mtspr SPRN_DBAT7L,r10 | |
1096 | mtspr SPRN_IBAT4U,r10 | |
1097 | mtspr SPRN_IBAT4L,r10 | |
1098 | mtspr SPRN_IBAT5U,r10 | |
1099 | mtspr SPRN_IBAT5L,r10 | |
1100 | mtspr SPRN_IBAT6U,r10 | |
1101 | mtspr SPRN_IBAT6L,r10 | |
1102 | mtspr SPRN_IBAT7U,r10 | |
1103 | mtspr SPRN_IBAT7L,r10 | |
7c03d653 | 1104 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) |
14cf11af PM |
1105 | blr |
1106 | ||
1107 | flush_tlbs: | |
1108 | lis r10, 0x40 | |
1109 | 1: addic. r10, r10, -0x1000 | |
1110 | tlbie r10 | |
9acd57ca | 1111 | bgt 1b |
14cf11af PM |
1112 | sync |
1113 | blr | |
1114 | ||
1115 | mmu_off: | |
1116 | addi r4, r3, __after_mmu_off - _start | |
1117 | mfmsr r3 | |
1118 | andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */ | |
1119 | beqlr | |
1120 | andc r3,r3,r0 | |
1121 | mtspr SPRN_SRR0,r4 | |
1122 | mtspr SPRN_SRR1,r3 | |
1123 | sync | |
1124 | RFI | |
1125 | ||
14cf11af | 1126 | /* |
4a5cbf17 BH |
1127 | * On 601, we use 3 BATs to map up to 24M of RAM at _PAGE_OFFSET |
1128 | * (we keep one for debugging) and on others, we use one 256M BAT. | |
14cf11af PM |
1129 | */ |
1130 | initial_bats: | |
ccdcef72 | 1131 | lis r11,PAGE_OFFSET@h |
14cf11af PM |
1132 | mfspr r9,SPRN_PVR |
1133 | rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ | |
1134 | cmpwi 0,r9,1 | |
1135 | bne 4f | |
1136 | ori r11,r11,4 /* set up BAT registers for 601 */ | |
1137 | li r8,0x7f /* valid, block length = 8MB */ | |
14cf11af PM |
1138 | mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */ |
1139 | mtspr SPRN_IBAT0L,r8 /* lower BAT register */ | |
4a5cbf17 BH |
1140 | addis r11,r11,0x800000@h |
1141 | addis r8,r8,0x800000@h | |
1142 | mtspr SPRN_IBAT1U,r11 | |
1143 | mtspr SPRN_IBAT1L,r8 | |
1144 | addis r11,r11,0x800000@h | |
1145 | addis r8,r8,0x800000@h | |
1146 | mtspr SPRN_IBAT2U,r11 | |
1147 | mtspr SPRN_IBAT2L,r8 | |
14cf11af PM |
1148 | isync |
1149 | blr | |
14cf11af PM |
1150 | |
1151 | 4: tophys(r8,r11) | |
1152 | #ifdef CONFIG_SMP | |
1153 | ori r8,r8,0x12 /* R/W access, M=1 */ | |
1154 | #else | |
1155 | ori r8,r8,2 /* R/W access */ | |
1156 | #endif /* CONFIG_SMP */ | |
14cf11af | 1157 | ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */ |
14cf11af | 1158 | |
14cf11af PM |
1159 | mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */ |
1160 | mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */ | |
1161 | mtspr SPRN_IBAT0L,r8 | |
1162 | mtspr SPRN_IBAT0U,r11 | |
1163 | isync | |
1164 | blr | |
1165 | ||
14cf11af | 1166 | |
f21f49ea | 1167 | #ifdef CONFIG_BOOTX_TEXT |
51d3082f BH |
1168 | setup_disp_bat: |
1169 | /* | |
1170 | * setup the display bat prepared for us in prom.c | |
1171 | */ | |
1172 | mflr r8 | |
1173 | bl reloc_offset | |
1174 | mtlr r8 | |
1175 | addis r8,r3,disp_BAT@ha | |
1176 | addi r8,r8,disp_BAT@l | |
1177 | cmpwi cr0,r8,0 | |
1178 | beqlr | |
1179 | lwz r11,0(r8) | |
1180 | lwz r8,4(r8) | |
1181 | mfspr r9,SPRN_PVR | |
1182 | rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ | |
1183 | cmpwi 0,r9,1 | |
1184 | beq 1f | |
1185 | mtspr SPRN_DBAT3L,r8 | |
1186 | mtspr SPRN_DBAT3U,r11 | |
1187 | blr | |
1188 | 1: mtspr SPRN_IBAT3L,r8 | |
1189 | mtspr SPRN_IBAT3U,r11 | |
1190 | blr | |
f21f49ea | 1191 | #endif /* CONFIG_BOOTX_TEXT */ |
51d3082f | 1192 | |
c374e00e SW |
1193 | #ifdef CONFIG_PPC_EARLY_DEBUG_CPM |
1194 | setup_cpm_bat: | |
1195 | lis r8, 0xf000 | |
1196 | ori r8, r8, 0x002a | |
1197 | mtspr SPRN_DBAT1L, r8 | |
1198 | ||
1199 | lis r11, 0xf000 | |
1200 | ori r11, r11, (BL_1M << 2) | 2 | |
1201 | mtspr SPRN_DBAT1U, r11 | |
1202 | ||
1203 | blr | |
1204 | #endif | |
1205 | ||
14cf11af PM |
1206 | #ifdef CONFIG_8260 |
1207 | /* Jump into the system reset for the rom. | |
1208 | * We first disable the MMU, and then jump to the ROM reset address. | |
1209 | * | |
1210 | * r3 is the board info structure, r4 is the location for starting. | |
1211 | * I use this for building a small kernel that can load other kernels, | |
1212 | * rather than trying to write or rely on a rom monitor that can tftp load. | |
1213 | */ | |
1214 | .globl m8260_gorom | |
1215 | m8260_gorom: | |
1216 | mfmsr r0 | |
1217 | rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */ | |
1218 | sync | |
1219 | mtmsr r0 | |
1220 | sync | |
1221 | mfspr r11, SPRN_HID0 | |
1222 | lis r10, 0 | |
1223 | ori r10,r10,HID0_ICE|HID0_DCE | |
1224 | andc r11, r11, r10 | |
1225 | mtspr SPRN_HID0, r11 | |
1226 | isync | |
1227 | li r5, MSR_ME|MSR_RI | |
1228 | lis r6,2f@h | |
1229 | addis r6,r6,-KERNELBASE@h | |
1230 | ori r6,r6,2f@l | |
1231 | mtspr SPRN_SRR0,r6 | |
1232 | mtspr SPRN_SRR1,r5 | |
1233 | isync | |
1234 | sync | |
1235 | rfi | |
1236 | 2: | |
1237 | mtlr r4 | |
1238 | blr | |
1239 | #endif | |
1240 | ||
1241 | ||
1242 | /* | |
1243 | * We put a few things here that have to be page-aligned. | |
1244 | * This stuff goes at the beginning of the data segment, | |
1245 | * which is page-aligned. | |
1246 | */ | |
1247 | .data | |
1248 | .globl sdata | |
1249 | sdata: | |
1250 | .globl empty_zero_page | |
1251 | empty_zero_page: | |
1252 | .space 4096 | |
1253 | ||
1254 | .globl swapper_pg_dir | |
1255 | swapper_pg_dir: | |
bee86f14 | 1256 | .space PGD_TABLE_SIZE |
14cf11af | 1257 | |
14cf11af PM |
1258 | .globl intercept_table |
1259 | intercept_table: | |
1260 | .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700 | |
1261 | .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0 | |
1262 | .long 0, 0, 0, i0x1300, 0, 0, 0, 0 | |
1263 | .long 0, 0, 0, 0, 0, 0, 0, 0 | |
1264 | .long 0, 0, 0, 0, 0, 0, 0, 0 | |
1265 | .long 0, 0, 0, 0, 0, 0, 0, 0 | |
1266 | ||
1267 | /* Room for two PTE pointers, usually the kernel and current user pointers | |
1268 | * to their respective root page table. | |
1269 | */ | |
1270 | abatron_pteptrs: | |
1271 | .space 8 |