Merge tag 'mvebu-fixes-5.2-2' of git://git.infradead.org/linux-mvebu into arm/fixes
[linux-2.6-block.git] / arch / powerpc / kernel / head_32.S
CommitLineData
2874c5fd 1/* SPDX-License-Identifier: GPL-2.0-or-later */
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2/*
3 * PowerPC version
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 *
6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Adapted for Power Macintosh by Paul Mackerras.
9 * Low-level exception handlers and MMU support
10 * rewritten by Paul Mackerras.
11 * Copyright (C) 1996 Paul Mackerras.
12 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
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13 *
14 * This file contains the low-level support and setup for the
15 * PowerPC platform, including trap and interrupt dispatch.
16 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
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17 */
18
e7039845 19#include <linux/init.h>
b3b8dc6c 20#include <asm/reg.h>
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21#include <asm/page.h>
22#include <asm/mmu.h>
23#include <asm/pgtable.h>
24#include <asm/cputable.h>
25#include <asm/cache.h>
26#include <asm/thread_info.h>
27#include <asm/ppc_asm.h>
28#include <asm/asm-offsets.h>
ec2b36b9 29#include <asm/ptrace.h>
5e696617 30#include <asm/bug.h>
dd84c217 31#include <asm/kvm_book3s_asm.h>
9445aa1a 32#include <asm/export.h>
2c86cd18 33#include <asm/feature-fixups.h>
14cf11af 34
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35#include "head_32.h"
36
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37/* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
38#define LOAD_BAT(n, reg, RA, RB) \
39 /* see the comment for clear_bats() -- Cort */ \
40 li RA,0; \
41 mtspr SPRN_IBAT##n##U,RA; \
42 mtspr SPRN_DBAT##n##U,RA; \
43 lwz RA,(n*16)+0(reg); \
44 lwz RB,(n*16)+4(reg); \
45 mtspr SPRN_IBAT##n##U,RA; \
46 mtspr SPRN_IBAT##n##L,RB; \
47 beq 1f; \
48 lwz RA,(n*16)+8(reg); \
49 lwz RB,(n*16)+12(reg); \
50 mtspr SPRN_DBAT##n##U,RA; \
51 mtspr SPRN_DBAT##n##L,RB; \
521:
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e7039845 54 __HEAD
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55 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
56 .stabs "head_32.S",N_SO,0,0,0f
14cf11af 570:
748a7683 58_ENTRY(_stext);
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59
60/*
61 * _start is defined this way because the XCOFF loader in the OpenFirmware
62 * on the powermac expects the entry point to be a procedure descriptor.
63 */
748a7683 64_ENTRY(_start);
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65 /*
66 * These are here for legacy reasons, the kernel used to
67 * need to look like a coff function entry for the pmac
68 * but we're always started by some kind of bootloader now.
69 * -- Cort
70 */
71 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
72 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
73 nop
74
75/* PMAC
76 * Enter here with the kernel text, data and bss loaded starting at
77 * 0, running with virtual == physical mapping.
78 * r5 points to the prom entry point (the client interface handler
79 * address). Address translation is turned on, with the prom
80 * managing the hash table. Interrupts are disabled. The stack
81 * pointer (r1) points to just below the end of the half-meg region
82 * from 0x380000 - 0x400000, which is mapped in already.
83 *
84 * If we are booted from MacOS via BootX, we enter with the kernel
85 * image loaded somewhere, and the following values in registers:
86 * r3: 'BooX' (0x426f6f58)
87 * r4: virtual address of boot_infos_t
88 * r5: 0
89 *
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90 * PREP
91 * This is jumped to on prep systems right after the kernel is relocated
92 * to its proper place in memory by the boot loader. The expected layout
93 * of the regs is:
94 * r3: ptr to residual data
95 * r4: initrd_start or if no initrd then 0
96 * r5: initrd_end - unused if r4 is 0
97 * r6: Start of command line string
98 * r7: End of command line string
99 *
100 * This just gets a minimal mmu environment setup so we can call
101 * start_here() to do the real work.
102 * -- Cort
103 */
104
105 .globl __start
106__start:
107/*
108 * We have to do any OF calls before we map ourselves to KERNELBASE,
109 * because OF may have I/O devices mapped into that area
110 * (particularly on CHRP).
111 */
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112 cmpwi 0,r5,0
113 beq 1f
2bda347b 114
28794d34 115#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
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116 /* find out where we are now */
117 bcl 20,31,$+4
1180: mflr r8 /* r8 = runtime addr here */
119 addis r8,r8,(_stext - 0b)@ha
120 addi r8,r8,(_stext - 0b)@l /* current runtime base addr */
9b6b563c 121 bl prom_init
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122#endif /* CONFIG_PPC_OF_BOOT_TRAMPOLINE */
123
124 /* We never return. We also hit that trap if trying to boot
125 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
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126 trap
127
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128/*
129 * Check for BootX signature when supporting PowerMac and branch to
130 * appropriate trampoline if it's present
131 */
132#ifdef CONFIG_PPC_PMAC
1331: lis r31,0x426f
134 ori r31,r31,0x6f58
135 cmpw 0,r3,r31
136 bne 1f
137 bl bootx_init
138 trap
139#endif /* CONFIG_PPC_PMAC */
140
6dece0eb 1411: mr r31,r3 /* save device tree ptr */
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142 li r24,0 /* cpu # */
143
144/*
145 * early_init() does the early machine identification and does
146 * the necessary low-level setup and clears the BSS
147 * -- Cort <cort@fsmlabs.com>
148 */
149 bl early_init
150
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151/* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
152 * the physical address we are running at, returned by early_init()
153 */
154 bl mmu_off
155__after_mmu_off:
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156 bl clear_bats
157 bl flush_tlbs
158
159 bl initial_bats
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160 bl load_segment_registers
161#ifdef CONFIG_KASAN
162 bl early_hash_table
163#endif
f21f49ea 164#if defined(CONFIG_BOOTX_TEXT)
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165 bl setup_disp_bat
166#endif
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167#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
168 bl setup_cpm_bat
169#endif
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170#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
171 bl setup_usbgecko_bat
172#endif
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173
174/*
175 * Call setup_cpu for CPU 0 and initialize 6xx Idle
176 */
177 bl reloc_offset
178 li r24,0 /* cpu# */
179 bl call_setup_cpu /* Call setup_cpu for this CPU */
d7cceda9 180#ifdef CONFIG_PPC_BOOK3S_32
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181 bl reloc_offset
182 bl init_idle_6xx
d7cceda9 183#endif /* CONFIG_PPC_BOOK3S_32 */
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184
185
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186/*
187 * We need to run with _start at physical address 0.
188 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
189 * the exception vectors at 0 (and therefore this copy
190 * overwrites OF's exception vectors with our own).
9b6b563c 191 * The MMU is off at this point.
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192 */
193 bl reloc_offset
194 mr r26,r3
195 addis r4,r3,KERNELBASE@h /* current address of _start */
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196 lis r5,PHYSICAL_START@h
197 cmplw 0,r4,r5 /* already running at PHYSICAL_START? */
14cf11af 198 bne relocate_kernel
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199/*
200 * we now have the 1st 16M of ram mapped with the bats.
201 * prep needs the mmu to be turned on here, but pmac already has it on.
202 * this shouldn't bother the pmac since it just gets turned on again
203 * as we jump to our code at KERNELBASE. -- Cort
204 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
205 * off, and in other cases, we now turn it off before changing BATs above.
206 */
207turn_on_mmu:
208 mfmsr r0
215b8237 209 ori r0,r0,MSR_DR|MSR_IR|MSR_RI
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210 mtspr SPRN_SRR1,r0
211 lis r0,start_here@h
212 ori r0,r0,start_here@l
213 mtspr SPRN_SRR0,r0
214 SYNC
215 RFI /* enables MMU */
216
217/*
218 * We need __secondary_hold as a place to hold the other cpus on
219 * an SMP machine, even when we are running a UP kernel.
220 */
221 . = 0xc0 /* for prep bootloader */
222 li r3,1 /* MTX only has 1 cpu */
223 .globl __secondary_hold
224__secondary_hold:
225 /* tell the master we're here */
bbd0abda 226 stw r3,__secondary_hold_acknowledge@l(0)
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227#ifdef CONFIG_SMP
228100: lwz r4,0(0)
229 /* wait until we're told to start */
230 cmpw 0,r4,r3
231 bne 100b
232 /* our cpu # was at addr 0 - go */
233 mr r24,r3 /* cpu # */
234 b __secondary_start
235#else
236 b .
237#endif /* CONFIG_SMP */
238
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239 .globl __secondary_hold_spinloop
240__secondary_hold_spinloop:
241 .long 0
242 .globl __secondary_hold_acknowledge
243__secondary_hold_acknowledge:
244 .long -1
245
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246/* System reset */
247/* core99 pmac starts the seconary here by changing the vector, and
dc1c1ca3 248 putting it back to what it was (unknown_exception) when done. */
dc1c1ca3 249 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
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250
251/* Machine check */
252/*
253 * On CHRP, this is complicated by the fact that we could get a
254 * machine check inside RTAS, and we have no guarantee that certain
255 * critical registers will have the values we expect. The set of
256 * registers that might have bad values includes all the GPRs
257 * and all the BATs. We indicate that we are in RTAS by putting
258 * a non-zero value, the address of the exception frame to use,
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259 * in thread.rtas_sp. The machine check handler checks thread.rtas_sp
260 * and uses its value if it is non-zero.
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261 * (Other exception handlers assume that r1 is a valid kernel stack
262 * pointer when we take an exception from supervisor mode.)
263 * -- paulus.
264 */
265 . = 0x200
dd84c217 266 DO_KVM 0x200
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267 mtspr SPRN_SPRG_SCRATCH0,r10
268 mtspr SPRN_SPRG_SCRATCH1,r11
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269 mfcr r10
270#ifdef CONFIG_PPC_CHRP
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271 mfspr r11, SPRN_SPRG_THREAD
272 lwz r11, RTAS_SP(r11)
273 cmpwi cr1, r11, 0
274 bne cr1, 7f
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275#endif /* CONFIG_PPC_CHRP */
276 EXCEPTION_PROLOG_1
2777: EXCEPTION_PROLOG_2
278 addi r3,r1,STACK_FRAME_OVERHEAD
279#ifdef CONFIG_PPC_CHRP
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280 bne cr1,1f
281#endif
dc1c1ca3 282 EXC_XFER_STD(0x200, machine_check_exception)
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283#ifdef CONFIG_PPC_CHRP
2841: b machine_check_in_rtas
285#endif
286
287/* Data access exception. */
288 . = 0x300
dd84c217 289 DO_KVM 0x300
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290DataAccess:
291 EXCEPTION_PROLOG
14cf11af 292 mfspr r10,SPRN_DSISR
4ee7084e 293 stw r10,_DSISR(r11)
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294#ifdef CONFIG_PPC_KUAP
295 andis. r0,r10,(DSISR_BAD_FAULT_32S | DSISR_DABRMATCH | DSISR_PROTFAULT)@h
296#else
f23ab3ef 297 andis. r0,r10,(DSISR_BAD_FAULT_32S|DSISR_DABRMATCH)@h
a68c31fc 298#endif
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299 bne 1f /* if not, try to put a PTE */
300 mfspr r4,SPRN_DAR /* into the hash table */
301 rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
4a3a224c 302BEGIN_MMU_FTR_SECTION
14cf11af 303 bl hash_page
4a3a224c 304END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
4ee7084e 3051: lwz r5,_DSISR(r11) /* get DSISR value */
14cf11af 306 mfspr r4,SPRN_DAR
a546498f 307 EXC_XFER_LITE(0x300, handle_page_fault)
14cf11af 308
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309
310/* Instruction access exception. */
311 . = 0x400
dd84c217 312 DO_KVM 0x400
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313InstructionAccess:
314 EXCEPTION_PROLOG
b4c001dc 315 andis. r0,r9,SRR1_ISI_NOPT@h /* no pte found? */
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316 beq 1f /* if so, try to put a PTE */
317 li r3,0 /* into the hash table */
318 mr r4,r12 /* SRR0 is fault address */
4a3a224c 319BEGIN_MMU_FTR_SECTION
14cf11af 320 bl hash_page
4a3a224c 321END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
14cf11af 3221: mr r4,r12
b4c001dc 323 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
a546498f 324 EXC_XFER_LITE(0x400, handle_page_fault)
14cf11af 325
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326/* External interrupt */
327 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
328
329/* Alignment exception */
330 . = 0x600
dd84c217 331 DO_KVM 0x600
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332Alignment:
333 EXCEPTION_PROLOG
334 mfspr r4,SPRN_DAR
335 stw r4,_DAR(r11)
336 mfspr r5,SPRN_DSISR
337 stw r5,_DSISR(r11)
338 addi r3,r1,STACK_FRAME_OVERHEAD
642770dd 339 EXC_XFER_STD(0x600, alignment_exception)
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340
341/* Program check exception */
dc1c1ca3 342 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
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343
344/* Floating-point unavailable */
345 . = 0x800
dd84c217 346 DO_KVM 0x800
14cf11af 347FPUnavailable:
aa42c69c
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348BEGIN_FTR_SECTION
349/*
350 * Certain Freescale cores don't have a FPU and treat fp instructions
351 * as a FP Unavailable exception. Redirect to illegal/emulation handling.
352 */
353 b ProgramCheck
354END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
14cf11af 355 EXCEPTION_PROLOG
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356 beq 1f
357 bl load_up_fpu /* if from user, just load it up */
358 b fast_exception_return
3591: addi r3,r1,STACK_FRAME_OVERHEAD
642770dd 360 EXC_XFER_LITE(0x800, kernel_fp_unavailable_exception)
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361
362/* Decrementer */
363 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
364
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365 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_STD)
366 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_STD)
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367
368/* System call */
369 . = 0xc00
dd84c217 370 DO_KVM 0xc00
14cf11af 371SystemCall:
b86fb888 372 SYSCALL_ENTRY 0xc00
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373
374/* Single step - not used on 601 */
dc1c1ca3 375 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
642770dd 376 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_STD)
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377
378/*
379 * The Altivec unavailable trap is at 0x0f20. Foo.
380 * We effectively remap it to 0x3000.
381 * We include an altivec unavailable exception vector even if
382 * not configured for Altivec, so that you can't panic a
383 * non-altivec kernel running on a machine with altivec just
384 * by executing an altivec instruction.
385 */
386 . = 0xf00
dd84c217 387 DO_KVM 0xf00
555d97ac 388 b PerformanceMonitor
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389
390 . = 0xf20
dd84c217 391 DO_KVM 0xf20
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392 b AltiVecUnavailable
393
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394/*
395 * Handle TLB miss for instruction on 603/603e.
396 * Note: we get an alternate set of r0 - r3 to use automatically.
397 */
398 . = 0x1000
399InstructionTLBMiss:
400/*
00fcb147 401 * r0: scratch
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402 * r1: linux style pte ( later becomes ppc hardware pte )
403 * r2: ptr to linux-style pte
404 * r3: scratch
405 */
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406 /* Get PTE (linux-style) and check access */
407 mfspr r3,SPRN_IMISS
a8a12199 408#if defined(CONFIG_MODULES) || defined(CONFIG_DEBUG_PAGEALLOC)
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409 lis r1,PAGE_OFFSET@h /* check if kernel address */
410 cmplw 0,r1,r3
a8a12199 411#endif
93c4a162 412 mfspr r2, SPRN_SPRG_PGDIR
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413#ifdef CONFIG_SWAP
414 li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
415#else
451b3ec0 416 li r1,_PAGE_PRESENT | _PAGE_EXEC
84de6ab0 417#endif
a8a12199 418#if defined(CONFIG_MODULES) || defined(CONFIG_DEBUG_PAGEALLOC)
8a13c4f9 419 bge- 112f
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420 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
421 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
a8a12199 422#endif
93c4a162 423112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
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424 lwz r2,0(r2) /* get pmd entry */
425 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
426 beq- InstructionAddressInvalid /* return if no mapping */
427 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
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428 lwz r0,0(r2) /* get linux-style pte */
429 andc. r1,r1,r0 /* check access & ~permission */
14cf11af 430 bne- InstructionAddressInvalid /* return if access not permitted */
14cf11af 431 /* Convert linux-style PTE to low word of PPC-style PTE */
f342adca
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432 rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
433 ori r1, r1, 0xe06 /* clear out reserved bits */
434 andc r1, r0, r1 /* PP = user? 1 : 0 */
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435BEGIN_FTR_SECTION
436 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
437END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
14cf11af 438 mtspr SPRN_RPA,r1
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439 tlbli r3
440 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
441 mtcrf 0x80,r3
442 rfi
443InstructionAddressInvalid:
444 mfspr r3,SPRN_SRR1
445 rlwinm r1,r3,9,6,6 /* Get load/store bit */
446
447 addis r1,r1,0x2000
448 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
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449 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
450 or r2,r2,r1
451 mtspr SPRN_SRR1,r2
452 mfspr r1,SPRN_IMISS /* Get failing address */
453 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
454 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
455 xor r1,r1,r2
456 mtspr SPRN_DAR,r1 /* Set fault address */
457 mfmsr r0 /* Restore "normal" registers */
458 xoris r0,r0,MSR_TGPR>>16
459 mtcrf 0x80,r3 /* Restore CR0 */
460 mtmsr r0
461 b InstructionAccess
462
463/*
464 * Handle TLB miss for DATA Load operation on 603/603e
465 */
466 . = 0x1100
467DataLoadTLBMiss:
468/*
00fcb147 469 * r0: scratch
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470 * r1: linux style pte ( later becomes ppc hardware pte )
471 * r2: ptr to linux-style pte
472 * r3: scratch
473 */
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474 /* Get PTE (linux-style) and check access */
475 mfspr r3,SPRN_DMISS
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476 lis r1,PAGE_OFFSET@h /* check if kernel address */
477 cmplw 0,r1,r3
93c4a162 478 mfspr r2, SPRN_SPRG_PGDIR
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479#ifdef CONFIG_SWAP
480 li r1, _PAGE_PRESENT | _PAGE_ACCESSED
481#else
451b3ec0 482 li r1, _PAGE_PRESENT
84de6ab0 483#endif
8a13c4f9 484 bge- 112f
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485 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
486 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
93c4a162 487112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
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488 lwz r2,0(r2) /* get pmd entry */
489 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
490 beq- DataAddressInvalid /* return if no mapping */
491 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
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492 lwz r0,0(r2) /* get linux-style pte */
493 andc. r1,r1,r0 /* check access & ~permission */
14cf11af 494 bne- DataAddressInvalid /* return if access not permitted */
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495 /*
496 * NOTE! We are assuming this is not an SMP system, otherwise
497 * we would need to update the pte atomically with lwarx/stwcx.
498 */
14cf11af 499 /* Convert linux-style PTE to low word of PPC-style PTE */
f342adca 500 rlwinm r1,r0,32-9,30,30 /* _PAGE_RW -> PP msb */
f68e7927 501 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
eb3436a0 502 rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
a4bd6a93 503 ori r1,r1,0xe04 /* clear out reserved bits */
f342adca 504 andc r1,r0,r1 /* PP = user? rw? 1: 3: 0 */
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505BEGIN_FTR_SECTION
506 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
507END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
14cf11af 508 mtspr SPRN_RPA,r1
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509 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
510 mtcrf 0x80,r2
511BEGIN_MMU_FTR_SECTION
512 li r0,1
ee43eb78 513 mfspr r1,SPRN_SPRG_603_LRU
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514 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
515 slw r0,r0,r2
516 xor r1,r0,r1
517 srw r0,r1,r2
ee43eb78 518 mtspr SPRN_SPRG_603_LRU,r1
2319f123
KG
519 mfspr r2,SPRN_SRR1
520 rlwimi r2,r0,31-14,14,14
521 mtspr SPRN_SRR1,r2
522END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
14cf11af 523 tlbld r3
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524 rfi
525DataAddressInvalid:
526 mfspr r3,SPRN_SRR1
527 rlwinm r1,r3,9,6,6 /* Get load/store bit */
528 addis r1,r1,0x2000
529 mtspr SPRN_DSISR,r1
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PM
530 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
531 mtspr SPRN_SRR1,r2
532 mfspr r1,SPRN_DMISS /* Get failing address */
533 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
534 beq 20f /* Jump if big endian */
535 xori r1,r1,3
53620: mtspr SPRN_DAR,r1 /* Set fault address */
537 mfmsr r0 /* Restore "normal" registers */
538 xoris r0,r0,MSR_TGPR>>16
539 mtcrf 0x80,r3 /* Restore CR0 */
540 mtmsr r0
541 b DataAccess
542
543/*
544 * Handle TLB miss for DATA Store on 603/603e
545 */
546 . = 0x1200
547DataStoreTLBMiss:
548/*
00fcb147 549 * r0: scratch
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550 * r1: linux style pte ( later becomes ppc hardware pte )
551 * r2: ptr to linux-style pte
552 * r3: scratch
553 */
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554 /* Get PTE (linux-style) and check access */
555 mfspr r3,SPRN_DMISS
8a13c4f9
KG
556 lis r1,PAGE_OFFSET@h /* check if kernel address */
557 cmplw 0,r1,r3
93c4a162 558 mfspr r2, SPRN_SPRG_PGDIR
84de6ab0
CL
559#ifdef CONFIG_SWAP
560 li r1, _PAGE_RW | _PAGE_PRESENT | _PAGE_ACCESSED
561#else
562 li r1, _PAGE_RW | _PAGE_PRESENT
563#endif
8a13c4f9 564 bge- 112f
2c12393f
CL
565 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
566 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
93c4a162 567112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
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568 lwz r2,0(r2) /* get pmd entry */
569 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
570 beq- DataAddressInvalid /* return if no mapping */
571 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
eb3436a0
KG
572 lwz r0,0(r2) /* get linux-style pte */
573 andc. r1,r1,r0 /* check access & ~permission */
14cf11af 574 bne- DataAddressInvalid /* return if access not permitted */
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575 /*
576 * NOTE! We are assuming this is not an SMP system, otherwise
577 * we would need to update the pte atomically with lwarx/stwcx.
578 */
14cf11af 579 /* Convert linux-style PTE to low word of PPC-style PTE */
f342adca
CL
580 rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
581 li r1,0xe06 /* clear out reserved bits & PP msb */
582 andc r1,r0,r1 /* PP = user? 1: 0 */
345953cf
KG
583BEGIN_FTR_SECTION
584 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
585END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
14cf11af 586 mtspr SPRN_RPA,r1
2319f123
KG
587 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
588 mtcrf 0x80,r2
589BEGIN_MMU_FTR_SECTION
590 li r0,1
ee43eb78 591 mfspr r1,SPRN_SPRG_603_LRU
2319f123
KG
592 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
593 slw r0,r0,r2
594 xor r1,r0,r1
595 srw r0,r1,r2
ee43eb78 596 mtspr SPRN_SPRG_603_LRU,r1
2319f123
KG
597 mfspr r2,SPRN_SRR1
598 rlwimi r2,r0,31-14,14,14
599 mtspr SPRN_SRR1,r2
600END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
14cf11af 601 tlbld r3
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602 rfi
603
604#ifndef CONFIG_ALTIVEC
dc1c1ca3 605#define altivec_assist_exception unknown_exception
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606#endif
607
642770dd
CL
608 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_STD)
609 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_STD)
610 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_STD)
611 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_STD)
14cf11af 612 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
642770dd
CL
613 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_STD)
614 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_STD)
615 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_STD)
616 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_STD)
617 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_STD)
618 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_STD)
619 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_STD)
620 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_STD)
621 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_STD)
622 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_STD)
623 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_STD)
624 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_STD)
625 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_STD)
626 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_STD)
627 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_STD)
628 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_STD)
629 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_STD)
630 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_STD)
631 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_STD)
632 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_STD)
633 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_STD)
634 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_STD)
635 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_STD)
636 EXCEPTION(0x2f00, Trap_2f, unknown_exception, EXC_XFER_STD)
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637
638 . = 0x3000
639
640AltiVecUnavailable:
641 EXCEPTION_PROLOG
642#ifdef CONFIG_ALTIVEC
37f9ef55
BH
643 beq 1f
644 bl load_up_altivec /* if from user, just load it up */
645 b fast_exception_return
14cf11af 646#endif /* CONFIG_ALTIVEC */
37f9ef55 6471: addi r3,r1,STACK_FRAME_OVERHEAD
642770dd 648 EXC_XFER_LITE(0xf20, altivec_unavailable_exception)
14cf11af 649
555d97ac
AF
650PerformanceMonitor:
651 EXCEPTION_PROLOG
652 addi r3,r1,STACK_FRAME_OVERHEAD
653 EXC_XFER_STD(0xf00, performance_monitor_exception)
654
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655
656/*
657 * This code is jumped to from the startup code to copy
ccdcef72 658 * the kernel image to physical address PHYSICAL_START.
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659 */
660relocate_kernel:
661 addis r9,r26,klimit@ha /* fetch klimit */
662 lwz r25,klimit@l(r9)
663 addis r25,r25,-KERNELBASE@h
ccdcef72 664 lis r3,PHYSICAL_START@h /* Destination base address */
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665 li r6,0 /* Destination offset */
666 li r5,0x4000 /* # bytes of memory to copy */
667 bl copy_and_flush /* copy the first 0x4000 bytes */
668 addi r0,r3,4f@l /* jump to the address of 4f */
669 mtctr r0 /* in copy and do the rest. */
670 bctr /* jump to the copy */
6714: mr r5,r25
672 bl copy_and_flush /* copy the rest */
673 b turn_on_mmu
674
675/*
676 * Copy routine used to copy the kernel to start at physical address 0
677 * and flush and invalidate the caches as needed.
678 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
679 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
680 */
748a7683 681_ENTRY(copy_and_flush)
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682 addi r5,r5,-4
683 addi r6,r6,-4
7dffb720 6844: li r0,L1_CACHE_BYTES/4
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685 mtctr r0
6863: addi r6,r6,4 /* copy a cache line */
687 lwzx r0,r6,r4
688 stwx r0,r6,r3
689 bdnz 3b
690 dcbst r6,r3 /* write it to memory */
691 sync
692 icbi r6,r3 /* flush the icache line */
693 cmplw 0,r6,r5
694 blt 4b
695 sync /* additional sync needed on g4 */
696 isync
697 addi r5,r5,4
698 addi r6,r6,4
699 blr
700
14cf11af 701#ifdef CONFIG_SMP
ee0339f2
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702 .globl __secondary_start_mpc86xx
703__secondary_start_mpc86xx:
704 mfspr r3, SPRN_PIR
705 stw r3, __secondary_hold_acknowledge@l(0)
706 mr r24, r3 /* cpu # */
707 b __secondary_start
708
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709 .globl __secondary_start_pmac_0
710__secondary_start_pmac_0:
711 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
712 li r24,0
713 b 1f
714 li r24,1
715 b 1f
716 li r24,2
717 b 1f
718 li r24,3
7191:
720 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
721 set to map the 0xf0000000 - 0xffffffff region */
722 mfmsr r0
723 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
724 SYNC
725 mtmsr r0
726 isync
727
728 .globl __secondary_start
729__secondary_start:
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730 /* Copy some CPU settings from CPU 0 */
731 bl __restore_cpu_setup
732
733 lis r3,-KERNELBASE@h
734 mr r4,r24
14cf11af 735 bl call_setup_cpu /* Call setup_cpu for this CPU */
d7cceda9 736#ifdef CONFIG_PPC_BOOK3S_32
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737 lis r3,-KERNELBASE@h
738 bl init_idle_6xx
d7cceda9 739#endif /* CONFIG_PPC_BOOK3S_32 */
14cf11af 740
4e67bfd7 741 /* get current's stack and current */
7c19c2e5
CL
742 lis r2,secondary_current@ha
743 tophys(r2,r2)
744 lwz r2,secondary_current@l(r2)
ed1cd6de
CL
745 tophys(r1,r2)
746 lwz r1,TASK_STACK(r1)
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747
748 /* stack */
749 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
750 li r0,0
751 tophys(r3,r1)
752 stw r0,0(r3)
753
754 /* load up the MMU */
755 bl load_up_mmu
756
757 /* ptr to phys current thread */
758 tophys(r4,r2)
759 addi r4,r4,THREAD /* phys address of our thread_struct */
ee43eb78 760 mtspr SPRN_SPRG_THREAD,r4
4622a2d4
CL
761 lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
762 ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
763 mtspr SPRN_SPRG_PGDIR, r4
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764
765 /* enable MMU and jump to start_secondary */
766 li r4,MSR_KERNEL
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767 lis r3,start_secondary@h
768 ori r3,r3,start_secondary@l
769 mtspr SPRN_SRR0,r3
770 mtspr SPRN_SRR1,r4
771 SYNC
772 RFI
773#endif /* CONFIG_SMP */
774
dd84c217
AG
775#ifdef CONFIG_KVM_BOOK3S_HANDLER
776#include "../kvm/book3s_rmhandlers.S"
777#endif
778
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779/*
780 * Those generic dummy functions are kept for CPUs not
d7cceda9 781 * included in CONFIG_PPC_BOOK3S_32
14cf11af 782 */
d7cceda9 783#if !defined(CONFIG_PPC_BOOK3S_32)
748a7683 784_ENTRY(__save_cpu_setup)
14cf11af 785 blr
748a7683 786_ENTRY(__restore_cpu_setup)
14cf11af 787 blr
d7cceda9 788#endif /* !defined(CONFIG_PPC_BOOK3S_32) */
14cf11af 789
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790/*
791 * Load stuff into the MMU. Intended to be called with
792 * IR=0 and DR=0.
793 */
215b8237
CL
794#ifdef CONFIG_KASAN
795early_hash_table:
796 sync /* Force all PTE updates to finish */
797 isync
798 tlbia /* Clear all TLB entries */
799 sync /* wait for tlbia/tlbie to finish */
800 TLBSYNC /* ... on all CPUs */
801 /* Load the SDR1 register (hash table base & size) */
802 lis r6, early_hash - PAGE_OFFSET@h
803 ori r6, r6, 3 /* 256kB table */
804 mtspr SPRN_SDR1, r6
805 blr
806#endif
807
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808load_up_mmu:
809 sync /* Force all PTE updates to finish */
810 isync
811 tlbia /* Clear all TLB entries */
812 sync /* wait for tlbia/tlbie to finish */
813 TLBSYNC /* ... on all CPUs */
814 /* Load the SDR1 register (hash table base & size) */
815 lis r6,_SDR1@ha
816 tophys(r6,r6)
817 lwz r6,_SDR1@l(r6)
818 mtspr SPRN_SDR1,r6
187a0067 819
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820/* Load the BAT registers with the values set up by MMU_init.
821 MMU_init takes care of whether we're on a 601 or not. */
822 mfpvr r3
823 srwi r3,r3,16
824 cmpwi r3,1
825 lis r3,BATS@ha
826 addi r3,r3,BATS@l
827 tophys(r3,r3)
828 LOAD_BAT(0,r3,r4,r5)
829 LOAD_BAT(1,r3,r4,r5)
830 LOAD_BAT(2,r3,r4,r5)
831 LOAD_BAT(3,r3,r4,r5)
7c03d653 832BEGIN_MMU_FTR_SECTION
ee0339f2
JL
833 LOAD_BAT(4,r3,r4,r5)
834 LOAD_BAT(5,r3,r4,r5)
835 LOAD_BAT(6,r3,r4,r5)
836 LOAD_BAT(7,r3,r4,r5)
7c03d653 837END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
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838 blr
839
215b8237
CL
840load_segment_registers:
841 li r0, NUM_USER_SEGMENTS /* load up user segment register values */
842 mtctr r0 /* for context 0 */
843 li r3, 0 /* Kp = 0, Ks = 0, VSID = 0 */
844#ifdef CONFIG_PPC_KUEP
845 oris r3, r3, SR_NX@h /* Set Nx */
846#endif
847#ifdef CONFIG_PPC_KUAP
848 oris r3, r3, SR_KS@h /* Set Ks */
849#endif
850 li r4, 0
8513: mtsrin r3, r4
852 addi r3, r3, 0x111 /* increment VSID */
853 addis r4, r4, 0x1000 /* address of next segment */
854 bdnz 3b
855 li r0, 16 - NUM_USER_SEGMENTS /* load up kernel segment registers */
856 mtctr r0 /* for context 0 */
857 rlwinm r3, r3, 0, ~SR_NX /* Nx = 0 */
858 rlwinm r3, r3, 0, ~SR_KS /* Ks = 0 */
859 oris r3, r3, SR_KP@h /* Kp = 1 */
8603: mtsrin r3, r4
861 addi r3, r3, 0x111 /* increment VSID */
862 addis r4, r4, 0x1000 /* address of next segment */
863 bdnz 3b
864 blr
865
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866/*
867 * This is where the main kernel code starts.
868 */
869start_here:
870 /* ptr to current */
871 lis r2,init_task@h
872 ori r2,r2,init_task@l
873 /* Set up for using our exception vectors */
874 /* ptr to phys current thread */
875 tophys(r4,r2)
876 addi r4,r4,THREAD /* init task's THREAD */
ee43eb78 877 mtspr SPRN_SPRG_THREAD,r4
4622a2d4
CL
878 lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
879 ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
880 mtspr SPRN_SPRG_PGDIR, r4
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881
882 /* stack */
883 lis r1,init_thread_union@ha
884 addi r1,r1,init_thread_union@l
885 li r0,0
886 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
887/*
187a0067 888 * Do early platform-specific initialization,
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889 * and set up the MMU.
890 */
2edb16ef
CL
891#ifdef CONFIG_KASAN
892 bl kasan_early_init
893#endif
6dece0eb
SW
894 li r3,0
895 mr r4,r31
14cf11af 896 bl machine_init
22c841c9 897 bl __save_cpu_setup
14cf11af 898 bl MMU_init
72f208c6
CL
899BEGIN_MMU_FTR_SECTION
900 bl MMU_init_hw_patch
901END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
14cf11af 902
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903/*
904 * Go back to running unmapped so we can load up new values
905 * for SDR1 (hash table pointer) and the segment registers
906 * and change to using our exception vectors.
907 */
908 lis r4,2f@h
909 ori r4,r4,2f@l
910 tophys(r4,r4)
911 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
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912 mtspr SPRN_SRR0,r4
913 mtspr SPRN_SRR1,r3
914 SYNC
915 RFI
916/* Load up the kernel context */
9172: bl load_up_mmu
918
919#ifdef CONFIG_BDI_SWITCH
920 /* Add helper information for the Abatron bdiGDB debugger.
921 * We do this here because we know the mmu is disabled, and
922 * will be enabled for real in just a few instructions.
923 */
924 lis r5, abatron_pteptrs@h
925 ori r5, r5, abatron_pteptrs@l
926 stw r5, 0xf0(r0) /* This much match your Abatron config */
927 lis r6, swapper_pg_dir@h
928 ori r6, r6, swapper_pg_dir@l
929 tophys(r5, r5)
930 stw r6, 0(r5)
931#endif /* CONFIG_BDI_SWITCH */
932
933/* Now turn on the MMU for real! */
934 li r4,MSR_KERNEL
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935 lis r3,start_kernel@h
936 ori r3,r3,start_kernel@l
937 mtspr SPRN_SRR0,r3
938 mtspr SPRN_SRR1,r4
939 SYNC
940 RFI
941
942/*
5e696617
BH
943 * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
944 *
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945 * Set up the segment registers for a new context.
946 */
5e696617
BH
947_ENTRY(switch_mmu_context)
948 lwz r3,MMCONTEXTID(r4)
949 cmpwi cr0,r3,0
950 blt- 4f
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951 mulli r3,r3,897 /* multiply context by skew factor */
952 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
31ed2b13
CL
953#ifdef CONFIG_PPC_KUEP
954 oris r3, r3, SR_NX@h /* Set Nx */
a68c31fc
CL
955#endif
956#ifdef CONFIG_PPC_KUAP
957 oris r3, r3, SR_KS@h /* Set Ks */
31ed2b13 958#endif
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959 li r0,NUM_USER_SEGMENTS
960 mtctr r0
961
93c4a162 962 lwz r4, MM_PGD(r4)
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963#ifdef CONFIG_BDI_SWITCH
964 /* Context switch the PTE pointer for the Abatron BDI2000.
965 * The PGDIR is passed as second argument.
966 */
40058337
CL
967 lis r5, abatron_pteptrs@ha
968 stw r4, abatron_pteptrs@l + 0x4(r5)
14cf11af 969#endif
93c4a162
CL
970 tophys(r4, r4)
971 mtspr SPRN_SPRG_PGDIR, r4
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972 li r4,0
973 isync
9743:
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975 mtsrin r3,r4
976 addi r3,r3,0x111 /* next VSID */
977 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
978 addis r4,r4,0x1000 /* address of next segment */
979 bdnz 3b
980 sync
981 isync
982 blr
5e696617
BH
9834: trap
984 EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0
985 blr
9445aa1a 986EXPORT_SYMBOL(switch_mmu_context)
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987
988/*
989 * An undocumented "feature" of 604e requires that the v bit
990 * be cleared before changing BAT values.
991 *
992 * Also, newer IBM firmware does not clear bat3 and 4 so
993 * this makes sure it's done.
994 * -- Cort
995 */
996clear_bats:
997 li r10,0
998 mfspr r9,SPRN_PVR
999 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1000 cmpwi r9, 1
1001 beq 1f
1002
1003 mtspr SPRN_DBAT0U,r10
1004 mtspr SPRN_DBAT0L,r10
1005 mtspr SPRN_DBAT1U,r10
1006 mtspr SPRN_DBAT1L,r10
1007 mtspr SPRN_DBAT2U,r10
1008 mtspr SPRN_DBAT2L,r10
1009 mtspr SPRN_DBAT3U,r10
1010 mtspr SPRN_DBAT3L,r10
10111:
1012 mtspr SPRN_IBAT0U,r10
1013 mtspr SPRN_IBAT0L,r10
1014 mtspr SPRN_IBAT1U,r10
1015 mtspr SPRN_IBAT1L,r10
1016 mtspr SPRN_IBAT2U,r10
1017 mtspr SPRN_IBAT2L,r10
1018 mtspr SPRN_IBAT3U,r10
1019 mtspr SPRN_IBAT3L,r10
7c03d653 1020BEGIN_MMU_FTR_SECTION
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1021 /* Here's a tweak: at this point, CPU setup have
1022 * not been called yet, so HIGH_BAT_EN may not be
1023 * set in HID0 for the 745x processors. However, it
1024 * seems that doesn't affect our ability to actually
1025 * write to these SPRs.
1026 */
1027 mtspr SPRN_DBAT4U,r10
1028 mtspr SPRN_DBAT4L,r10
1029 mtspr SPRN_DBAT5U,r10
1030 mtspr SPRN_DBAT5L,r10
1031 mtspr SPRN_DBAT6U,r10
1032 mtspr SPRN_DBAT6L,r10
1033 mtspr SPRN_DBAT7U,r10
1034 mtspr SPRN_DBAT7L,r10
1035 mtspr SPRN_IBAT4U,r10
1036 mtspr SPRN_IBAT4L,r10
1037 mtspr SPRN_IBAT5U,r10
1038 mtspr SPRN_IBAT5L,r10
1039 mtspr SPRN_IBAT6U,r10
1040 mtspr SPRN_IBAT6L,r10
1041 mtspr SPRN_IBAT7U,r10
1042 mtspr SPRN_IBAT7L,r10
7c03d653 1043END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
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1044 blr
1045
5e04ae85
CL
1046_ENTRY(update_bats)
1047 lis r4, 1f@h
1048 ori r4, r4, 1f@l
1049 tophys(r4, r4)
1050 mfmsr r6
1051 mflr r7
1052 li r3, MSR_KERNEL & ~(MSR_IR | MSR_DR)
1053 rlwinm r0, r6, 0, ~MSR_RI
1054 rlwinm r0, r0, 0, ~MSR_EE
1055 mtmsr r0
1056 mtspr SPRN_SRR0, r4
1057 mtspr SPRN_SRR1, r3
1058 SYNC
1059 RFI
10601: bl clear_bats
1061 lis r3, BATS@ha
1062 addi r3, r3, BATS@l
1063 tophys(r3, r3)
1064 LOAD_BAT(0, r3, r4, r5)
1065 LOAD_BAT(1, r3, r4, r5)
1066 LOAD_BAT(2, r3, r4, r5)
1067 LOAD_BAT(3, r3, r4, r5)
1068BEGIN_MMU_FTR_SECTION
1069 LOAD_BAT(4, r3, r4, r5)
1070 LOAD_BAT(5, r3, r4, r5)
1071 LOAD_BAT(6, r3, r4, r5)
1072 LOAD_BAT(7, r3, r4, r5)
1073END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1074 li r3, MSR_KERNEL & ~(MSR_IR | MSR_DR | MSR_RI)
1075 mtmsr r3
1076 mtspr SPRN_SRR0, r7
1077 mtspr SPRN_SRR1, r6
1078 SYNC
1079 RFI
1080
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PM
1081flush_tlbs:
1082 lis r10, 0x40
10831: addic. r10, r10, -0x1000
1084 tlbie r10
9acd57ca 1085 bgt 1b
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PM
1086 sync
1087 blr
1088
1089mmu_off:
1090 addi r4, r3, __after_mmu_off - _start
1091 mfmsr r3
1092 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1093 beqlr
1094 andc r3,r3,r0
1095 mtspr SPRN_SRR0,r4
1096 mtspr SPRN_SRR1,r3
1097 sync
1098 RFI
1099
14cf11af 1100/*
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BH
1101 * On 601, we use 3 BATs to map up to 24M of RAM at _PAGE_OFFSET
1102 * (we keep one for debugging) and on others, we use one 256M BAT.
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PM
1103 */
1104initial_bats:
ccdcef72 1105 lis r11,PAGE_OFFSET@h
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1106 mfspr r9,SPRN_PVR
1107 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1108 cmpwi 0,r9,1
1109 bne 4f
1110 ori r11,r11,4 /* set up BAT registers for 601 */
1111 li r8,0x7f /* valid, block length = 8MB */
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1112 mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
1113 mtspr SPRN_IBAT0L,r8 /* lower BAT register */
4a5cbf17
BH
1114 addis r11,r11,0x800000@h
1115 addis r8,r8,0x800000@h
1116 mtspr SPRN_IBAT1U,r11
1117 mtspr SPRN_IBAT1L,r8
1118 addis r11,r11,0x800000@h
1119 addis r8,r8,0x800000@h
1120 mtspr SPRN_IBAT2U,r11
1121 mtspr SPRN_IBAT2L,r8
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1122 isync
1123 blr
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1124
11254: tophys(r8,r11)
1126#ifdef CONFIG_SMP
1127 ori r8,r8,0x12 /* R/W access, M=1 */
1128#else
1129 ori r8,r8,2 /* R/W access */
1130#endif /* CONFIG_SMP */
14cf11af 1131 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
14cf11af 1132
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PM
1133 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
1134 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1135 mtspr SPRN_IBAT0L,r8
1136 mtspr SPRN_IBAT0U,r11
1137 isync
1138 blr
1139
14cf11af 1140
f21f49ea 1141#ifdef CONFIG_BOOTX_TEXT
51d3082f
BH
1142setup_disp_bat:
1143 /*
1144 * setup the display bat prepared for us in prom.c
1145 */
1146 mflr r8
1147 bl reloc_offset
1148 mtlr r8
1149 addis r8,r3,disp_BAT@ha
1150 addi r8,r8,disp_BAT@l
1151 cmpwi cr0,r8,0
1152 beqlr
1153 lwz r11,0(r8)
1154 lwz r8,4(r8)
1155 mfspr r9,SPRN_PVR
1156 rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */
1157 cmpwi 0,r9,1
1158 beq 1f
1159 mtspr SPRN_DBAT3L,r8
1160 mtspr SPRN_DBAT3U,r11
1161 blr
11621: mtspr SPRN_IBAT3L,r8
1163 mtspr SPRN_IBAT3U,r11
1164 blr
f21f49ea 1165#endif /* CONFIG_BOOTX_TEXT */
51d3082f 1166
c374e00e
SW
1167#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1168setup_cpm_bat:
1169 lis r8, 0xf000
1170 ori r8, r8, 0x002a
1171 mtspr SPRN_DBAT1L, r8
1172
1173 lis r11, 0xf000
1174 ori r11, r11, (BL_1M << 2) | 2
1175 mtspr SPRN_DBAT1U, r11
1176
1177 blr
1178#endif
1179
d1d56f8c
AH
1180#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
1181setup_usbgecko_bat:
1182 /* prepare a BAT for early io */
1183#if defined(CONFIG_GAMECUBE)
1184 lis r8, 0x0c00
1185#elif defined(CONFIG_WII)
1186 lis r8, 0x0d00
1187#else
1188#error Invalid platform for USB Gecko based early debugging.
1189#endif
1190 /*
1191 * The virtual address used must match the virtual address
1192 * associated to the fixmap entry FIX_EARLY_DEBUG_BASE.
1193 */
1194 lis r11, 0xfffe /* top 128K */
1195 ori r8, r8, 0x002a /* uncached, guarded ,rw */
1196 ori r11, r11, 0x2 /* 128K, Vs=1, Vp=0 */
1197 mtspr SPRN_DBAT1L, r8
1198 mtspr SPRN_DBAT1U, r11
1199 blr
1200#endif
1201
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1202#ifdef CONFIG_8260
1203/* Jump into the system reset for the rom.
1204 * We first disable the MMU, and then jump to the ROM reset address.
1205 *
1206 * r3 is the board info structure, r4 is the location for starting.
1207 * I use this for building a small kernel that can load other kernels,
1208 * rather than trying to write or rely on a rom monitor that can tftp load.
1209 */
1210 .globl m8260_gorom
1211m8260_gorom:
1212 mfmsr r0
1213 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1214 sync
1215 mtmsr r0
1216 sync
1217 mfspr r11, SPRN_HID0
1218 lis r10, 0
1219 ori r10,r10,HID0_ICE|HID0_DCE
1220 andc r11, r11, r10
1221 mtspr SPRN_HID0, r11
1222 isync
1223 li r5, MSR_ME|MSR_RI
1224 lis r6,2f@h
1225 addis r6,r6,-KERNELBASE@h
1226 ori r6,r6,2f@l
1227 mtspr SPRN_SRR0,r6
1228 mtspr SPRN_SRR1,r5
1229 isync
1230 sync
1231 rfi
12322:
1233 mtlr r4
1234 blr
1235#endif
1236
1237
1238/*
1239 * We put a few things here that have to be page-aligned.
1240 * This stuff goes at the beginning of the data segment,
1241 * which is page-aligned.
1242 */
1243 .data
1244 .globl sdata
1245sdata:
1246 .globl empty_zero_page
1247empty_zero_page:
1248 .space 4096
9445aa1a 1249EXPORT_SYMBOL(empty_zero_page)
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PM
1250
1251 .globl swapper_pg_dir
1252swapper_pg_dir:
bee86f14 1253 .space PGD_TABLE_SIZE
14cf11af 1254
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PM
1255/* Room for two PTE pointers, usually the kernel and current user pointers
1256 * to their respective root page table.
1257 */
1258abatron_pteptrs:
1259 .space 8